不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_cmFunc.h@6:b3885567877c, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7 
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_cmFunc.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS Cortex-M Core Function Access Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version V4.10
MikamiUitOpen 4:c1beacfc42c7 5 * @date 18. March 2015
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #ifndef __CORE_CMFUNC_H
MikamiUitOpen 4:c1beacfc42c7 39 #define __CORE_CMFUNC_H
MikamiUitOpen 4:c1beacfc42c7 40
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 /* ########################### Core Function Access ########################### */
MikamiUitOpen 4:c1beacfc42c7 43 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 4:c1beacfc42c7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MikamiUitOpen 4:c1beacfc42c7 45 @{
MikamiUitOpen 4:c1beacfc42c7 46 */
MikamiUitOpen 4:c1beacfc42c7 47
MikamiUitOpen 4:c1beacfc42c7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 4:c1beacfc42c7 49 /* ARM armcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 50
MikamiUitOpen 4:c1beacfc42c7 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 4:c1beacfc42c7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 4:c1beacfc42c7 53 #endif
MikamiUitOpen 4:c1beacfc42c7 54
MikamiUitOpen 4:c1beacfc42c7 55 /* intrinsic void __enable_irq(); */
MikamiUitOpen 4:c1beacfc42c7 56 /* intrinsic void __disable_irq(); */
MikamiUitOpen 4:c1beacfc42c7 57
MikamiUitOpen 4:c1beacfc42c7 58 /** \brief Get Control Register
MikamiUitOpen 4:c1beacfc42c7 59
MikamiUitOpen 4:c1beacfc42c7 60 This function returns the content of the Control Register.
MikamiUitOpen 4:c1beacfc42c7 61
MikamiUitOpen 4:c1beacfc42c7 62 \return Control Register value
MikamiUitOpen 4:c1beacfc42c7 63 */
MikamiUitOpen 4:c1beacfc42c7 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 4:c1beacfc42c7 65 {
MikamiUitOpen 4:c1beacfc42c7 66 register uint32_t __regControl __ASM("control");
MikamiUitOpen 4:c1beacfc42c7 67 return(__regControl);
MikamiUitOpen 4:c1beacfc42c7 68 }
MikamiUitOpen 4:c1beacfc42c7 69
MikamiUitOpen 4:c1beacfc42c7 70
MikamiUitOpen 4:c1beacfc42c7 71 /** \brief Set Control Register
MikamiUitOpen 4:c1beacfc42c7 72
MikamiUitOpen 4:c1beacfc42c7 73 This function writes the given value to the Control Register.
MikamiUitOpen 4:c1beacfc42c7 74
MikamiUitOpen 4:c1beacfc42c7 75 \param [in] control Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 76 */
MikamiUitOpen 4:c1beacfc42c7 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 4:c1beacfc42c7 78 {
MikamiUitOpen 4:c1beacfc42c7 79 register uint32_t __regControl __ASM("control");
MikamiUitOpen 4:c1beacfc42c7 80 __regControl = control;
MikamiUitOpen 4:c1beacfc42c7 81 }
MikamiUitOpen 4:c1beacfc42c7 82
MikamiUitOpen 4:c1beacfc42c7 83
MikamiUitOpen 4:c1beacfc42c7 84 /** \brief Get IPSR Register
MikamiUitOpen 4:c1beacfc42c7 85
MikamiUitOpen 4:c1beacfc42c7 86 This function returns the content of the IPSR Register.
MikamiUitOpen 4:c1beacfc42c7 87
MikamiUitOpen 4:c1beacfc42c7 88 \return IPSR Register value
MikamiUitOpen 4:c1beacfc42c7 89 */
MikamiUitOpen 4:c1beacfc42c7 90 __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 4:c1beacfc42c7 91 {
MikamiUitOpen 4:c1beacfc42c7 92 register uint32_t __regIPSR __ASM("ipsr");
MikamiUitOpen 4:c1beacfc42c7 93 return(__regIPSR);
MikamiUitOpen 4:c1beacfc42c7 94 }
MikamiUitOpen 4:c1beacfc42c7 95
MikamiUitOpen 4:c1beacfc42c7 96
MikamiUitOpen 4:c1beacfc42c7 97 /** \brief Get APSR Register
MikamiUitOpen 4:c1beacfc42c7 98
MikamiUitOpen 4:c1beacfc42c7 99 This function returns the content of the APSR Register.
MikamiUitOpen 4:c1beacfc42c7 100
MikamiUitOpen 4:c1beacfc42c7 101 \return APSR Register value
MikamiUitOpen 4:c1beacfc42c7 102 */
MikamiUitOpen 4:c1beacfc42c7 103 __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 4:c1beacfc42c7 104 {
MikamiUitOpen 4:c1beacfc42c7 105 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 4:c1beacfc42c7 106 return(__regAPSR);
MikamiUitOpen 4:c1beacfc42c7 107 }
MikamiUitOpen 4:c1beacfc42c7 108
MikamiUitOpen 4:c1beacfc42c7 109
MikamiUitOpen 4:c1beacfc42c7 110 /** \brief Get xPSR Register
MikamiUitOpen 4:c1beacfc42c7 111
MikamiUitOpen 4:c1beacfc42c7 112 This function returns the content of the xPSR Register.
MikamiUitOpen 4:c1beacfc42c7 113
MikamiUitOpen 4:c1beacfc42c7 114 \return xPSR Register value
MikamiUitOpen 4:c1beacfc42c7 115 */
MikamiUitOpen 4:c1beacfc42c7 116 __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 4:c1beacfc42c7 117 {
MikamiUitOpen 4:c1beacfc42c7 118 register uint32_t __regXPSR __ASM("xpsr");
MikamiUitOpen 4:c1beacfc42c7 119 return(__regXPSR);
MikamiUitOpen 4:c1beacfc42c7 120 }
MikamiUitOpen 4:c1beacfc42c7 121
MikamiUitOpen 4:c1beacfc42c7 122
MikamiUitOpen 4:c1beacfc42c7 123 /** \brief Get Process Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 124
MikamiUitOpen 4:c1beacfc42c7 125 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 4:c1beacfc42c7 126
MikamiUitOpen 4:c1beacfc42c7 127 \return PSP Register value
MikamiUitOpen 4:c1beacfc42c7 128 */
MikamiUitOpen 4:c1beacfc42c7 129 __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 4:c1beacfc42c7 130 {
MikamiUitOpen 4:c1beacfc42c7 131 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 4:c1beacfc42c7 132 return(__regProcessStackPointer);
MikamiUitOpen 4:c1beacfc42c7 133 }
MikamiUitOpen 4:c1beacfc42c7 134
MikamiUitOpen 4:c1beacfc42c7 135
MikamiUitOpen 4:c1beacfc42c7 136 /** \brief Set Process Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 137
MikamiUitOpen 4:c1beacfc42c7 138 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 4:c1beacfc42c7 139
MikamiUitOpen 4:c1beacfc42c7 140 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 141 */
MikamiUitOpen 4:c1beacfc42c7 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 4:c1beacfc42c7 143 {
MikamiUitOpen 4:c1beacfc42c7 144 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 4:c1beacfc42c7 145 __regProcessStackPointer = topOfProcStack;
MikamiUitOpen 4:c1beacfc42c7 146 }
MikamiUitOpen 4:c1beacfc42c7 147
MikamiUitOpen 4:c1beacfc42c7 148
MikamiUitOpen 4:c1beacfc42c7 149 /** \brief Get Main Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 150
MikamiUitOpen 4:c1beacfc42c7 151 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 4:c1beacfc42c7 152
MikamiUitOpen 4:c1beacfc42c7 153 \return MSP Register value
MikamiUitOpen 4:c1beacfc42c7 154 */
MikamiUitOpen 4:c1beacfc42c7 155 __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 4:c1beacfc42c7 156 {
MikamiUitOpen 4:c1beacfc42c7 157 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 4:c1beacfc42c7 158 return(__regMainStackPointer);
MikamiUitOpen 4:c1beacfc42c7 159 }
MikamiUitOpen 4:c1beacfc42c7 160
MikamiUitOpen 4:c1beacfc42c7 161
MikamiUitOpen 4:c1beacfc42c7 162 /** \brief Set Main Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 163
MikamiUitOpen 4:c1beacfc42c7 164 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 4:c1beacfc42c7 165
MikamiUitOpen 4:c1beacfc42c7 166 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 167 */
MikamiUitOpen 4:c1beacfc42c7 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 4:c1beacfc42c7 169 {
MikamiUitOpen 4:c1beacfc42c7 170 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 4:c1beacfc42c7 171 __regMainStackPointer = topOfMainStack;
MikamiUitOpen 4:c1beacfc42c7 172 }
MikamiUitOpen 4:c1beacfc42c7 173
MikamiUitOpen 4:c1beacfc42c7 174
MikamiUitOpen 4:c1beacfc42c7 175 /** \brief Get Priority Mask
MikamiUitOpen 4:c1beacfc42c7 176
MikamiUitOpen 4:c1beacfc42c7 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 4:c1beacfc42c7 178
MikamiUitOpen 4:c1beacfc42c7 179 \return Priority Mask value
MikamiUitOpen 4:c1beacfc42c7 180 */
MikamiUitOpen 4:c1beacfc42c7 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 4:c1beacfc42c7 182 {
MikamiUitOpen 4:c1beacfc42c7 183 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 4:c1beacfc42c7 184 return(__regPriMask);
MikamiUitOpen 4:c1beacfc42c7 185 }
MikamiUitOpen 4:c1beacfc42c7 186
MikamiUitOpen 4:c1beacfc42c7 187
MikamiUitOpen 4:c1beacfc42c7 188 /** \brief Set Priority Mask
MikamiUitOpen 4:c1beacfc42c7 189
MikamiUitOpen 4:c1beacfc42c7 190 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 4:c1beacfc42c7 191
MikamiUitOpen 4:c1beacfc42c7 192 \param [in] priMask Priority Mask
MikamiUitOpen 4:c1beacfc42c7 193 */
MikamiUitOpen 4:c1beacfc42c7 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 4:c1beacfc42c7 195 {
MikamiUitOpen 4:c1beacfc42c7 196 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 4:c1beacfc42c7 197 __regPriMask = (priMask);
MikamiUitOpen 4:c1beacfc42c7 198 }
MikamiUitOpen 4:c1beacfc42c7 199
MikamiUitOpen 4:c1beacfc42c7 200
MikamiUitOpen 4:c1beacfc42c7 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 4:c1beacfc42c7 202
MikamiUitOpen 4:c1beacfc42c7 203 /** \brief Enable FIQ
MikamiUitOpen 4:c1beacfc42c7 204
MikamiUitOpen 4:c1beacfc42c7 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 206 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 207 */
MikamiUitOpen 4:c1beacfc42c7 208 #define __enable_fault_irq __enable_fiq
MikamiUitOpen 4:c1beacfc42c7 209
MikamiUitOpen 4:c1beacfc42c7 210
MikamiUitOpen 4:c1beacfc42c7 211 /** \brief Disable FIQ
MikamiUitOpen 4:c1beacfc42c7 212
MikamiUitOpen 4:c1beacfc42c7 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 214 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 215 */
MikamiUitOpen 4:c1beacfc42c7 216 #define __disable_fault_irq __disable_fiq
MikamiUitOpen 4:c1beacfc42c7 217
MikamiUitOpen 4:c1beacfc42c7 218
MikamiUitOpen 4:c1beacfc42c7 219 /** \brief Get Base Priority
MikamiUitOpen 4:c1beacfc42c7 220
MikamiUitOpen 4:c1beacfc42c7 221 This function returns the current value of the Base Priority register.
MikamiUitOpen 4:c1beacfc42c7 222
MikamiUitOpen 4:c1beacfc42c7 223 \return Base Priority register value
MikamiUitOpen 4:c1beacfc42c7 224 */
MikamiUitOpen 4:c1beacfc42c7 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 4:c1beacfc42c7 226 {
MikamiUitOpen 4:c1beacfc42c7 227 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 4:c1beacfc42c7 228 return(__regBasePri);
MikamiUitOpen 4:c1beacfc42c7 229 }
MikamiUitOpen 4:c1beacfc42c7 230
MikamiUitOpen 4:c1beacfc42c7 231
MikamiUitOpen 4:c1beacfc42c7 232 /** \brief Set Base Priority
MikamiUitOpen 4:c1beacfc42c7 233
MikamiUitOpen 4:c1beacfc42c7 234 This function assigns the given value to the Base Priority register.
MikamiUitOpen 4:c1beacfc42c7 235
MikamiUitOpen 4:c1beacfc42c7 236 \param [in] basePri Base Priority value to set
MikamiUitOpen 4:c1beacfc42c7 237 */
MikamiUitOpen 4:c1beacfc42c7 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
MikamiUitOpen 4:c1beacfc42c7 239 {
MikamiUitOpen 4:c1beacfc42c7 240 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 4:c1beacfc42c7 241 __regBasePri = (basePri & 0xff);
MikamiUitOpen 4:c1beacfc42c7 242 }
MikamiUitOpen 4:c1beacfc42c7 243
MikamiUitOpen 4:c1beacfc42c7 244
MikamiUitOpen 4:c1beacfc42c7 245 /** \brief Set Base Priority with condition
MikamiUitOpen 4:c1beacfc42c7 246
MikamiUitOpen 4:c1beacfc42c7 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 4:c1beacfc42c7 248 or the new value increases the BASEPRI priority level.
MikamiUitOpen 4:c1beacfc42c7 249
MikamiUitOpen 4:c1beacfc42c7 250 \param [in] basePri Base Priority value to set
MikamiUitOpen 4:c1beacfc42c7 251 */
MikamiUitOpen 4:c1beacfc42c7 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
MikamiUitOpen 4:c1beacfc42c7 253 {
MikamiUitOpen 4:c1beacfc42c7 254 register uint32_t __regBasePriMax __ASM("basepri_max");
MikamiUitOpen 4:c1beacfc42c7 255 __regBasePriMax = (basePri & 0xff);
MikamiUitOpen 4:c1beacfc42c7 256 }
MikamiUitOpen 4:c1beacfc42c7 257
MikamiUitOpen 4:c1beacfc42c7 258
MikamiUitOpen 4:c1beacfc42c7 259 /** \brief Get Fault Mask
MikamiUitOpen 4:c1beacfc42c7 260
MikamiUitOpen 4:c1beacfc42c7 261 This function returns the current value of the Fault Mask register.
MikamiUitOpen 4:c1beacfc42c7 262
MikamiUitOpen 4:c1beacfc42c7 263 \return Fault Mask register value
MikamiUitOpen 4:c1beacfc42c7 264 */
MikamiUitOpen 4:c1beacfc42c7 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 4:c1beacfc42c7 266 {
MikamiUitOpen 4:c1beacfc42c7 267 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 4:c1beacfc42c7 268 return(__regFaultMask);
MikamiUitOpen 4:c1beacfc42c7 269 }
MikamiUitOpen 4:c1beacfc42c7 270
MikamiUitOpen 4:c1beacfc42c7 271
MikamiUitOpen 4:c1beacfc42c7 272 /** \brief Set Fault Mask
MikamiUitOpen 4:c1beacfc42c7 273
MikamiUitOpen 4:c1beacfc42c7 274 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 4:c1beacfc42c7 275
MikamiUitOpen 4:c1beacfc42c7 276 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 4:c1beacfc42c7 277 */
MikamiUitOpen 4:c1beacfc42c7 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 4:c1beacfc42c7 279 {
MikamiUitOpen 4:c1beacfc42c7 280 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 4:c1beacfc42c7 281 __regFaultMask = (faultMask & (uint32_t)1);
MikamiUitOpen 4:c1beacfc42c7 282 }
MikamiUitOpen 4:c1beacfc42c7 283
MikamiUitOpen 4:c1beacfc42c7 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 4:c1beacfc42c7 285
MikamiUitOpen 4:c1beacfc42c7 286
MikamiUitOpen 4:c1beacfc42c7 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 4:c1beacfc42c7 288
MikamiUitOpen 4:c1beacfc42c7 289 /** \brief Get FPSCR
MikamiUitOpen 4:c1beacfc42c7 290
MikamiUitOpen 4:c1beacfc42c7 291 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 292
MikamiUitOpen 4:c1beacfc42c7 293 \return Floating Point Status/Control register value
MikamiUitOpen 4:c1beacfc42c7 294 */
MikamiUitOpen 4:c1beacfc42c7 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 4:c1beacfc42c7 296 {
MikamiUitOpen 4:c1beacfc42c7 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 298 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 4:c1beacfc42c7 299 return(__regfpscr);
MikamiUitOpen 4:c1beacfc42c7 300 #else
MikamiUitOpen 4:c1beacfc42c7 301 return(0);
MikamiUitOpen 4:c1beacfc42c7 302 #endif
MikamiUitOpen 4:c1beacfc42c7 303 }
MikamiUitOpen 4:c1beacfc42c7 304
MikamiUitOpen 4:c1beacfc42c7 305
MikamiUitOpen 4:c1beacfc42c7 306 /** \brief Set FPSCR
MikamiUitOpen 4:c1beacfc42c7 307
MikamiUitOpen 4:c1beacfc42c7 308 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 309
MikamiUitOpen 4:c1beacfc42c7 310 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 4:c1beacfc42c7 311 */
MikamiUitOpen 4:c1beacfc42c7 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 4:c1beacfc42c7 313 {
MikamiUitOpen 4:c1beacfc42c7 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 315 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 4:c1beacfc42c7 316 __regfpscr = (fpscr);
MikamiUitOpen 4:c1beacfc42c7 317 #endif
MikamiUitOpen 4:c1beacfc42c7 318 }
MikamiUitOpen 4:c1beacfc42c7 319
MikamiUitOpen 4:c1beacfc42c7 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 4:c1beacfc42c7 321
MikamiUitOpen 4:c1beacfc42c7 322
MikamiUitOpen 4:c1beacfc42c7 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 4:c1beacfc42c7 324 /* GNU gcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 325
MikamiUitOpen 4:c1beacfc42c7 326 /** \brief Enable IRQ Interrupts
MikamiUitOpen 4:c1beacfc42c7 327
MikamiUitOpen 4:c1beacfc42c7 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 329 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 330 */
MikamiUitOpen 4:c1beacfc42c7 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MikamiUitOpen 4:c1beacfc42c7 332 {
MikamiUitOpen 4:c1beacfc42c7 333 __ASM volatile ("cpsie i" : : : "memory");
MikamiUitOpen 4:c1beacfc42c7 334 }
MikamiUitOpen 4:c1beacfc42c7 335
MikamiUitOpen 4:c1beacfc42c7 336
MikamiUitOpen 4:c1beacfc42c7 337 /** \brief Disable IRQ Interrupts
MikamiUitOpen 4:c1beacfc42c7 338
MikamiUitOpen 4:c1beacfc42c7 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 340 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 341 */
MikamiUitOpen 4:c1beacfc42c7 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
MikamiUitOpen 4:c1beacfc42c7 343 {
MikamiUitOpen 4:c1beacfc42c7 344 __ASM volatile ("cpsid i" : : : "memory");
MikamiUitOpen 4:c1beacfc42c7 345 }
MikamiUitOpen 4:c1beacfc42c7 346
MikamiUitOpen 4:c1beacfc42c7 347
MikamiUitOpen 4:c1beacfc42c7 348 /** \brief Get Control Register
MikamiUitOpen 4:c1beacfc42c7 349
MikamiUitOpen 4:c1beacfc42c7 350 This function returns the content of the Control Register.
MikamiUitOpen 4:c1beacfc42c7 351
MikamiUitOpen 4:c1beacfc42c7 352 \return Control Register value
MikamiUitOpen 4:c1beacfc42c7 353 */
MikamiUitOpen 4:c1beacfc42c7 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 4:c1beacfc42c7 355 {
MikamiUitOpen 4:c1beacfc42c7 356 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 357
MikamiUitOpen 4:c1beacfc42c7 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 359 return(result);
MikamiUitOpen 4:c1beacfc42c7 360 }
MikamiUitOpen 4:c1beacfc42c7 361
MikamiUitOpen 4:c1beacfc42c7 362
MikamiUitOpen 4:c1beacfc42c7 363 /** \brief Set Control Register
MikamiUitOpen 4:c1beacfc42c7 364
MikamiUitOpen 4:c1beacfc42c7 365 This function writes the given value to the Control Register.
MikamiUitOpen 4:c1beacfc42c7 366
MikamiUitOpen 4:c1beacfc42c7 367 \param [in] control Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 368 */
MikamiUitOpen 4:c1beacfc42c7 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 4:c1beacfc42c7 370 {
MikamiUitOpen 4:c1beacfc42c7 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
MikamiUitOpen 4:c1beacfc42c7 372 }
MikamiUitOpen 4:c1beacfc42c7 373
MikamiUitOpen 4:c1beacfc42c7 374
MikamiUitOpen 4:c1beacfc42c7 375 /** \brief Get IPSR Register
MikamiUitOpen 4:c1beacfc42c7 376
MikamiUitOpen 4:c1beacfc42c7 377 This function returns the content of the IPSR Register.
MikamiUitOpen 4:c1beacfc42c7 378
MikamiUitOpen 4:c1beacfc42c7 379 \return IPSR Register value
MikamiUitOpen 4:c1beacfc42c7 380 */
MikamiUitOpen 4:c1beacfc42c7 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 4:c1beacfc42c7 382 {
MikamiUitOpen 4:c1beacfc42c7 383 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 384
MikamiUitOpen 4:c1beacfc42c7 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 386 return(result);
MikamiUitOpen 4:c1beacfc42c7 387 }
MikamiUitOpen 4:c1beacfc42c7 388
MikamiUitOpen 4:c1beacfc42c7 389
MikamiUitOpen 4:c1beacfc42c7 390 /** \brief Get APSR Register
MikamiUitOpen 4:c1beacfc42c7 391
MikamiUitOpen 4:c1beacfc42c7 392 This function returns the content of the APSR Register.
MikamiUitOpen 4:c1beacfc42c7 393
MikamiUitOpen 4:c1beacfc42c7 394 \return APSR Register value
MikamiUitOpen 4:c1beacfc42c7 395 */
MikamiUitOpen 4:c1beacfc42c7 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 4:c1beacfc42c7 397 {
MikamiUitOpen 4:c1beacfc42c7 398 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 399
MikamiUitOpen 4:c1beacfc42c7 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 401 return(result);
MikamiUitOpen 4:c1beacfc42c7 402 }
MikamiUitOpen 4:c1beacfc42c7 403
MikamiUitOpen 4:c1beacfc42c7 404
MikamiUitOpen 4:c1beacfc42c7 405 /** \brief Get xPSR Register
MikamiUitOpen 4:c1beacfc42c7 406
MikamiUitOpen 4:c1beacfc42c7 407 This function returns the content of the xPSR Register.
MikamiUitOpen 4:c1beacfc42c7 408
MikamiUitOpen 4:c1beacfc42c7 409 \return xPSR Register value
MikamiUitOpen 4:c1beacfc42c7 410 */
MikamiUitOpen 4:c1beacfc42c7 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 4:c1beacfc42c7 412 {
MikamiUitOpen 4:c1beacfc42c7 413 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 414
MikamiUitOpen 4:c1beacfc42c7 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 416 return(result);
MikamiUitOpen 4:c1beacfc42c7 417 }
MikamiUitOpen 4:c1beacfc42c7 418
MikamiUitOpen 4:c1beacfc42c7 419
MikamiUitOpen 4:c1beacfc42c7 420 /** \brief Get Process Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 421
MikamiUitOpen 4:c1beacfc42c7 422 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 4:c1beacfc42c7 423
MikamiUitOpen 4:c1beacfc42c7 424 \return PSP Register value
MikamiUitOpen 4:c1beacfc42c7 425 */
MikamiUitOpen 4:c1beacfc42c7 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 4:c1beacfc42c7 427 {
MikamiUitOpen 4:c1beacfc42c7 428 register uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 429
MikamiUitOpen 4:c1beacfc42c7 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 431 return(result);
MikamiUitOpen 4:c1beacfc42c7 432 }
MikamiUitOpen 4:c1beacfc42c7 433
MikamiUitOpen 4:c1beacfc42c7 434
MikamiUitOpen 4:c1beacfc42c7 435 /** \brief Set Process Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 436
MikamiUitOpen 4:c1beacfc42c7 437 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 4:c1beacfc42c7 438
MikamiUitOpen 4:c1beacfc42c7 439 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 440 */
MikamiUitOpen 4:c1beacfc42c7 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 4:c1beacfc42c7 442 {
MikamiUitOpen 4:c1beacfc42c7 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
MikamiUitOpen 4:c1beacfc42c7 444 }
MikamiUitOpen 4:c1beacfc42c7 445
MikamiUitOpen 4:c1beacfc42c7 446
MikamiUitOpen 4:c1beacfc42c7 447 /** \brief Get Main Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 448
MikamiUitOpen 4:c1beacfc42c7 449 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 4:c1beacfc42c7 450
MikamiUitOpen 4:c1beacfc42c7 451 \return MSP Register value
MikamiUitOpen 4:c1beacfc42c7 452 */
MikamiUitOpen 4:c1beacfc42c7 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 4:c1beacfc42c7 454 {
MikamiUitOpen 4:c1beacfc42c7 455 register uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 456
MikamiUitOpen 4:c1beacfc42c7 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 458 return(result);
MikamiUitOpen 4:c1beacfc42c7 459 }
MikamiUitOpen 4:c1beacfc42c7 460
MikamiUitOpen 4:c1beacfc42c7 461
MikamiUitOpen 4:c1beacfc42c7 462 /** \brief Set Main Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 463
MikamiUitOpen 4:c1beacfc42c7 464 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 4:c1beacfc42c7 465
MikamiUitOpen 4:c1beacfc42c7 466 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 467 */
MikamiUitOpen 4:c1beacfc42c7 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 4:c1beacfc42c7 469 {
MikamiUitOpen 4:c1beacfc42c7 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
MikamiUitOpen 4:c1beacfc42c7 471 }
MikamiUitOpen 4:c1beacfc42c7 472
MikamiUitOpen 4:c1beacfc42c7 473
MikamiUitOpen 4:c1beacfc42c7 474 /** \brief Get Priority Mask
MikamiUitOpen 4:c1beacfc42c7 475
MikamiUitOpen 4:c1beacfc42c7 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 4:c1beacfc42c7 477
MikamiUitOpen 4:c1beacfc42c7 478 \return Priority Mask value
MikamiUitOpen 4:c1beacfc42c7 479 */
MikamiUitOpen 4:c1beacfc42c7 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 4:c1beacfc42c7 481 {
MikamiUitOpen 4:c1beacfc42c7 482 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 483
MikamiUitOpen 4:c1beacfc42c7 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 485 return(result);
MikamiUitOpen 4:c1beacfc42c7 486 }
MikamiUitOpen 4:c1beacfc42c7 487
MikamiUitOpen 4:c1beacfc42c7 488
MikamiUitOpen 4:c1beacfc42c7 489 /** \brief Set Priority Mask
MikamiUitOpen 4:c1beacfc42c7 490
MikamiUitOpen 4:c1beacfc42c7 491 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 4:c1beacfc42c7 492
MikamiUitOpen 4:c1beacfc42c7 493 \param [in] priMask Priority Mask
MikamiUitOpen 4:c1beacfc42c7 494 */
MikamiUitOpen 4:c1beacfc42c7 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 4:c1beacfc42c7 496 {
MikamiUitOpen 4:c1beacfc42c7 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
MikamiUitOpen 4:c1beacfc42c7 498 }
MikamiUitOpen 4:c1beacfc42c7 499
MikamiUitOpen 4:c1beacfc42c7 500
MikamiUitOpen 4:c1beacfc42c7 501 #if (__CORTEX_M >= 0x03)
MikamiUitOpen 4:c1beacfc42c7 502
MikamiUitOpen 4:c1beacfc42c7 503 /** \brief Enable FIQ
MikamiUitOpen 4:c1beacfc42c7 504
MikamiUitOpen 4:c1beacfc42c7 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 506 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 507 */
MikamiUitOpen 4:c1beacfc42c7 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
MikamiUitOpen 4:c1beacfc42c7 509 {
MikamiUitOpen 4:c1beacfc42c7 510 __ASM volatile ("cpsie f" : : : "memory");
MikamiUitOpen 4:c1beacfc42c7 511 }
MikamiUitOpen 4:c1beacfc42c7 512
MikamiUitOpen 4:c1beacfc42c7 513
MikamiUitOpen 4:c1beacfc42c7 514 /** \brief Disable FIQ
MikamiUitOpen 4:c1beacfc42c7 515
MikamiUitOpen 4:c1beacfc42c7 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 517 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 518 */
MikamiUitOpen 4:c1beacfc42c7 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
MikamiUitOpen 4:c1beacfc42c7 520 {
MikamiUitOpen 4:c1beacfc42c7 521 __ASM volatile ("cpsid f" : : : "memory");
MikamiUitOpen 4:c1beacfc42c7 522 }
MikamiUitOpen 4:c1beacfc42c7 523
MikamiUitOpen 4:c1beacfc42c7 524
MikamiUitOpen 4:c1beacfc42c7 525 /** \brief Get Base Priority
MikamiUitOpen 4:c1beacfc42c7 526
MikamiUitOpen 4:c1beacfc42c7 527 This function returns the current value of the Base Priority register.
MikamiUitOpen 4:c1beacfc42c7 528
MikamiUitOpen 4:c1beacfc42c7 529 \return Base Priority register value
MikamiUitOpen 4:c1beacfc42c7 530 */
MikamiUitOpen 4:c1beacfc42c7 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 4:c1beacfc42c7 532 {
MikamiUitOpen 4:c1beacfc42c7 533 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 534
MikamiUitOpen 4:c1beacfc42c7 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 536 return(result);
MikamiUitOpen 4:c1beacfc42c7 537 }
MikamiUitOpen 4:c1beacfc42c7 538
MikamiUitOpen 4:c1beacfc42c7 539
MikamiUitOpen 4:c1beacfc42c7 540 /** \brief Set Base Priority
MikamiUitOpen 4:c1beacfc42c7 541
MikamiUitOpen 4:c1beacfc42c7 542 This function assigns the given value to the Base Priority register.
MikamiUitOpen 4:c1beacfc42c7 543
MikamiUitOpen 4:c1beacfc42c7 544 \param [in] basePri Base Priority value to set
MikamiUitOpen 4:c1beacfc42c7 545 */
MikamiUitOpen 4:c1beacfc42c7 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 547 {
MikamiUitOpen 4:c1beacfc42c7 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
MikamiUitOpen 4:c1beacfc42c7 549 }
MikamiUitOpen 4:c1beacfc42c7 550
MikamiUitOpen 4:c1beacfc42c7 551
MikamiUitOpen 4:c1beacfc42c7 552 /** \brief Set Base Priority with condition
MikamiUitOpen 4:c1beacfc42c7 553
MikamiUitOpen 4:c1beacfc42c7 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 4:c1beacfc42c7 555 or the new value increases the BASEPRI priority level.
MikamiUitOpen 4:c1beacfc42c7 556
MikamiUitOpen 4:c1beacfc42c7 557 \param [in] basePri Base Priority value to set
MikamiUitOpen 4:c1beacfc42c7 558 */
MikamiUitOpen 4:c1beacfc42c7 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 560 {
MikamiUitOpen 4:c1beacfc42c7 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
MikamiUitOpen 4:c1beacfc42c7 562 }
MikamiUitOpen 4:c1beacfc42c7 563
MikamiUitOpen 4:c1beacfc42c7 564
MikamiUitOpen 4:c1beacfc42c7 565 /** \brief Get Fault Mask
MikamiUitOpen 4:c1beacfc42c7 566
MikamiUitOpen 4:c1beacfc42c7 567 This function returns the current value of the Fault Mask register.
MikamiUitOpen 4:c1beacfc42c7 568
MikamiUitOpen 4:c1beacfc42c7 569 \return Fault Mask register value
MikamiUitOpen 4:c1beacfc42c7 570 */
MikamiUitOpen 4:c1beacfc42c7 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 4:c1beacfc42c7 572 {
MikamiUitOpen 4:c1beacfc42c7 573 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 574
MikamiUitOpen 4:c1beacfc42c7 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 576 return(result);
MikamiUitOpen 4:c1beacfc42c7 577 }
MikamiUitOpen 4:c1beacfc42c7 578
MikamiUitOpen 4:c1beacfc42c7 579
MikamiUitOpen 4:c1beacfc42c7 580 /** \brief Set Fault Mask
MikamiUitOpen 4:c1beacfc42c7 581
MikamiUitOpen 4:c1beacfc42c7 582 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 4:c1beacfc42c7 583
MikamiUitOpen 4:c1beacfc42c7 584 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 4:c1beacfc42c7 585 */
MikamiUitOpen 4:c1beacfc42c7 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 4:c1beacfc42c7 587 {
MikamiUitOpen 4:c1beacfc42c7 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
MikamiUitOpen 4:c1beacfc42c7 589 }
MikamiUitOpen 4:c1beacfc42c7 590
MikamiUitOpen 4:c1beacfc42c7 591 #endif /* (__CORTEX_M >= 0x03) */
MikamiUitOpen 4:c1beacfc42c7 592
MikamiUitOpen 4:c1beacfc42c7 593
MikamiUitOpen 4:c1beacfc42c7 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 4:c1beacfc42c7 595
MikamiUitOpen 4:c1beacfc42c7 596 /** \brief Get FPSCR
MikamiUitOpen 4:c1beacfc42c7 597
MikamiUitOpen 4:c1beacfc42c7 598 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 599
MikamiUitOpen 4:c1beacfc42c7 600 \return Floating Point Status/Control register value
MikamiUitOpen 4:c1beacfc42c7 601 */
MikamiUitOpen 4:c1beacfc42c7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 4:c1beacfc42c7 603 {
MikamiUitOpen 4:c1beacfc42c7 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 605 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 606
MikamiUitOpen 4:c1beacfc42c7 607 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 4:c1beacfc42c7 608 __ASM volatile ("");
MikamiUitOpen 4:c1beacfc42c7 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 610 __ASM volatile ("");
MikamiUitOpen 4:c1beacfc42c7 611 return(result);
MikamiUitOpen 4:c1beacfc42c7 612 #else
MikamiUitOpen 4:c1beacfc42c7 613 return(0);
MikamiUitOpen 4:c1beacfc42c7 614 #endif
MikamiUitOpen 4:c1beacfc42c7 615 }
MikamiUitOpen 4:c1beacfc42c7 616
MikamiUitOpen 4:c1beacfc42c7 617
MikamiUitOpen 4:c1beacfc42c7 618 /** \brief Set FPSCR
MikamiUitOpen 4:c1beacfc42c7 619
MikamiUitOpen 4:c1beacfc42c7 620 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 621
MikamiUitOpen 4:c1beacfc42c7 622 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 4:c1beacfc42c7 623 */
MikamiUitOpen 4:c1beacfc42c7 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 4:c1beacfc42c7 625 {
MikamiUitOpen 4:c1beacfc42c7 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 627 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 4:c1beacfc42c7 628 __ASM volatile ("");
MikamiUitOpen 4:c1beacfc42c7 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
MikamiUitOpen 4:c1beacfc42c7 630 __ASM volatile ("");
MikamiUitOpen 4:c1beacfc42c7 631 #endif
MikamiUitOpen 4:c1beacfc42c7 632 }
MikamiUitOpen 4:c1beacfc42c7 633
MikamiUitOpen 4:c1beacfc42c7 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 4:c1beacfc42c7 635
MikamiUitOpen 4:c1beacfc42c7 636
MikamiUitOpen 4:c1beacfc42c7 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 4:c1beacfc42c7 638 /* IAR iccarm specific functions */
MikamiUitOpen 4:c1beacfc42c7 639 #include <cmsis_iar.h>
MikamiUitOpen 4:c1beacfc42c7 640
MikamiUitOpen 4:c1beacfc42c7 641
MikamiUitOpen 4:c1beacfc42c7 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 4:c1beacfc42c7 643 /* TI CCS specific functions */
MikamiUitOpen 4:c1beacfc42c7 644 #include <cmsis_ccs.h>
MikamiUitOpen 4:c1beacfc42c7 645
MikamiUitOpen 4:c1beacfc42c7 646
MikamiUitOpen 4:c1beacfc42c7 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 4:c1beacfc42c7 648 /* TASKING carm specific functions */
MikamiUitOpen 4:c1beacfc42c7 649 /*
MikamiUitOpen 4:c1beacfc42c7 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
MikamiUitOpen 4:c1beacfc42c7 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
MikamiUitOpen 4:c1beacfc42c7 652 * Including the CMSIS ones.
MikamiUitOpen 4:c1beacfc42c7 653 */
MikamiUitOpen 4:c1beacfc42c7 654
MikamiUitOpen 4:c1beacfc42c7 655
MikamiUitOpen 4:c1beacfc42c7 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 4:c1beacfc42c7 657 /* Cosmic specific functions */
MikamiUitOpen 4:c1beacfc42c7 658 #include <cmsis_csm.h>
MikamiUitOpen 4:c1beacfc42c7 659
MikamiUitOpen 4:c1beacfc42c7 660 #endif
MikamiUitOpen 4:c1beacfc42c7 661
MikamiUitOpen 4:c1beacfc42c7 662 /*@} end of CMSIS_Core_RegAccFunctions */
MikamiUitOpen 4:c1beacfc42c7 663
MikamiUitOpen 4:c1beacfc42c7 664 #endif /* __CORE_CMFUNC_H */