不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_cm4_simd.h@6:b3885567877c, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7 
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_cm4_simd.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS Cortex-M4 SIMD Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version V3.20
MikamiUitOpen 4:c1beacfc42c7 5 * @date 25. February 2013
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 39 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 40 #endif
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 #ifndef __CORE_CM4_SIMD_H
MikamiUitOpen 4:c1beacfc42c7 43 #define __CORE_CM4_SIMD_H
MikamiUitOpen 4:c1beacfc42c7 44
MikamiUitOpen 4:c1beacfc42c7 45
MikamiUitOpen 4:c1beacfc42c7 46 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 47 * Hardware Abstraction Layer
MikamiUitOpen 4:c1beacfc42c7 48 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 49
MikamiUitOpen 4:c1beacfc42c7 50
MikamiUitOpen 4:c1beacfc42c7 51 /* ################### Compiler specific Intrinsics ########################### */
MikamiUitOpen 4:c1beacfc42c7 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
MikamiUitOpen 4:c1beacfc42c7 53 Access to dedicated SIMD instructions
MikamiUitOpen 4:c1beacfc42c7 54 @{
MikamiUitOpen 4:c1beacfc42c7 55 */
MikamiUitOpen 4:c1beacfc42c7 56
MikamiUitOpen 4:c1beacfc42c7 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 4:c1beacfc42c7 58 /* ARM armcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 59
MikamiUitOpen 4:c1beacfc42c7 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 61 #define __SADD8 __sadd8
MikamiUitOpen 4:c1beacfc42c7 62 #define __QADD8 __qadd8
MikamiUitOpen 4:c1beacfc42c7 63 #define __SHADD8 __shadd8
MikamiUitOpen 4:c1beacfc42c7 64 #define __UADD8 __uadd8
MikamiUitOpen 4:c1beacfc42c7 65 #define __UQADD8 __uqadd8
MikamiUitOpen 4:c1beacfc42c7 66 #define __UHADD8 __uhadd8
MikamiUitOpen 4:c1beacfc42c7 67 #define __SSUB8 __ssub8
MikamiUitOpen 4:c1beacfc42c7 68 #define __QSUB8 __qsub8
MikamiUitOpen 4:c1beacfc42c7 69 #define __SHSUB8 __shsub8
MikamiUitOpen 4:c1beacfc42c7 70 #define __USUB8 __usub8
MikamiUitOpen 4:c1beacfc42c7 71 #define __UQSUB8 __uqsub8
MikamiUitOpen 4:c1beacfc42c7 72 #define __UHSUB8 __uhsub8
MikamiUitOpen 4:c1beacfc42c7 73 #define __SADD16 __sadd16
MikamiUitOpen 4:c1beacfc42c7 74 #define __QADD16 __qadd16
MikamiUitOpen 4:c1beacfc42c7 75 #define __SHADD16 __shadd16
MikamiUitOpen 4:c1beacfc42c7 76 #define __UADD16 __uadd16
MikamiUitOpen 4:c1beacfc42c7 77 #define __UQADD16 __uqadd16
MikamiUitOpen 4:c1beacfc42c7 78 #define __UHADD16 __uhadd16
MikamiUitOpen 4:c1beacfc42c7 79 #define __SSUB16 __ssub16
MikamiUitOpen 4:c1beacfc42c7 80 #define __QSUB16 __qsub16
MikamiUitOpen 4:c1beacfc42c7 81 #define __SHSUB16 __shsub16
MikamiUitOpen 4:c1beacfc42c7 82 #define __USUB16 __usub16
MikamiUitOpen 4:c1beacfc42c7 83 #define __UQSUB16 __uqsub16
MikamiUitOpen 4:c1beacfc42c7 84 #define __UHSUB16 __uhsub16
MikamiUitOpen 4:c1beacfc42c7 85 #define __SASX __sasx
MikamiUitOpen 4:c1beacfc42c7 86 #define __QASX __qasx
MikamiUitOpen 4:c1beacfc42c7 87 #define __SHASX __shasx
MikamiUitOpen 4:c1beacfc42c7 88 #define __UASX __uasx
MikamiUitOpen 4:c1beacfc42c7 89 #define __UQASX __uqasx
MikamiUitOpen 4:c1beacfc42c7 90 #define __UHASX __uhasx
MikamiUitOpen 4:c1beacfc42c7 91 #define __SSAX __ssax
MikamiUitOpen 4:c1beacfc42c7 92 #define __QSAX __qsax
MikamiUitOpen 4:c1beacfc42c7 93 #define __SHSAX __shsax
MikamiUitOpen 4:c1beacfc42c7 94 #define __USAX __usax
MikamiUitOpen 4:c1beacfc42c7 95 #define __UQSAX __uqsax
MikamiUitOpen 4:c1beacfc42c7 96 #define __UHSAX __uhsax
MikamiUitOpen 4:c1beacfc42c7 97 #define __USAD8 __usad8
MikamiUitOpen 4:c1beacfc42c7 98 #define __USADA8 __usada8
MikamiUitOpen 4:c1beacfc42c7 99 #define __SSAT16 __ssat16
MikamiUitOpen 4:c1beacfc42c7 100 #define __USAT16 __usat16
MikamiUitOpen 4:c1beacfc42c7 101 #define __UXTB16 __uxtb16
MikamiUitOpen 4:c1beacfc42c7 102 #define __UXTAB16 __uxtab16
MikamiUitOpen 4:c1beacfc42c7 103 #define __SXTB16 __sxtb16
MikamiUitOpen 4:c1beacfc42c7 104 #define __SXTAB16 __sxtab16
MikamiUitOpen 4:c1beacfc42c7 105 #define __SMUAD __smuad
MikamiUitOpen 4:c1beacfc42c7 106 #define __SMUADX __smuadx
MikamiUitOpen 4:c1beacfc42c7 107 #define __SMLAD __smlad
MikamiUitOpen 4:c1beacfc42c7 108 #define __SMLADX __smladx
MikamiUitOpen 4:c1beacfc42c7 109 #define __SMLALD __smlald
MikamiUitOpen 4:c1beacfc42c7 110 #define __SMLALDX __smlaldx
MikamiUitOpen 4:c1beacfc42c7 111 #define __SMUSD __smusd
MikamiUitOpen 4:c1beacfc42c7 112 #define __SMUSDX __smusdx
MikamiUitOpen 4:c1beacfc42c7 113 #define __SMLSD __smlsd
MikamiUitOpen 4:c1beacfc42c7 114 #define __SMLSDX __smlsdx
MikamiUitOpen 4:c1beacfc42c7 115 #define __SMLSLD __smlsld
MikamiUitOpen 4:c1beacfc42c7 116 #define __SMLSLDX __smlsldx
MikamiUitOpen 4:c1beacfc42c7 117 #define __SEL __sel
MikamiUitOpen 4:c1beacfc42c7 118 #define __QADD __qadd
MikamiUitOpen 4:c1beacfc42c7 119 #define __QSUB __qsub
MikamiUitOpen 4:c1beacfc42c7 120
MikamiUitOpen 4:c1beacfc42c7 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
MikamiUitOpen 4:c1beacfc42c7 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
MikamiUitOpen 4:c1beacfc42c7 123
MikamiUitOpen 4:c1beacfc42c7 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
MikamiUitOpen 4:c1beacfc42c7 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
MikamiUitOpen 4:c1beacfc42c7 126
MikamiUitOpen 4:c1beacfc42c7 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
MikamiUitOpen 4:c1beacfc42c7 128 ((int64_t)(ARG3) << 32) ) >> 32))
MikamiUitOpen 4:c1beacfc42c7 129
MikamiUitOpen 4:c1beacfc42c7 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 131
MikamiUitOpen 4:c1beacfc42c7 132
MikamiUitOpen 4:c1beacfc42c7 133
MikamiUitOpen 4:c1beacfc42c7 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 4:c1beacfc42c7 135 /* IAR iccarm specific functions */
MikamiUitOpen 4:c1beacfc42c7 136
MikamiUitOpen 4:c1beacfc42c7 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 138 #include <cmsis_iar.h>
MikamiUitOpen 4:c1beacfc42c7 139
MikamiUitOpen 4:c1beacfc42c7 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 141
MikamiUitOpen 4:c1beacfc42c7 142
MikamiUitOpen 4:c1beacfc42c7 143
MikamiUitOpen 4:c1beacfc42c7 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 4:c1beacfc42c7 145 /* TI CCS specific functions */
MikamiUitOpen 4:c1beacfc42c7 146
MikamiUitOpen 4:c1beacfc42c7 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 148 #include <cmsis_ccs.h>
MikamiUitOpen 4:c1beacfc42c7 149
MikamiUitOpen 4:c1beacfc42c7 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 151
MikamiUitOpen 4:c1beacfc42c7 152
MikamiUitOpen 4:c1beacfc42c7 153
MikamiUitOpen 4:c1beacfc42c7 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 4:c1beacfc42c7 155 /* GNU gcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 156
MikamiUitOpen 4:c1beacfc42c7 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 159 {
MikamiUitOpen 4:c1beacfc42c7 160 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 161
MikamiUitOpen 4:c1beacfc42c7 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 163 return(result);
MikamiUitOpen 4:c1beacfc42c7 164 }
MikamiUitOpen 4:c1beacfc42c7 165
MikamiUitOpen 4:c1beacfc42c7 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 167 {
MikamiUitOpen 4:c1beacfc42c7 168 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 169
MikamiUitOpen 4:c1beacfc42c7 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 171 return(result);
MikamiUitOpen 4:c1beacfc42c7 172 }
MikamiUitOpen 4:c1beacfc42c7 173
MikamiUitOpen 4:c1beacfc42c7 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 175 {
MikamiUitOpen 4:c1beacfc42c7 176 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 177
MikamiUitOpen 4:c1beacfc42c7 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 179 return(result);
MikamiUitOpen 4:c1beacfc42c7 180 }
MikamiUitOpen 4:c1beacfc42c7 181
MikamiUitOpen 4:c1beacfc42c7 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 183 {
MikamiUitOpen 4:c1beacfc42c7 184 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 185
MikamiUitOpen 4:c1beacfc42c7 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 187 return(result);
MikamiUitOpen 4:c1beacfc42c7 188 }
MikamiUitOpen 4:c1beacfc42c7 189
MikamiUitOpen 4:c1beacfc42c7 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 191 {
MikamiUitOpen 4:c1beacfc42c7 192 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 193
MikamiUitOpen 4:c1beacfc42c7 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 195 return(result);
MikamiUitOpen 4:c1beacfc42c7 196 }
MikamiUitOpen 4:c1beacfc42c7 197
MikamiUitOpen 4:c1beacfc42c7 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 199 {
MikamiUitOpen 4:c1beacfc42c7 200 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 201
MikamiUitOpen 4:c1beacfc42c7 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 203 return(result);
MikamiUitOpen 4:c1beacfc42c7 204 }
MikamiUitOpen 4:c1beacfc42c7 205
MikamiUitOpen 4:c1beacfc42c7 206
MikamiUitOpen 4:c1beacfc42c7 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 208 {
MikamiUitOpen 4:c1beacfc42c7 209 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 210
MikamiUitOpen 4:c1beacfc42c7 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 212 return(result);
MikamiUitOpen 4:c1beacfc42c7 213 }
MikamiUitOpen 4:c1beacfc42c7 214
MikamiUitOpen 4:c1beacfc42c7 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 216 {
MikamiUitOpen 4:c1beacfc42c7 217 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 218
MikamiUitOpen 4:c1beacfc42c7 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 220 return(result);
MikamiUitOpen 4:c1beacfc42c7 221 }
MikamiUitOpen 4:c1beacfc42c7 222
MikamiUitOpen 4:c1beacfc42c7 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 224 {
MikamiUitOpen 4:c1beacfc42c7 225 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 226
MikamiUitOpen 4:c1beacfc42c7 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 228 return(result);
MikamiUitOpen 4:c1beacfc42c7 229 }
MikamiUitOpen 4:c1beacfc42c7 230
MikamiUitOpen 4:c1beacfc42c7 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 232 {
MikamiUitOpen 4:c1beacfc42c7 233 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 234
MikamiUitOpen 4:c1beacfc42c7 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 236 return(result);
MikamiUitOpen 4:c1beacfc42c7 237 }
MikamiUitOpen 4:c1beacfc42c7 238
MikamiUitOpen 4:c1beacfc42c7 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 240 {
MikamiUitOpen 4:c1beacfc42c7 241 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 242
MikamiUitOpen 4:c1beacfc42c7 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 244 return(result);
MikamiUitOpen 4:c1beacfc42c7 245 }
MikamiUitOpen 4:c1beacfc42c7 246
MikamiUitOpen 4:c1beacfc42c7 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 248 {
MikamiUitOpen 4:c1beacfc42c7 249 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 250
MikamiUitOpen 4:c1beacfc42c7 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 252 return(result);
MikamiUitOpen 4:c1beacfc42c7 253 }
MikamiUitOpen 4:c1beacfc42c7 254
MikamiUitOpen 4:c1beacfc42c7 255
MikamiUitOpen 4:c1beacfc42c7 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 257 {
MikamiUitOpen 4:c1beacfc42c7 258 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 259
MikamiUitOpen 4:c1beacfc42c7 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 261 return(result);
MikamiUitOpen 4:c1beacfc42c7 262 }
MikamiUitOpen 4:c1beacfc42c7 263
MikamiUitOpen 4:c1beacfc42c7 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 265 {
MikamiUitOpen 4:c1beacfc42c7 266 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 267
MikamiUitOpen 4:c1beacfc42c7 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 269 return(result);
MikamiUitOpen 4:c1beacfc42c7 270 }
MikamiUitOpen 4:c1beacfc42c7 271
MikamiUitOpen 4:c1beacfc42c7 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 273 {
MikamiUitOpen 4:c1beacfc42c7 274 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 275
MikamiUitOpen 4:c1beacfc42c7 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 277 return(result);
MikamiUitOpen 4:c1beacfc42c7 278 }
MikamiUitOpen 4:c1beacfc42c7 279
MikamiUitOpen 4:c1beacfc42c7 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 281 {
MikamiUitOpen 4:c1beacfc42c7 282 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 283
MikamiUitOpen 4:c1beacfc42c7 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 285 return(result);
MikamiUitOpen 4:c1beacfc42c7 286 }
MikamiUitOpen 4:c1beacfc42c7 287
MikamiUitOpen 4:c1beacfc42c7 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 289 {
MikamiUitOpen 4:c1beacfc42c7 290 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 291
MikamiUitOpen 4:c1beacfc42c7 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 293 return(result);
MikamiUitOpen 4:c1beacfc42c7 294 }
MikamiUitOpen 4:c1beacfc42c7 295
MikamiUitOpen 4:c1beacfc42c7 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 297 {
MikamiUitOpen 4:c1beacfc42c7 298 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 299
MikamiUitOpen 4:c1beacfc42c7 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 301 return(result);
MikamiUitOpen 4:c1beacfc42c7 302 }
MikamiUitOpen 4:c1beacfc42c7 303
MikamiUitOpen 4:c1beacfc42c7 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 305 {
MikamiUitOpen 4:c1beacfc42c7 306 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 307
MikamiUitOpen 4:c1beacfc42c7 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 309 return(result);
MikamiUitOpen 4:c1beacfc42c7 310 }
MikamiUitOpen 4:c1beacfc42c7 311
MikamiUitOpen 4:c1beacfc42c7 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 313 {
MikamiUitOpen 4:c1beacfc42c7 314 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 315
MikamiUitOpen 4:c1beacfc42c7 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 317 return(result);
MikamiUitOpen 4:c1beacfc42c7 318 }
MikamiUitOpen 4:c1beacfc42c7 319
MikamiUitOpen 4:c1beacfc42c7 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 321 {
MikamiUitOpen 4:c1beacfc42c7 322 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 323
MikamiUitOpen 4:c1beacfc42c7 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 325 return(result);
MikamiUitOpen 4:c1beacfc42c7 326 }
MikamiUitOpen 4:c1beacfc42c7 327
MikamiUitOpen 4:c1beacfc42c7 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 329 {
MikamiUitOpen 4:c1beacfc42c7 330 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 331
MikamiUitOpen 4:c1beacfc42c7 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 333 return(result);
MikamiUitOpen 4:c1beacfc42c7 334 }
MikamiUitOpen 4:c1beacfc42c7 335
MikamiUitOpen 4:c1beacfc42c7 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 337 {
MikamiUitOpen 4:c1beacfc42c7 338 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 339
MikamiUitOpen 4:c1beacfc42c7 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 341 return(result);
MikamiUitOpen 4:c1beacfc42c7 342 }
MikamiUitOpen 4:c1beacfc42c7 343
MikamiUitOpen 4:c1beacfc42c7 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 345 {
MikamiUitOpen 4:c1beacfc42c7 346 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 347
MikamiUitOpen 4:c1beacfc42c7 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 349 return(result);
MikamiUitOpen 4:c1beacfc42c7 350 }
MikamiUitOpen 4:c1beacfc42c7 351
MikamiUitOpen 4:c1beacfc42c7 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 353 {
MikamiUitOpen 4:c1beacfc42c7 354 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 355
MikamiUitOpen 4:c1beacfc42c7 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 357 return(result);
MikamiUitOpen 4:c1beacfc42c7 358 }
MikamiUitOpen 4:c1beacfc42c7 359
MikamiUitOpen 4:c1beacfc42c7 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 361 {
MikamiUitOpen 4:c1beacfc42c7 362 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 363
MikamiUitOpen 4:c1beacfc42c7 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 365 return(result);
MikamiUitOpen 4:c1beacfc42c7 366 }
MikamiUitOpen 4:c1beacfc42c7 367
MikamiUitOpen 4:c1beacfc42c7 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 369 {
MikamiUitOpen 4:c1beacfc42c7 370 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 371
MikamiUitOpen 4:c1beacfc42c7 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 373 return(result);
MikamiUitOpen 4:c1beacfc42c7 374 }
MikamiUitOpen 4:c1beacfc42c7 375
MikamiUitOpen 4:c1beacfc42c7 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 377 {
MikamiUitOpen 4:c1beacfc42c7 378 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 379
MikamiUitOpen 4:c1beacfc42c7 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 381 return(result);
MikamiUitOpen 4:c1beacfc42c7 382 }
MikamiUitOpen 4:c1beacfc42c7 383
MikamiUitOpen 4:c1beacfc42c7 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 385 {
MikamiUitOpen 4:c1beacfc42c7 386 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 387
MikamiUitOpen 4:c1beacfc42c7 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 389 return(result);
MikamiUitOpen 4:c1beacfc42c7 390 }
MikamiUitOpen 4:c1beacfc42c7 391
MikamiUitOpen 4:c1beacfc42c7 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 393 {
MikamiUitOpen 4:c1beacfc42c7 394 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 395
MikamiUitOpen 4:c1beacfc42c7 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 397 return(result);
MikamiUitOpen 4:c1beacfc42c7 398 }
MikamiUitOpen 4:c1beacfc42c7 399
MikamiUitOpen 4:c1beacfc42c7 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 401 {
MikamiUitOpen 4:c1beacfc42c7 402 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 403
MikamiUitOpen 4:c1beacfc42c7 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 405 return(result);
MikamiUitOpen 4:c1beacfc42c7 406 }
MikamiUitOpen 4:c1beacfc42c7 407
MikamiUitOpen 4:c1beacfc42c7 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 409 {
MikamiUitOpen 4:c1beacfc42c7 410 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 411
MikamiUitOpen 4:c1beacfc42c7 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 413 return(result);
MikamiUitOpen 4:c1beacfc42c7 414 }
MikamiUitOpen 4:c1beacfc42c7 415
MikamiUitOpen 4:c1beacfc42c7 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 417 {
MikamiUitOpen 4:c1beacfc42c7 418 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 419
MikamiUitOpen 4:c1beacfc42c7 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 421 return(result);
MikamiUitOpen 4:c1beacfc42c7 422 }
MikamiUitOpen 4:c1beacfc42c7 423
MikamiUitOpen 4:c1beacfc42c7 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 425 {
MikamiUitOpen 4:c1beacfc42c7 426 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 427
MikamiUitOpen 4:c1beacfc42c7 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 429 return(result);
MikamiUitOpen 4:c1beacfc42c7 430 }
MikamiUitOpen 4:c1beacfc42c7 431
MikamiUitOpen 4:c1beacfc42c7 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 433 {
MikamiUitOpen 4:c1beacfc42c7 434 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 435
MikamiUitOpen 4:c1beacfc42c7 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 437 return(result);
MikamiUitOpen 4:c1beacfc42c7 438 }
MikamiUitOpen 4:c1beacfc42c7 439
MikamiUitOpen 4:c1beacfc42c7 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 441 {
MikamiUitOpen 4:c1beacfc42c7 442 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 443
MikamiUitOpen 4:c1beacfc42c7 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 445 return(result);
MikamiUitOpen 4:c1beacfc42c7 446 }
MikamiUitOpen 4:c1beacfc42c7 447
MikamiUitOpen 4:c1beacfc42c7 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 449 {
MikamiUitOpen 4:c1beacfc42c7 450 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 451
MikamiUitOpen 4:c1beacfc42c7 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 453 return(result);
MikamiUitOpen 4:c1beacfc42c7 454 }
MikamiUitOpen 4:c1beacfc42c7 455
MikamiUitOpen 4:c1beacfc42c7 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 457 {
MikamiUitOpen 4:c1beacfc42c7 458 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 459
MikamiUitOpen 4:c1beacfc42c7 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 461 return(result);
MikamiUitOpen 4:c1beacfc42c7 462 }
MikamiUitOpen 4:c1beacfc42c7 463
MikamiUitOpen 4:c1beacfc42c7 464 #define __SSAT16(ARG1,ARG2) \
MikamiUitOpen 4:c1beacfc42c7 465 ({ \
MikamiUitOpen 4:c1beacfc42c7 466 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 4:c1beacfc42c7 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 4:c1beacfc42c7 468 __RES; \
MikamiUitOpen 4:c1beacfc42c7 469 })
MikamiUitOpen 4:c1beacfc42c7 470
MikamiUitOpen 4:c1beacfc42c7 471 #define __USAT16(ARG1,ARG2) \
MikamiUitOpen 4:c1beacfc42c7 472 ({ \
MikamiUitOpen 4:c1beacfc42c7 473 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 4:c1beacfc42c7 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 4:c1beacfc42c7 475 __RES; \
MikamiUitOpen 4:c1beacfc42c7 476 })
MikamiUitOpen 4:c1beacfc42c7 477
MikamiUitOpen 4:c1beacfc42c7 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
MikamiUitOpen 4:c1beacfc42c7 479 {
MikamiUitOpen 4:c1beacfc42c7 480 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 481
MikamiUitOpen 4:c1beacfc42c7 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 4:c1beacfc42c7 483 return(result);
MikamiUitOpen 4:c1beacfc42c7 484 }
MikamiUitOpen 4:c1beacfc42c7 485
MikamiUitOpen 4:c1beacfc42c7 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 487 {
MikamiUitOpen 4:c1beacfc42c7 488 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 489
MikamiUitOpen 4:c1beacfc42c7 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 491 return(result);
MikamiUitOpen 4:c1beacfc42c7 492 }
MikamiUitOpen 4:c1beacfc42c7 493
MikamiUitOpen 4:c1beacfc42c7 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
MikamiUitOpen 4:c1beacfc42c7 495 {
MikamiUitOpen 4:c1beacfc42c7 496 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 497
MikamiUitOpen 4:c1beacfc42c7 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 4:c1beacfc42c7 499 return(result);
MikamiUitOpen 4:c1beacfc42c7 500 }
MikamiUitOpen 4:c1beacfc42c7 501
MikamiUitOpen 4:c1beacfc42c7 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 503 {
MikamiUitOpen 4:c1beacfc42c7 504 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 505
MikamiUitOpen 4:c1beacfc42c7 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 507 return(result);
MikamiUitOpen 4:c1beacfc42c7 508 }
MikamiUitOpen 4:c1beacfc42c7 509
MikamiUitOpen 4:c1beacfc42c7 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 511 {
MikamiUitOpen 4:c1beacfc42c7 512 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 513
MikamiUitOpen 4:c1beacfc42c7 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 515 return(result);
MikamiUitOpen 4:c1beacfc42c7 516 }
MikamiUitOpen 4:c1beacfc42c7 517
MikamiUitOpen 4:c1beacfc42c7 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 519 {
MikamiUitOpen 4:c1beacfc42c7 520 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 521
MikamiUitOpen 4:c1beacfc42c7 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 523 return(result);
MikamiUitOpen 4:c1beacfc42c7 524 }
MikamiUitOpen 4:c1beacfc42c7 525
MikamiUitOpen 4:c1beacfc42c7 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 527 {
MikamiUitOpen 4:c1beacfc42c7 528 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 529
MikamiUitOpen 4:c1beacfc42c7 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 531 return(result);
MikamiUitOpen 4:c1beacfc42c7 532 }
MikamiUitOpen 4:c1beacfc42c7 533
MikamiUitOpen 4:c1beacfc42c7 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 535 {
MikamiUitOpen 4:c1beacfc42c7 536 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 537
MikamiUitOpen 4:c1beacfc42c7 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 539 return(result);
MikamiUitOpen 4:c1beacfc42c7 540 }
MikamiUitOpen 4:c1beacfc42c7 541
MikamiUitOpen 4:c1beacfc42c7 542 #define __SMLALD(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 543 ({ \
MikamiUitOpen 4:c1beacfc42c7 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 4:c1beacfc42c7 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 4:c1beacfc42c7 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 4:c1beacfc42c7 547 })
MikamiUitOpen 4:c1beacfc42c7 548
MikamiUitOpen 4:c1beacfc42c7 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 550 ({ \
MikamiUitOpen 4:c1beacfc42c7 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 4:c1beacfc42c7 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 4:c1beacfc42c7 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 4:c1beacfc42c7 554 })
MikamiUitOpen 4:c1beacfc42c7 555
MikamiUitOpen 4:c1beacfc42c7 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 557 {
MikamiUitOpen 4:c1beacfc42c7 558 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 559
MikamiUitOpen 4:c1beacfc42c7 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 561 return(result);
MikamiUitOpen 4:c1beacfc42c7 562 }
MikamiUitOpen 4:c1beacfc42c7 563
MikamiUitOpen 4:c1beacfc42c7 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 565 {
MikamiUitOpen 4:c1beacfc42c7 566 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 567
MikamiUitOpen 4:c1beacfc42c7 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 569 return(result);
MikamiUitOpen 4:c1beacfc42c7 570 }
MikamiUitOpen 4:c1beacfc42c7 571
MikamiUitOpen 4:c1beacfc42c7 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 573 {
MikamiUitOpen 4:c1beacfc42c7 574 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 575
MikamiUitOpen 4:c1beacfc42c7 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 577 return(result);
MikamiUitOpen 4:c1beacfc42c7 578 }
MikamiUitOpen 4:c1beacfc42c7 579
MikamiUitOpen 4:c1beacfc42c7 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 581 {
MikamiUitOpen 4:c1beacfc42c7 582 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 583
MikamiUitOpen 4:c1beacfc42c7 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 585 return(result);
MikamiUitOpen 4:c1beacfc42c7 586 }
MikamiUitOpen 4:c1beacfc42c7 587
MikamiUitOpen 4:c1beacfc42c7 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 589 ({ \
MikamiUitOpen 4:c1beacfc42c7 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 4:c1beacfc42c7 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 4:c1beacfc42c7 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 4:c1beacfc42c7 593 })
MikamiUitOpen 4:c1beacfc42c7 594
MikamiUitOpen 4:c1beacfc42c7 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 596 ({ \
MikamiUitOpen 4:c1beacfc42c7 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 4:c1beacfc42c7 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 4:c1beacfc42c7 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 4:c1beacfc42c7 600 })
MikamiUitOpen 4:c1beacfc42c7 601
MikamiUitOpen 4:c1beacfc42c7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 603 {
MikamiUitOpen 4:c1beacfc42c7 604 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 605
MikamiUitOpen 4:c1beacfc42c7 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 607 return(result);
MikamiUitOpen 4:c1beacfc42c7 608 }
MikamiUitOpen 4:c1beacfc42c7 609
MikamiUitOpen 4:c1beacfc42c7 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 611 {
MikamiUitOpen 4:c1beacfc42c7 612 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 613
MikamiUitOpen 4:c1beacfc42c7 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 615 return(result);
MikamiUitOpen 4:c1beacfc42c7 616 }
MikamiUitOpen 4:c1beacfc42c7 617
MikamiUitOpen 4:c1beacfc42c7 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 619 {
MikamiUitOpen 4:c1beacfc42c7 620 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 621
MikamiUitOpen 4:c1beacfc42c7 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 623 return(result);
MikamiUitOpen 4:c1beacfc42c7 624 }
MikamiUitOpen 4:c1beacfc42c7 625
MikamiUitOpen 4:c1beacfc42c7 626 #define __PKHBT(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 627 ({ \
MikamiUitOpen 4:c1beacfc42c7 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 4:c1beacfc42c7 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 4:c1beacfc42c7 630 __RES; \
MikamiUitOpen 4:c1beacfc42c7 631 })
MikamiUitOpen 4:c1beacfc42c7 632
MikamiUitOpen 4:c1beacfc42c7 633 #define __PKHTB(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 634 ({ \
MikamiUitOpen 4:c1beacfc42c7 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 4:c1beacfc42c7 636 if (ARG3 == 0) \
MikamiUitOpen 4:c1beacfc42c7 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
MikamiUitOpen 4:c1beacfc42c7 638 else \
MikamiUitOpen 4:c1beacfc42c7 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 4:c1beacfc42c7 640 __RES; \
MikamiUitOpen 4:c1beacfc42c7 641 })
MikamiUitOpen 4:c1beacfc42c7 642
MikamiUitOpen 4:c1beacfc42c7 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
MikamiUitOpen 4:c1beacfc42c7 644 {
MikamiUitOpen 4:c1beacfc42c7 645 int32_t result;
MikamiUitOpen 4:c1beacfc42c7 646
MikamiUitOpen 4:c1beacfc42c7 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 648 return(result);
MikamiUitOpen 4:c1beacfc42c7 649 }
MikamiUitOpen 4:c1beacfc42c7 650
MikamiUitOpen 4:c1beacfc42c7 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 652
MikamiUitOpen 4:c1beacfc42c7 653
MikamiUitOpen 4:c1beacfc42c7 654
MikamiUitOpen 4:c1beacfc42c7 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 4:c1beacfc42c7 656 /* TASKING carm specific functions */
MikamiUitOpen 4:c1beacfc42c7 657
MikamiUitOpen 4:c1beacfc42c7 658
MikamiUitOpen 4:c1beacfc42c7 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 660 /* not yet supported */
MikamiUitOpen 4:c1beacfc42c7 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 662
MikamiUitOpen 4:c1beacfc42c7 663
MikamiUitOpen 4:c1beacfc42c7 664 #endif
MikamiUitOpen 4:c1beacfc42c7 665
MikamiUitOpen 4:c1beacfc42c7 666 /*@} end of group CMSIS_SIMD_intrinsics */
MikamiUitOpen 4:c1beacfc42c7 667
MikamiUitOpen 4:c1beacfc42c7 668
MikamiUitOpen 4:c1beacfc42c7 669 #endif /* __CORE_CM4_SIMD_H */
MikamiUitOpen 4:c1beacfc42c7 670
MikamiUitOpen 4:c1beacfc42c7 671 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 672 }
MikamiUitOpen 4:c1beacfc42c7 673 #endif