F746_Spectrogram - Realtime spectrogram for DISCO-F746NG. On-board M…

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Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies: F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_cm4.h@6:b3885567877c, 2017-04-10 (annotated)

Committer:: MikamiUitOpen
Date:: Mon Apr 10 13:43:07 2017 +0000
Revision:: 6:b3885567877c
Parent:: 4:c1beacfc42c7

Who changed what in which revision?

User	Revision	Line number	New contents of line
MikamiUitOpen	4:c1beacfc42c7	1	/************************************************************************//
MikamiUitOpen	4:c1beacfc42c7	2	* @file core_cm4.h
MikamiUitOpen	4:c1beacfc42c7	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
MikamiUitOpen	4:c1beacfc42c7	4	* @version V4.10
MikamiUitOpen	4:c1beacfc42c7	5	* @date 18. March 2015
MikamiUitOpen	4:c1beacfc42c7	6	*
MikamiUitOpen	4:c1beacfc42c7	7	* @note
MikamiUitOpen	4:c1beacfc42c7	8	*
MikamiUitOpen	4:c1beacfc42c7	9	******************************************************************************/
MikamiUitOpen	4:c1beacfc42c7	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen	4:c1beacfc42c7	11
MikamiUitOpen	4:c1beacfc42c7	12	All rights reserved.
MikamiUitOpen	4:c1beacfc42c7	13	Redistribution and use in source and binary forms, with or without
MikamiUitOpen	4:c1beacfc42c7	14	modification, are permitted provided that the following conditions are met:
MikamiUitOpen	4:c1beacfc42c7	15	- Redistributions of source code must retain the above copyright
MikamiUitOpen	4:c1beacfc42c7	16	notice, this list of conditions and the following disclaimer.
MikamiUitOpen	4:c1beacfc42c7	17	- Redistributions in binary form must reproduce the above copyright
MikamiUitOpen	4:c1beacfc42c7	18	notice, this list of conditions and the following disclaimer in the
MikamiUitOpen	4:c1beacfc42c7	19	documentation and/or other materials provided with the distribution.
MikamiUitOpen	4:c1beacfc42c7	20	- Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen	4:c1beacfc42c7	21	to endorse or promote products derived from this software without
MikamiUitOpen	4:c1beacfc42c7	22	specific prior written permission.
MikamiUitOpen	4:c1beacfc42c7	23	*
MikamiUitOpen	4:c1beacfc42c7	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen	4:c1beacfc42c7	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen	4:c1beacfc42c7	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen	4:c1beacfc42c7	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen	4:c1beacfc42c7	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen	4:c1beacfc42c7	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen	4:c1beacfc42c7	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen	4:c1beacfc42c7	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen	4:c1beacfc42c7	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen	4:c1beacfc42c7	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen	4:c1beacfc42c7	34	POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen	4:c1beacfc42c7	35	---------------------------------------------------------------------------*/
MikamiUitOpen	4:c1beacfc42c7	36
MikamiUitOpen	4:c1beacfc42c7	37
MikamiUitOpen	4:c1beacfc42c7	38	#if defined ( __ICCARM__ )
MikamiUitOpen	4:c1beacfc42c7	39	#pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen	4:c1beacfc42c7	40	#endif
MikamiUitOpen	4:c1beacfc42c7	41
MikamiUitOpen	4:c1beacfc42c7	42	#ifndef __CORE_CM4_H_GENERIC
MikamiUitOpen	4:c1beacfc42c7	43	#define __CORE_CM4_H_GENERIC
MikamiUitOpen	4:c1beacfc42c7	44
MikamiUitOpen	4:c1beacfc42c7	45	#ifdef __cplusplus
MikamiUitOpen	4:c1beacfc42c7	46	extern "C" {
MikamiUitOpen	4:c1beacfc42c7	47	#endif
MikamiUitOpen	4:c1beacfc42c7	48
MikamiUitOpen	4:c1beacfc42c7	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen	4:c1beacfc42c7	50	CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen	4:c1beacfc42c7	51
MikamiUitOpen	4:c1beacfc42c7	52	\li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen	4:c1beacfc42c7	53	Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen	4:c1beacfc42c7	54
MikamiUitOpen	4:c1beacfc42c7	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen	4:c1beacfc42c7	56	Unions are used for effective representation of core registers.
MikamiUitOpen	4:c1beacfc42c7	57
MikamiUitOpen	4:c1beacfc42c7	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen	4:c1beacfc42c7	59	Function-like macros are used to allow more efficient code.
MikamiUitOpen	4:c1beacfc42c7	60	*/
MikamiUitOpen	4:c1beacfc42c7	61
MikamiUitOpen	4:c1beacfc42c7	62
MikamiUitOpen	4:c1beacfc42c7	63	/*******************************************************************************
MikamiUitOpen	4:c1beacfc42c7	64	* CMSIS definitions
MikamiUitOpen	4:c1beacfc42c7	65	******************************************************************************/
MikamiUitOpen	4:c1beacfc42c7	66	/** \ingroup Cortex_M4
MikamiUitOpen	4:c1beacfc42c7	67	@{
MikamiUitOpen	4:c1beacfc42c7	68	*/
MikamiUitOpen	4:c1beacfc42c7	69
MikamiUitOpen	4:c1beacfc42c7	70	/* CMSIS CM4 definitions */
MikamiUitOpen	4:c1beacfc42c7	71	#define __CM4_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
MikamiUitOpen	4:c1beacfc42c7	72	#define __CM4_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
MikamiUitOpen	4:c1beacfc42c7	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
MikamiUitOpen	4:c1beacfc42c7	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
MikamiUitOpen	4:c1beacfc42c7	75
MikamiUitOpen	4:c1beacfc42c7	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
MikamiUitOpen	4:c1beacfc42c7	77
MikamiUitOpen	4:c1beacfc42c7	78
MikamiUitOpen	4:c1beacfc42c7	79	#if defined ( __CC_ARM )
MikamiUitOpen	4:c1beacfc42c7	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
MikamiUitOpen	4:c1beacfc42c7	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
MikamiUitOpen	4:c1beacfc42c7	82	#define __STATIC_INLINE static __inline
MikamiUitOpen	4:c1beacfc42c7	83
MikamiUitOpen	4:c1beacfc42c7	84	#elif defined ( __GNUC__ )
MikamiUitOpen	4:c1beacfc42c7	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
MikamiUitOpen	4:c1beacfc42c7	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
MikamiUitOpen	4:c1beacfc42c7	87	#define __STATIC_INLINE static inline
MikamiUitOpen	4:c1beacfc42c7	88
MikamiUitOpen	4:c1beacfc42c7	89	#elif defined ( __ICCARM__ )
MikamiUitOpen	4:c1beacfc42c7	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
MikamiUitOpen	4:c1beacfc42c7	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
MikamiUitOpen	4:c1beacfc42c7	92	#define __STATIC_INLINE static inline
MikamiUitOpen	4:c1beacfc42c7	93
MikamiUitOpen	4:c1beacfc42c7	94	#elif defined ( __TMS470__ )
MikamiUitOpen	4:c1beacfc42c7	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
MikamiUitOpen	4:c1beacfc42c7	96	#define __STATIC_INLINE static inline
MikamiUitOpen	4:c1beacfc42c7	97
MikamiUitOpen	4:c1beacfc42c7	98	#elif defined ( __TASKING__ )
MikamiUitOpen	4:c1beacfc42c7	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
MikamiUitOpen	4:c1beacfc42c7	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
MikamiUitOpen	4:c1beacfc42c7	101	#define __STATIC_INLINE static inline
MikamiUitOpen	4:c1beacfc42c7	102
MikamiUitOpen	4:c1beacfc42c7	103	#elif defined ( __CSMC__ )
MikamiUitOpen	4:c1beacfc42c7	104	#define __packed
MikamiUitOpen	4:c1beacfc42c7	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
MikamiUitOpen	4:c1beacfc42c7	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
MikamiUitOpen	4:c1beacfc42c7	107	#define __STATIC_INLINE static inline
MikamiUitOpen	4:c1beacfc42c7	108
MikamiUitOpen	4:c1beacfc42c7	109	#endif
MikamiUitOpen	4:c1beacfc42c7	110
MikamiUitOpen	4:c1beacfc42c7	111	/** __FPU_USED indicates whether an FPU is used or not.
MikamiUitOpen	4:c1beacfc42c7	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
MikamiUitOpen	4:c1beacfc42c7	113	*/
MikamiUitOpen	4:c1beacfc42c7	114	#if defined ( __CC_ARM )
MikamiUitOpen	4:c1beacfc42c7	115	#if defined __TARGET_FPU_VFP
MikamiUitOpen	4:c1beacfc42c7	116	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	117	#define __FPU_USED 1
MikamiUitOpen	4:c1beacfc42c7	118	#else
MikamiUitOpen	4:c1beacfc42c7	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen	4:c1beacfc42c7	120	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	121	#endif
MikamiUitOpen	4:c1beacfc42c7	122	#else
MikamiUitOpen	4:c1beacfc42c7	123	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	124	#endif
MikamiUitOpen	4:c1beacfc42c7	125
MikamiUitOpen	4:c1beacfc42c7	126	#elif defined ( __GNUC__ )
MikamiUitOpen	4:c1beacfc42c7	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen	4:c1beacfc42c7	128	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	129	#define __FPU_USED 1
MikamiUitOpen	4:c1beacfc42c7	130	#else
MikamiUitOpen	4:c1beacfc42c7	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen	4:c1beacfc42c7	132	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	133	#endif
MikamiUitOpen	4:c1beacfc42c7	134	#else
MikamiUitOpen	4:c1beacfc42c7	135	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	136	#endif
MikamiUitOpen	4:c1beacfc42c7	137
MikamiUitOpen	4:c1beacfc42c7	138	#elif defined ( __ICCARM__ )
MikamiUitOpen	4:c1beacfc42c7	139	#if defined __ARMVFP__
MikamiUitOpen	4:c1beacfc42c7	140	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	141	#define __FPU_USED 1
MikamiUitOpen	4:c1beacfc42c7	142	#else
MikamiUitOpen	4:c1beacfc42c7	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen	4:c1beacfc42c7	144	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	145	#endif
MikamiUitOpen	4:c1beacfc42c7	146	#else
MikamiUitOpen	4:c1beacfc42c7	147	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	148	#endif
MikamiUitOpen	4:c1beacfc42c7	149
MikamiUitOpen	4:c1beacfc42c7	150	#elif defined ( __TMS470__ )
MikamiUitOpen	4:c1beacfc42c7	151	#if defined __TI_VFP_SUPPORT__
MikamiUitOpen	4:c1beacfc42c7	152	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	153	#define __FPU_USED 1
MikamiUitOpen	4:c1beacfc42c7	154	#else
MikamiUitOpen	4:c1beacfc42c7	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen	4:c1beacfc42c7	156	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	157	#endif
MikamiUitOpen	4:c1beacfc42c7	158	#else
MikamiUitOpen	4:c1beacfc42c7	159	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	160	#endif
MikamiUitOpen	4:c1beacfc42c7	161
MikamiUitOpen	4:c1beacfc42c7	162	#elif defined ( __TASKING__ )
MikamiUitOpen	4:c1beacfc42c7	163	#if defined __FPU_VFP__
MikamiUitOpen	4:c1beacfc42c7	164	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	165	#define __FPU_USED 1
MikamiUitOpen	4:c1beacfc42c7	166	#else
MikamiUitOpen	4:c1beacfc42c7	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen	4:c1beacfc42c7	168	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	169	#endif
MikamiUitOpen	4:c1beacfc42c7	170	#else
MikamiUitOpen	4:c1beacfc42c7	171	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	172	#endif
MikamiUitOpen	4:c1beacfc42c7	173
MikamiUitOpen	4:c1beacfc42c7	174	#elif defined ( __CSMC__ ) /* Cosmic */
MikamiUitOpen	4:c1beacfc42c7	175	#if ( __CSMC__ & 0x400) // FPU present for parser
MikamiUitOpen	4:c1beacfc42c7	176	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	177	#define __FPU_USED 1
MikamiUitOpen	4:c1beacfc42c7	178	#else
MikamiUitOpen	4:c1beacfc42c7	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen	4:c1beacfc42c7	180	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	181	#endif
MikamiUitOpen	4:c1beacfc42c7	182	#else
MikamiUitOpen	4:c1beacfc42c7	183	#define __FPU_USED 0
MikamiUitOpen	4:c1beacfc42c7	184	#endif
MikamiUitOpen	4:c1beacfc42c7	185	#endif
MikamiUitOpen	4:c1beacfc42c7	186
MikamiUitOpen	4:c1beacfc42c7	187	#include <stdint.h> /* standard types definitions */
MikamiUitOpen	4:c1beacfc42c7	188	#include <core_cmInstr.h> /* Core Instruction Access */
MikamiUitOpen	4:c1beacfc42c7	189	#include <core_cmFunc.h> /* Core Function Access */
MikamiUitOpen	4:c1beacfc42c7	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
MikamiUitOpen	4:c1beacfc42c7	191
MikamiUitOpen	4:c1beacfc42c7	192	#ifdef __cplusplus
MikamiUitOpen	4:c1beacfc42c7	193	}
MikamiUitOpen	4:c1beacfc42c7	194	#endif
MikamiUitOpen	4:c1beacfc42c7	195
MikamiUitOpen	4:c1beacfc42c7	196	#endif /* __CORE_CM4_H_GENERIC */
MikamiUitOpen	4:c1beacfc42c7	197
MikamiUitOpen	4:c1beacfc42c7	198	#ifndef __CMSIS_GENERIC
MikamiUitOpen	4:c1beacfc42c7	199
MikamiUitOpen	4:c1beacfc42c7	200	#ifndef __CORE_CM4_H_DEPENDANT
MikamiUitOpen	4:c1beacfc42c7	201	#define __CORE_CM4_H_DEPENDANT
MikamiUitOpen	4:c1beacfc42c7	202
MikamiUitOpen	4:c1beacfc42c7	203	#ifdef __cplusplus
MikamiUitOpen	4:c1beacfc42c7	204	extern "C" {
MikamiUitOpen	4:c1beacfc42c7	205	#endif
MikamiUitOpen	4:c1beacfc42c7	206
MikamiUitOpen	4:c1beacfc42c7	207	/* check device defines and use defaults */
MikamiUitOpen	4:c1beacfc42c7	208	#if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen	4:c1beacfc42c7	209	#ifndef __CM4_REV
MikamiUitOpen	4:c1beacfc42c7	210	#define __CM4_REV 0x0000
MikamiUitOpen	4:c1beacfc42c7	211	#warning "__CM4_REV not defined in device header file; using default!"
MikamiUitOpen	4:c1beacfc42c7	212	#endif
MikamiUitOpen	4:c1beacfc42c7	213
MikamiUitOpen	4:c1beacfc42c7	214	#ifndef __FPU_PRESENT
MikamiUitOpen	4:c1beacfc42c7	215	#define __FPU_PRESENT 0
MikamiUitOpen	4:c1beacfc42c7	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen	4:c1beacfc42c7	217	#endif
MikamiUitOpen	4:c1beacfc42c7	218
MikamiUitOpen	4:c1beacfc42c7	219	#ifndef __MPU_PRESENT
MikamiUitOpen	4:c1beacfc42c7	220	#define __MPU_PRESENT 0
MikamiUitOpen	4:c1beacfc42c7	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen	4:c1beacfc42c7	222	#endif
MikamiUitOpen	4:c1beacfc42c7	223
MikamiUitOpen	4:c1beacfc42c7	224	#ifndef __NVIC_PRIO_BITS
MikamiUitOpen	4:c1beacfc42c7	225	#define __NVIC_PRIO_BITS 4
MikamiUitOpen	4:c1beacfc42c7	226	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MikamiUitOpen	4:c1beacfc42c7	227	#endif
MikamiUitOpen	4:c1beacfc42c7	228
MikamiUitOpen	4:c1beacfc42c7	229	#ifndef __Vendor_SysTickConfig
MikamiUitOpen	4:c1beacfc42c7	230	#define __Vendor_SysTickConfig 0
MikamiUitOpen	4:c1beacfc42c7	231	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MikamiUitOpen	4:c1beacfc42c7	232	#endif
MikamiUitOpen	4:c1beacfc42c7	233	#endif
MikamiUitOpen	4:c1beacfc42c7	234
MikamiUitOpen	4:c1beacfc42c7	235	/* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen	4:c1beacfc42c7	236	/**
MikamiUitOpen	4:c1beacfc42c7	237	\defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen	4:c1beacfc42c7	238
MikamiUitOpen	4:c1beacfc42c7	239	<strong>IO Type Qualifiers</strong> are used
MikamiUitOpen	4:c1beacfc42c7	240	\li to specify the access to peripheral variables.
MikamiUitOpen	4:c1beacfc42c7	241	\li for automatic generation of peripheral register debug information.
MikamiUitOpen	4:c1beacfc42c7	242	*/
MikamiUitOpen	4:c1beacfc42c7	243	#ifdef __cplusplus
MikamiUitOpen	4:c1beacfc42c7	244	#define __I volatile /!< Defines 'read only' permissions /
MikamiUitOpen	4:c1beacfc42c7	245	#else
MikamiUitOpen	4:c1beacfc42c7	246	#define __I volatile const /!< Defines 'read only' permissions /
MikamiUitOpen	4:c1beacfc42c7	247	#endif
MikamiUitOpen	4:c1beacfc42c7	248	#define __O volatile /!< Defines 'write only' permissions /
MikamiUitOpen	4:c1beacfc42c7	249	#define __IO volatile /!< Defines 'read / write' permissions /
MikamiUitOpen	4:c1beacfc42c7	250
MikamiUitOpen	4:c1beacfc42c7	251	/@} end of group Cortex_M4 /
MikamiUitOpen	4:c1beacfc42c7	252
MikamiUitOpen	4:c1beacfc42c7	253
MikamiUitOpen	4:c1beacfc42c7	254
MikamiUitOpen	4:c1beacfc42c7	255	/*******************************************************************************
MikamiUitOpen	4:c1beacfc42c7	256	* Register Abstraction
MikamiUitOpen	4:c1beacfc42c7	257	Core Register contain:
MikamiUitOpen	4:c1beacfc42c7	258	- Core Register
MikamiUitOpen	4:c1beacfc42c7	259	- Core NVIC Register
MikamiUitOpen	4:c1beacfc42c7	260	- Core SCB Register
MikamiUitOpen	4:c1beacfc42c7	261	- Core SysTick Register
MikamiUitOpen	4:c1beacfc42c7	262	- Core Debug Register
MikamiUitOpen	4:c1beacfc42c7	263	- Core MPU Register
MikamiUitOpen	4:c1beacfc42c7	264	- Core FPU Register
MikamiUitOpen	4:c1beacfc42c7	265	******************************************************************************/
MikamiUitOpen	4:c1beacfc42c7	266	/** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen	4:c1beacfc42c7	267	\brief Type definitions and defines for Cortex-M processor based devices.
MikamiUitOpen	4:c1beacfc42c7	268	*/
MikamiUitOpen	4:c1beacfc42c7	269
MikamiUitOpen	4:c1beacfc42c7	270	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	271	\defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen	4:c1beacfc42c7	272	\brief Core Register type definitions.
MikamiUitOpen	4:c1beacfc42c7	273	@{
MikamiUitOpen	4:c1beacfc42c7	274	*/
MikamiUitOpen	4:c1beacfc42c7	275
MikamiUitOpen	4:c1beacfc42c7	276	/** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen	4:c1beacfc42c7	277	*/
MikamiUitOpen	4:c1beacfc42c7	278	typedef union
MikamiUitOpen	4:c1beacfc42c7	279	{
MikamiUitOpen	4:c1beacfc42c7	280	struct
MikamiUitOpen	4:c1beacfc42c7	281	{
MikamiUitOpen	4:c1beacfc42c7	282	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
MikamiUitOpen	4:c1beacfc42c7	283	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
MikamiUitOpen	4:c1beacfc42c7	284	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
MikamiUitOpen	4:c1beacfc42c7	285	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
MikamiUitOpen	4:c1beacfc42c7	286	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
MikamiUitOpen	4:c1beacfc42c7	287	uint32_t C:1; /!< bit: 29 Carry condition code flag /
MikamiUitOpen	4:c1beacfc42c7	288	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
MikamiUitOpen	4:c1beacfc42c7	289	uint32_t N:1; /!< bit: 31 Negative condition code flag /
MikamiUitOpen	4:c1beacfc42c7	290	} b; /!< Structure used for bit access /
MikamiUitOpen	4:c1beacfc42c7	291	uint32_t w; /!< Type used for word access /
MikamiUitOpen	4:c1beacfc42c7	292	} APSR_Type;
MikamiUitOpen	4:c1beacfc42c7	293
MikamiUitOpen	4:c1beacfc42c7	294	/* APSR Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	295	#define APSR_N_Pos 31 /!< APSR: N Position /
MikamiUitOpen	4:c1beacfc42c7	296	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
MikamiUitOpen	4:c1beacfc42c7	297
MikamiUitOpen	4:c1beacfc42c7	298	#define APSR_Z_Pos 30 /!< APSR: Z Position /
MikamiUitOpen	4:c1beacfc42c7	299	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
MikamiUitOpen	4:c1beacfc42c7	300
MikamiUitOpen	4:c1beacfc42c7	301	#define APSR_C_Pos 29 /!< APSR: C Position /
MikamiUitOpen	4:c1beacfc42c7	302	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
MikamiUitOpen	4:c1beacfc42c7	303
MikamiUitOpen	4:c1beacfc42c7	304	#define APSR_V_Pos 28 /!< APSR: V Position /
MikamiUitOpen	4:c1beacfc42c7	305	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
MikamiUitOpen	4:c1beacfc42c7	306
MikamiUitOpen	4:c1beacfc42c7	307	#define APSR_Q_Pos 27 /!< APSR: Q Position /
MikamiUitOpen	4:c1beacfc42c7	308	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
MikamiUitOpen	4:c1beacfc42c7	309
MikamiUitOpen	4:c1beacfc42c7	310	#define APSR_GE_Pos 16 /!< APSR: GE Position /
MikamiUitOpen	4:c1beacfc42c7	311	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
MikamiUitOpen	4:c1beacfc42c7	312
MikamiUitOpen	4:c1beacfc42c7	313
MikamiUitOpen	4:c1beacfc42c7	314	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
MikamiUitOpen	4:c1beacfc42c7	315	*/
MikamiUitOpen	4:c1beacfc42c7	316	typedef union
MikamiUitOpen	4:c1beacfc42c7	317	{
MikamiUitOpen	4:c1beacfc42c7	318	struct
MikamiUitOpen	4:c1beacfc42c7	319	{
MikamiUitOpen	4:c1beacfc42c7	320	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
MikamiUitOpen	4:c1beacfc42c7	321	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
MikamiUitOpen	4:c1beacfc42c7	322	} b; /!< Structure used for bit access /
MikamiUitOpen	4:c1beacfc42c7	323	uint32_t w; /!< Type used for word access /
MikamiUitOpen	4:c1beacfc42c7	324	} IPSR_Type;
MikamiUitOpen	4:c1beacfc42c7	325
MikamiUitOpen	4:c1beacfc42c7	326	/* IPSR Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	327	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
MikamiUitOpen	4:c1beacfc42c7	328	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
MikamiUitOpen	4:c1beacfc42c7	329
MikamiUitOpen	4:c1beacfc42c7	330
MikamiUitOpen	4:c1beacfc42c7	331	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MikamiUitOpen	4:c1beacfc42c7	332	*/
MikamiUitOpen	4:c1beacfc42c7	333	typedef union
MikamiUitOpen	4:c1beacfc42c7	334	{
MikamiUitOpen	4:c1beacfc42c7	335	struct
MikamiUitOpen	4:c1beacfc42c7	336	{
MikamiUitOpen	4:c1beacfc42c7	337	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
MikamiUitOpen	4:c1beacfc42c7	338	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
MikamiUitOpen	4:c1beacfc42c7	339	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
MikamiUitOpen	4:c1beacfc42c7	340	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
MikamiUitOpen	4:c1beacfc42c7	341	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
MikamiUitOpen	4:c1beacfc42c7	342	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
MikamiUitOpen	4:c1beacfc42c7	343	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
MikamiUitOpen	4:c1beacfc42c7	344	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
MikamiUitOpen	4:c1beacfc42c7	345	uint32_t C:1; /!< bit: 29 Carry condition code flag /
MikamiUitOpen	4:c1beacfc42c7	346	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
MikamiUitOpen	4:c1beacfc42c7	347	uint32_t N:1; /!< bit: 31 Negative condition code flag /
MikamiUitOpen	4:c1beacfc42c7	348	} b; /!< Structure used for bit access /
MikamiUitOpen	4:c1beacfc42c7	349	uint32_t w; /!< Type used for word access /
MikamiUitOpen	4:c1beacfc42c7	350	} xPSR_Type;
MikamiUitOpen	4:c1beacfc42c7	351
MikamiUitOpen	4:c1beacfc42c7	352	/* xPSR Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	353	#define xPSR_N_Pos 31 /!< xPSR: N Position /
MikamiUitOpen	4:c1beacfc42c7	354	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
MikamiUitOpen	4:c1beacfc42c7	355
MikamiUitOpen	4:c1beacfc42c7	356	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
MikamiUitOpen	4:c1beacfc42c7	357	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
MikamiUitOpen	4:c1beacfc42c7	358
MikamiUitOpen	4:c1beacfc42c7	359	#define xPSR_C_Pos 29 /!< xPSR: C Position /
MikamiUitOpen	4:c1beacfc42c7	360	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
MikamiUitOpen	4:c1beacfc42c7	361
MikamiUitOpen	4:c1beacfc42c7	362	#define xPSR_V_Pos 28 /!< xPSR: V Position /
MikamiUitOpen	4:c1beacfc42c7	363	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
MikamiUitOpen	4:c1beacfc42c7	364
MikamiUitOpen	4:c1beacfc42c7	365	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
MikamiUitOpen	4:c1beacfc42c7	366	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
MikamiUitOpen	4:c1beacfc42c7	367
MikamiUitOpen	4:c1beacfc42c7	368	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
MikamiUitOpen	4:c1beacfc42c7	369	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
MikamiUitOpen	4:c1beacfc42c7	370
MikamiUitOpen	4:c1beacfc42c7	371	#define xPSR_T_Pos 24 /!< xPSR: T Position /
MikamiUitOpen	4:c1beacfc42c7	372	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
MikamiUitOpen	4:c1beacfc42c7	373
MikamiUitOpen	4:c1beacfc42c7	374	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
MikamiUitOpen	4:c1beacfc42c7	375	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
MikamiUitOpen	4:c1beacfc42c7	376
MikamiUitOpen	4:c1beacfc42c7	377	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
MikamiUitOpen	4:c1beacfc42c7	378	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
MikamiUitOpen	4:c1beacfc42c7	379
MikamiUitOpen	4:c1beacfc42c7	380
MikamiUitOpen	4:c1beacfc42c7	381	/** \brief Union type to access the Control Registers (CONTROL).
MikamiUitOpen	4:c1beacfc42c7	382	*/
MikamiUitOpen	4:c1beacfc42c7	383	typedef union
MikamiUitOpen	4:c1beacfc42c7	384	{
MikamiUitOpen	4:c1beacfc42c7	385	struct
MikamiUitOpen	4:c1beacfc42c7	386	{
MikamiUitOpen	4:c1beacfc42c7	387	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
MikamiUitOpen	4:c1beacfc42c7	388	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
MikamiUitOpen	4:c1beacfc42c7	389	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
MikamiUitOpen	4:c1beacfc42c7	390	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
MikamiUitOpen	4:c1beacfc42c7	391	} b; /!< Structure used for bit access /
MikamiUitOpen	4:c1beacfc42c7	392	uint32_t w; /!< Type used for word access /
MikamiUitOpen	4:c1beacfc42c7	393	} CONTROL_Type;
MikamiUitOpen	4:c1beacfc42c7	394
MikamiUitOpen	4:c1beacfc42c7	395	/* CONTROL Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	396	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
MikamiUitOpen	4:c1beacfc42c7	397	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
MikamiUitOpen	4:c1beacfc42c7	398
MikamiUitOpen	4:c1beacfc42c7	399	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
MikamiUitOpen	4:c1beacfc42c7	400	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
MikamiUitOpen	4:c1beacfc42c7	401
MikamiUitOpen	4:c1beacfc42c7	402	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
MikamiUitOpen	4:c1beacfc42c7	403	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
MikamiUitOpen	4:c1beacfc42c7	404
MikamiUitOpen	4:c1beacfc42c7	405	/@} end of group CMSIS_CORE /
MikamiUitOpen	4:c1beacfc42c7	406
MikamiUitOpen	4:c1beacfc42c7	407
MikamiUitOpen	4:c1beacfc42c7	408	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	409	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MikamiUitOpen	4:c1beacfc42c7	410	\brief Type definitions for the NVIC Registers
MikamiUitOpen	4:c1beacfc42c7	411	@{
MikamiUitOpen	4:c1beacfc42c7	412	*/
MikamiUitOpen	4:c1beacfc42c7	413
MikamiUitOpen	4:c1beacfc42c7	414	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MikamiUitOpen	4:c1beacfc42c7	415	*/
MikamiUitOpen	4:c1beacfc42c7	416	typedef struct
MikamiUitOpen	4:c1beacfc42c7	417	{
MikamiUitOpen	4:c1beacfc42c7	418	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
MikamiUitOpen	4:c1beacfc42c7	419	uint32_t RESERVED0[24];
MikamiUitOpen	4:c1beacfc42c7	420	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
MikamiUitOpen	4:c1beacfc42c7	421	uint32_t RSERVED1[24];
MikamiUitOpen	4:c1beacfc42c7	422	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
MikamiUitOpen	4:c1beacfc42c7	423	uint32_t RESERVED2[24];
MikamiUitOpen	4:c1beacfc42c7	424	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
MikamiUitOpen	4:c1beacfc42c7	425	uint32_t RESERVED3[24];
MikamiUitOpen	4:c1beacfc42c7	426	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
MikamiUitOpen	4:c1beacfc42c7	427	uint32_t RESERVED4[56];
MikamiUitOpen	4:c1beacfc42c7	428	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
MikamiUitOpen	4:c1beacfc42c7	429	uint32_t RESERVED5[644];
MikamiUitOpen	4:c1beacfc42c7	430	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
MikamiUitOpen	4:c1beacfc42c7	431	} NVIC_Type;
MikamiUitOpen	4:c1beacfc42c7	432
MikamiUitOpen	4:c1beacfc42c7	433	/* Software Triggered Interrupt Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	434	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
MikamiUitOpen	4:c1beacfc42c7	435	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
MikamiUitOpen	4:c1beacfc42c7	436
MikamiUitOpen	4:c1beacfc42c7	437	/@} end of group CMSIS_NVIC /
MikamiUitOpen	4:c1beacfc42c7	438
MikamiUitOpen	4:c1beacfc42c7	439
MikamiUitOpen	4:c1beacfc42c7	440	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	441	\defgroup CMSIS_SCB System Control Block (SCB)
MikamiUitOpen	4:c1beacfc42c7	442	\brief Type definitions for the System Control Block Registers
MikamiUitOpen	4:c1beacfc42c7	443	@{
MikamiUitOpen	4:c1beacfc42c7	444	*/
MikamiUitOpen	4:c1beacfc42c7	445
MikamiUitOpen	4:c1beacfc42c7	446	/** \brief Structure type to access the System Control Block (SCB).
MikamiUitOpen	4:c1beacfc42c7	447	*/
MikamiUitOpen	4:c1beacfc42c7	448	typedef struct
MikamiUitOpen	4:c1beacfc42c7	449	{
MikamiUitOpen	4:c1beacfc42c7	450	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
MikamiUitOpen	4:c1beacfc42c7	451	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
MikamiUitOpen	4:c1beacfc42c7	452	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
MikamiUitOpen	4:c1beacfc42c7	453	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
MikamiUitOpen	4:c1beacfc42c7	454	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
MikamiUitOpen	4:c1beacfc42c7	455	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
MikamiUitOpen	4:c1beacfc42c7	456	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
MikamiUitOpen	4:c1beacfc42c7	457	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
MikamiUitOpen	4:c1beacfc42c7	458	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
MikamiUitOpen	4:c1beacfc42c7	459	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
MikamiUitOpen	4:c1beacfc42c7	460	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
MikamiUitOpen	4:c1beacfc42c7	461	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
MikamiUitOpen	4:c1beacfc42c7	462	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
MikamiUitOpen	4:c1beacfc42c7	463	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
MikamiUitOpen	4:c1beacfc42c7	464	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
MikamiUitOpen	4:c1beacfc42c7	465	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
MikamiUitOpen	4:c1beacfc42c7	466	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
MikamiUitOpen	4:c1beacfc42c7	467	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
MikamiUitOpen	4:c1beacfc42c7	468	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
MikamiUitOpen	4:c1beacfc42c7	469	uint32_t RESERVED0[5];
MikamiUitOpen	4:c1beacfc42c7	470	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
MikamiUitOpen	4:c1beacfc42c7	471	} SCB_Type;
MikamiUitOpen	4:c1beacfc42c7	472
MikamiUitOpen	4:c1beacfc42c7	473	/* SCB CPUID Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	474	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
MikamiUitOpen	4:c1beacfc42c7	475	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
MikamiUitOpen	4:c1beacfc42c7	476
MikamiUitOpen	4:c1beacfc42c7	477	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
MikamiUitOpen	4:c1beacfc42c7	478	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
MikamiUitOpen	4:c1beacfc42c7	479
MikamiUitOpen	4:c1beacfc42c7	480	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
MikamiUitOpen	4:c1beacfc42c7	481	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
MikamiUitOpen	4:c1beacfc42c7	482
MikamiUitOpen	4:c1beacfc42c7	483	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
MikamiUitOpen	4:c1beacfc42c7	484	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
MikamiUitOpen	4:c1beacfc42c7	485
MikamiUitOpen	4:c1beacfc42c7	486	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
MikamiUitOpen	4:c1beacfc42c7	487	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
MikamiUitOpen	4:c1beacfc42c7	488
MikamiUitOpen	4:c1beacfc42c7	489	/* SCB Interrupt Control State Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	490	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
MikamiUitOpen	4:c1beacfc42c7	491	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
MikamiUitOpen	4:c1beacfc42c7	492
MikamiUitOpen	4:c1beacfc42c7	493	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
MikamiUitOpen	4:c1beacfc42c7	494	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
MikamiUitOpen	4:c1beacfc42c7	495
MikamiUitOpen	4:c1beacfc42c7	496	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
MikamiUitOpen	4:c1beacfc42c7	497	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
MikamiUitOpen	4:c1beacfc42c7	498
MikamiUitOpen	4:c1beacfc42c7	499	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
MikamiUitOpen	4:c1beacfc42c7	500	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
MikamiUitOpen	4:c1beacfc42c7	501
MikamiUitOpen	4:c1beacfc42c7	502	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
MikamiUitOpen	4:c1beacfc42c7	503	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
MikamiUitOpen	4:c1beacfc42c7	504
MikamiUitOpen	4:c1beacfc42c7	505	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
MikamiUitOpen	4:c1beacfc42c7	506	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
MikamiUitOpen	4:c1beacfc42c7	507
MikamiUitOpen	4:c1beacfc42c7	508	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
MikamiUitOpen	4:c1beacfc42c7	509	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
MikamiUitOpen	4:c1beacfc42c7	510
MikamiUitOpen	4:c1beacfc42c7	511	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
MikamiUitOpen	4:c1beacfc42c7	512	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
MikamiUitOpen	4:c1beacfc42c7	513
MikamiUitOpen	4:c1beacfc42c7	514	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
MikamiUitOpen	4:c1beacfc42c7	515	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
MikamiUitOpen	4:c1beacfc42c7	516
MikamiUitOpen	4:c1beacfc42c7	517	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
MikamiUitOpen	4:c1beacfc42c7	518	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
MikamiUitOpen	4:c1beacfc42c7	519
MikamiUitOpen	4:c1beacfc42c7	520	/* SCB Vector Table Offset Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	521	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
MikamiUitOpen	4:c1beacfc42c7	522	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
MikamiUitOpen	4:c1beacfc42c7	523
MikamiUitOpen	4:c1beacfc42c7	524	/* SCB Application Interrupt and Reset Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	525	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
MikamiUitOpen	4:c1beacfc42c7	526	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
MikamiUitOpen	4:c1beacfc42c7	527
MikamiUitOpen	4:c1beacfc42c7	528	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
MikamiUitOpen	4:c1beacfc42c7	529	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
MikamiUitOpen	4:c1beacfc42c7	530
MikamiUitOpen	4:c1beacfc42c7	531	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
MikamiUitOpen	4:c1beacfc42c7	532	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
MikamiUitOpen	4:c1beacfc42c7	533
MikamiUitOpen	4:c1beacfc42c7	534	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
MikamiUitOpen	4:c1beacfc42c7	535	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
MikamiUitOpen	4:c1beacfc42c7	536
MikamiUitOpen	4:c1beacfc42c7	537	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
MikamiUitOpen	4:c1beacfc42c7	538	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
MikamiUitOpen	4:c1beacfc42c7	539
MikamiUitOpen	4:c1beacfc42c7	540	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
MikamiUitOpen	4:c1beacfc42c7	541	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
MikamiUitOpen	4:c1beacfc42c7	542
MikamiUitOpen	4:c1beacfc42c7	543	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
MikamiUitOpen	4:c1beacfc42c7	544	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
MikamiUitOpen	4:c1beacfc42c7	545
MikamiUitOpen	4:c1beacfc42c7	546	/* SCB System Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	547	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
MikamiUitOpen	4:c1beacfc42c7	548	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
MikamiUitOpen	4:c1beacfc42c7	549
MikamiUitOpen	4:c1beacfc42c7	550	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
MikamiUitOpen	4:c1beacfc42c7	551	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
MikamiUitOpen	4:c1beacfc42c7	552
MikamiUitOpen	4:c1beacfc42c7	553	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
MikamiUitOpen	4:c1beacfc42c7	554	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
MikamiUitOpen	4:c1beacfc42c7	555
MikamiUitOpen	4:c1beacfc42c7	556	/* SCB Configuration Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	557	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
MikamiUitOpen	4:c1beacfc42c7	558	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
MikamiUitOpen	4:c1beacfc42c7	559
MikamiUitOpen	4:c1beacfc42c7	560	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
MikamiUitOpen	4:c1beacfc42c7	561	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
MikamiUitOpen	4:c1beacfc42c7	562
MikamiUitOpen	4:c1beacfc42c7	563	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
MikamiUitOpen	4:c1beacfc42c7	564	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
MikamiUitOpen	4:c1beacfc42c7	565
MikamiUitOpen	4:c1beacfc42c7	566	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
MikamiUitOpen	4:c1beacfc42c7	567	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
MikamiUitOpen	4:c1beacfc42c7	568
MikamiUitOpen	4:c1beacfc42c7	569	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
MikamiUitOpen	4:c1beacfc42c7	570	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
MikamiUitOpen	4:c1beacfc42c7	571
MikamiUitOpen	4:c1beacfc42c7	572	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
MikamiUitOpen	4:c1beacfc42c7	573	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
MikamiUitOpen	4:c1beacfc42c7	574
MikamiUitOpen	4:c1beacfc42c7	575	/* SCB System Handler Control and State Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	576	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
MikamiUitOpen	4:c1beacfc42c7	577	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	578
MikamiUitOpen	4:c1beacfc42c7	579	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
MikamiUitOpen	4:c1beacfc42c7	580	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	581
MikamiUitOpen	4:c1beacfc42c7	582	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
MikamiUitOpen	4:c1beacfc42c7	583	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	584
MikamiUitOpen	4:c1beacfc42c7	585	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
MikamiUitOpen	4:c1beacfc42c7	586	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
MikamiUitOpen	4:c1beacfc42c7	587
MikamiUitOpen	4:c1beacfc42c7	588	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
MikamiUitOpen	4:c1beacfc42c7	589	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
MikamiUitOpen	4:c1beacfc42c7	590
MikamiUitOpen	4:c1beacfc42c7	591	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
MikamiUitOpen	4:c1beacfc42c7	592	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
MikamiUitOpen	4:c1beacfc42c7	593
MikamiUitOpen	4:c1beacfc42c7	594	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
MikamiUitOpen	4:c1beacfc42c7	595	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
MikamiUitOpen	4:c1beacfc42c7	596
MikamiUitOpen	4:c1beacfc42c7	597	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
MikamiUitOpen	4:c1beacfc42c7	598	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
MikamiUitOpen	4:c1beacfc42c7	599
MikamiUitOpen	4:c1beacfc42c7	600	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
MikamiUitOpen	4:c1beacfc42c7	601	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
MikamiUitOpen	4:c1beacfc42c7	602
MikamiUitOpen	4:c1beacfc42c7	603	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
MikamiUitOpen	4:c1beacfc42c7	604	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
MikamiUitOpen	4:c1beacfc42c7	605
MikamiUitOpen	4:c1beacfc42c7	606	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
MikamiUitOpen	4:c1beacfc42c7	607	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
MikamiUitOpen	4:c1beacfc42c7	608
MikamiUitOpen	4:c1beacfc42c7	609	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
MikamiUitOpen	4:c1beacfc42c7	610	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
MikamiUitOpen	4:c1beacfc42c7	611
MikamiUitOpen	4:c1beacfc42c7	612	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
MikamiUitOpen	4:c1beacfc42c7	613	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
MikamiUitOpen	4:c1beacfc42c7	614
MikamiUitOpen	4:c1beacfc42c7	615	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
MikamiUitOpen	4:c1beacfc42c7	616	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
MikamiUitOpen	4:c1beacfc42c7	617
MikamiUitOpen	4:c1beacfc42c7	618	/* SCB Configurable Fault Status Registers Definitions */
MikamiUitOpen	4:c1beacfc42c7	619	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
MikamiUitOpen	4:c1beacfc42c7	620	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
MikamiUitOpen	4:c1beacfc42c7	621
MikamiUitOpen	4:c1beacfc42c7	622	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
MikamiUitOpen	4:c1beacfc42c7	623	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
MikamiUitOpen	4:c1beacfc42c7	624
MikamiUitOpen	4:c1beacfc42c7	625	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
MikamiUitOpen	4:c1beacfc42c7	626	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
MikamiUitOpen	4:c1beacfc42c7	627
MikamiUitOpen	4:c1beacfc42c7	628	/* SCB Hard Fault Status Registers Definitions */
MikamiUitOpen	4:c1beacfc42c7	629	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
MikamiUitOpen	4:c1beacfc42c7	630	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
MikamiUitOpen	4:c1beacfc42c7	631
MikamiUitOpen	4:c1beacfc42c7	632	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
MikamiUitOpen	4:c1beacfc42c7	633	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
MikamiUitOpen	4:c1beacfc42c7	634
MikamiUitOpen	4:c1beacfc42c7	635	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
MikamiUitOpen	4:c1beacfc42c7	636	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
MikamiUitOpen	4:c1beacfc42c7	637
MikamiUitOpen	4:c1beacfc42c7	638	/* SCB Debug Fault Status Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	639	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
MikamiUitOpen	4:c1beacfc42c7	640	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
MikamiUitOpen	4:c1beacfc42c7	641
MikamiUitOpen	4:c1beacfc42c7	642	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
MikamiUitOpen	4:c1beacfc42c7	643	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
MikamiUitOpen	4:c1beacfc42c7	644
MikamiUitOpen	4:c1beacfc42c7	645	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
MikamiUitOpen	4:c1beacfc42c7	646	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
MikamiUitOpen	4:c1beacfc42c7	647
MikamiUitOpen	4:c1beacfc42c7	648	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
MikamiUitOpen	4:c1beacfc42c7	649	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
MikamiUitOpen	4:c1beacfc42c7	650
MikamiUitOpen	4:c1beacfc42c7	651	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
MikamiUitOpen	4:c1beacfc42c7	652	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
MikamiUitOpen	4:c1beacfc42c7	653
MikamiUitOpen	4:c1beacfc42c7	654	/@} end of group CMSIS_SCB /
MikamiUitOpen	4:c1beacfc42c7	655
MikamiUitOpen	4:c1beacfc42c7	656
MikamiUitOpen	4:c1beacfc42c7	657	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	658	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
MikamiUitOpen	4:c1beacfc42c7	659	\brief Type definitions for the System Control and ID Register not in the SCB
MikamiUitOpen	4:c1beacfc42c7	660	@{
MikamiUitOpen	4:c1beacfc42c7	661	*/
MikamiUitOpen	4:c1beacfc42c7	662
MikamiUitOpen	4:c1beacfc42c7	663	/** \brief Structure type to access the System Control and ID Register not in the SCB.
MikamiUitOpen	4:c1beacfc42c7	664	*/
MikamiUitOpen	4:c1beacfc42c7	665	typedef struct
MikamiUitOpen	4:c1beacfc42c7	666	{
MikamiUitOpen	4:c1beacfc42c7	667	uint32_t RESERVED0[1];
MikamiUitOpen	4:c1beacfc42c7	668	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
MikamiUitOpen	4:c1beacfc42c7	669	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
MikamiUitOpen	4:c1beacfc42c7	670	} SCnSCB_Type;
MikamiUitOpen	4:c1beacfc42c7	671
MikamiUitOpen	4:c1beacfc42c7	672	/* Interrupt Controller Type Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	673	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
MikamiUitOpen	4:c1beacfc42c7	674	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
MikamiUitOpen	4:c1beacfc42c7	675
MikamiUitOpen	4:c1beacfc42c7	676	/* Auxiliary Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	677	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
MikamiUitOpen	4:c1beacfc42c7	678	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
MikamiUitOpen	4:c1beacfc42c7	679
MikamiUitOpen	4:c1beacfc42c7	680	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
MikamiUitOpen	4:c1beacfc42c7	681	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
MikamiUitOpen	4:c1beacfc42c7	682
MikamiUitOpen	4:c1beacfc42c7	683	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
MikamiUitOpen	4:c1beacfc42c7	684	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
MikamiUitOpen	4:c1beacfc42c7	685
MikamiUitOpen	4:c1beacfc42c7	686	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
MikamiUitOpen	4:c1beacfc42c7	687	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
MikamiUitOpen	4:c1beacfc42c7	688
MikamiUitOpen	4:c1beacfc42c7	689	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
MikamiUitOpen	4:c1beacfc42c7	690	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
MikamiUitOpen	4:c1beacfc42c7	691
MikamiUitOpen	4:c1beacfc42c7	692	/@} end of group CMSIS_SCnotSCB /
MikamiUitOpen	4:c1beacfc42c7	693
MikamiUitOpen	4:c1beacfc42c7	694
MikamiUitOpen	4:c1beacfc42c7	695	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	696	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
MikamiUitOpen	4:c1beacfc42c7	697	\brief Type definitions for the System Timer Registers.
MikamiUitOpen	4:c1beacfc42c7	698	@{
MikamiUitOpen	4:c1beacfc42c7	699	*/
MikamiUitOpen	4:c1beacfc42c7	700
MikamiUitOpen	4:c1beacfc42c7	701	/** \brief Structure type to access the System Timer (SysTick).
MikamiUitOpen	4:c1beacfc42c7	702	*/
MikamiUitOpen	4:c1beacfc42c7	703	typedef struct
MikamiUitOpen	4:c1beacfc42c7	704	{
MikamiUitOpen	4:c1beacfc42c7	705	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
MikamiUitOpen	4:c1beacfc42c7	706	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
MikamiUitOpen	4:c1beacfc42c7	707	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
MikamiUitOpen	4:c1beacfc42c7	708	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
MikamiUitOpen	4:c1beacfc42c7	709	} SysTick_Type;
MikamiUitOpen	4:c1beacfc42c7	710
MikamiUitOpen	4:c1beacfc42c7	711	/* SysTick Control / Status Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	712	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
MikamiUitOpen	4:c1beacfc42c7	713	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
MikamiUitOpen	4:c1beacfc42c7	714
MikamiUitOpen	4:c1beacfc42c7	715	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
MikamiUitOpen	4:c1beacfc42c7	716	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
MikamiUitOpen	4:c1beacfc42c7	717
MikamiUitOpen	4:c1beacfc42c7	718	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
MikamiUitOpen	4:c1beacfc42c7	719	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
MikamiUitOpen	4:c1beacfc42c7	720
MikamiUitOpen	4:c1beacfc42c7	721	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
MikamiUitOpen	4:c1beacfc42c7	722	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
MikamiUitOpen	4:c1beacfc42c7	723
MikamiUitOpen	4:c1beacfc42c7	724	/* SysTick Reload Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	725	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
MikamiUitOpen	4:c1beacfc42c7	726	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
MikamiUitOpen	4:c1beacfc42c7	727
MikamiUitOpen	4:c1beacfc42c7	728	/* SysTick Current Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	729	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
MikamiUitOpen	4:c1beacfc42c7	730	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
MikamiUitOpen	4:c1beacfc42c7	731
MikamiUitOpen	4:c1beacfc42c7	732	/* SysTick Calibration Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	733	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
MikamiUitOpen	4:c1beacfc42c7	734	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
MikamiUitOpen	4:c1beacfc42c7	735
MikamiUitOpen	4:c1beacfc42c7	736	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
MikamiUitOpen	4:c1beacfc42c7	737	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
MikamiUitOpen	4:c1beacfc42c7	738
MikamiUitOpen	4:c1beacfc42c7	739	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
MikamiUitOpen	4:c1beacfc42c7	740	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
MikamiUitOpen	4:c1beacfc42c7	741
MikamiUitOpen	4:c1beacfc42c7	742	/@} end of group CMSIS_SysTick /
MikamiUitOpen	4:c1beacfc42c7	743
MikamiUitOpen	4:c1beacfc42c7	744
MikamiUitOpen	4:c1beacfc42c7	745	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	746	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
MikamiUitOpen	4:c1beacfc42c7	747	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
MikamiUitOpen	4:c1beacfc42c7	748	@{
MikamiUitOpen	4:c1beacfc42c7	749	*/
MikamiUitOpen	4:c1beacfc42c7	750
MikamiUitOpen	4:c1beacfc42c7	751	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
MikamiUitOpen	4:c1beacfc42c7	752	*/
MikamiUitOpen	4:c1beacfc42c7	753	typedef struct
MikamiUitOpen	4:c1beacfc42c7	754	{
MikamiUitOpen	4:c1beacfc42c7	755	__O union
MikamiUitOpen	4:c1beacfc42c7	756	{
MikamiUitOpen	4:c1beacfc42c7	757	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
MikamiUitOpen	4:c1beacfc42c7	758	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
MikamiUitOpen	4:c1beacfc42c7	759	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
MikamiUitOpen	4:c1beacfc42c7	760	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
MikamiUitOpen	4:c1beacfc42c7	761	uint32_t RESERVED0[864];
MikamiUitOpen	4:c1beacfc42c7	762	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
MikamiUitOpen	4:c1beacfc42c7	763	uint32_t RESERVED1[15];
MikamiUitOpen	4:c1beacfc42c7	764	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
MikamiUitOpen	4:c1beacfc42c7	765	uint32_t RESERVED2[15];
MikamiUitOpen	4:c1beacfc42c7	766	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
MikamiUitOpen	4:c1beacfc42c7	767	uint32_t RESERVED3[29];
MikamiUitOpen	4:c1beacfc42c7	768	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
MikamiUitOpen	4:c1beacfc42c7	769	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
MikamiUitOpen	4:c1beacfc42c7	770	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
MikamiUitOpen	4:c1beacfc42c7	771	uint32_t RESERVED4[43];
MikamiUitOpen	4:c1beacfc42c7	772	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
MikamiUitOpen	4:c1beacfc42c7	773	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
MikamiUitOpen	4:c1beacfc42c7	774	uint32_t RESERVED5[6];
MikamiUitOpen	4:c1beacfc42c7	775	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
MikamiUitOpen	4:c1beacfc42c7	776	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
MikamiUitOpen	4:c1beacfc42c7	777	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
MikamiUitOpen	4:c1beacfc42c7	778	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
MikamiUitOpen	4:c1beacfc42c7	779	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
MikamiUitOpen	4:c1beacfc42c7	780	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
MikamiUitOpen	4:c1beacfc42c7	781	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
MikamiUitOpen	4:c1beacfc42c7	782	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
MikamiUitOpen	4:c1beacfc42c7	783	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
MikamiUitOpen	4:c1beacfc42c7	784	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
MikamiUitOpen	4:c1beacfc42c7	785	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
MikamiUitOpen	4:c1beacfc42c7	786	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
MikamiUitOpen	4:c1beacfc42c7	787	} ITM_Type;
MikamiUitOpen	4:c1beacfc42c7	788
MikamiUitOpen	4:c1beacfc42c7	789	/* ITM Trace Privilege Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	790	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
MikamiUitOpen	4:c1beacfc42c7	791	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
MikamiUitOpen	4:c1beacfc42c7	792
MikamiUitOpen	4:c1beacfc42c7	793	/* ITM Trace Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	794	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
MikamiUitOpen	4:c1beacfc42c7	795	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
MikamiUitOpen	4:c1beacfc42c7	796
MikamiUitOpen	4:c1beacfc42c7	797	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
MikamiUitOpen	4:c1beacfc42c7	798	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
MikamiUitOpen	4:c1beacfc42c7	799
MikamiUitOpen	4:c1beacfc42c7	800	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
MikamiUitOpen	4:c1beacfc42c7	801	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
MikamiUitOpen	4:c1beacfc42c7	802
MikamiUitOpen	4:c1beacfc42c7	803	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
MikamiUitOpen	4:c1beacfc42c7	804	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
MikamiUitOpen	4:c1beacfc42c7	805
MikamiUitOpen	4:c1beacfc42c7	806	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
MikamiUitOpen	4:c1beacfc42c7	807	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
MikamiUitOpen	4:c1beacfc42c7	808
MikamiUitOpen	4:c1beacfc42c7	809	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
MikamiUitOpen	4:c1beacfc42c7	810	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	811
MikamiUitOpen	4:c1beacfc42c7	812	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
MikamiUitOpen	4:c1beacfc42c7	813	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
MikamiUitOpen	4:c1beacfc42c7	814
MikamiUitOpen	4:c1beacfc42c7	815	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
MikamiUitOpen	4:c1beacfc42c7	816	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
MikamiUitOpen	4:c1beacfc42c7	817
MikamiUitOpen	4:c1beacfc42c7	818	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
MikamiUitOpen	4:c1beacfc42c7	819	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
MikamiUitOpen	4:c1beacfc42c7	820
MikamiUitOpen	4:c1beacfc42c7	821	/* ITM Integration Write Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	822	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
MikamiUitOpen	4:c1beacfc42c7	823	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
MikamiUitOpen	4:c1beacfc42c7	824
MikamiUitOpen	4:c1beacfc42c7	825	/* ITM Integration Read Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	826	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
MikamiUitOpen	4:c1beacfc42c7	827	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
MikamiUitOpen	4:c1beacfc42c7	828
MikamiUitOpen	4:c1beacfc42c7	829	/* ITM Integration Mode Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	830	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
MikamiUitOpen	4:c1beacfc42c7	831	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
MikamiUitOpen	4:c1beacfc42c7	832
MikamiUitOpen	4:c1beacfc42c7	833	/* ITM Lock Status Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	834	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
MikamiUitOpen	4:c1beacfc42c7	835	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
MikamiUitOpen	4:c1beacfc42c7	836
MikamiUitOpen	4:c1beacfc42c7	837	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
MikamiUitOpen	4:c1beacfc42c7	838	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
MikamiUitOpen	4:c1beacfc42c7	839
MikamiUitOpen	4:c1beacfc42c7	840	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
MikamiUitOpen	4:c1beacfc42c7	841	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
MikamiUitOpen	4:c1beacfc42c7	842
MikamiUitOpen	4:c1beacfc42c7	843	/@}/ /* end of group CMSIS_ITM */
MikamiUitOpen	4:c1beacfc42c7	844
MikamiUitOpen	4:c1beacfc42c7	845
MikamiUitOpen	4:c1beacfc42c7	846	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	847	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
MikamiUitOpen	4:c1beacfc42c7	848	\brief Type definitions for the Data Watchpoint and Trace (DWT)
MikamiUitOpen	4:c1beacfc42c7	849	@{
MikamiUitOpen	4:c1beacfc42c7	850	*/
MikamiUitOpen	4:c1beacfc42c7	851
MikamiUitOpen	4:c1beacfc42c7	852	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
MikamiUitOpen	4:c1beacfc42c7	853	*/
MikamiUitOpen	4:c1beacfc42c7	854	typedef struct
MikamiUitOpen	4:c1beacfc42c7	855	{
MikamiUitOpen	4:c1beacfc42c7	856	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
MikamiUitOpen	4:c1beacfc42c7	857	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
MikamiUitOpen	4:c1beacfc42c7	858	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
MikamiUitOpen	4:c1beacfc42c7	859	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
MikamiUitOpen	4:c1beacfc42c7	860	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
MikamiUitOpen	4:c1beacfc42c7	861	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
MikamiUitOpen	4:c1beacfc42c7	862	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
MikamiUitOpen	4:c1beacfc42c7	863	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
MikamiUitOpen	4:c1beacfc42c7	864	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
MikamiUitOpen	4:c1beacfc42c7	865	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
MikamiUitOpen	4:c1beacfc42c7	866	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
MikamiUitOpen	4:c1beacfc42c7	867	uint32_t RESERVED0[1];
MikamiUitOpen	4:c1beacfc42c7	868	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
MikamiUitOpen	4:c1beacfc42c7	869	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
MikamiUitOpen	4:c1beacfc42c7	870	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
MikamiUitOpen	4:c1beacfc42c7	871	uint32_t RESERVED1[1];
MikamiUitOpen	4:c1beacfc42c7	872	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
MikamiUitOpen	4:c1beacfc42c7	873	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
MikamiUitOpen	4:c1beacfc42c7	874	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
MikamiUitOpen	4:c1beacfc42c7	875	uint32_t RESERVED2[1];
MikamiUitOpen	4:c1beacfc42c7	876	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
MikamiUitOpen	4:c1beacfc42c7	877	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
MikamiUitOpen	4:c1beacfc42c7	878	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
MikamiUitOpen	4:c1beacfc42c7	879	} DWT_Type;
MikamiUitOpen	4:c1beacfc42c7	880
MikamiUitOpen	4:c1beacfc42c7	881	/* DWT Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	882	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
MikamiUitOpen	4:c1beacfc42c7	883	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
MikamiUitOpen	4:c1beacfc42c7	884
MikamiUitOpen	4:c1beacfc42c7	885	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
MikamiUitOpen	4:c1beacfc42c7	886	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
MikamiUitOpen	4:c1beacfc42c7	887
MikamiUitOpen	4:c1beacfc42c7	888	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
MikamiUitOpen	4:c1beacfc42c7	889	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
MikamiUitOpen	4:c1beacfc42c7	890
MikamiUitOpen	4:c1beacfc42c7	891	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
MikamiUitOpen	4:c1beacfc42c7	892	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
MikamiUitOpen	4:c1beacfc42c7	893
MikamiUitOpen	4:c1beacfc42c7	894	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
MikamiUitOpen	4:c1beacfc42c7	895	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
MikamiUitOpen	4:c1beacfc42c7	896
MikamiUitOpen	4:c1beacfc42c7	897	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
MikamiUitOpen	4:c1beacfc42c7	898	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	899
MikamiUitOpen	4:c1beacfc42c7	900	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
MikamiUitOpen	4:c1beacfc42c7	901	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	902
MikamiUitOpen	4:c1beacfc42c7	903	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
MikamiUitOpen	4:c1beacfc42c7	904	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	905
MikamiUitOpen	4:c1beacfc42c7	906	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
MikamiUitOpen	4:c1beacfc42c7	907	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	908
MikamiUitOpen	4:c1beacfc42c7	909	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
MikamiUitOpen	4:c1beacfc42c7	910	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	911
MikamiUitOpen	4:c1beacfc42c7	912	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
MikamiUitOpen	4:c1beacfc42c7	913	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	914
MikamiUitOpen	4:c1beacfc42c7	915	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
MikamiUitOpen	4:c1beacfc42c7	916	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
MikamiUitOpen	4:c1beacfc42c7	917
MikamiUitOpen	4:c1beacfc42c7	918	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
MikamiUitOpen	4:c1beacfc42c7	919	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
MikamiUitOpen	4:c1beacfc42c7	920
MikamiUitOpen	4:c1beacfc42c7	921	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
MikamiUitOpen	4:c1beacfc42c7	922	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
MikamiUitOpen	4:c1beacfc42c7	923
MikamiUitOpen	4:c1beacfc42c7	924	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
MikamiUitOpen	4:c1beacfc42c7	925	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
MikamiUitOpen	4:c1beacfc42c7	926
MikamiUitOpen	4:c1beacfc42c7	927	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
MikamiUitOpen	4:c1beacfc42c7	928	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
MikamiUitOpen	4:c1beacfc42c7	929
MikamiUitOpen	4:c1beacfc42c7	930	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
MikamiUitOpen	4:c1beacfc42c7	931	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
MikamiUitOpen	4:c1beacfc42c7	932
MikamiUitOpen	4:c1beacfc42c7	933	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
MikamiUitOpen	4:c1beacfc42c7	934	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
MikamiUitOpen	4:c1beacfc42c7	935
MikamiUitOpen	4:c1beacfc42c7	936	/* DWT CPI Count Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	937	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
MikamiUitOpen	4:c1beacfc42c7	938	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
MikamiUitOpen	4:c1beacfc42c7	939
MikamiUitOpen	4:c1beacfc42c7	940	/* DWT Exception Overhead Count Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	941	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
MikamiUitOpen	4:c1beacfc42c7	942	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
MikamiUitOpen	4:c1beacfc42c7	943
MikamiUitOpen	4:c1beacfc42c7	944	/* DWT Sleep Count Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	945	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
MikamiUitOpen	4:c1beacfc42c7	946	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
MikamiUitOpen	4:c1beacfc42c7	947
MikamiUitOpen	4:c1beacfc42c7	948	/* DWT LSU Count Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	949	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
MikamiUitOpen	4:c1beacfc42c7	950	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
MikamiUitOpen	4:c1beacfc42c7	951
MikamiUitOpen	4:c1beacfc42c7	952	/* DWT Folded-instruction Count Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	953	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
MikamiUitOpen	4:c1beacfc42c7	954	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
MikamiUitOpen	4:c1beacfc42c7	955
MikamiUitOpen	4:c1beacfc42c7	956	/* DWT Comparator Mask Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	957	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
MikamiUitOpen	4:c1beacfc42c7	958	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
MikamiUitOpen	4:c1beacfc42c7	959
MikamiUitOpen	4:c1beacfc42c7	960	/* DWT Comparator Function Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	961	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
MikamiUitOpen	4:c1beacfc42c7	962	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
MikamiUitOpen	4:c1beacfc42c7	963
MikamiUitOpen	4:c1beacfc42c7	964	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
MikamiUitOpen	4:c1beacfc42c7	965	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
MikamiUitOpen	4:c1beacfc42c7	966
MikamiUitOpen	4:c1beacfc42c7	967	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
MikamiUitOpen	4:c1beacfc42c7	968	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
MikamiUitOpen	4:c1beacfc42c7	969
MikamiUitOpen	4:c1beacfc42c7	970	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
MikamiUitOpen	4:c1beacfc42c7	971	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
MikamiUitOpen	4:c1beacfc42c7	972
MikamiUitOpen	4:c1beacfc42c7	973	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
MikamiUitOpen	4:c1beacfc42c7	974	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
MikamiUitOpen	4:c1beacfc42c7	975
MikamiUitOpen	4:c1beacfc42c7	976	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
MikamiUitOpen	4:c1beacfc42c7	977	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
MikamiUitOpen	4:c1beacfc42c7	978
MikamiUitOpen	4:c1beacfc42c7	979	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
MikamiUitOpen	4:c1beacfc42c7	980	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
MikamiUitOpen	4:c1beacfc42c7	981
MikamiUitOpen	4:c1beacfc42c7	982	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
MikamiUitOpen	4:c1beacfc42c7	983	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
MikamiUitOpen	4:c1beacfc42c7	984
MikamiUitOpen	4:c1beacfc42c7	985	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
MikamiUitOpen	4:c1beacfc42c7	986	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
MikamiUitOpen	4:c1beacfc42c7	987
MikamiUitOpen	4:c1beacfc42c7	988	/@}/ /* end of group CMSIS_DWT */
MikamiUitOpen	4:c1beacfc42c7	989
MikamiUitOpen	4:c1beacfc42c7	990
MikamiUitOpen	4:c1beacfc42c7	991	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	992	\defgroup CMSIS_TPI Trace Port Interface (TPI)
MikamiUitOpen	4:c1beacfc42c7	993	\brief Type definitions for the Trace Port Interface (TPI)
MikamiUitOpen	4:c1beacfc42c7	994	@{
MikamiUitOpen	4:c1beacfc42c7	995	*/
MikamiUitOpen	4:c1beacfc42c7	996
MikamiUitOpen	4:c1beacfc42c7	997	/** \brief Structure type to access the Trace Port Interface Register (TPI).
MikamiUitOpen	4:c1beacfc42c7	998	*/
MikamiUitOpen	4:c1beacfc42c7	999	typedef struct
MikamiUitOpen	4:c1beacfc42c7	1000	{
MikamiUitOpen	4:c1beacfc42c7	1001	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
MikamiUitOpen	4:c1beacfc42c7	1002	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
MikamiUitOpen	4:c1beacfc42c7	1003	uint32_t RESERVED0[2];
MikamiUitOpen	4:c1beacfc42c7	1004	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
MikamiUitOpen	4:c1beacfc42c7	1005	uint32_t RESERVED1[55];
MikamiUitOpen	4:c1beacfc42c7	1006	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
MikamiUitOpen	4:c1beacfc42c7	1007	uint32_t RESERVED2[131];
MikamiUitOpen	4:c1beacfc42c7	1008	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
MikamiUitOpen	4:c1beacfc42c7	1009	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
MikamiUitOpen	4:c1beacfc42c7	1010	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
MikamiUitOpen	4:c1beacfc42c7	1011	uint32_t RESERVED3[759];
MikamiUitOpen	4:c1beacfc42c7	1012	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
MikamiUitOpen	4:c1beacfc42c7	1013	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
MikamiUitOpen	4:c1beacfc42c7	1014	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
MikamiUitOpen	4:c1beacfc42c7	1015	uint32_t RESERVED4[1];
MikamiUitOpen	4:c1beacfc42c7	1016	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
MikamiUitOpen	4:c1beacfc42c7	1017	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
MikamiUitOpen	4:c1beacfc42c7	1018	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
MikamiUitOpen	4:c1beacfc42c7	1019	uint32_t RESERVED5[39];
MikamiUitOpen	4:c1beacfc42c7	1020	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
MikamiUitOpen	4:c1beacfc42c7	1021	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
MikamiUitOpen	4:c1beacfc42c7	1022	uint32_t RESERVED7[8];
MikamiUitOpen	4:c1beacfc42c7	1023	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
MikamiUitOpen	4:c1beacfc42c7	1024	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
MikamiUitOpen	4:c1beacfc42c7	1025	} TPI_Type;
MikamiUitOpen	4:c1beacfc42c7	1026
MikamiUitOpen	4:c1beacfc42c7	1027	/* TPI Asynchronous Clock Prescaler Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1028	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
MikamiUitOpen	4:c1beacfc42c7	1029	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
MikamiUitOpen	4:c1beacfc42c7	1030
MikamiUitOpen	4:c1beacfc42c7	1031	/* TPI Selected Pin Protocol Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1032	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
MikamiUitOpen	4:c1beacfc42c7	1033	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
MikamiUitOpen	4:c1beacfc42c7	1034
MikamiUitOpen	4:c1beacfc42c7	1035	/* TPI Formatter and Flush Status Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1036	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
MikamiUitOpen	4:c1beacfc42c7	1037	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
MikamiUitOpen	4:c1beacfc42c7	1038
MikamiUitOpen	4:c1beacfc42c7	1039	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
MikamiUitOpen	4:c1beacfc42c7	1040	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
MikamiUitOpen	4:c1beacfc42c7	1041
MikamiUitOpen	4:c1beacfc42c7	1042	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
MikamiUitOpen	4:c1beacfc42c7	1043	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
MikamiUitOpen	4:c1beacfc42c7	1044
MikamiUitOpen	4:c1beacfc42c7	1045	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
MikamiUitOpen	4:c1beacfc42c7	1046	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
MikamiUitOpen	4:c1beacfc42c7	1047
MikamiUitOpen	4:c1beacfc42c7	1048	/* TPI Formatter and Flush Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1049	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
MikamiUitOpen	4:c1beacfc42c7	1050	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
MikamiUitOpen	4:c1beacfc42c7	1051
MikamiUitOpen	4:c1beacfc42c7	1052	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
MikamiUitOpen	4:c1beacfc42c7	1053	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
MikamiUitOpen	4:c1beacfc42c7	1054
MikamiUitOpen	4:c1beacfc42c7	1055	/* TPI TRIGGER Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1056	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
MikamiUitOpen	4:c1beacfc42c7	1057	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
MikamiUitOpen	4:c1beacfc42c7	1058
MikamiUitOpen	4:c1beacfc42c7	1059	/* TPI Integration ETM Data Register Definitions (FIFO0) */
MikamiUitOpen	4:c1beacfc42c7	1060	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
MikamiUitOpen	4:c1beacfc42c7	1061	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1062
MikamiUitOpen	4:c1beacfc42c7	1063	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
MikamiUitOpen	4:c1beacfc42c7	1064	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
MikamiUitOpen	4:c1beacfc42c7	1065
MikamiUitOpen	4:c1beacfc42c7	1066	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
MikamiUitOpen	4:c1beacfc42c7	1067	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1068
MikamiUitOpen	4:c1beacfc42c7	1069	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
MikamiUitOpen	4:c1beacfc42c7	1070	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
MikamiUitOpen	4:c1beacfc42c7	1071
MikamiUitOpen	4:c1beacfc42c7	1072	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
MikamiUitOpen	4:c1beacfc42c7	1073	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
MikamiUitOpen	4:c1beacfc42c7	1074
MikamiUitOpen	4:c1beacfc42c7	1075	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
MikamiUitOpen	4:c1beacfc42c7	1076	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
MikamiUitOpen	4:c1beacfc42c7	1077
MikamiUitOpen	4:c1beacfc42c7	1078	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
MikamiUitOpen	4:c1beacfc42c7	1079	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
MikamiUitOpen	4:c1beacfc42c7	1080
MikamiUitOpen	4:c1beacfc42c7	1081	/* TPI ITATBCTR2 Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1082	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
MikamiUitOpen	4:c1beacfc42c7	1083	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
MikamiUitOpen	4:c1beacfc42c7	1084
MikamiUitOpen	4:c1beacfc42c7	1085	/* TPI Integration ITM Data Register Definitions (FIFO1) */
MikamiUitOpen	4:c1beacfc42c7	1086	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
MikamiUitOpen	4:c1beacfc42c7	1087	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1088
MikamiUitOpen	4:c1beacfc42c7	1089	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
MikamiUitOpen	4:c1beacfc42c7	1090	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
MikamiUitOpen	4:c1beacfc42c7	1091
MikamiUitOpen	4:c1beacfc42c7	1092	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
MikamiUitOpen	4:c1beacfc42c7	1093	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1094
MikamiUitOpen	4:c1beacfc42c7	1095	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
MikamiUitOpen	4:c1beacfc42c7	1096	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
MikamiUitOpen	4:c1beacfc42c7	1097
MikamiUitOpen	4:c1beacfc42c7	1098	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
MikamiUitOpen	4:c1beacfc42c7	1099	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
MikamiUitOpen	4:c1beacfc42c7	1100
MikamiUitOpen	4:c1beacfc42c7	1101	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
MikamiUitOpen	4:c1beacfc42c7	1102	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
MikamiUitOpen	4:c1beacfc42c7	1103
MikamiUitOpen	4:c1beacfc42c7	1104	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
MikamiUitOpen	4:c1beacfc42c7	1105	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
MikamiUitOpen	4:c1beacfc42c7	1106
MikamiUitOpen	4:c1beacfc42c7	1107	/* TPI ITATBCTR0 Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1108	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
MikamiUitOpen	4:c1beacfc42c7	1109	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
MikamiUitOpen	4:c1beacfc42c7	1110
MikamiUitOpen	4:c1beacfc42c7	1111	/* TPI Integration Mode Control Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1112	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
MikamiUitOpen	4:c1beacfc42c7	1113	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
MikamiUitOpen	4:c1beacfc42c7	1114
MikamiUitOpen	4:c1beacfc42c7	1115	/* TPI DEVID Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1116	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
MikamiUitOpen	4:c1beacfc42c7	1117	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1118
MikamiUitOpen	4:c1beacfc42c7	1119	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
MikamiUitOpen	4:c1beacfc42c7	1120	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1121
MikamiUitOpen	4:c1beacfc42c7	1122	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
MikamiUitOpen	4:c1beacfc42c7	1123	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1124
MikamiUitOpen	4:c1beacfc42c7	1125	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
MikamiUitOpen	4:c1beacfc42c7	1126	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
MikamiUitOpen	4:c1beacfc42c7	1127
MikamiUitOpen	4:c1beacfc42c7	1128	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
MikamiUitOpen	4:c1beacfc42c7	1129	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
MikamiUitOpen	4:c1beacfc42c7	1130
MikamiUitOpen	4:c1beacfc42c7	1131	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
MikamiUitOpen	4:c1beacfc42c7	1132	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
MikamiUitOpen	4:c1beacfc42c7	1133
MikamiUitOpen	4:c1beacfc42c7	1134	/* TPI DEVTYPE Register Definitions */
MikamiUitOpen	4:c1beacfc42c7	1135	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
MikamiUitOpen	4:c1beacfc42c7	1136	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
MikamiUitOpen	4:c1beacfc42c7	1137
MikamiUitOpen	4:c1beacfc42c7	1138	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
MikamiUitOpen	4:c1beacfc42c7	1139	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
MikamiUitOpen	4:c1beacfc42c7	1140
MikamiUitOpen	4:c1beacfc42c7	1141	/@}/ /* end of group CMSIS_TPI */
MikamiUitOpen	4:c1beacfc42c7	1142
MikamiUitOpen	4:c1beacfc42c7	1143
MikamiUitOpen	4:c1beacfc42c7	1144	#if (__MPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	1145	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	1146	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
MikamiUitOpen	4:c1beacfc42c7	1147	\brief Type definitions for the Memory Protection Unit (MPU)
MikamiUitOpen	4:c1beacfc42c7	1148	@{
MikamiUitOpen	4:c1beacfc42c7	1149	*/
MikamiUitOpen	4:c1beacfc42c7	1150
MikamiUitOpen	4:c1beacfc42c7	1151	/** \brief Structure type to access the Memory Protection Unit (MPU).
MikamiUitOpen	4:c1beacfc42c7	1152	*/
MikamiUitOpen	4:c1beacfc42c7	1153	typedef struct
MikamiUitOpen	4:c1beacfc42c7	1154	{
MikamiUitOpen	4:c1beacfc42c7	1155	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
MikamiUitOpen	4:c1beacfc42c7	1156	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
MikamiUitOpen	4:c1beacfc42c7	1157	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
MikamiUitOpen	4:c1beacfc42c7	1158	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
MikamiUitOpen	4:c1beacfc42c7	1159	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
MikamiUitOpen	4:c1beacfc42c7	1160	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
MikamiUitOpen	4:c1beacfc42c7	1161	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
MikamiUitOpen	4:c1beacfc42c7	1162	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
MikamiUitOpen	4:c1beacfc42c7	1163	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
MikamiUitOpen	4:c1beacfc42c7	1164	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
MikamiUitOpen	4:c1beacfc42c7	1165	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
MikamiUitOpen	4:c1beacfc42c7	1166	} MPU_Type;
MikamiUitOpen	4:c1beacfc42c7	1167
MikamiUitOpen	4:c1beacfc42c7	1168	/* MPU Type Register */
MikamiUitOpen	4:c1beacfc42c7	1169	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
MikamiUitOpen	4:c1beacfc42c7	1170	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
MikamiUitOpen	4:c1beacfc42c7	1171
MikamiUitOpen	4:c1beacfc42c7	1172	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
MikamiUitOpen	4:c1beacfc42c7	1173	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
MikamiUitOpen	4:c1beacfc42c7	1174
MikamiUitOpen	4:c1beacfc42c7	1175	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
MikamiUitOpen	4:c1beacfc42c7	1176	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
MikamiUitOpen	4:c1beacfc42c7	1177
MikamiUitOpen	4:c1beacfc42c7	1178	/* MPU Control Register */
MikamiUitOpen	4:c1beacfc42c7	1179	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
MikamiUitOpen	4:c1beacfc42c7	1180	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
MikamiUitOpen	4:c1beacfc42c7	1181
MikamiUitOpen	4:c1beacfc42c7	1182	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
MikamiUitOpen	4:c1beacfc42c7	1183	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
MikamiUitOpen	4:c1beacfc42c7	1184
MikamiUitOpen	4:c1beacfc42c7	1185	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
MikamiUitOpen	4:c1beacfc42c7	1186	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
MikamiUitOpen	4:c1beacfc42c7	1187
MikamiUitOpen	4:c1beacfc42c7	1188	/* MPU Region Number Register */
MikamiUitOpen	4:c1beacfc42c7	1189	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
MikamiUitOpen	4:c1beacfc42c7	1190	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
MikamiUitOpen	4:c1beacfc42c7	1191
MikamiUitOpen	4:c1beacfc42c7	1192	/* MPU Region Base Address Register */
MikamiUitOpen	4:c1beacfc42c7	1193	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
MikamiUitOpen	4:c1beacfc42c7	1194	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
MikamiUitOpen	4:c1beacfc42c7	1195
MikamiUitOpen	4:c1beacfc42c7	1196	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
MikamiUitOpen	4:c1beacfc42c7	1197	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
MikamiUitOpen	4:c1beacfc42c7	1198
MikamiUitOpen	4:c1beacfc42c7	1199	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
MikamiUitOpen	4:c1beacfc42c7	1200	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
MikamiUitOpen	4:c1beacfc42c7	1201
MikamiUitOpen	4:c1beacfc42c7	1202	/* MPU Region Attribute and Size Register */
MikamiUitOpen	4:c1beacfc42c7	1203	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
MikamiUitOpen	4:c1beacfc42c7	1204	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
MikamiUitOpen	4:c1beacfc42c7	1205
MikamiUitOpen	4:c1beacfc42c7	1206	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
MikamiUitOpen	4:c1beacfc42c7	1207	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
MikamiUitOpen	4:c1beacfc42c7	1208
MikamiUitOpen	4:c1beacfc42c7	1209	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
MikamiUitOpen	4:c1beacfc42c7	1210	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
MikamiUitOpen	4:c1beacfc42c7	1211
MikamiUitOpen	4:c1beacfc42c7	1212	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
MikamiUitOpen	4:c1beacfc42c7	1213	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
MikamiUitOpen	4:c1beacfc42c7	1214
MikamiUitOpen	4:c1beacfc42c7	1215	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
MikamiUitOpen	4:c1beacfc42c7	1216	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
MikamiUitOpen	4:c1beacfc42c7	1217
MikamiUitOpen	4:c1beacfc42c7	1218	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
MikamiUitOpen	4:c1beacfc42c7	1219	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
MikamiUitOpen	4:c1beacfc42c7	1220
MikamiUitOpen	4:c1beacfc42c7	1221	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
MikamiUitOpen	4:c1beacfc42c7	1222	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
MikamiUitOpen	4:c1beacfc42c7	1223
MikamiUitOpen	4:c1beacfc42c7	1224	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
MikamiUitOpen	4:c1beacfc42c7	1225	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
MikamiUitOpen	4:c1beacfc42c7	1226
MikamiUitOpen	4:c1beacfc42c7	1227	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
MikamiUitOpen	4:c1beacfc42c7	1228	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
MikamiUitOpen	4:c1beacfc42c7	1229
MikamiUitOpen	4:c1beacfc42c7	1230	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
MikamiUitOpen	4:c1beacfc42c7	1231	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
MikamiUitOpen	4:c1beacfc42c7	1232
MikamiUitOpen	4:c1beacfc42c7	1233	/@} end of group CMSIS_MPU /
MikamiUitOpen	4:c1beacfc42c7	1234	#endif
MikamiUitOpen	4:c1beacfc42c7	1235
MikamiUitOpen	4:c1beacfc42c7	1236
MikamiUitOpen	4:c1beacfc42c7	1237	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	1238	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	1239	\defgroup CMSIS_FPU Floating Point Unit (FPU)
MikamiUitOpen	4:c1beacfc42c7	1240	\brief Type definitions for the Floating Point Unit (FPU)
MikamiUitOpen	4:c1beacfc42c7	1241	@{
MikamiUitOpen	4:c1beacfc42c7	1242	*/
MikamiUitOpen	4:c1beacfc42c7	1243
MikamiUitOpen	4:c1beacfc42c7	1244	/** \brief Structure type to access the Floating Point Unit (FPU).
MikamiUitOpen	4:c1beacfc42c7	1245	*/
MikamiUitOpen	4:c1beacfc42c7	1246	typedef struct
MikamiUitOpen	4:c1beacfc42c7	1247	{
MikamiUitOpen	4:c1beacfc42c7	1248	uint32_t RESERVED0[1];
MikamiUitOpen	4:c1beacfc42c7	1249	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
MikamiUitOpen	4:c1beacfc42c7	1250	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
MikamiUitOpen	4:c1beacfc42c7	1251	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
MikamiUitOpen	4:c1beacfc42c7	1252	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
MikamiUitOpen	4:c1beacfc42c7	1253	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
MikamiUitOpen	4:c1beacfc42c7	1254	} FPU_Type;
MikamiUitOpen	4:c1beacfc42c7	1255
MikamiUitOpen	4:c1beacfc42c7	1256	/* Floating-Point Context Control Register */
MikamiUitOpen	4:c1beacfc42c7	1257	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
MikamiUitOpen	4:c1beacfc42c7	1258	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1259
MikamiUitOpen	4:c1beacfc42c7	1260	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
MikamiUitOpen	4:c1beacfc42c7	1261	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1262
MikamiUitOpen	4:c1beacfc42c7	1263	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
MikamiUitOpen	4:c1beacfc42c7	1264	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1265
MikamiUitOpen	4:c1beacfc42c7	1266	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
MikamiUitOpen	4:c1beacfc42c7	1267	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1268
MikamiUitOpen	4:c1beacfc42c7	1269	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
MikamiUitOpen	4:c1beacfc42c7	1270	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1271
MikamiUitOpen	4:c1beacfc42c7	1272	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
MikamiUitOpen	4:c1beacfc42c7	1273	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1274
MikamiUitOpen	4:c1beacfc42c7	1275	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
MikamiUitOpen	4:c1beacfc42c7	1276	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1277
MikamiUitOpen	4:c1beacfc42c7	1278	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
MikamiUitOpen	4:c1beacfc42c7	1279	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1280
MikamiUitOpen	4:c1beacfc42c7	1281	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
MikamiUitOpen	4:c1beacfc42c7	1282	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1283
MikamiUitOpen	4:c1beacfc42c7	1284	/* Floating-Point Context Address Register */
MikamiUitOpen	4:c1beacfc42c7	1285	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
MikamiUitOpen	4:c1beacfc42c7	1286	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1287
MikamiUitOpen	4:c1beacfc42c7	1288	/* Floating-Point Default Status Control Register */
MikamiUitOpen	4:c1beacfc42c7	1289	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
MikamiUitOpen	4:c1beacfc42c7	1290	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1291
MikamiUitOpen	4:c1beacfc42c7	1292	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
MikamiUitOpen	4:c1beacfc42c7	1293	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1294
MikamiUitOpen	4:c1beacfc42c7	1295	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
MikamiUitOpen	4:c1beacfc42c7	1296	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1297
MikamiUitOpen	4:c1beacfc42c7	1298	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
MikamiUitOpen	4:c1beacfc42c7	1299	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
MikamiUitOpen	4:c1beacfc42c7	1300
MikamiUitOpen	4:c1beacfc42c7	1301	/* Media and FP Feature Register 0 */
MikamiUitOpen	4:c1beacfc42c7	1302	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
MikamiUitOpen	4:c1beacfc42c7	1303	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1304
MikamiUitOpen	4:c1beacfc42c7	1305	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
MikamiUitOpen	4:c1beacfc42c7	1306	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1307
MikamiUitOpen	4:c1beacfc42c7	1308	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
MikamiUitOpen	4:c1beacfc42c7	1309	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1310
MikamiUitOpen	4:c1beacfc42c7	1311	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
MikamiUitOpen	4:c1beacfc42c7	1312	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1313
MikamiUitOpen	4:c1beacfc42c7	1314	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
MikamiUitOpen	4:c1beacfc42c7	1315	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1316
MikamiUitOpen	4:c1beacfc42c7	1317	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
MikamiUitOpen	4:c1beacfc42c7	1318	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1319
MikamiUitOpen	4:c1beacfc42c7	1320	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
MikamiUitOpen	4:c1beacfc42c7	1321	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1322
MikamiUitOpen	4:c1beacfc42c7	1323	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
MikamiUitOpen	4:c1beacfc42c7	1324	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1325
MikamiUitOpen	4:c1beacfc42c7	1326	/* Media and FP Feature Register 1 */
MikamiUitOpen	4:c1beacfc42c7	1327	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
MikamiUitOpen	4:c1beacfc42c7	1328	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1329
MikamiUitOpen	4:c1beacfc42c7	1330	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
MikamiUitOpen	4:c1beacfc42c7	1331	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1332
MikamiUitOpen	4:c1beacfc42c7	1333	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
MikamiUitOpen	4:c1beacfc42c7	1334	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1335
MikamiUitOpen	4:c1beacfc42c7	1336	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
MikamiUitOpen	4:c1beacfc42c7	1337	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
MikamiUitOpen	4:c1beacfc42c7	1338
MikamiUitOpen	4:c1beacfc42c7	1339	/@} end of group CMSIS_FPU /
MikamiUitOpen	4:c1beacfc42c7	1340	#endif
MikamiUitOpen	4:c1beacfc42c7	1341
MikamiUitOpen	4:c1beacfc42c7	1342
MikamiUitOpen	4:c1beacfc42c7	1343	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	1344	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MikamiUitOpen	4:c1beacfc42c7	1345	\brief Type definitions for the Core Debug Registers
MikamiUitOpen	4:c1beacfc42c7	1346	@{
MikamiUitOpen	4:c1beacfc42c7	1347	*/
MikamiUitOpen	4:c1beacfc42c7	1348
MikamiUitOpen	4:c1beacfc42c7	1349	/** \brief Structure type to access the Core Debug Register (CoreDebug).
MikamiUitOpen	4:c1beacfc42c7	1350	*/
MikamiUitOpen	4:c1beacfc42c7	1351	typedef struct
MikamiUitOpen	4:c1beacfc42c7	1352	{
MikamiUitOpen	4:c1beacfc42c7	1353	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
MikamiUitOpen	4:c1beacfc42c7	1354	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
MikamiUitOpen	4:c1beacfc42c7	1355	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
MikamiUitOpen	4:c1beacfc42c7	1356	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
MikamiUitOpen	4:c1beacfc42c7	1357	} CoreDebug_Type;
MikamiUitOpen	4:c1beacfc42c7	1358
MikamiUitOpen	4:c1beacfc42c7	1359	/* Debug Halting Control and Status Register */
MikamiUitOpen	4:c1beacfc42c7	1360	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
MikamiUitOpen	4:c1beacfc42c7	1361	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
MikamiUitOpen	4:c1beacfc42c7	1362
MikamiUitOpen	4:c1beacfc42c7	1363	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
MikamiUitOpen	4:c1beacfc42c7	1364	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
MikamiUitOpen	4:c1beacfc42c7	1365
MikamiUitOpen	4:c1beacfc42c7	1366	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
MikamiUitOpen	4:c1beacfc42c7	1367	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
MikamiUitOpen	4:c1beacfc42c7	1368
MikamiUitOpen	4:c1beacfc42c7	1369	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
MikamiUitOpen	4:c1beacfc42c7	1370	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
MikamiUitOpen	4:c1beacfc42c7	1371
MikamiUitOpen	4:c1beacfc42c7	1372	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
MikamiUitOpen	4:c1beacfc42c7	1373	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
MikamiUitOpen	4:c1beacfc42c7	1374
MikamiUitOpen	4:c1beacfc42c7	1375	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
MikamiUitOpen	4:c1beacfc42c7	1376	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
MikamiUitOpen	4:c1beacfc42c7	1377
MikamiUitOpen	4:c1beacfc42c7	1378	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
MikamiUitOpen	4:c1beacfc42c7	1379	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
MikamiUitOpen	4:c1beacfc42c7	1380
MikamiUitOpen	4:c1beacfc42c7	1381	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
MikamiUitOpen	4:c1beacfc42c7	1382	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
MikamiUitOpen	4:c1beacfc42c7	1383
MikamiUitOpen	4:c1beacfc42c7	1384	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
MikamiUitOpen	4:c1beacfc42c7	1385	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
MikamiUitOpen	4:c1beacfc42c7	1386
MikamiUitOpen	4:c1beacfc42c7	1387	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
MikamiUitOpen	4:c1beacfc42c7	1388	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
MikamiUitOpen	4:c1beacfc42c7	1389
MikamiUitOpen	4:c1beacfc42c7	1390	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
MikamiUitOpen	4:c1beacfc42c7	1391	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
MikamiUitOpen	4:c1beacfc42c7	1392
MikamiUitOpen	4:c1beacfc42c7	1393	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
MikamiUitOpen	4:c1beacfc42c7	1394	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
MikamiUitOpen	4:c1beacfc42c7	1395
MikamiUitOpen	4:c1beacfc42c7	1396	/* Debug Core Register Selector Register */
MikamiUitOpen	4:c1beacfc42c7	1397	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
MikamiUitOpen	4:c1beacfc42c7	1398	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
MikamiUitOpen	4:c1beacfc42c7	1399
MikamiUitOpen	4:c1beacfc42c7	1400	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
MikamiUitOpen	4:c1beacfc42c7	1401	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
MikamiUitOpen	4:c1beacfc42c7	1402
MikamiUitOpen	4:c1beacfc42c7	1403	/* Debug Exception and Monitor Control Register */
MikamiUitOpen	4:c1beacfc42c7	1404	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
MikamiUitOpen	4:c1beacfc42c7	1405	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
MikamiUitOpen	4:c1beacfc42c7	1406
MikamiUitOpen	4:c1beacfc42c7	1407	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
MikamiUitOpen	4:c1beacfc42c7	1408	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
MikamiUitOpen	4:c1beacfc42c7	1409
MikamiUitOpen	4:c1beacfc42c7	1410	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
MikamiUitOpen	4:c1beacfc42c7	1411	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
MikamiUitOpen	4:c1beacfc42c7	1412
MikamiUitOpen	4:c1beacfc42c7	1413	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
MikamiUitOpen	4:c1beacfc42c7	1414	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
MikamiUitOpen	4:c1beacfc42c7	1415
MikamiUitOpen	4:c1beacfc42c7	1416	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
MikamiUitOpen	4:c1beacfc42c7	1417	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
MikamiUitOpen	4:c1beacfc42c7	1418
MikamiUitOpen	4:c1beacfc42c7	1419	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
MikamiUitOpen	4:c1beacfc42c7	1420	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
MikamiUitOpen	4:c1beacfc42c7	1421
MikamiUitOpen	4:c1beacfc42c7	1422	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
MikamiUitOpen	4:c1beacfc42c7	1423	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
MikamiUitOpen	4:c1beacfc42c7	1424
MikamiUitOpen	4:c1beacfc42c7	1425	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
MikamiUitOpen	4:c1beacfc42c7	1426	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
MikamiUitOpen	4:c1beacfc42c7	1427
MikamiUitOpen	4:c1beacfc42c7	1428	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
MikamiUitOpen	4:c1beacfc42c7	1429	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
MikamiUitOpen	4:c1beacfc42c7	1430
MikamiUitOpen	4:c1beacfc42c7	1431	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
MikamiUitOpen	4:c1beacfc42c7	1432	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
MikamiUitOpen	4:c1beacfc42c7	1433
MikamiUitOpen	4:c1beacfc42c7	1434	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
MikamiUitOpen	4:c1beacfc42c7	1435	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
MikamiUitOpen	4:c1beacfc42c7	1436
MikamiUitOpen	4:c1beacfc42c7	1437	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
MikamiUitOpen	4:c1beacfc42c7	1438	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
MikamiUitOpen	4:c1beacfc42c7	1439
MikamiUitOpen	4:c1beacfc42c7	1440	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
MikamiUitOpen	4:c1beacfc42c7	1441	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
MikamiUitOpen	4:c1beacfc42c7	1442
MikamiUitOpen	4:c1beacfc42c7	1443	/@} end of group CMSIS_CoreDebug /
MikamiUitOpen	4:c1beacfc42c7	1444
MikamiUitOpen	4:c1beacfc42c7	1445
MikamiUitOpen	4:c1beacfc42c7	1446	/** \ingroup CMSIS_core_register
MikamiUitOpen	4:c1beacfc42c7	1447	\defgroup CMSIS_core_base Core Definitions
MikamiUitOpen	4:c1beacfc42c7	1448	\brief Definitions for base addresses, unions, and structures.
MikamiUitOpen	4:c1beacfc42c7	1449	@{
MikamiUitOpen	4:c1beacfc42c7	1450	*/
MikamiUitOpen	4:c1beacfc42c7	1451
MikamiUitOpen	4:c1beacfc42c7	1452	/* Memory mapping of Cortex-M4 Hardware */
MikamiUitOpen	4:c1beacfc42c7	1453	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
MikamiUitOpen	4:c1beacfc42c7	1454	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
MikamiUitOpen	4:c1beacfc42c7	1455	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
MikamiUitOpen	4:c1beacfc42c7	1456	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
MikamiUitOpen	4:c1beacfc42c7	1457	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
MikamiUitOpen	4:c1beacfc42c7	1458	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
MikamiUitOpen	4:c1beacfc42c7	1459	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
MikamiUitOpen	4:c1beacfc42c7	1460	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
MikamiUitOpen	4:c1beacfc42c7	1461
MikamiUitOpen	4:c1beacfc42c7	1462	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
MikamiUitOpen	4:c1beacfc42c7	1463	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
MikamiUitOpen	4:c1beacfc42c7	1464	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
MikamiUitOpen	4:c1beacfc42c7	1465	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
MikamiUitOpen	4:c1beacfc42c7	1466	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
MikamiUitOpen	4:c1beacfc42c7	1467	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
MikamiUitOpen	4:c1beacfc42c7	1468	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
MikamiUitOpen	4:c1beacfc42c7	1469	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
MikamiUitOpen	4:c1beacfc42c7	1470
MikamiUitOpen	4:c1beacfc42c7	1471	#if (__MPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	1472	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
MikamiUitOpen	4:c1beacfc42c7	1473	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
MikamiUitOpen	4:c1beacfc42c7	1474	#endif
MikamiUitOpen	4:c1beacfc42c7	1475
MikamiUitOpen	4:c1beacfc42c7	1476	#if (__FPU_PRESENT == 1)
MikamiUitOpen	4:c1beacfc42c7	1477	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
MikamiUitOpen	4:c1beacfc42c7	1478	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
MikamiUitOpen	4:c1beacfc42c7	1479	#endif
MikamiUitOpen	4:c1beacfc42c7	1480
MikamiUitOpen	4:c1beacfc42c7	1481	/@} /
MikamiUitOpen	4:c1beacfc42c7	1482
MikamiUitOpen	4:c1beacfc42c7	1483
MikamiUitOpen	4:c1beacfc42c7	1484
MikamiUitOpen	4:c1beacfc42c7	1485	/*******************************************************************************
MikamiUitOpen	4:c1beacfc42c7	1486	* Hardware Abstraction Layer
MikamiUitOpen	4:c1beacfc42c7	1487	Core Function Interface contains:
MikamiUitOpen	4:c1beacfc42c7	1488	- Core NVIC Functions
MikamiUitOpen	4:c1beacfc42c7	1489	- Core SysTick Functions
MikamiUitOpen	4:c1beacfc42c7	1490	- Core Debug Functions
MikamiUitOpen	4:c1beacfc42c7	1491	- Core Register Access Functions
MikamiUitOpen	4:c1beacfc42c7	1492	******************************************************************************/
MikamiUitOpen	4:c1beacfc42c7	1493	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MikamiUitOpen	4:c1beacfc42c7	1494	*/
MikamiUitOpen	4:c1beacfc42c7	1495
MikamiUitOpen	4:c1beacfc42c7	1496
MikamiUitOpen	4:c1beacfc42c7	1497
MikamiUitOpen	4:c1beacfc42c7	1498	/* ########################## NVIC functions #################################### */
MikamiUitOpen	4:c1beacfc42c7	1499	/** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen	4:c1beacfc42c7	1500	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
MikamiUitOpen	4:c1beacfc42c7	1501	\brief Functions that manage interrupts and exceptions via the NVIC.
MikamiUitOpen	4:c1beacfc42c7	1502	@{
MikamiUitOpen	4:c1beacfc42c7	1503	*/
MikamiUitOpen	4:c1beacfc42c7	1504
MikamiUitOpen	4:c1beacfc42c7	1505	/** \brief Set Priority Grouping
MikamiUitOpen	4:c1beacfc42c7	1506
MikamiUitOpen	4:c1beacfc42c7	1507	The function sets the priority grouping field using the required unlock sequence.
MikamiUitOpen	4:c1beacfc42c7	1508	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
MikamiUitOpen	4:c1beacfc42c7	1509	Only values from 0..7 are used.
MikamiUitOpen	4:c1beacfc42c7	1510	In case of a conflict between priority grouping and available
MikamiUitOpen	4:c1beacfc42c7	1511	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MikamiUitOpen	4:c1beacfc42c7	1512
MikamiUitOpen	4:c1beacfc42c7	1513	\param [in] PriorityGroup Priority grouping field.
MikamiUitOpen	4:c1beacfc42c7	1514	*/
MikamiUitOpen	4:c1beacfc42c7	1515	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
MikamiUitOpen	4:c1beacfc42c7	1516	{
MikamiUitOpen	4:c1beacfc42c7	1517	uint32_t reg_value;
MikamiUitOpen	4:c1beacfc42c7	1518	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen	4:c1beacfc42c7	1519
MikamiUitOpen	4:c1beacfc42c7	1520	reg_value = SCB->AIRCR; /* read old register configuration */
MikamiUitOpen	4:c1beacfc42c7	1521	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
MikamiUitOpen	4:c1beacfc42c7	1522	reg_value = (reg_value \|
MikamiUitOpen	4:c1beacfc42c7	1523	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
MikamiUitOpen	4:c1beacfc42c7	1524	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
MikamiUitOpen	4:c1beacfc42c7	1525	SCB->AIRCR = reg_value;
MikamiUitOpen	4:c1beacfc42c7	1526	}
MikamiUitOpen	4:c1beacfc42c7	1527
MikamiUitOpen	4:c1beacfc42c7	1528
MikamiUitOpen	4:c1beacfc42c7	1529	/** \brief Get Priority Grouping
MikamiUitOpen	4:c1beacfc42c7	1530
MikamiUitOpen	4:c1beacfc42c7	1531	The function reads the priority grouping field from the NVIC Interrupt Controller.
MikamiUitOpen	4:c1beacfc42c7	1532
MikamiUitOpen	4:c1beacfc42c7	1533	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
MikamiUitOpen	4:c1beacfc42c7	1534	*/
MikamiUitOpen	4:c1beacfc42c7	1535	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
MikamiUitOpen	4:c1beacfc42c7	1536	{
MikamiUitOpen	4:c1beacfc42c7	1537	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
MikamiUitOpen	4:c1beacfc42c7	1538	}
MikamiUitOpen	4:c1beacfc42c7	1539
MikamiUitOpen	4:c1beacfc42c7	1540
MikamiUitOpen	4:c1beacfc42c7	1541	/** \brief Enable External Interrupt
MikamiUitOpen	4:c1beacfc42c7	1542
MikamiUitOpen	4:c1beacfc42c7	1543	The function enables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen	4:c1beacfc42c7	1544
MikamiUitOpen	4:c1beacfc42c7	1545	\param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen	4:c1beacfc42c7	1546	*/
MikamiUitOpen	4:c1beacfc42c7	1547	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
MikamiUitOpen	4:c1beacfc42c7	1548	{
MikamiUitOpen	4:c1beacfc42c7	1549	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen	4:c1beacfc42c7	1550	}
MikamiUitOpen	4:c1beacfc42c7	1551
MikamiUitOpen	4:c1beacfc42c7	1552
MikamiUitOpen	4:c1beacfc42c7	1553	/** \brief Disable External Interrupt
MikamiUitOpen	4:c1beacfc42c7	1554
MikamiUitOpen	4:c1beacfc42c7	1555	The function disables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen	4:c1beacfc42c7	1556
MikamiUitOpen	4:c1beacfc42c7	1557	\param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen	4:c1beacfc42c7	1558	*/
MikamiUitOpen	4:c1beacfc42c7	1559	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
MikamiUitOpen	4:c1beacfc42c7	1560	{
MikamiUitOpen	4:c1beacfc42c7	1561	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen	4:c1beacfc42c7	1562	}
MikamiUitOpen	4:c1beacfc42c7	1563
MikamiUitOpen	4:c1beacfc42c7	1564
MikamiUitOpen	4:c1beacfc42c7	1565	/** \brief Get Pending Interrupt
MikamiUitOpen	4:c1beacfc42c7	1566
MikamiUitOpen	4:c1beacfc42c7	1567	The function reads the pending register in the NVIC and returns the pending bit
MikamiUitOpen	4:c1beacfc42c7	1568	for the specified interrupt.
MikamiUitOpen	4:c1beacfc42c7	1569
MikamiUitOpen	4:c1beacfc42c7	1570	\param [in] IRQn Interrupt number.
MikamiUitOpen	4:c1beacfc42c7	1571
MikamiUitOpen	4:c1beacfc42c7	1572	\return 0 Interrupt status is not pending.
MikamiUitOpen	4:c1beacfc42c7	1573	\return 1 Interrupt status is pending.
MikamiUitOpen	4:c1beacfc42c7	1574	*/
MikamiUitOpen	4:c1beacfc42c7	1575	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen	4:c1beacfc42c7	1576	{
MikamiUitOpen	4:c1beacfc42c7	1577	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen	4:c1beacfc42c7	1578	}
MikamiUitOpen	4:c1beacfc42c7	1579
MikamiUitOpen	4:c1beacfc42c7	1580
MikamiUitOpen	4:c1beacfc42c7	1581	/** \brief Set Pending Interrupt
MikamiUitOpen	4:c1beacfc42c7	1582
MikamiUitOpen	4:c1beacfc42c7	1583	The function sets the pending bit of an external interrupt.
MikamiUitOpen	4:c1beacfc42c7	1584
MikamiUitOpen	4:c1beacfc42c7	1585	\param [in] IRQn Interrupt number. Value cannot be negative.
MikamiUitOpen	4:c1beacfc42c7	1586	*/
MikamiUitOpen	4:c1beacfc42c7	1587	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen	4:c1beacfc42c7	1588	{
MikamiUitOpen	4:c1beacfc42c7	1589	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen	4:c1beacfc42c7	1590	}
MikamiUitOpen	4:c1beacfc42c7	1591
MikamiUitOpen	4:c1beacfc42c7	1592
MikamiUitOpen	4:c1beacfc42c7	1593	/** \brief Clear Pending Interrupt
MikamiUitOpen	4:c1beacfc42c7	1594
MikamiUitOpen	4:c1beacfc42c7	1595	The function clears the pending bit of an external interrupt.
MikamiUitOpen	4:c1beacfc42c7	1596
MikamiUitOpen	4:c1beacfc42c7	1597	\param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen	4:c1beacfc42c7	1598	*/
MikamiUitOpen	4:c1beacfc42c7	1599	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen	4:c1beacfc42c7	1600	{
MikamiUitOpen	4:c1beacfc42c7	1601	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen	4:c1beacfc42c7	1602	}
MikamiUitOpen	4:c1beacfc42c7	1603
MikamiUitOpen	4:c1beacfc42c7	1604
MikamiUitOpen	4:c1beacfc42c7	1605	/** \brief Get Active Interrupt
MikamiUitOpen	4:c1beacfc42c7	1606
MikamiUitOpen	4:c1beacfc42c7	1607	The function reads the active register in NVIC and returns the active bit.
MikamiUitOpen	4:c1beacfc42c7	1608
MikamiUitOpen	4:c1beacfc42c7	1609	\param [in] IRQn Interrupt number.
MikamiUitOpen	4:c1beacfc42c7	1610
MikamiUitOpen	4:c1beacfc42c7	1611	\return 0 Interrupt status is not active.
MikamiUitOpen	4:c1beacfc42c7	1612	\return 1 Interrupt status is active.
MikamiUitOpen	4:c1beacfc42c7	1613	*/
MikamiUitOpen	4:c1beacfc42c7	1614	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
MikamiUitOpen	4:c1beacfc42c7	1615	{
MikamiUitOpen	4:c1beacfc42c7	1616	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen	4:c1beacfc42c7	1617	}
MikamiUitOpen	4:c1beacfc42c7	1618
MikamiUitOpen	4:c1beacfc42c7	1619
MikamiUitOpen	4:c1beacfc42c7	1620	/** \brief Set Interrupt Priority
MikamiUitOpen	4:c1beacfc42c7	1621
MikamiUitOpen	4:c1beacfc42c7	1622	The function sets the priority of an interrupt.
MikamiUitOpen	4:c1beacfc42c7	1623
MikamiUitOpen	4:c1beacfc42c7	1624	\note The priority cannot be set for every core interrupt.
MikamiUitOpen	4:c1beacfc42c7	1625
MikamiUitOpen	4:c1beacfc42c7	1626	\param [in] IRQn Interrupt number.
MikamiUitOpen	4:c1beacfc42c7	1627	\param [in] priority Priority to set.
MikamiUitOpen	4:c1beacfc42c7	1628	*/
MikamiUitOpen	4:c1beacfc42c7	1629	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MikamiUitOpen	4:c1beacfc42c7	1630	{
MikamiUitOpen	4:c1beacfc42c7	1631	if((int32_t)IRQn < 0) {
MikamiUitOpen	4:c1beacfc42c7	1632	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MikamiUitOpen	4:c1beacfc42c7	1633	}
MikamiUitOpen	4:c1beacfc42c7	1634	else {
MikamiUitOpen	4:c1beacfc42c7	1635	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MikamiUitOpen	4:c1beacfc42c7	1636	}
MikamiUitOpen	4:c1beacfc42c7	1637	}
MikamiUitOpen	4:c1beacfc42c7	1638
MikamiUitOpen	4:c1beacfc42c7	1639
MikamiUitOpen	4:c1beacfc42c7	1640	/** \brief Get Interrupt Priority
MikamiUitOpen	4:c1beacfc42c7	1641
MikamiUitOpen	4:c1beacfc42c7	1642	The function reads the priority of an interrupt. The interrupt
MikamiUitOpen	4:c1beacfc42c7	1643	number can be positive to specify an external (device specific)
MikamiUitOpen	4:c1beacfc42c7	1644	interrupt, or negative to specify an internal (core) interrupt.
MikamiUitOpen	4:c1beacfc42c7	1645
MikamiUitOpen	4:c1beacfc42c7	1646
MikamiUitOpen	4:c1beacfc42c7	1647	\param [in] IRQn Interrupt number.
MikamiUitOpen	4:c1beacfc42c7	1648	\return Interrupt Priority. Value is aligned automatically to the implemented
MikamiUitOpen	4:c1beacfc42c7	1649	priority bits of the microcontroller.
MikamiUitOpen	4:c1beacfc42c7	1650	*/
MikamiUitOpen	4:c1beacfc42c7	1651	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
MikamiUitOpen	4:c1beacfc42c7	1652	{
MikamiUitOpen	4:c1beacfc42c7	1653
MikamiUitOpen	4:c1beacfc42c7	1654	if((int32_t)IRQn < 0) {
MikamiUitOpen	4:c1beacfc42c7	1655	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen	4:c1beacfc42c7	1656	}
MikamiUitOpen	4:c1beacfc42c7	1657	else {
MikamiUitOpen	4:c1beacfc42c7	1658	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen	4:c1beacfc42c7	1659	}
MikamiUitOpen	4:c1beacfc42c7	1660	}
MikamiUitOpen	4:c1beacfc42c7	1661
MikamiUitOpen	4:c1beacfc42c7	1662
MikamiUitOpen	4:c1beacfc42c7	1663	/** \brief Encode Priority
MikamiUitOpen	4:c1beacfc42c7	1664
MikamiUitOpen	4:c1beacfc42c7	1665	The function encodes the priority for an interrupt with the given priority group,
MikamiUitOpen	4:c1beacfc42c7	1666	preemptive priority value, and subpriority value.
MikamiUitOpen	4:c1beacfc42c7	1667	In case of a conflict between priority grouping and available
MikamiUitOpen	4:c1beacfc42c7	1668	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MikamiUitOpen	4:c1beacfc42c7	1669
MikamiUitOpen	4:c1beacfc42c7	1670	\param [in] PriorityGroup Used priority group.
MikamiUitOpen	4:c1beacfc42c7	1671	\param [in] PreemptPriority Preemptive priority value (starting from 0).
MikamiUitOpen	4:c1beacfc42c7	1672	\param [in] SubPriority Subpriority value (starting from 0).
MikamiUitOpen	4:c1beacfc42c7	1673	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
MikamiUitOpen	4:c1beacfc42c7	1674	*/
MikamiUitOpen	4:c1beacfc42c7	1675	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
MikamiUitOpen	4:c1beacfc42c7	1676	{
MikamiUitOpen	4:c1beacfc42c7	1677	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen	4:c1beacfc42c7	1678	uint32_t PreemptPriorityBits;
MikamiUitOpen	4:c1beacfc42c7	1679	uint32_t SubPriorityBits;
MikamiUitOpen	4:c1beacfc42c7	1680
MikamiUitOpen	4:c1beacfc42c7	1681	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MikamiUitOpen	4:c1beacfc42c7	1682	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MikamiUitOpen	4:c1beacfc42c7	1683
MikamiUitOpen	4:c1beacfc42c7	1684	return (
MikamiUitOpen	4:c1beacfc42c7	1685	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
MikamiUitOpen	4:c1beacfc42c7	1686	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
MikamiUitOpen	4:c1beacfc42c7	1687	);
MikamiUitOpen	4:c1beacfc42c7	1688	}
MikamiUitOpen	4:c1beacfc42c7	1689
MikamiUitOpen	4:c1beacfc42c7	1690
MikamiUitOpen	4:c1beacfc42c7	1691	/** \brief Decode Priority
MikamiUitOpen	4:c1beacfc42c7	1692
MikamiUitOpen	4:c1beacfc42c7	1693	The function decodes an interrupt priority value with a given priority group to
MikamiUitOpen	4:c1beacfc42c7	1694	preemptive priority value and subpriority value.
MikamiUitOpen	4:c1beacfc42c7	1695	In case of a conflict between priority grouping and available
MikamiUitOpen	4:c1beacfc42c7	1696	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
MikamiUitOpen	4:c1beacfc42c7	1697
MikamiUitOpen	4:c1beacfc42c7	1698	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
MikamiUitOpen	4:c1beacfc42c7	1699	\param [in] PriorityGroup Used priority group.
MikamiUitOpen	4:c1beacfc42c7	1700	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
MikamiUitOpen	4:c1beacfc42c7	1701	\param [out] pSubPriority Subpriority value (starting from 0).
MikamiUitOpen	4:c1beacfc42c7	1702	*/
MikamiUitOpen	4:c1beacfc42c7	1703	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
MikamiUitOpen	4:c1beacfc42c7	1704	{
MikamiUitOpen	4:c1beacfc42c7	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen	4:c1beacfc42c7	1706	uint32_t PreemptPriorityBits;
MikamiUitOpen	4:c1beacfc42c7	1707	uint32_t SubPriorityBits;
MikamiUitOpen	4:c1beacfc42c7	1708
MikamiUitOpen	4:c1beacfc42c7	1709	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MikamiUitOpen	4:c1beacfc42c7	1710	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MikamiUitOpen	4:c1beacfc42c7	1711
MikamiUitOpen	4:c1beacfc42c7	1712	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
MikamiUitOpen	4:c1beacfc42c7	1713	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
MikamiUitOpen	4:c1beacfc42c7	1714	}
MikamiUitOpen	4:c1beacfc42c7	1715
MikamiUitOpen	4:c1beacfc42c7	1716
MikamiUitOpen	4:c1beacfc42c7	1717	/** \brief System Reset
MikamiUitOpen	4:c1beacfc42c7	1718
MikamiUitOpen	4:c1beacfc42c7	1719	The function initiates a system reset request to reset the MCU.
MikamiUitOpen	4:c1beacfc42c7	1720	*/
MikamiUitOpen	4:c1beacfc42c7	1721	__STATIC_INLINE void NVIC_SystemReset(void)
MikamiUitOpen	4:c1beacfc42c7	1722	{
MikamiUitOpen	4:c1beacfc42c7	1723	__DSB(); /* Ensure all outstanding memory accesses included
MikamiUitOpen	4:c1beacfc42c7	1724	buffered write are completed before reset */
MikamiUitOpen	4:c1beacfc42c7	1725	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
MikamiUitOpen	4:c1beacfc42c7	1726	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
MikamiUitOpen	4:c1beacfc42c7	1727	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
MikamiUitOpen	4:c1beacfc42c7	1728	__DSB(); /* Ensure completion of memory access */
MikamiUitOpen	4:c1beacfc42c7	1729	while(1) { __NOP(); } /* wait until reset */
MikamiUitOpen	4:c1beacfc42c7	1730	}
MikamiUitOpen	4:c1beacfc42c7	1731
MikamiUitOpen	4:c1beacfc42c7	1732	/@} end of CMSIS_Core_NVICFunctions /
MikamiUitOpen	4:c1beacfc42c7	1733
MikamiUitOpen	4:c1beacfc42c7	1734
MikamiUitOpen	4:c1beacfc42c7	1735
MikamiUitOpen	4:c1beacfc42c7	1736	/* ################################## SysTick function ############################################ */
MikamiUitOpen	4:c1beacfc42c7	1737	/** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen	4:c1beacfc42c7	1738	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MikamiUitOpen	4:c1beacfc42c7	1739	\brief Functions that configure the System.
MikamiUitOpen	4:c1beacfc42c7	1740	@{
MikamiUitOpen	4:c1beacfc42c7	1741	*/
MikamiUitOpen	4:c1beacfc42c7	1742
MikamiUitOpen	4:c1beacfc42c7	1743	#if (__Vendor_SysTickConfig == 0)
MikamiUitOpen	4:c1beacfc42c7	1744
MikamiUitOpen	4:c1beacfc42c7	1745	/** \brief System Tick Configuration
MikamiUitOpen	4:c1beacfc42c7	1746
MikamiUitOpen	4:c1beacfc42c7	1747	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MikamiUitOpen	4:c1beacfc42c7	1748	Counter is in free running mode to generate periodic interrupts.
MikamiUitOpen	4:c1beacfc42c7	1749
MikamiUitOpen	4:c1beacfc42c7	1750	\param [in] ticks Number of ticks between two interrupts.
MikamiUitOpen	4:c1beacfc42c7	1751
MikamiUitOpen	4:c1beacfc42c7	1752	\return 0 Function succeeded.
MikamiUitOpen	4:c1beacfc42c7	1753	\return 1 Function failed.
MikamiUitOpen	4:c1beacfc42c7	1754
MikamiUitOpen	4:c1beacfc42c7	1755	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MikamiUitOpen	4:c1beacfc42c7	1756	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MikamiUitOpen	4:c1beacfc42c7	1757	must contain a vendor-specific implementation of this function.
MikamiUitOpen	4:c1beacfc42c7	1758
MikamiUitOpen	4:c1beacfc42c7	1759	*/
MikamiUitOpen	4:c1beacfc42c7	1760	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MikamiUitOpen	4:c1beacfc42c7	1761	{
MikamiUitOpen	4:c1beacfc42c7	1762	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
MikamiUitOpen	4:c1beacfc42c7	1763
MikamiUitOpen	4:c1beacfc42c7	1764	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MikamiUitOpen	4:c1beacfc42c7	1765	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MikamiUitOpen	4:c1beacfc42c7	1766	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MikamiUitOpen	4:c1beacfc42c7	1767	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
MikamiUitOpen	4:c1beacfc42c7	1768	SysTick_CTRL_TICKINT_Msk \|
MikamiUitOpen	4:c1beacfc42c7	1769	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MikamiUitOpen	4:c1beacfc42c7	1770	return (0UL); /* Function successful */
MikamiUitOpen	4:c1beacfc42c7	1771	}
MikamiUitOpen	4:c1beacfc42c7	1772
MikamiUitOpen	4:c1beacfc42c7	1773	#endif
MikamiUitOpen	4:c1beacfc42c7	1774
MikamiUitOpen	4:c1beacfc42c7	1775	/@} end of CMSIS_Core_SysTickFunctions /
MikamiUitOpen	4:c1beacfc42c7	1776
MikamiUitOpen	4:c1beacfc42c7	1777
MikamiUitOpen	4:c1beacfc42c7	1778
MikamiUitOpen	4:c1beacfc42c7	1779	/* ##################################### Debug In/Output function ########################################### */
MikamiUitOpen	4:c1beacfc42c7	1780	/** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen	4:c1beacfc42c7	1781	\defgroup CMSIS_core_DebugFunctions ITM Functions
MikamiUitOpen	4:c1beacfc42c7	1782	\brief Functions that access the ITM debug interface.
MikamiUitOpen	4:c1beacfc42c7	1783	@{
MikamiUitOpen	4:c1beacfc42c7	1784	*/
MikamiUitOpen	4:c1beacfc42c7	1785
MikamiUitOpen	4:c1beacfc42c7	1786	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
MikamiUitOpen	4:c1beacfc42c7	1787	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
MikamiUitOpen	4:c1beacfc42c7	1788
MikamiUitOpen	4:c1beacfc42c7	1789
MikamiUitOpen	4:c1beacfc42c7	1790	/** \brief ITM Send Character
MikamiUitOpen	4:c1beacfc42c7	1791
MikamiUitOpen	4:c1beacfc42c7	1792	The function transmits a character via the ITM channel 0, and
MikamiUitOpen	4:c1beacfc42c7	1793	\li Just returns when no debugger is connected that has booked the output.
MikamiUitOpen	4:c1beacfc42c7	1794	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
MikamiUitOpen	4:c1beacfc42c7	1795
MikamiUitOpen	4:c1beacfc42c7	1796	\param [in] ch Character to transmit.
MikamiUitOpen	4:c1beacfc42c7	1797
MikamiUitOpen	4:c1beacfc42c7	1798	\returns Character to transmit.
MikamiUitOpen	4:c1beacfc42c7	1799	*/
MikamiUitOpen	4:c1beacfc42c7	1800	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
MikamiUitOpen	4:c1beacfc42c7	1801	{
MikamiUitOpen	4:c1beacfc42c7	1802	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
MikamiUitOpen	4:c1beacfc42c7	1803	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
MikamiUitOpen	4:c1beacfc42c7	1804	{
MikamiUitOpen	4:c1beacfc42c7	1805	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
MikamiUitOpen	4:c1beacfc42c7	1806	ITM->PORT[0].u8 = (uint8_t)ch;
MikamiUitOpen	4:c1beacfc42c7	1807	}
MikamiUitOpen	4:c1beacfc42c7	1808	return (ch);
MikamiUitOpen	4:c1beacfc42c7	1809	}
MikamiUitOpen	4:c1beacfc42c7	1810
MikamiUitOpen	4:c1beacfc42c7	1811
MikamiUitOpen	4:c1beacfc42c7	1812	/** \brief ITM Receive Character
MikamiUitOpen	4:c1beacfc42c7	1813
MikamiUitOpen	4:c1beacfc42c7	1814	The function inputs a character via the external variable \ref ITM_RxBuffer.
MikamiUitOpen	4:c1beacfc42c7	1815
MikamiUitOpen	4:c1beacfc42c7	1816	\return Received character.
MikamiUitOpen	4:c1beacfc42c7	1817	\return -1 No character pending.
MikamiUitOpen	4:c1beacfc42c7	1818	*/
MikamiUitOpen	4:c1beacfc42c7	1819	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
MikamiUitOpen	4:c1beacfc42c7	1820	int32_t ch = -1; /* no character available */
MikamiUitOpen	4:c1beacfc42c7	1821
MikamiUitOpen	4:c1beacfc42c7	1822	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
MikamiUitOpen	4:c1beacfc42c7	1823	ch = ITM_RxBuffer;
MikamiUitOpen	4:c1beacfc42c7	1824	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
MikamiUitOpen	4:c1beacfc42c7	1825	}
MikamiUitOpen	4:c1beacfc42c7	1826
MikamiUitOpen	4:c1beacfc42c7	1827	return (ch);
MikamiUitOpen	4:c1beacfc42c7	1828	}
MikamiUitOpen	4:c1beacfc42c7	1829
MikamiUitOpen	4:c1beacfc42c7	1830
MikamiUitOpen	4:c1beacfc42c7	1831	/** \brief ITM Check Character
MikamiUitOpen	4:c1beacfc42c7	1832
MikamiUitOpen	4:c1beacfc42c7	1833	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
MikamiUitOpen	4:c1beacfc42c7	1834
MikamiUitOpen	4:c1beacfc42c7	1835	\return 0 No character available.
MikamiUitOpen	4:c1beacfc42c7	1836	\return 1 Character available.
MikamiUitOpen	4:c1beacfc42c7	1837	*/
MikamiUitOpen	4:c1beacfc42c7	1838	__STATIC_INLINE int32_t ITM_CheckChar (void) {
MikamiUitOpen	4:c1beacfc42c7	1839
MikamiUitOpen	4:c1beacfc42c7	1840	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
MikamiUitOpen	4:c1beacfc42c7	1841	return (0); /* no character available */
MikamiUitOpen	4:c1beacfc42c7	1842	} else {
MikamiUitOpen	4:c1beacfc42c7	1843	return (1); /* character available */
MikamiUitOpen	4:c1beacfc42c7	1844	}
MikamiUitOpen	4:c1beacfc42c7	1845	}
MikamiUitOpen	4:c1beacfc42c7	1846
MikamiUitOpen	4:c1beacfc42c7	1847	/@} end of CMSIS_core_DebugFunctions /
MikamiUitOpen	4:c1beacfc42c7	1848
MikamiUitOpen	4:c1beacfc42c7	1849
MikamiUitOpen	4:c1beacfc42c7	1850
MikamiUitOpen	4:c1beacfc42c7	1851
MikamiUitOpen	4:c1beacfc42c7	1852	#ifdef __cplusplus
MikamiUitOpen	4:c1beacfc42c7	1853	}
MikamiUitOpen	4:c1beacfc42c7	1854	#endif
MikamiUitOpen	4:c1beacfc42c7	1855
MikamiUitOpen	4:c1beacfc42c7	1856	#endif /* __CORE_CM4_H_DEPENDANT */
MikamiUitOpen	4:c1beacfc42c7	1857
MikamiUitOpen	4:c1beacfc42c7	1858	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	22 May 2016
Imports:	468
Forks:	1
Commits:	7
Dependents:	0
Dependencies:	3
Followers:	14

The code in this repository is Apache licensed.

mbed_src_STM32F7/targets/cmsis/core_cm4.h@6:b3885567877c, 2017-04-10 (annotated)

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