不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_cmSimd.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 * @file core_cmSimd.h
MikamiUitOpen 6:38f7dce055d0 3 * @brief CMSIS Cortex-M SIMD Header File
MikamiUitOpen 6:38f7dce055d0 4 * @version V4.10
MikamiUitOpen 6:38f7dce055d0 5 * @date 18. March 2015
MikamiUitOpen 6:38f7dce055d0 6 *
MikamiUitOpen 6:38f7dce055d0 7 * @note
MikamiUitOpen 6:38f7dce055d0 8 *
MikamiUitOpen 6:38f7dce055d0 9 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11
MikamiUitOpen 6:38f7dce055d0 12 All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 *
MikamiUitOpen 6:38f7dce055d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 #if defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 6:38f7dce055d0 40 #endif
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 #ifndef __CORE_CMSIMD_H
MikamiUitOpen 6:38f7dce055d0 43 #define __CORE_CMSIMD_H
MikamiUitOpen 6:38f7dce055d0 44
MikamiUitOpen 6:38f7dce055d0 45 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 46 extern "C" {
MikamiUitOpen 6:38f7dce055d0 47 #endif
MikamiUitOpen 6:38f7dce055d0 48
MikamiUitOpen 6:38f7dce055d0 49
MikamiUitOpen 6:38f7dce055d0 50 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 51 * Hardware Abstraction Layer
MikamiUitOpen 6:38f7dce055d0 52 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 53
MikamiUitOpen 6:38f7dce055d0 54
MikamiUitOpen 6:38f7dce055d0 55 /* ################### Compiler specific Intrinsics ########################### */
MikamiUitOpen 6:38f7dce055d0 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
MikamiUitOpen 6:38f7dce055d0 57 Access to dedicated SIMD instructions
MikamiUitOpen 6:38f7dce055d0 58 @{
MikamiUitOpen 6:38f7dce055d0 59 */
MikamiUitOpen 6:38f7dce055d0 60
MikamiUitOpen 6:38f7dce055d0 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 6:38f7dce055d0 62 /* ARM armcc specific functions */
MikamiUitOpen 6:38f7dce055d0 63 #define __SADD8 __sadd8
MikamiUitOpen 6:38f7dce055d0 64 #define __QADD8 __qadd8
MikamiUitOpen 6:38f7dce055d0 65 #define __SHADD8 __shadd8
MikamiUitOpen 6:38f7dce055d0 66 #define __UADD8 __uadd8
MikamiUitOpen 6:38f7dce055d0 67 #define __UQADD8 __uqadd8
MikamiUitOpen 6:38f7dce055d0 68 #define __UHADD8 __uhadd8
MikamiUitOpen 6:38f7dce055d0 69 #define __SSUB8 __ssub8
MikamiUitOpen 6:38f7dce055d0 70 #define __QSUB8 __qsub8
MikamiUitOpen 6:38f7dce055d0 71 #define __SHSUB8 __shsub8
MikamiUitOpen 6:38f7dce055d0 72 #define __USUB8 __usub8
MikamiUitOpen 6:38f7dce055d0 73 #define __UQSUB8 __uqsub8
MikamiUitOpen 6:38f7dce055d0 74 #define __UHSUB8 __uhsub8
MikamiUitOpen 6:38f7dce055d0 75 #define __SADD16 __sadd16
MikamiUitOpen 6:38f7dce055d0 76 #define __QADD16 __qadd16
MikamiUitOpen 6:38f7dce055d0 77 #define __SHADD16 __shadd16
MikamiUitOpen 6:38f7dce055d0 78 #define __UADD16 __uadd16
MikamiUitOpen 6:38f7dce055d0 79 #define __UQADD16 __uqadd16
MikamiUitOpen 6:38f7dce055d0 80 #define __UHADD16 __uhadd16
MikamiUitOpen 6:38f7dce055d0 81 #define __SSUB16 __ssub16
MikamiUitOpen 6:38f7dce055d0 82 #define __QSUB16 __qsub16
MikamiUitOpen 6:38f7dce055d0 83 #define __SHSUB16 __shsub16
MikamiUitOpen 6:38f7dce055d0 84 #define __USUB16 __usub16
MikamiUitOpen 6:38f7dce055d0 85 #define __UQSUB16 __uqsub16
MikamiUitOpen 6:38f7dce055d0 86 #define __UHSUB16 __uhsub16
MikamiUitOpen 6:38f7dce055d0 87 #define __SASX __sasx
MikamiUitOpen 6:38f7dce055d0 88 #define __QASX __qasx
MikamiUitOpen 6:38f7dce055d0 89 #define __SHASX __shasx
MikamiUitOpen 6:38f7dce055d0 90 #define __UASX __uasx
MikamiUitOpen 6:38f7dce055d0 91 #define __UQASX __uqasx
MikamiUitOpen 6:38f7dce055d0 92 #define __UHASX __uhasx
MikamiUitOpen 6:38f7dce055d0 93 #define __SSAX __ssax
MikamiUitOpen 6:38f7dce055d0 94 #define __QSAX __qsax
MikamiUitOpen 6:38f7dce055d0 95 #define __SHSAX __shsax
MikamiUitOpen 6:38f7dce055d0 96 #define __USAX __usax
MikamiUitOpen 6:38f7dce055d0 97 #define __UQSAX __uqsax
MikamiUitOpen 6:38f7dce055d0 98 #define __UHSAX __uhsax
MikamiUitOpen 6:38f7dce055d0 99 #define __USAD8 __usad8
MikamiUitOpen 6:38f7dce055d0 100 #define __USADA8 __usada8
MikamiUitOpen 6:38f7dce055d0 101 #define __SSAT16 __ssat16
MikamiUitOpen 6:38f7dce055d0 102 #define __USAT16 __usat16
MikamiUitOpen 6:38f7dce055d0 103 #define __UXTB16 __uxtb16
MikamiUitOpen 6:38f7dce055d0 104 #define __UXTAB16 __uxtab16
MikamiUitOpen 6:38f7dce055d0 105 #define __SXTB16 __sxtb16
MikamiUitOpen 6:38f7dce055d0 106 #define __SXTAB16 __sxtab16
MikamiUitOpen 6:38f7dce055d0 107 #define __SMUAD __smuad
MikamiUitOpen 6:38f7dce055d0 108 #define __SMUADX __smuadx
MikamiUitOpen 6:38f7dce055d0 109 #define __SMLAD __smlad
MikamiUitOpen 6:38f7dce055d0 110 #define __SMLADX __smladx
MikamiUitOpen 6:38f7dce055d0 111 #define __SMLALD __smlald
MikamiUitOpen 6:38f7dce055d0 112 #define __SMLALDX __smlaldx
MikamiUitOpen 6:38f7dce055d0 113 #define __SMUSD __smusd
MikamiUitOpen 6:38f7dce055d0 114 #define __SMUSDX __smusdx
MikamiUitOpen 6:38f7dce055d0 115 #define __SMLSD __smlsd
MikamiUitOpen 6:38f7dce055d0 116 #define __SMLSDX __smlsdx
MikamiUitOpen 6:38f7dce055d0 117 #define __SMLSLD __smlsld
MikamiUitOpen 6:38f7dce055d0 118 #define __SMLSLDX __smlsldx
MikamiUitOpen 6:38f7dce055d0 119 #define __SEL __sel
MikamiUitOpen 6:38f7dce055d0 120 #define __QADD __qadd
MikamiUitOpen 6:38f7dce055d0 121 #define __QSUB __qsub
MikamiUitOpen 6:38f7dce055d0 122
MikamiUitOpen 6:38f7dce055d0 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
MikamiUitOpen 6:38f7dce055d0 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
MikamiUitOpen 6:38f7dce055d0 125
MikamiUitOpen 6:38f7dce055d0 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
MikamiUitOpen 6:38f7dce055d0 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
MikamiUitOpen 6:38f7dce055d0 128
MikamiUitOpen 6:38f7dce055d0 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
MikamiUitOpen 6:38f7dce055d0 130 ((int64_t)(ARG3) << 32) ) >> 32))
MikamiUitOpen 6:38f7dce055d0 131
MikamiUitOpen 6:38f7dce055d0 132
MikamiUitOpen 6:38f7dce055d0 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 6:38f7dce055d0 134 /* GNU gcc specific functions */
MikamiUitOpen 6:38f7dce055d0 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 136 {
MikamiUitOpen 6:38f7dce055d0 137 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 138
MikamiUitOpen 6:38f7dce055d0 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 140 return(result);
MikamiUitOpen 6:38f7dce055d0 141 }
MikamiUitOpen 6:38f7dce055d0 142
MikamiUitOpen 6:38f7dce055d0 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 144 {
MikamiUitOpen 6:38f7dce055d0 145 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 146
MikamiUitOpen 6:38f7dce055d0 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 148 return(result);
MikamiUitOpen 6:38f7dce055d0 149 }
MikamiUitOpen 6:38f7dce055d0 150
MikamiUitOpen 6:38f7dce055d0 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 152 {
MikamiUitOpen 6:38f7dce055d0 153 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 154
MikamiUitOpen 6:38f7dce055d0 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 156 return(result);
MikamiUitOpen 6:38f7dce055d0 157 }
MikamiUitOpen 6:38f7dce055d0 158
MikamiUitOpen 6:38f7dce055d0 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 160 {
MikamiUitOpen 6:38f7dce055d0 161 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 162
MikamiUitOpen 6:38f7dce055d0 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 164 return(result);
MikamiUitOpen 6:38f7dce055d0 165 }
MikamiUitOpen 6:38f7dce055d0 166
MikamiUitOpen 6:38f7dce055d0 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 168 {
MikamiUitOpen 6:38f7dce055d0 169 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 170
MikamiUitOpen 6:38f7dce055d0 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 172 return(result);
MikamiUitOpen 6:38f7dce055d0 173 }
MikamiUitOpen 6:38f7dce055d0 174
MikamiUitOpen 6:38f7dce055d0 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 176 {
MikamiUitOpen 6:38f7dce055d0 177 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 178
MikamiUitOpen 6:38f7dce055d0 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 180 return(result);
MikamiUitOpen 6:38f7dce055d0 181 }
MikamiUitOpen 6:38f7dce055d0 182
MikamiUitOpen 6:38f7dce055d0 183
MikamiUitOpen 6:38f7dce055d0 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 185 {
MikamiUitOpen 6:38f7dce055d0 186 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 187
MikamiUitOpen 6:38f7dce055d0 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 189 return(result);
MikamiUitOpen 6:38f7dce055d0 190 }
MikamiUitOpen 6:38f7dce055d0 191
MikamiUitOpen 6:38f7dce055d0 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 193 {
MikamiUitOpen 6:38f7dce055d0 194 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 195
MikamiUitOpen 6:38f7dce055d0 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 197 return(result);
MikamiUitOpen 6:38f7dce055d0 198 }
MikamiUitOpen 6:38f7dce055d0 199
MikamiUitOpen 6:38f7dce055d0 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 201 {
MikamiUitOpen 6:38f7dce055d0 202 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 203
MikamiUitOpen 6:38f7dce055d0 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 205 return(result);
MikamiUitOpen 6:38f7dce055d0 206 }
MikamiUitOpen 6:38f7dce055d0 207
MikamiUitOpen 6:38f7dce055d0 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 209 {
MikamiUitOpen 6:38f7dce055d0 210 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 211
MikamiUitOpen 6:38f7dce055d0 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 213 return(result);
MikamiUitOpen 6:38f7dce055d0 214 }
MikamiUitOpen 6:38f7dce055d0 215
MikamiUitOpen 6:38f7dce055d0 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 217 {
MikamiUitOpen 6:38f7dce055d0 218 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 219
MikamiUitOpen 6:38f7dce055d0 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 221 return(result);
MikamiUitOpen 6:38f7dce055d0 222 }
MikamiUitOpen 6:38f7dce055d0 223
MikamiUitOpen 6:38f7dce055d0 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 225 {
MikamiUitOpen 6:38f7dce055d0 226 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 227
MikamiUitOpen 6:38f7dce055d0 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 229 return(result);
MikamiUitOpen 6:38f7dce055d0 230 }
MikamiUitOpen 6:38f7dce055d0 231
MikamiUitOpen 6:38f7dce055d0 232
MikamiUitOpen 6:38f7dce055d0 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 234 {
MikamiUitOpen 6:38f7dce055d0 235 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 236
MikamiUitOpen 6:38f7dce055d0 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 238 return(result);
MikamiUitOpen 6:38f7dce055d0 239 }
MikamiUitOpen 6:38f7dce055d0 240
MikamiUitOpen 6:38f7dce055d0 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 242 {
MikamiUitOpen 6:38f7dce055d0 243 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 244
MikamiUitOpen 6:38f7dce055d0 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 246 return(result);
MikamiUitOpen 6:38f7dce055d0 247 }
MikamiUitOpen 6:38f7dce055d0 248
MikamiUitOpen 6:38f7dce055d0 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 250 {
MikamiUitOpen 6:38f7dce055d0 251 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 252
MikamiUitOpen 6:38f7dce055d0 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 254 return(result);
MikamiUitOpen 6:38f7dce055d0 255 }
MikamiUitOpen 6:38f7dce055d0 256
MikamiUitOpen 6:38f7dce055d0 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 258 {
MikamiUitOpen 6:38f7dce055d0 259 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 260
MikamiUitOpen 6:38f7dce055d0 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 262 return(result);
MikamiUitOpen 6:38f7dce055d0 263 }
MikamiUitOpen 6:38f7dce055d0 264
MikamiUitOpen 6:38f7dce055d0 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 266 {
MikamiUitOpen 6:38f7dce055d0 267 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 268
MikamiUitOpen 6:38f7dce055d0 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 270 return(result);
MikamiUitOpen 6:38f7dce055d0 271 }
MikamiUitOpen 6:38f7dce055d0 272
MikamiUitOpen 6:38f7dce055d0 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 274 {
MikamiUitOpen 6:38f7dce055d0 275 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 276
MikamiUitOpen 6:38f7dce055d0 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 278 return(result);
MikamiUitOpen 6:38f7dce055d0 279 }
MikamiUitOpen 6:38f7dce055d0 280
MikamiUitOpen 6:38f7dce055d0 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 282 {
MikamiUitOpen 6:38f7dce055d0 283 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 284
MikamiUitOpen 6:38f7dce055d0 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 286 return(result);
MikamiUitOpen 6:38f7dce055d0 287 }
MikamiUitOpen 6:38f7dce055d0 288
MikamiUitOpen 6:38f7dce055d0 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 290 {
MikamiUitOpen 6:38f7dce055d0 291 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 292
MikamiUitOpen 6:38f7dce055d0 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 294 return(result);
MikamiUitOpen 6:38f7dce055d0 295 }
MikamiUitOpen 6:38f7dce055d0 296
MikamiUitOpen 6:38f7dce055d0 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 298 {
MikamiUitOpen 6:38f7dce055d0 299 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 300
MikamiUitOpen 6:38f7dce055d0 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 302 return(result);
MikamiUitOpen 6:38f7dce055d0 303 }
MikamiUitOpen 6:38f7dce055d0 304
MikamiUitOpen 6:38f7dce055d0 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 306 {
MikamiUitOpen 6:38f7dce055d0 307 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 308
MikamiUitOpen 6:38f7dce055d0 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 310 return(result);
MikamiUitOpen 6:38f7dce055d0 311 }
MikamiUitOpen 6:38f7dce055d0 312
MikamiUitOpen 6:38f7dce055d0 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 314 {
MikamiUitOpen 6:38f7dce055d0 315 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 316
MikamiUitOpen 6:38f7dce055d0 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 318 return(result);
MikamiUitOpen 6:38f7dce055d0 319 }
MikamiUitOpen 6:38f7dce055d0 320
MikamiUitOpen 6:38f7dce055d0 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 322 {
MikamiUitOpen 6:38f7dce055d0 323 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 324
MikamiUitOpen 6:38f7dce055d0 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 326 return(result);
MikamiUitOpen 6:38f7dce055d0 327 }
MikamiUitOpen 6:38f7dce055d0 328
MikamiUitOpen 6:38f7dce055d0 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 330 {
MikamiUitOpen 6:38f7dce055d0 331 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 332
MikamiUitOpen 6:38f7dce055d0 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 334 return(result);
MikamiUitOpen 6:38f7dce055d0 335 }
MikamiUitOpen 6:38f7dce055d0 336
MikamiUitOpen 6:38f7dce055d0 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 338 {
MikamiUitOpen 6:38f7dce055d0 339 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 340
MikamiUitOpen 6:38f7dce055d0 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 342 return(result);
MikamiUitOpen 6:38f7dce055d0 343 }
MikamiUitOpen 6:38f7dce055d0 344
MikamiUitOpen 6:38f7dce055d0 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 346 {
MikamiUitOpen 6:38f7dce055d0 347 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 348
MikamiUitOpen 6:38f7dce055d0 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 350 return(result);
MikamiUitOpen 6:38f7dce055d0 351 }
MikamiUitOpen 6:38f7dce055d0 352
MikamiUitOpen 6:38f7dce055d0 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 354 {
MikamiUitOpen 6:38f7dce055d0 355 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 356
MikamiUitOpen 6:38f7dce055d0 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 358 return(result);
MikamiUitOpen 6:38f7dce055d0 359 }
MikamiUitOpen 6:38f7dce055d0 360
MikamiUitOpen 6:38f7dce055d0 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 362 {
MikamiUitOpen 6:38f7dce055d0 363 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 364
MikamiUitOpen 6:38f7dce055d0 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 366 return(result);
MikamiUitOpen 6:38f7dce055d0 367 }
MikamiUitOpen 6:38f7dce055d0 368
MikamiUitOpen 6:38f7dce055d0 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 370 {
MikamiUitOpen 6:38f7dce055d0 371 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 372
MikamiUitOpen 6:38f7dce055d0 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 374 return(result);
MikamiUitOpen 6:38f7dce055d0 375 }
MikamiUitOpen 6:38f7dce055d0 376
MikamiUitOpen 6:38f7dce055d0 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 378 {
MikamiUitOpen 6:38f7dce055d0 379 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 380
MikamiUitOpen 6:38f7dce055d0 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 382 return(result);
MikamiUitOpen 6:38f7dce055d0 383 }
MikamiUitOpen 6:38f7dce055d0 384
MikamiUitOpen 6:38f7dce055d0 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 386 {
MikamiUitOpen 6:38f7dce055d0 387 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 388
MikamiUitOpen 6:38f7dce055d0 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 390 return(result);
MikamiUitOpen 6:38f7dce055d0 391 }
MikamiUitOpen 6:38f7dce055d0 392
MikamiUitOpen 6:38f7dce055d0 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 394 {
MikamiUitOpen 6:38f7dce055d0 395 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 396
MikamiUitOpen 6:38f7dce055d0 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 398 return(result);
MikamiUitOpen 6:38f7dce055d0 399 }
MikamiUitOpen 6:38f7dce055d0 400
MikamiUitOpen 6:38f7dce055d0 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 402 {
MikamiUitOpen 6:38f7dce055d0 403 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 404
MikamiUitOpen 6:38f7dce055d0 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 406 return(result);
MikamiUitOpen 6:38f7dce055d0 407 }
MikamiUitOpen 6:38f7dce055d0 408
MikamiUitOpen 6:38f7dce055d0 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 410 {
MikamiUitOpen 6:38f7dce055d0 411 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 412
MikamiUitOpen 6:38f7dce055d0 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 414 return(result);
MikamiUitOpen 6:38f7dce055d0 415 }
MikamiUitOpen 6:38f7dce055d0 416
MikamiUitOpen 6:38f7dce055d0 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 418 {
MikamiUitOpen 6:38f7dce055d0 419 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 420
MikamiUitOpen 6:38f7dce055d0 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 422 return(result);
MikamiUitOpen 6:38f7dce055d0 423 }
MikamiUitOpen 6:38f7dce055d0 424
MikamiUitOpen 6:38f7dce055d0 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 426 {
MikamiUitOpen 6:38f7dce055d0 427 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 428
MikamiUitOpen 6:38f7dce055d0 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 430 return(result);
MikamiUitOpen 6:38f7dce055d0 431 }
MikamiUitOpen 6:38f7dce055d0 432
MikamiUitOpen 6:38f7dce055d0 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 434 {
MikamiUitOpen 6:38f7dce055d0 435 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 436
MikamiUitOpen 6:38f7dce055d0 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 438 return(result);
MikamiUitOpen 6:38f7dce055d0 439 }
MikamiUitOpen 6:38f7dce055d0 440
MikamiUitOpen 6:38f7dce055d0 441 #define __SSAT16(ARG1,ARG2) \
MikamiUitOpen 6:38f7dce055d0 442 ({ \
MikamiUitOpen 6:38f7dce055d0 443 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 6:38f7dce055d0 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 6:38f7dce055d0 445 __RES; \
MikamiUitOpen 6:38f7dce055d0 446 })
MikamiUitOpen 6:38f7dce055d0 447
MikamiUitOpen 6:38f7dce055d0 448 #define __USAT16(ARG1,ARG2) \
MikamiUitOpen 6:38f7dce055d0 449 ({ \
MikamiUitOpen 6:38f7dce055d0 450 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 6:38f7dce055d0 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 6:38f7dce055d0 452 __RES; \
MikamiUitOpen 6:38f7dce055d0 453 })
MikamiUitOpen 6:38f7dce055d0 454
MikamiUitOpen 6:38f7dce055d0 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
MikamiUitOpen 6:38f7dce055d0 456 {
MikamiUitOpen 6:38f7dce055d0 457 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 458
MikamiUitOpen 6:38f7dce055d0 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 6:38f7dce055d0 460 return(result);
MikamiUitOpen 6:38f7dce055d0 461 }
MikamiUitOpen 6:38f7dce055d0 462
MikamiUitOpen 6:38f7dce055d0 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 464 {
MikamiUitOpen 6:38f7dce055d0 465 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 466
MikamiUitOpen 6:38f7dce055d0 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 468 return(result);
MikamiUitOpen 6:38f7dce055d0 469 }
MikamiUitOpen 6:38f7dce055d0 470
MikamiUitOpen 6:38f7dce055d0 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
MikamiUitOpen 6:38f7dce055d0 472 {
MikamiUitOpen 6:38f7dce055d0 473 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 474
MikamiUitOpen 6:38f7dce055d0 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 6:38f7dce055d0 476 return(result);
MikamiUitOpen 6:38f7dce055d0 477 }
MikamiUitOpen 6:38f7dce055d0 478
MikamiUitOpen 6:38f7dce055d0 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 480 {
MikamiUitOpen 6:38f7dce055d0 481 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 482
MikamiUitOpen 6:38f7dce055d0 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 484 return(result);
MikamiUitOpen 6:38f7dce055d0 485 }
MikamiUitOpen 6:38f7dce055d0 486
MikamiUitOpen 6:38f7dce055d0 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 488 {
MikamiUitOpen 6:38f7dce055d0 489 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 490
MikamiUitOpen 6:38f7dce055d0 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 492 return(result);
MikamiUitOpen 6:38f7dce055d0 493 }
MikamiUitOpen 6:38f7dce055d0 494
MikamiUitOpen 6:38f7dce055d0 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 496 {
MikamiUitOpen 6:38f7dce055d0 497 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 498
MikamiUitOpen 6:38f7dce055d0 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 500 return(result);
MikamiUitOpen 6:38f7dce055d0 501 }
MikamiUitOpen 6:38f7dce055d0 502
MikamiUitOpen 6:38f7dce055d0 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 504 {
MikamiUitOpen 6:38f7dce055d0 505 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 506
MikamiUitOpen 6:38f7dce055d0 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 508 return(result);
MikamiUitOpen 6:38f7dce055d0 509 }
MikamiUitOpen 6:38f7dce055d0 510
MikamiUitOpen 6:38f7dce055d0 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 512 {
MikamiUitOpen 6:38f7dce055d0 513 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 514
MikamiUitOpen 6:38f7dce055d0 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 516 return(result);
MikamiUitOpen 6:38f7dce055d0 517 }
MikamiUitOpen 6:38f7dce055d0 518
MikamiUitOpen 6:38f7dce055d0 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 6:38f7dce055d0 520 {
MikamiUitOpen 6:38f7dce055d0 521 union llreg_u{
MikamiUitOpen 6:38f7dce055d0 522 uint32_t w32[2];
MikamiUitOpen 6:38f7dce055d0 523 uint64_t w64;
MikamiUitOpen 6:38f7dce055d0 524 } llr;
MikamiUitOpen 6:38f7dce055d0 525 llr.w64 = acc;
MikamiUitOpen 6:38f7dce055d0 526
MikamiUitOpen 6:38f7dce055d0 527 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 6:38f7dce055d0 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 6:38f7dce055d0 529 #else // Big endian
MikamiUitOpen 6:38f7dce055d0 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 6:38f7dce055d0 531 #endif
MikamiUitOpen 6:38f7dce055d0 532
MikamiUitOpen 6:38f7dce055d0 533 return(llr.w64);
MikamiUitOpen 6:38f7dce055d0 534 }
MikamiUitOpen 6:38f7dce055d0 535
MikamiUitOpen 6:38f7dce055d0 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 6:38f7dce055d0 537 {
MikamiUitOpen 6:38f7dce055d0 538 union llreg_u{
MikamiUitOpen 6:38f7dce055d0 539 uint32_t w32[2];
MikamiUitOpen 6:38f7dce055d0 540 uint64_t w64;
MikamiUitOpen 6:38f7dce055d0 541 } llr;
MikamiUitOpen 6:38f7dce055d0 542 llr.w64 = acc;
MikamiUitOpen 6:38f7dce055d0 543
MikamiUitOpen 6:38f7dce055d0 544 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 6:38f7dce055d0 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 6:38f7dce055d0 546 #else // Big endian
MikamiUitOpen 6:38f7dce055d0 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 6:38f7dce055d0 548 #endif
MikamiUitOpen 6:38f7dce055d0 549
MikamiUitOpen 6:38f7dce055d0 550 return(llr.w64);
MikamiUitOpen 6:38f7dce055d0 551 }
MikamiUitOpen 6:38f7dce055d0 552
MikamiUitOpen 6:38f7dce055d0 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 554 {
MikamiUitOpen 6:38f7dce055d0 555 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 556
MikamiUitOpen 6:38f7dce055d0 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 558 return(result);
MikamiUitOpen 6:38f7dce055d0 559 }
MikamiUitOpen 6:38f7dce055d0 560
MikamiUitOpen 6:38f7dce055d0 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 562 {
MikamiUitOpen 6:38f7dce055d0 563 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 564
MikamiUitOpen 6:38f7dce055d0 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 566 return(result);
MikamiUitOpen 6:38f7dce055d0 567 }
MikamiUitOpen 6:38f7dce055d0 568
MikamiUitOpen 6:38f7dce055d0 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 570 {
MikamiUitOpen 6:38f7dce055d0 571 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 572
MikamiUitOpen 6:38f7dce055d0 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 574 return(result);
MikamiUitOpen 6:38f7dce055d0 575 }
MikamiUitOpen 6:38f7dce055d0 576
MikamiUitOpen 6:38f7dce055d0 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 578 {
MikamiUitOpen 6:38f7dce055d0 579 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 580
MikamiUitOpen 6:38f7dce055d0 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 582 return(result);
MikamiUitOpen 6:38f7dce055d0 583 }
MikamiUitOpen 6:38f7dce055d0 584
MikamiUitOpen 6:38f7dce055d0 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 6:38f7dce055d0 586 {
MikamiUitOpen 6:38f7dce055d0 587 union llreg_u{
MikamiUitOpen 6:38f7dce055d0 588 uint32_t w32[2];
MikamiUitOpen 6:38f7dce055d0 589 uint64_t w64;
MikamiUitOpen 6:38f7dce055d0 590 } llr;
MikamiUitOpen 6:38f7dce055d0 591 llr.w64 = acc;
MikamiUitOpen 6:38f7dce055d0 592
MikamiUitOpen 6:38f7dce055d0 593 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 6:38f7dce055d0 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 6:38f7dce055d0 595 #else // Big endian
MikamiUitOpen 6:38f7dce055d0 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 6:38f7dce055d0 597 #endif
MikamiUitOpen 6:38f7dce055d0 598
MikamiUitOpen 6:38f7dce055d0 599 return(llr.w64);
MikamiUitOpen 6:38f7dce055d0 600 }
MikamiUitOpen 6:38f7dce055d0 601
MikamiUitOpen 6:38f7dce055d0 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 6:38f7dce055d0 603 {
MikamiUitOpen 6:38f7dce055d0 604 union llreg_u{
MikamiUitOpen 6:38f7dce055d0 605 uint32_t w32[2];
MikamiUitOpen 6:38f7dce055d0 606 uint64_t w64;
MikamiUitOpen 6:38f7dce055d0 607 } llr;
MikamiUitOpen 6:38f7dce055d0 608 llr.w64 = acc;
MikamiUitOpen 6:38f7dce055d0 609
MikamiUitOpen 6:38f7dce055d0 610 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 6:38f7dce055d0 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 6:38f7dce055d0 612 #else // Big endian
MikamiUitOpen 6:38f7dce055d0 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 6:38f7dce055d0 614 #endif
MikamiUitOpen 6:38f7dce055d0 615
MikamiUitOpen 6:38f7dce055d0 616 return(llr.w64);
MikamiUitOpen 6:38f7dce055d0 617 }
MikamiUitOpen 6:38f7dce055d0 618
MikamiUitOpen 6:38f7dce055d0 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 620 {
MikamiUitOpen 6:38f7dce055d0 621 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 622
MikamiUitOpen 6:38f7dce055d0 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 624 return(result);
MikamiUitOpen 6:38f7dce055d0 625 }
MikamiUitOpen 6:38f7dce055d0 626
MikamiUitOpen 6:38f7dce055d0 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 628 {
MikamiUitOpen 6:38f7dce055d0 629 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 630
MikamiUitOpen 6:38f7dce055d0 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 632 return(result);
MikamiUitOpen 6:38f7dce055d0 633 }
MikamiUitOpen 6:38f7dce055d0 634
MikamiUitOpen 6:38f7dce055d0 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 636 {
MikamiUitOpen 6:38f7dce055d0 637 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 638
MikamiUitOpen 6:38f7dce055d0 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 640 return(result);
MikamiUitOpen 6:38f7dce055d0 641 }
MikamiUitOpen 6:38f7dce055d0 642
MikamiUitOpen 6:38f7dce055d0 643 #define __PKHBT(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 644 ({ \
MikamiUitOpen 6:38f7dce055d0 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 6:38f7dce055d0 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 6:38f7dce055d0 647 __RES; \
MikamiUitOpen 6:38f7dce055d0 648 })
MikamiUitOpen 6:38f7dce055d0 649
MikamiUitOpen 6:38f7dce055d0 650 #define __PKHTB(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 651 ({ \
MikamiUitOpen 6:38f7dce055d0 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 6:38f7dce055d0 653 if (ARG3 == 0) \
MikamiUitOpen 6:38f7dce055d0 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
MikamiUitOpen 6:38f7dce055d0 655 else \
MikamiUitOpen 6:38f7dce055d0 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 6:38f7dce055d0 657 __RES; \
MikamiUitOpen 6:38f7dce055d0 658 })
MikamiUitOpen 6:38f7dce055d0 659
MikamiUitOpen 6:38f7dce055d0 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
MikamiUitOpen 6:38f7dce055d0 661 {
MikamiUitOpen 6:38f7dce055d0 662 int32_t result;
MikamiUitOpen 6:38f7dce055d0 663
MikamiUitOpen 6:38f7dce055d0 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 665 return(result);
MikamiUitOpen 6:38f7dce055d0 666 }
MikamiUitOpen 6:38f7dce055d0 667
MikamiUitOpen 6:38f7dce055d0 668
MikamiUitOpen 6:38f7dce055d0 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 6:38f7dce055d0 670 /* IAR iccarm specific functions */
MikamiUitOpen 6:38f7dce055d0 671 #include <cmsis_iar.h>
MikamiUitOpen 6:38f7dce055d0 672
MikamiUitOpen 6:38f7dce055d0 673
MikamiUitOpen 6:38f7dce055d0 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 6:38f7dce055d0 675 /* TI CCS specific functions */
MikamiUitOpen 6:38f7dce055d0 676 #include <cmsis_ccs.h>
MikamiUitOpen 6:38f7dce055d0 677
MikamiUitOpen 6:38f7dce055d0 678
MikamiUitOpen 6:38f7dce055d0 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 6:38f7dce055d0 680 /* TASKING carm specific functions */
MikamiUitOpen 6:38f7dce055d0 681 /* not yet supported */
MikamiUitOpen 6:38f7dce055d0 682
MikamiUitOpen 6:38f7dce055d0 683
MikamiUitOpen 6:38f7dce055d0 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 6:38f7dce055d0 685 /* Cosmic specific functions */
MikamiUitOpen 6:38f7dce055d0 686 #include <cmsis_csm.h>
MikamiUitOpen 6:38f7dce055d0 687
MikamiUitOpen 6:38f7dce055d0 688 #endif
MikamiUitOpen 6:38f7dce055d0 689
MikamiUitOpen 6:38f7dce055d0 690 /*@} end of group CMSIS_SIMD_intrinsics */
MikamiUitOpen 6:38f7dce055d0 691
MikamiUitOpen 6:38f7dce055d0 692
MikamiUitOpen 6:38f7dce055d0 693 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 694 }
MikamiUitOpen 6:38f7dce055d0 695 #endif
MikamiUitOpen 6:38f7dce055d0 696
MikamiUitOpen 6:38f7dce055d0 697 #endif /* __CORE_CMSIMD_H */