不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_cmInstr.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 * @file core_cmInstr.h
MikamiUitOpen 6:38f7dce055d0 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
MikamiUitOpen 6:38f7dce055d0 4 * @version V4.10
MikamiUitOpen 6:38f7dce055d0 5 * @date 18. March 2015
MikamiUitOpen 6:38f7dce055d0 6 *
MikamiUitOpen 6:38f7dce055d0 7 * @note
MikamiUitOpen 6:38f7dce055d0 8 *
MikamiUitOpen 6:38f7dce055d0 9 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11
MikamiUitOpen 6:38f7dce055d0 12 All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 *
MikamiUitOpen 6:38f7dce055d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 #ifndef __CORE_CMINSTR_H
MikamiUitOpen 6:38f7dce055d0 39 #define __CORE_CMINSTR_H
MikamiUitOpen 6:38f7dce055d0 40
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 /* ########################## Core Instruction Access ######################### */
MikamiUitOpen 6:38f7dce055d0 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
MikamiUitOpen 6:38f7dce055d0 44 Access to dedicated instructions
MikamiUitOpen 6:38f7dce055d0 45 @{
MikamiUitOpen 6:38f7dce055d0 46 */
MikamiUitOpen 6:38f7dce055d0 47
MikamiUitOpen 6:38f7dce055d0 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 6:38f7dce055d0 49 /* ARM armcc specific functions */
MikamiUitOpen 6:38f7dce055d0 50
MikamiUitOpen 6:38f7dce055d0 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 6:38f7dce055d0 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 6:38f7dce055d0 53 #endif
MikamiUitOpen 6:38f7dce055d0 54
MikamiUitOpen 6:38f7dce055d0 55
MikamiUitOpen 6:38f7dce055d0 56 /** \brief No Operation
MikamiUitOpen 6:38f7dce055d0 57
MikamiUitOpen 6:38f7dce055d0 58 No Operation does nothing. This instruction can be used for code alignment purposes.
MikamiUitOpen 6:38f7dce055d0 59 */
MikamiUitOpen 6:38f7dce055d0 60 #define __NOP __nop
MikamiUitOpen 6:38f7dce055d0 61
MikamiUitOpen 6:38f7dce055d0 62
MikamiUitOpen 6:38f7dce055d0 63 /** \brief Wait For Interrupt
MikamiUitOpen 6:38f7dce055d0 64
MikamiUitOpen 6:38f7dce055d0 65 Wait For Interrupt is a hint instruction that suspends execution
MikamiUitOpen 6:38f7dce055d0 66 until one of a number of events occurs.
MikamiUitOpen 6:38f7dce055d0 67 */
MikamiUitOpen 6:38f7dce055d0 68 #define __WFI __wfi
MikamiUitOpen 6:38f7dce055d0 69
MikamiUitOpen 6:38f7dce055d0 70
MikamiUitOpen 6:38f7dce055d0 71 /** \brief Wait For Event
MikamiUitOpen 6:38f7dce055d0 72
MikamiUitOpen 6:38f7dce055d0 73 Wait For Event is a hint instruction that permits the processor to enter
MikamiUitOpen 6:38f7dce055d0 74 a low-power state until one of a number of events occurs.
MikamiUitOpen 6:38f7dce055d0 75 */
MikamiUitOpen 6:38f7dce055d0 76 #define __WFE __wfe
MikamiUitOpen 6:38f7dce055d0 77
MikamiUitOpen 6:38f7dce055d0 78
MikamiUitOpen 6:38f7dce055d0 79 /** \brief Send Event
MikamiUitOpen 6:38f7dce055d0 80
MikamiUitOpen 6:38f7dce055d0 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
MikamiUitOpen 6:38f7dce055d0 82 */
MikamiUitOpen 6:38f7dce055d0 83 #define __SEV __sev
MikamiUitOpen 6:38f7dce055d0 84
MikamiUitOpen 6:38f7dce055d0 85
MikamiUitOpen 6:38f7dce055d0 86 /** \brief Instruction Synchronization Barrier
MikamiUitOpen 6:38f7dce055d0 87
MikamiUitOpen 6:38f7dce055d0 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
MikamiUitOpen 6:38f7dce055d0 89 so that all instructions following the ISB are fetched from cache or
MikamiUitOpen 6:38f7dce055d0 90 memory, after the instruction has been completed.
MikamiUitOpen 6:38f7dce055d0 91 */
MikamiUitOpen 6:38f7dce055d0 92 #define __ISB() do {\
MikamiUitOpen 6:38f7dce055d0 93 __schedule_barrier();\
MikamiUitOpen 6:38f7dce055d0 94 __isb(0xF);\
MikamiUitOpen 6:38f7dce055d0 95 __schedule_barrier();\
MikamiUitOpen 6:38f7dce055d0 96 } while (0)
MikamiUitOpen 6:38f7dce055d0 97
MikamiUitOpen 6:38f7dce055d0 98 /** \brief Data Synchronization Barrier
MikamiUitOpen 6:38f7dce055d0 99
MikamiUitOpen 6:38f7dce055d0 100 This function acts as a special kind of Data Memory Barrier.
MikamiUitOpen 6:38f7dce055d0 101 It completes when all explicit memory accesses before this instruction complete.
MikamiUitOpen 6:38f7dce055d0 102 */
MikamiUitOpen 6:38f7dce055d0 103 #define __DSB() do {\
MikamiUitOpen 6:38f7dce055d0 104 __schedule_barrier();\
MikamiUitOpen 6:38f7dce055d0 105 __dsb(0xF);\
MikamiUitOpen 6:38f7dce055d0 106 __schedule_barrier();\
MikamiUitOpen 6:38f7dce055d0 107 } while (0)
MikamiUitOpen 6:38f7dce055d0 108
MikamiUitOpen 6:38f7dce055d0 109 /** \brief Data Memory Barrier
MikamiUitOpen 6:38f7dce055d0 110
MikamiUitOpen 6:38f7dce055d0 111 This function ensures the apparent order of the explicit memory operations before
MikamiUitOpen 6:38f7dce055d0 112 and after the instruction, without ensuring their completion.
MikamiUitOpen 6:38f7dce055d0 113 */
MikamiUitOpen 6:38f7dce055d0 114 #define __DMB() do {\
MikamiUitOpen 6:38f7dce055d0 115 __schedule_barrier();\
MikamiUitOpen 6:38f7dce055d0 116 __dmb(0xF);\
MikamiUitOpen 6:38f7dce055d0 117 __schedule_barrier();\
MikamiUitOpen 6:38f7dce055d0 118 } while (0)
MikamiUitOpen 6:38f7dce055d0 119
MikamiUitOpen 6:38f7dce055d0 120 /** \brief Reverse byte order (32 bit)
MikamiUitOpen 6:38f7dce055d0 121
MikamiUitOpen 6:38f7dce055d0 122 This function reverses the byte order in integer value.
MikamiUitOpen 6:38f7dce055d0 123
MikamiUitOpen 6:38f7dce055d0 124 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 125 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 126 */
MikamiUitOpen 6:38f7dce055d0 127 #define __REV __rev
MikamiUitOpen 6:38f7dce055d0 128
MikamiUitOpen 6:38f7dce055d0 129
MikamiUitOpen 6:38f7dce055d0 130 /** \brief Reverse byte order (16 bit)
MikamiUitOpen 6:38f7dce055d0 131
MikamiUitOpen 6:38f7dce055d0 132 This function reverses the byte order in two unsigned short values.
MikamiUitOpen 6:38f7dce055d0 133
MikamiUitOpen 6:38f7dce055d0 134 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 135 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 136 */
MikamiUitOpen 6:38f7dce055d0 137 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 6:38f7dce055d0 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 139 {
MikamiUitOpen 6:38f7dce055d0 140 rev16 r0, r0
MikamiUitOpen 6:38f7dce055d0 141 bx lr
MikamiUitOpen 6:38f7dce055d0 142 }
MikamiUitOpen 6:38f7dce055d0 143 #endif
MikamiUitOpen 6:38f7dce055d0 144
MikamiUitOpen 6:38f7dce055d0 145 /** \brief Reverse byte order in signed short value
MikamiUitOpen 6:38f7dce055d0 146
MikamiUitOpen 6:38f7dce055d0 147 This function reverses the byte order in a signed short value with sign extension to integer.
MikamiUitOpen 6:38f7dce055d0 148
MikamiUitOpen 6:38f7dce055d0 149 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 150 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 151 */
MikamiUitOpen 6:38f7dce055d0 152 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 6:38f7dce055d0 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
MikamiUitOpen 6:38f7dce055d0 154 {
MikamiUitOpen 6:38f7dce055d0 155 revsh r0, r0
MikamiUitOpen 6:38f7dce055d0 156 bx lr
MikamiUitOpen 6:38f7dce055d0 157 }
MikamiUitOpen 6:38f7dce055d0 158 #endif
MikamiUitOpen 6:38f7dce055d0 159
MikamiUitOpen 6:38f7dce055d0 160
MikamiUitOpen 6:38f7dce055d0 161 /** \brief Rotate Right in unsigned value (32 bit)
MikamiUitOpen 6:38f7dce055d0 162
MikamiUitOpen 6:38f7dce055d0 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
MikamiUitOpen 6:38f7dce055d0 164
MikamiUitOpen 6:38f7dce055d0 165 \param [in] value Value to rotate
MikamiUitOpen 6:38f7dce055d0 166 \param [in] value Number of Bits to rotate
MikamiUitOpen 6:38f7dce055d0 167 \return Rotated value
MikamiUitOpen 6:38f7dce055d0 168 */
MikamiUitOpen 6:38f7dce055d0 169 #define __ROR __ror
MikamiUitOpen 6:38f7dce055d0 170
MikamiUitOpen 6:38f7dce055d0 171
MikamiUitOpen 6:38f7dce055d0 172 /** \brief Breakpoint
MikamiUitOpen 6:38f7dce055d0 173
MikamiUitOpen 6:38f7dce055d0 174 This function causes the processor to enter Debug state.
MikamiUitOpen 6:38f7dce055d0 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
MikamiUitOpen 6:38f7dce055d0 176
MikamiUitOpen 6:38f7dce055d0 177 \param [in] value is ignored by the processor.
MikamiUitOpen 6:38f7dce055d0 178 If required, a debugger can use it to store additional information about the breakpoint.
MikamiUitOpen 6:38f7dce055d0 179 */
MikamiUitOpen 6:38f7dce055d0 180 #define __BKPT(value) __breakpoint(value)
MikamiUitOpen 6:38f7dce055d0 181
MikamiUitOpen 6:38f7dce055d0 182
MikamiUitOpen 6:38f7dce055d0 183 /** \brief Reverse bit order of value
MikamiUitOpen 6:38f7dce055d0 184
MikamiUitOpen 6:38f7dce055d0 185 This function reverses the bit order of the given value.
MikamiUitOpen 6:38f7dce055d0 186
MikamiUitOpen 6:38f7dce055d0 187 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 188 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 189 */
MikamiUitOpen 6:38f7dce055d0 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 6:38f7dce055d0 191 #define __RBIT __rbit
MikamiUitOpen 6:38f7dce055d0 192 #else
MikamiUitOpen 6:38f7dce055d0 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 194 {
MikamiUitOpen 6:38f7dce055d0 195 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
MikamiUitOpen 6:38f7dce055d0 197
MikamiUitOpen 6:38f7dce055d0 198 result = value; // r will be reversed bits of v; first get LSB of v
MikamiUitOpen 6:38f7dce055d0 199 for (value >>= 1; value; value >>= 1)
MikamiUitOpen 6:38f7dce055d0 200 {
MikamiUitOpen 6:38f7dce055d0 201 result <<= 1;
MikamiUitOpen 6:38f7dce055d0 202 result |= value & 1;
MikamiUitOpen 6:38f7dce055d0 203 s--;
MikamiUitOpen 6:38f7dce055d0 204 }
MikamiUitOpen 6:38f7dce055d0 205 result <<= s; // shift when v's highest bits are zero
MikamiUitOpen 6:38f7dce055d0 206 return(result);
MikamiUitOpen 6:38f7dce055d0 207 }
MikamiUitOpen 6:38f7dce055d0 208 #endif
MikamiUitOpen 6:38f7dce055d0 209
MikamiUitOpen 6:38f7dce055d0 210
MikamiUitOpen 6:38f7dce055d0 211 /** \brief Count leading zeros
MikamiUitOpen 6:38f7dce055d0 212
MikamiUitOpen 6:38f7dce055d0 213 This function counts the number of leading zeros of a data value.
MikamiUitOpen 6:38f7dce055d0 214
MikamiUitOpen 6:38f7dce055d0 215 \param [in] value Value to count the leading zeros
MikamiUitOpen 6:38f7dce055d0 216 \return number of leading zeros in value
MikamiUitOpen 6:38f7dce055d0 217 */
MikamiUitOpen 6:38f7dce055d0 218 #define __CLZ __clz
MikamiUitOpen 6:38f7dce055d0 219
MikamiUitOpen 6:38f7dce055d0 220
MikamiUitOpen 6:38f7dce055d0 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 6:38f7dce055d0 222
MikamiUitOpen 6:38f7dce055d0 223 /** \brief LDR Exclusive (8 bit)
MikamiUitOpen 6:38f7dce055d0 224
MikamiUitOpen 6:38f7dce055d0 225 This function executes a exclusive LDR instruction for 8 bit value.
MikamiUitOpen 6:38f7dce055d0 226
MikamiUitOpen 6:38f7dce055d0 227 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 228 \return value of type uint8_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 229 */
MikamiUitOpen 6:38f7dce055d0 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
MikamiUitOpen 6:38f7dce055d0 231
MikamiUitOpen 6:38f7dce055d0 232
MikamiUitOpen 6:38f7dce055d0 233 /** \brief LDR Exclusive (16 bit)
MikamiUitOpen 6:38f7dce055d0 234
MikamiUitOpen 6:38f7dce055d0 235 This function executes a exclusive LDR instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 236
MikamiUitOpen 6:38f7dce055d0 237 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 238 \return value of type uint16_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 239 */
MikamiUitOpen 6:38f7dce055d0 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
MikamiUitOpen 6:38f7dce055d0 241
MikamiUitOpen 6:38f7dce055d0 242
MikamiUitOpen 6:38f7dce055d0 243 /** \brief LDR Exclusive (32 bit)
MikamiUitOpen 6:38f7dce055d0 244
MikamiUitOpen 6:38f7dce055d0 245 This function executes a exclusive LDR instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 246
MikamiUitOpen 6:38f7dce055d0 247 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 248 \return value of type uint32_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 249 */
MikamiUitOpen 6:38f7dce055d0 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
MikamiUitOpen 6:38f7dce055d0 251
MikamiUitOpen 6:38f7dce055d0 252
MikamiUitOpen 6:38f7dce055d0 253 /** \brief STR Exclusive (8 bit)
MikamiUitOpen 6:38f7dce055d0 254
MikamiUitOpen 6:38f7dce055d0 255 This function executes a exclusive STR instruction for 8 bit values.
MikamiUitOpen 6:38f7dce055d0 256
MikamiUitOpen 6:38f7dce055d0 257 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 258 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 259 \return 0 Function succeeded
MikamiUitOpen 6:38f7dce055d0 260 \return 1 Function failed
MikamiUitOpen 6:38f7dce055d0 261 */
MikamiUitOpen 6:38f7dce055d0 262 #define __STREXB(value, ptr) __strex(value, ptr)
MikamiUitOpen 6:38f7dce055d0 263
MikamiUitOpen 6:38f7dce055d0 264
MikamiUitOpen 6:38f7dce055d0 265 /** \brief STR Exclusive (16 bit)
MikamiUitOpen 6:38f7dce055d0 266
MikamiUitOpen 6:38f7dce055d0 267 This function executes a exclusive STR instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 268
MikamiUitOpen 6:38f7dce055d0 269 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 270 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 271 \return 0 Function succeeded
MikamiUitOpen 6:38f7dce055d0 272 \return 1 Function failed
MikamiUitOpen 6:38f7dce055d0 273 */
MikamiUitOpen 6:38f7dce055d0 274 #define __STREXH(value, ptr) __strex(value, ptr)
MikamiUitOpen 6:38f7dce055d0 275
MikamiUitOpen 6:38f7dce055d0 276
MikamiUitOpen 6:38f7dce055d0 277 /** \brief STR Exclusive (32 bit)
MikamiUitOpen 6:38f7dce055d0 278
MikamiUitOpen 6:38f7dce055d0 279 This function executes a exclusive STR instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 280
MikamiUitOpen 6:38f7dce055d0 281 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 282 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 283 \return 0 Function succeeded
MikamiUitOpen 6:38f7dce055d0 284 \return 1 Function failed
MikamiUitOpen 6:38f7dce055d0 285 */
MikamiUitOpen 6:38f7dce055d0 286 #define __STREXW(value, ptr) __strex(value, ptr)
MikamiUitOpen 6:38f7dce055d0 287
MikamiUitOpen 6:38f7dce055d0 288
MikamiUitOpen 6:38f7dce055d0 289 /** \brief Remove the exclusive lock
MikamiUitOpen 6:38f7dce055d0 290
MikamiUitOpen 6:38f7dce055d0 291 This function removes the exclusive lock which is created by LDREX.
MikamiUitOpen 6:38f7dce055d0 292
MikamiUitOpen 6:38f7dce055d0 293 */
MikamiUitOpen 6:38f7dce055d0 294 #define __CLREX __clrex
MikamiUitOpen 6:38f7dce055d0 295
MikamiUitOpen 6:38f7dce055d0 296
MikamiUitOpen 6:38f7dce055d0 297 /** \brief Signed Saturate
MikamiUitOpen 6:38f7dce055d0 298
MikamiUitOpen 6:38f7dce055d0 299 This function saturates a signed value.
MikamiUitOpen 6:38f7dce055d0 300
MikamiUitOpen 6:38f7dce055d0 301 \param [in] value Value to be saturated
MikamiUitOpen 6:38f7dce055d0 302 \param [in] sat Bit position to saturate to (1..32)
MikamiUitOpen 6:38f7dce055d0 303 \return Saturated value
MikamiUitOpen 6:38f7dce055d0 304 */
MikamiUitOpen 6:38f7dce055d0 305 #define __SSAT __ssat
MikamiUitOpen 6:38f7dce055d0 306
MikamiUitOpen 6:38f7dce055d0 307
MikamiUitOpen 6:38f7dce055d0 308 /** \brief Unsigned Saturate
MikamiUitOpen 6:38f7dce055d0 309
MikamiUitOpen 6:38f7dce055d0 310 This function saturates an unsigned value.
MikamiUitOpen 6:38f7dce055d0 311
MikamiUitOpen 6:38f7dce055d0 312 \param [in] value Value to be saturated
MikamiUitOpen 6:38f7dce055d0 313 \param [in] sat Bit position to saturate to (0..31)
MikamiUitOpen 6:38f7dce055d0 314 \return Saturated value
MikamiUitOpen 6:38f7dce055d0 315 */
MikamiUitOpen 6:38f7dce055d0 316 #define __USAT __usat
MikamiUitOpen 6:38f7dce055d0 317
MikamiUitOpen 6:38f7dce055d0 318
MikamiUitOpen 6:38f7dce055d0 319 /** \brief Rotate Right with Extend (32 bit)
MikamiUitOpen 6:38f7dce055d0 320
MikamiUitOpen 6:38f7dce055d0 321 This function moves each bit of a bitstring right by one bit.
MikamiUitOpen 6:38f7dce055d0 322 The carry input is shifted in at the left end of the bitstring.
MikamiUitOpen 6:38f7dce055d0 323
MikamiUitOpen 6:38f7dce055d0 324 \param [in] value Value to rotate
MikamiUitOpen 6:38f7dce055d0 325 \return Rotated value
MikamiUitOpen 6:38f7dce055d0 326 */
MikamiUitOpen 6:38f7dce055d0 327 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 6:38f7dce055d0 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 329 {
MikamiUitOpen 6:38f7dce055d0 330 rrx r0, r0
MikamiUitOpen 6:38f7dce055d0 331 bx lr
MikamiUitOpen 6:38f7dce055d0 332 }
MikamiUitOpen 6:38f7dce055d0 333 #endif
MikamiUitOpen 6:38f7dce055d0 334
MikamiUitOpen 6:38f7dce055d0 335
MikamiUitOpen 6:38f7dce055d0 336 /** \brief LDRT Unprivileged (8 bit)
MikamiUitOpen 6:38f7dce055d0 337
MikamiUitOpen 6:38f7dce055d0 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
MikamiUitOpen 6:38f7dce055d0 339
MikamiUitOpen 6:38f7dce055d0 340 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 341 \return value of type uint8_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 342 */
MikamiUitOpen 6:38f7dce055d0 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
MikamiUitOpen 6:38f7dce055d0 344
MikamiUitOpen 6:38f7dce055d0 345
MikamiUitOpen 6:38f7dce055d0 346 /** \brief LDRT Unprivileged (16 bit)
MikamiUitOpen 6:38f7dce055d0 347
MikamiUitOpen 6:38f7dce055d0 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 349
MikamiUitOpen 6:38f7dce055d0 350 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 351 \return value of type uint16_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 352 */
MikamiUitOpen 6:38f7dce055d0 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
MikamiUitOpen 6:38f7dce055d0 354
MikamiUitOpen 6:38f7dce055d0 355
MikamiUitOpen 6:38f7dce055d0 356 /** \brief LDRT Unprivileged (32 bit)
MikamiUitOpen 6:38f7dce055d0 357
MikamiUitOpen 6:38f7dce055d0 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 359
MikamiUitOpen 6:38f7dce055d0 360 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 361 \return value of type uint32_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 362 */
MikamiUitOpen 6:38f7dce055d0 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
MikamiUitOpen 6:38f7dce055d0 364
MikamiUitOpen 6:38f7dce055d0 365
MikamiUitOpen 6:38f7dce055d0 366 /** \brief STRT Unprivileged (8 bit)
MikamiUitOpen 6:38f7dce055d0 367
MikamiUitOpen 6:38f7dce055d0 368 This function executes a Unprivileged STRT instruction for 8 bit values.
MikamiUitOpen 6:38f7dce055d0 369
MikamiUitOpen 6:38f7dce055d0 370 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 371 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 372 */
MikamiUitOpen 6:38f7dce055d0 373 #define __STRBT(value, ptr) __strt(value, ptr)
MikamiUitOpen 6:38f7dce055d0 374
MikamiUitOpen 6:38f7dce055d0 375
MikamiUitOpen 6:38f7dce055d0 376 /** \brief STRT Unprivileged (16 bit)
MikamiUitOpen 6:38f7dce055d0 377
MikamiUitOpen 6:38f7dce055d0 378 This function executes a Unprivileged STRT instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 379
MikamiUitOpen 6:38f7dce055d0 380 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 381 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 382 */
MikamiUitOpen 6:38f7dce055d0 383 #define __STRHT(value, ptr) __strt(value, ptr)
MikamiUitOpen 6:38f7dce055d0 384
MikamiUitOpen 6:38f7dce055d0 385
MikamiUitOpen 6:38f7dce055d0 386 /** \brief STRT Unprivileged (32 bit)
MikamiUitOpen 6:38f7dce055d0 387
MikamiUitOpen 6:38f7dce055d0 388 This function executes a Unprivileged STRT instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 389
MikamiUitOpen 6:38f7dce055d0 390 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 391 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 392 */
MikamiUitOpen 6:38f7dce055d0 393 #define __STRT(value, ptr) __strt(value, ptr)
MikamiUitOpen 6:38f7dce055d0 394
MikamiUitOpen 6:38f7dce055d0 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 6:38f7dce055d0 396
MikamiUitOpen 6:38f7dce055d0 397
MikamiUitOpen 6:38f7dce055d0 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 6:38f7dce055d0 399 /* GNU gcc specific functions */
MikamiUitOpen 6:38f7dce055d0 400
MikamiUitOpen 6:38f7dce055d0 401 /* Define macros for porting to both thumb1 and thumb2.
MikamiUitOpen 6:38f7dce055d0 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
MikamiUitOpen 6:38f7dce055d0 403 * Otherwise, use general registers, specified by constrant "r" */
MikamiUitOpen 6:38f7dce055d0 404 #if defined (__thumb__) && !defined (__thumb2__)
MikamiUitOpen 6:38f7dce055d0 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
MikamiUitOpen 6:38f7dce055d0 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
MikamiUitOpen 6:38f7dce055d0 407 #else
MikamiUitOpen 6:38f7dce055d0 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
MikamiUitOpen 6:38f7dce055d0 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
MikamiUitOpen 6:38f7dce055d0 410 #endif
MikamiUitOpen 6:38f7dce055d0 411
MikamiUitOpen 6:38f7dce055d0 412 /** \brief No Operation
MikamiUitOpen 6:38f7dce055d0 413
MikamiUitOpen 6:38f7dce055d0 414 No Operation does nothing. This instruction can be used for code alignment purposes.
MikamiUitOpen 6:38f7dce055d0 415 */
MikamiUitOpen 6:38f7dce055d0 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
MikamiUitOpen 6:38f7dce055d0 417 {
MikamiUitOpen 6:38f7dce055d0 418 __ASM volatile ("nop");
MikamiUitOpen 6:38f7dce055d0 419 }
MikamiUitOpen 6:38f7dce055d0 420
MikamiUitOpen 6:38f7dce055d0 421
MikamiUitOpen 6:38f7dce055d0 422 /** \brief Wait For Interrupt
MikamiUitOpen 6:38f7dce055d0 423
MikamiUitOpen 6:38f7dce055d0 424 Wait For Interrupt is a hint instruction that suspends execution
MikamiUitOpen 6:38f7dce055d0 425 until one of a number of events occurs.
MikamiUitOpen 6:38f7dce055d0 426 */
MikamiUitOpen 6:38f7dce055d0 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
MikamiUitOpen 6:38f7dce055d0 428 {
MikamiUitOpen 6:38f7dce055d0 429 __ASM volatile ("wfi");
MikamiUitOpen 6:38f7dce055d0 430 }
MikamiUitOpen 6:38f7dce055d0 431
MikamiUitOpen 6:38f7dce055d0 432
MikamiUitOpen 6:38f7dce055d0 433 /** \brief Wait For Event
MikamiUitOpen 6:38f7dce055d0 434
MikamiUitOpen 6:38f7dce055d0 435 Wait For Event is a hint instruction that permits the processor to enter
MikamiUitOpen 6:38f7dce055d0 436 a low-power state until one of a number of events occurs.
MikamiUitOpen 6:38f7dce055d0 437 */
MikamiUitOpen 6:38f7dce055d0 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
MikamiUitOpen 6:38f7dce055d0 439 {
MikamiUitOpen 6:38f7dce055d0 440 __ASM volatile ("wfe");
MikamiUitOpen 6:38f7dce055d0 441 }
MikamiUitOpen 6:38f7dce055d0 442
MikamiUitOpen 6:38f7dce055d0 443
MikamiUitOpen 6:38f7dce055d0 444 /** \brief Send Event
MikamiUitOpen 6:38f7dce055d0 445
MikamiUitOpen 6:38f7dce055d0 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
MikamiUitOpen 6:38f7dce055d0 447 */
MikamiUitOpen 6:38f7dce055d0 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
MikamiUitOpen 6:38f7dce055d0 449 {
MikamiUitOpen 6:38f7dce055d0 450 __ASM volatile ("sev");
MikamiUitOpen 6:38f7dce055d0 451 }
MikamiUitOpen 6:38f7dce055d0 452
MikamiUitOpen 6:38f7dce055d0 453
MikamiUitOpen 6:38f7dce055d0 454 /** \brief Instruction Synchronization Barrier
MikamiUitOpen 6:38f7dce055d0 455
MikamiUitOpen 6:38f7dce055d0 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
MikamiUitOpen 6:38f7dce055d0 457 so that all instructions following the ISB are fetched from cache or
MikamiUitOpen 6:38f7dce055d0 458 memory, after the instruction has been completed.
MikamiUitOpen 6:38f7dce055d0 459 */
MikamiUitOpen 6:38f7dce055d0 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
MikamiUitOpen 6:38f7dce055d0 461 {
MikamiUitOpen 6:38f7dce055d0 462 __ASM volatile ("isb 0xF":::"memory");
MikamiUitOpen 6:38f7dce055d0 463 }
MikamiUitOpen 6:38f7dce055d0 464
MikamiUitOpen 6:38f7dce055d0 465
MikamiUitOpen 6:38f7dce055d0 466 /** \brief Data Synchronization Barrier
MikamiUitOpen 6:38f7dce055d0 467
MikamiUitOpen 6:38f7dce055d0 468 This function acts as a special kind of Data Memory Barrier.
MikamiUitOpen 6:38f7dce055d0 469 It completes when all explicit memory accesses before this instruction complete.
MikamiUitOpen 6:38f7dce055d0 470 */
MikamiUitOpen 6:38f7dce055d0 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
MikamiUitOpen 6:38f7dce055d0 472 {
MikamiUitOpen 6:38f7dce055d0 473 __ASM volatile ("dsb 0xF":::"memory");
MikamiUitOpen 6:38f7dce055d0 474 }
MikamiUitOpen 6:38f7dce055d0 475
MikamiUitOpen 6:38f7dce055d0 476
MikamiUitOpen 6:38f7dce055d0 477 /** \brief Data Memory Barrier
MikamiUitOpen 6:38f7dce055d0 478
MikamiUitOpen 6:38f7dce055d0 479 This function ensures the apparent order of the explicit memory operations before
MikamiUitOpen 6:38f7dce055d0 480 and after the instruction, without ensuring their completion.
MikamiUitOpen 6:38f7dce055d0 481 */
MikamiUitOpen 6:38f7dce055d0 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
MikamiUitOpen 6:38f7dce055d0 483 {
MikamiUitOpen 6:38f7dce055d0 484 __ASM volatile ("dmb 0xF":::"memory");
MikamiUitOpen 6:38f7dce055d0 485 }
MikamiUitOpen 6:38f7dce055d0 486
MikamiUitOpen 6:38f7dce055d0 487
MikamiUitOpen 6:38f7dce055d0 488 /** \brief Reverse byte order (32 bit)
MikamiUitOpen 6:38f7dce055d0 489
MikamiUitOpen 6:38f7dce055d0 490 This function reverses the byte order in integer value.
MikamiUitOpen 6:38f7dce055d0 491
MikamiUitOpen 6:38f7dce055d0 492 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 493 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 494 */
MikamiUitOpen 6:38f7dce055d0 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 496 {
MikamiUitOpen 6:38f7dce055d0 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
MikamiUitOpen 6:38f7dce055d0 498 return __builtin_bswap32(value);
MikamiUitOpen 6:38f7dce055d0 499 #else
MikamiUitOpen 6:38f7dce055d0 500 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 501
MikamiUitOpen 6:38f7dce055d0 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 6:38f7dce055d0 503 return(result);
MikamiUitOpen 6:38f7dce055d0 504 #endif
MikamiUitOpen 6:38f7dce055d0 505 }
MikamiUitOpen 6:38f7dce055d0 506
MikamiUitOpen 6:38f7dce055d0 507
MikamiUitOpen 6:38f7dce055d0 508 /** \brief Reverse byte order (16 bit)
MikamiUitOpen 6:38f7dce055d0 509
MikamiUitOpen 6:38f7dce055d0 510 This function reverses the byte order in two unsigned short values.
MikamiUitOpen 6:38f7dce055d0 511
MikamiUitOpen 6:38f7dce055d0 512 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 513 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 514 */
MikamiUitOpen 6:38f7dce055d0 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 516 {
MikamiUitOpen 6:38f7dce055d0 517 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 518
MikamiUitOpen 6:38f7dce055d0 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 6:38f7dce055d0 520 return(result);
MikamiUitOpen 6:38f7dce055d0 521 }
MikamiUitOpen 6:38f7dce055d0 522
MikamiUitOpen 6:38f7dce055d0 523
MikamiUitOpen 6:38f7dce055d0 524 /** \brief Reverse byte order in signed short value
MikamiUitOpen 6:38f7dce055d0 525
MikamiUitOpen 6:38f7dce055d0 526 This function reverses the byte order in a signed short value with sign extension to integer.
MikamiUitOpen 6:38f7dce055d0 527
MikamiUitOpen 6:38f7dce055d0 528 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 529 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 530 */
MikamiUitOpen 6:38f7dce055d0 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
MikamiUitOpen 6:38f7dce055d0 532 {
MikamiUitOpen 6:38f7dce055d0 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 6:38f7dce055d0 534 return (short)__builtin_bswap16(value);
MikamiUitOpen 6:38f7dce055d0 535 #else
MikamiUitOpen 6:38f7dce055d0 536 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 537
MikamiUitOpen 6:38f7dce055d0 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 6:38f7dce055d0 539 return(result);
MikamiUitOpen 6:38f7dce055d0 540 #endif
MikamiUitOpen 6:38f7dce055d0 541 }
MikamiUitOpen 6:38f7dce055d0 542
MikamiUitOpen 6:38f7dce055d0 543
MikamiUitOpen 6:38f7dce055d0 544 /** \brief Rotate Right in unsigned value (32 bit)
MikamiUitOpen 6:38f7dce055d0 545
MikamiUitOpen 6:38f7dce055d0 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
MikamiUitOpen 6:38f7dce055d0 547
MikamiUitOpen 6:38f7dce055d0 548 \param [in] value Value to rotate
MikamiUitOpen 6:38f7dce055d0 549 \param [in] value Number of Bits to rotate
MikamiUitOpen 6:38f7dce055d0 550 \return Rotated value
MikamiUitOpen 6:38f7dce055d0 551 */
MikamiUitOpen 6:38f7dce055d0 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 553 {
MikamiUitOpen 6:38f7dce055d0 554 return (op1 >> op2) | (op1 << (32 - op2));
MikamiUitOpen 6:38f7dce055d0 555 }
MikamiUitOpen 6:38f7dce055d0 556
MikamiUitOpen 6:38f7dce055d0 557
MikamiUitOpen 6:38f7dce055d0 558 /** \brief Breakpoint
MikamiUitOpen 6:38f7dce055d0 559
MikamiUitOpen 6:38f7dce055d0 560 This function causes the processor to enter Debug state.
MikamiUitOpen 6:38f7dce055d0 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
MikamiUitOpen 6:38f7dce055d0 562
MikamiUitOpen 6:38f7dce055d0 563 \param [in] value is ignored by the processor.
MikamiUitOpen 6:38f7dce055d0 564 If required, a debugger can use it to store additional information about the breakpoint.
MikamiUitOpen 6:38f7dce055d0 565 */
MikamiUitOpen 6:38f7dce055d0 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
MikamiUitOpen 6:38f7dce055d0 567
MikamiUitOpen 6:38f7dce055d0 568
MikamiUitOpen 6:38f7dce055d0 569 /** \brief Reverse bit order of value
MikamiUitOpen 6:38f7dce055d0 570
MikamiUitOpen 6:38f7dce055d0 571 This function reverses the bit order of the given value.
MikamiUitOpen 6:38f7dce055d0 572
MikamiUitOpen 6:38f7dce055d0 573 \param [in] value Value to reverse
MikamiUitOpen 6:38f7dce055d0 574 \return Reversed value
MikamiUitOpen 6:38f7dce055d0 575 */
MikamiUitOpen 6:38f7dce055d0 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 577 {
MikamiUitOpen 6:38f7dce055d0 578 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 579
MikamiUitOpen 6:38f7dce055d0 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 6:38f7dce055d0 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
MikamiUitOpen 6:38f7dce055d0 582 #else
MikamiUitOpen 6:38f7dce055d0 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
MikamiUitOpen 6:38f7dce055d0 584
MikamiUitOpen 6:38f7dce055d0 585 result = value; // r will be reversed bits of v; first get LSB of v
MikamiUitOpen 6:38f7dce055d0 586 for (value >>= 1; value; value >>= 1)
MikamiUitOpen 6:38f7dce055d0 587 {
MikamiUitOpen 6:38f7dce055d0 588 result <<= 1;
MikamiUitOpen 6:38f7dce055d0 589 result |= value & 1;
MikamiUitOpen 6:38f7dce055d0 590 s--;
MikamiUitOpen 6:38f7dce055d0 591 }
MikamiUitOpen 6:38f7dce055d0 592 result <<= s; // shift when v's highest bits are zero
MikamiUitOpen 6:38f7dce055d0 593 #endif
MikamiUitOpen 6:38f7dce055d0 594 return(result);
MikamiUitOpen 6:38f7dce055d0 595 }
MikamiUitOpen 6:38f7dce055d0 596
MikamiUitOpen 6:38f7dce055d0 597
MikamiUitOpen 6:38f7dce055d0 598 /** \brief Count leading zeros
MikamiUitOpen 6:38f7dce055d0 599
MikamiUitOpen 6:38f7dce055d0 600 This function counts the number of leading zeros of a data value.
MikamiUitOpen 6:38f7dce055d0 601
MikamiUitOpen 6:38f7dce055d0 602 \param [in] value Value to count the leading zeros
MikamiUitOpen 6:38f7dce055d0 603 \return number of leading zeros in value
MikamiUitOpen 6:38f7dce055d0 604 */
MikamiUitOpen 6:38f7dce055d0 605 #define __CLZ __builtin_clz
MikamiUitOpen 6:38f7dce055d0 606
MikamiUitOpen 6:38f7dce055d0 607
MikamiUitOpen 6:38f7dce055d0 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 6:38f7dce055d0 609
MikamiUitOpen 6:38f7dce055d0 610 /** \brief LDR Exclusive (8 bit)
MikamiUitOpen 6:38f7dce055d0 611
MikamiUitOpen 6:38f7dce055d0 612 This function executes a exclusive LDR instruction for 8 bit value.
MikamiUitOpen 6:38f7dce055d0 613
MikamiUitOpen 6:38f7dce055d0 614 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 615 \return value of type uint8_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 616 */
MikamiUitOpen 6:38f7dce055d0 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
MikamiUitOpen 6:38f7dce055d0 618 {
MikamiUitOpen 6:38f7dce055d0 619 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 620
MikamiUitOpen 6:38f7dce055d0 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 6:38f7dce055d0 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 6:38f7dce055d0 623 #else
MikamiUitOpen 6:38f7dce055d0 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 6:38f7dce055d0 625 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 6:38f7dce055d0 626 */
MikamiUitOpen 6:38f7dce055d0 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 6:38f7dce055d0 628 #endif
MikamiUitOpen 6:38f7dce055d0 629 return ((uint8_t) result); /* Add explicit type cast here */
MikamiUitOpen 6:38f7dce055d0 630 }
MikamiUitOpen 6:38f7dce055d0 631
MikamiUitOpen 6:38f7dce055d0 632
MikamiUitOpen 6:38f7dce055d0 633 /** \brief LDR Exclusive (16 bit)
MikamiUitOpen 6:38f7dce055d0 634
MikamiUitOpen 6:38f7dce055d0 635 This function executes a exclusive LDR instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 636
MikamiUitOpen 6:38f7dce055d0 637 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 638 \return value of type uint16_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 639 */
MikamiUitOpen 6:38f7dce055d0 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
MikamiUitOpen 6:38f7dce055d0 641 {
MikamiUitOpen 6:38f7dce055d0 642 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 643
MikamiUitOpen 6:38f7dce055d0 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 6:38f7dce055d0 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 6:38f7dce055d0 646 #else
MikamiUitOpen 6:38f7dce055d0 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 6:38f7dce055d0 648 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 6:38f7dce055d0 649 */
MikamiUitOpen 6:38f7dce055d0 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 6:38f7dce055d0 651 #endif
MikamiUitOpen 6:38f7dce055d0 652 return ((uint16_t) result); /* Add explicit type cast here */
MikamiUitOpen 6:38f7dce055d0 653 }
MikamiUitOpen 6:38f7dce055d0 654
MikamiUitOpen 6:38f7dce055d0 655
MikamiUitOpen 6:38f7dce055d0 656 /** \brief LDR Exclusive (32 bit)
MikamiUitOpen 6:38f7dce055d0 657
MikamiUitOpen 6:38f7dce055d0 658 This function executes a exclusive LDR instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 659
MikamiUitOpen 6:38f7dce055d0 660 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 661 \return value of type uint32_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 662 */
MikamiUitOpen 6:38f7dce055d0 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
MikamiUitOpen 6:38f7dce055d0 664 {
MikamiUitOpen 6:38f7dce055d0 665 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 666
MikamiUitOpen 6:38f7dce055d0 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 6:38f7dce055d0 668 return(result);
MikamiUitOpen 6:38f7dce055d0 669 }
MikamiUitOpen 6:38f7dce055d0 670
MikamiUitOpen 6:38f7dce055d0 671
MikamiUitOpen 6:38f7dce055d0 672 /** \brief STR Exclusive (8 bit)
MikamiUitOpen 6:38f7dce055d0 673
MikamiUitOpen 6:38f7dce055d0 674 This function executes a exclusive STR instruction for 8 bit values.
MikamiUitOpen 6:38f7dce055d0 675
MikamiUitOpen 6:38f7dce055d0 676 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 677 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 678 \return 0 Function succeeded
MikamiUitOpen 6:38f7dce055d0 679 \return 1 Function failed
MikamiUitOpen 6:38f7dce055d0 680 */
MikamiUitOpen 6:38f7dce055d0 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
MikamiUitOpen 6:38f7dce055d0 682 {
MikamiUitOpen 6:38f7dce055d0 683 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 684
MikamiUitOpen 6:38f7dce055d0 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 6:38f7dce055d0 686 return(result);
MikamiUitOpen 6:38f7dce055d0 687 }
MikamiUitOpen 6:38f7dce055d0 688
MikamiUitOpen 6:38f7dce055d0 689
MikamiUitOpen 6:38f7dce055d0 690 /** \brief STR Exclusive (16 bit)
MikamiUitOpen 6:38f7dce055d0 691
MikamiUitOpen 6:38f7dce055d0 692 This function executes a exclusive STR instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 693
MikamiUitOpen 6:38f7dce055d0 694 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 695 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 696 \return 0 Function succeeded
MikamiUitOpen 6:38f7dce055d0 697 \return 1 Function failed
MikamiUitOpen 6:38f7dce055d0 698 */
MikamiUitOpen 6:38f7dce055d0 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
MikamiUitOpen 6:38f7dce055d0 700 {
MikamiUitOpen 6:38f7dce055d0 701 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 702
MikamiUitOpen 6:38f7dce055d0 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 6:38f7dce055d0 704 return(result);
MikamiUitOpen 6:38f7dce055d0 705 }
MikamiUitOpen 6:38f7dce055d0 706
MikamiUitOpen 6:38f7dce055d0 707
MikamiUitOpen 6:38f7dce055d0 708 /** \brief STR Exclusive (32 bit)
MikamiUitOpen 6:38f7dce055d0 709
MikamiUitOpen 6:38f7dce055d0 710 This function executes a exclusive STR instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 711
MikamiUitOpen 6:38f7dce055d0 712 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 713 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 714 \return 0 Function succeeded
MikamiUitOpen 6:38f7dce055d0 715 \return 1 Function failed
MikamiUitOpen 6:38f7dce055d0 716 */
MikamiUitOpen 6:38f7dce055d0 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
MikamiUitOpen 6:38f7dce055d0 718 {
MikamiUitOpen 6:38f7dce055d0 719 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 720
MikamiUitOpen 6:38f7dce055d0 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
MikamiUitOpen 6:38f7dce055d0 722 return(result);
MikamiUitOpen 6:38f7dce055d0 723 }
MikamiUitOpen 6:38f7dce055d0 724
MikamiUitOpen 6:38f7dce055d0 725
MikamiUitOpen 6:38f7dce055d0 726 /** \brief Remove the exclusive lock
MikamiUitOpen 6:38f7dce055d0 727
MikamiUitOpen 6:38f7dce055d0 728 This function removes the exclusive lock which is created by LDREX.
MikamiUitOpen 6:38f7dce055d0 729
MikamiUitOpen 6:38f7dce055d0 730 */
MikamiUitOpen 6:38f7dce055d0 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
MikamiUitOpen 6:38f7dce055d0 732 {
MikamiUitOpen 6:38f7dce055d0 733 __ASM volatile ("clrex" ::: "memory");
MikamiUitOpen 6:38f7dce055d0 734 }
MikamiUitOpen 6:38f7dce055d0 735
MikamiUitOpen 6:38f7dce055d0 736
MikamiUitOpen 6:38f7dce055d0 737 /** \brief Signed Saturate
MikamiUitOpen 6:38f7dce055d0 738
MikamiUitOpen 6:38f7dce055d0 739 This function saturates a signed value.
MikamiUitOpen 6:38f7dce055d0 740
MikamiUitOpen 6:38f7dce055d0 741 \param [in] value Value to be saturated
MikamiUitOpen 6:38f7dce055d0 742 \param [in] sat Bit position to saturate to (1..32)
MikamiUitOpen 6:38f7dce055d0 743 \return Saturated value
MikamiUitOpen 6:38f7dce055d0 744 */
MikamiUitOpen 6:38f7dce055d0 745 #define __SSAT(ARG1,ARG2) \
MikamiUitOpen 6:38f7dce055d0 746 ({ \
MikamiUitOpen 6:38f7dce055d0 747 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 6:38f7dce055d0 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 6:38f7dce055d0 749 __RES; \
MikamiUitOpen 6:38f7dce055d0 750 })
MikamiUitOpen 6:38f7dce055d0 751
MikamiUitOpen 6:38f7dce055d0 752
MikamiUitOpen 6:38f7dce055d0 753 /** \brief Unsigned Saturate
MikamiUitOpen 6:38f7dce055d0 754
MikamiUitOpen 6:38f7dce055d0 755 This function saturates an unsigned value.
MikamiUitOpen 6:38f7dce055d0 756
MikamiUitOpen 6:38f7dce055d0 757 \param [in] value Value to be saturated
MikamiUitOpen 6:38f7dce055d0 758 \param [in] sat Bit position to saturate to (0..31)
MikamiUitOpen 6:38f7dce055d0 759 \return Saturated value
MikamiUitOpen 6:38f7dce055d0 760 */
MikamiUitOpen 6:38f7dce055d0 761 #define __USAT(ARG1,ARG2) \
MikamiUitOpen 6:38f7dce055d0 762 ({ \
MikamiUitOpen 6:38f7dce055d0 763 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 6:38f7dce055d0 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 6:38f7dce055d0 765 __RES; \
MikamiUitOpen 6:38f7dce055d0 766 })
MikamiUitOpen 6:38f7dce055d0 767
MikamiUitOpen 6:38f7dce055d0 768
MikamiUitOpen 6:38f7dce055d0 769 /** \brief Rotate Right with Extend (32 bit)
MikamiUitOpen 6:38f7dce055d0 770
MikamiUitOpen 6:38f7dce055d0 771 This function moves each bit of a bitstring right by one bit.
MikamiUitOpen 6:38f7dce055d0 772 The carry input is shifted in at the left end of the bitstring.
MikamiUitOpen 6:38f7dce055d0 773
MikamiUitOpen 6:38f7dce055d0 774 \param [in] value Value to rotate
MikamiUitOpen 6:38f7dce055d0 775 \return Rotated value
MikamiUitOpen 6:38f7dce055d0 776 */
MikamiUitOpen 6:38f7dce055d0 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 778 {
MikamiUitOpen 6:38f7dce055d0 779 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 780
MikamiUitOpen 6:38f7dce055d0 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 6:38f7dce055d0 782 return(result);
MikamiUitOpen 6:38f7dce055d0 783 }
MikamiUitOpen 6:38f7dce055d0 784
MikamiUitOpen 6:38f7dce055d0 785
MikamiUitOpen 6:38f7dce055d0 786 /** \brief LDRT Unprivileged (8 bit)
MikamiUitOpen 6:38f7dce055d0 787
MikamiUitOpen 6:38f7dce055d0 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
MikamiUitOpen 6:38f7dce055d0 789
MikamiUitOpen 6:38f7dce055d0 790 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 791 \return value of type uint8_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 792 */
MikamiUitOpen 6:38f7dce055d0 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
MikamiUitOpen 6:38f7dce055d0 794 {
MikamiUitOpen 6:38f7dce055d0 795 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 796
MikamiUitOpen 6:38f7dce055d0 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 6:38f7dce055d0 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 6:38f7dce055d0 799 #else
MikamiUitOpen 6:38f7dce055d0 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 6:38f7dce055d0 801 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 6:38f7dce055d0 802 */
MikamiUitOpen 6:38f7dce055d0 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 6:38f7dce055d0 804 #endif
MikamiUitOpen 6:38f7dce055d0 805 return ((uint8_t) result); /* Add explicit type cast here */
MikamiUitOpen 6:38f7dce055d0 806 }
MikamiUitOpen 6:38f7dce055d0 807
MikamiUitOpen 6:38f7dce055d0 808
MikamiUitOpen 6:38f7dce055d0 809 /** \brief LDRT Unprivileged (16 bit)
MikamiUitOpen 6:38f7dce055d0 810
MikamiUitOpen 6:38f7dce055d0 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 812
MikamiUitOpen 6:38f7dce055d0 813 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 814 \return value of type uint16_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 815 */
MikamiUitOpen 6:38f7dce055d0 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
MikamiUitOpen 6:38f7dce055d0 817 {
MikamiUitOpen 6:38f7dce055d0 818 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 819
MikamiUitOpen 6:38f7dce055d0 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 6:38f7dce055d0 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 6:38f7dce055d0 822 #else
MikamiUitOpen 6:38f7dce055d0 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 6:38f7dce055d0 824 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 6:38f7dce055d0 825 */
MikamiUitOpen 6:38f7dce055d0 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 6:38f7dce055d0 827 #endif
MikamiUitOpen 6:38f7dce055d0 828 return ((uint16_t) result); /* Add explicit type cast here */
MikamiUitOpen 6:38f7dce055d0 829 }
MikamiUitOpen 6:38f7dce055d0 830
MikamiUitOpen 6:38f7dce055d0 831
MikamiUitOpen 6:38f7dce055d0 832 /** \brief LDRT Unprivileged (32 bit)
MikamiUitOpen 6:38f7dce055d0 833
MikamiUitOpen 6:38f7dce055d0 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 835
MikamiUitOpen 6:38f7dce055d0 836 \param [in] ptr Pointer to data
MikamiUitOpen 6:38f7dce055d0 837 \return value of type uint32_t at (*ptr)
MikamiUitOpen 6:38f7dce055d0 838 */
MikamiUitOpen 6:38f7dce055d0 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
MikamiUitOpen 6:38f7dce055d0 840 {
MikamiUitOpen 6:38f7dce055d0 841 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 842
MikamiUitOpen 6:38f7dce055d0 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 6:38f7dce055d0 844 return(result);
MikamiUitOpen 6:38f7dce055d0 845 }
MikamiUitOpen 6:38f7dce055d0 846
MikamiUitOpen 6:38f7dce055d0 847
MikamiUitOpen 6:38f7dce055d0 848 /** \brief STRT Unprivileged (8 bit)
MikamiUitOpen 6:38f7dce055d0 849
MikamiUitOpen 6:38f7dce055d0 850 This function executes a Unprivileged STRT instruction for 8 bit values.
MikamiUitOpen 6:38f7dce055d0 851
MikamiUitOpen 6:38f7dce055d0 852 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 853 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 854 */
MikamiUitOpen 6:38f7dce055d0 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
MikamiUitOpen 6:38f7dce055d0 856 {
MikamiUitOpen 6:38f7dce055d0 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 6:38f7dce055d0 858 }
MikamiUitOpen 6:38f7dce055d0 859
MikamiUitOpen 6:38f7dce055d0 860
MikamiUitOpen 6:38f7dce055d0 861 /** \brief STRT Unprivileged (16 bit)
MikamiUitOpen 6:38f7dce055d0 862
MikamiUitOpen 6:38f7dce055d0 863 This function executes a Unprivileged STRT instruction for 16 bit values.
MikamiUitOpen 6:38f7dce055d0 864
MikamiUitOpen 6:38f7dce055d0 865 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 866 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 867 */
MikamiUitOpen 6:38f7dce055d0 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
MikamiUitOpen 6:38f7dce055d0 869 {
MikamiUitOpen 6:38f7dce055d0 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 6:38f7dce055d0 871 }
MikamiUitOpen 6:38f7dce055d0 872
MikamiUitOpen 6:38f7dce055d0 873
MikamiUitOpen 6:38f7dce055d0 874 /** \brief STRT Unprivileged (32 bit)
MikamiUitOpen 6:38f7dce055d0 875
MikamiUitOpen 6:38f7dce055d0 876 This function executes a Unprivileged STRT instruction for 32 bit values.
MikamiUitOpen 6:38f7dce055d0 877
MikamiUitOpen 6:38f7dce055d0 878 \param [in] value Value to store
MikamiUitOpen 6:38f7dce055d0 879 \param [in] ptr Pointer to location
MikamiUitOpen 6:38f7dce055d0 880 */
MikamiUitOpen 6:38f7dce055d0 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
MikamiUitOpen 6:38f7dce055d0 882 {
MikamiUitOpen 6:38f7dce055d0 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
MikamiUitOpen 6:38f7dce055d0 884 }
MikamiUitOpen 6:38f7dce055d0 885
MikamiUitOpen 6:38f7dce055d0 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 6:38f7dce055d0 887
MikamiUitOpen 6:38f7dce055d0 888
MikamiUitOpen 6:38f7dce055d0 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 6:38f7dce055d0 890 /* IAR iccarm specific functions */
MikamiUitOpen 6:38f7dce055d0 891 #include <cmsis_iar.h>
MikamiUitOpen 6:38f7dce055d0 892
MikamiUitOpen 6:38f7dce055d0 893
MikamiUitOpen 6:38f7dce055d0 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 6:38f7dce055d0 895 /* TI CCS specific functions */
MikamiUitOpen 6:38f7dce055d0 896 #include <cmsis_ccs.h>
MikamiUitOpen 6:38f7dce055d0 897
MikamiUitOpen 6:38f7dce055d0 898
MikamiUitOpen 6:38f7dce055d0 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 6:38f7dce055d0 900 /* TASKING carm specific functions */
MikamiUitOpen 6:38f7dce055d0 901 /*
MikamiUitOpen 6:38f7dce055d0 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
MikamiUitOpen 6:38f7dce055d0 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
MikamiUitOpen 6:38f7dce055d0 904 * Including the CMSIS ones.
MikamiUitOpen 6:38f7dce055d0 905 */
MikamiUitOpen 6:38f7dce055d0 906
MikamiUitOpen 6:38f7dce055d0 907
MikamiUitOpen 6:38f7dce055d0 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 6:38f7dce055d0 909 /* Cosmic specific functions */
MikamiUitOpen 6:38f7dce055d0 910 #include <cmsis_csm.h>
MikamiUitOpen 6:38f7dce055d0 911
MikamiUitOpen 6:38f7dce055d0 912 #endif
MikamiUitOpen 6:38f7dce055d0 913
MikamiUitOpen 6:38f7dce055d0 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
MikamiUitOpen 6:38f7dce055d0 915
MikamiUitOpen 6:38f7dce055d0 916 #endif /* __CORE_CMINSTR_H */