不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_cmFunc.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 * @file core_cmFunc.h
MikamiUitOpen 6:38f7dce055d0 3 * @brief CMSIS Cortex-M Core Function Access Header File
MikamiUitOpen 6:38f7dce055d0 4 * @version V4.10
MikamiUitOpen 6:38f7dce055d0 5 * @date 18. March 2015
MikamiUitOpen 6:38f7dce055d0 6 *
MikamiUitOpen 6:38f7dce055d0 7 * @note
MikamiUitOpen 6:38f7dce055d0 8 *
MikamiUitOpen 6:38f7dce055d0 9 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11
MikamiUitOpen 6:38f7dce055d0 12 All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 *
MikamiUitOpen 6:38f7dce055d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 #ifndef __CORE_CMFUNC_H
MikamiUitOpen 6:38f7dce055d0 39 #define __CORE_CMFUNC_H
MikamiUitOpen 6:38f7dce055d0 40
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 /* ########################### Core Function Access ########################### */
MikamiUitOpen 6:38f7dce055d0 43 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 6:38f7dce055d0 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MikamiUitOpen 6:38f7dce055d0 45 @{
MikamiUitOpen 6:38f7dce055d0 46 */
MikamiUitOpen 6:38f7dce055d0 47
MikamiUitOpen 6:38f7dce055d0 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 6:38f7dce055d0 49 /* ARM armcc specific functions */
MikamiUitOpen 6:38f7dce055d0 50
MikamiUitOpen 6:38f7dce055d0 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 6:38f7dce055d0 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 6:38f7dce055d0 53 #endif
MikamiUitOpen 6:38f7dce055d0 54
MikamiUitOpen 6:38f7dce055d0 55 /* intrinsic void __enable_irq(); */
MikamiUitOpen 6:38f7dce055d0 56 /* intrinsic void __disable_irq(); */
MikamiUitOpen 6:38f7dce055d0 57
MikamiUitOpen 6:38f7dce055d0 58 /** \brief Get Control Register
MikamiUitOpen 6:38f7dce055d0 59
MikamiUitOpen 6:38f7dce055d0 60 This function returns the content of the Control Register.
MikamiUitOpen 6:38f7dce055d0 61
MikamiUitOpen 6:38f7dce055d0 62 \return Control Register value
MikamiUitOpen 6:38f7dce055d0 63 */
MikamiUitOpen 6:38f7dce055d0 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 6:38f7dce055d0 65 {
MikamiUitOpen 6:38f7dce055d0 66 register uint32_t __regControl __ASM("control");
MikamiUitOpen 6:38f7dce055d0 67 return(__regControl);
MikamiUitOpen 6:38f7dce055d0 68 }
MikamiUitOpen 6:38f7dce055d0 69
MikamiUitOpen 6:38f7dce055d0 70
MikamiUitOpen 6:38f7dce055d0 71 /** \brief Set Control Register
MikamiUitOpen 6:38f7dce055d0 72
MikamiUitOpen 6:38f7dce055d0 73 This function writes the given value to the Control Register.
MikamiUitOpen 6:38f7dce055d0 74
MikamiUitOpen 6:38f7dce055d0 75 \param [in] control Control Register value to set
MikamiUitOpen 6:38f7dce055d0 76 */
MikamiUitOpen 6:38f7dce055d0 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 6:38f7dce055d0 78 {
MikamiUitOpen 6:38f7dce055d0 79 register uint32_t __regControl __ASM("control");
MikamiUitOpen 6:38f7dce055d0 80 __regControl = control;
MikamiUitOpen 6:38f7dce055d0 81 }
MikamiUitOpen 6:38f7dce055d0 82
MikamiUitOpen 6:38f7dce055d0 83
MikamiUitOpen 6:38f7dce055d0 84 /** \brief Get IPSR Register
MikamiUitOpen 6:38f7dce055d0 85
MikamiUitOpen 6:38f7dce055d0 86 This function returns the content of the IPSR Register.
MikamiUitOpen 6:38f7dce055d0 87
MikamiUitOpen 6:38f7dce055d0 88 \return IPSR Register value
MikamiUitOpen 6:38f7dce055d0 89 */
MikamiUitOpen 6:38f7dce055d0 90 __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 6:38f7dce055d0 91 {
MikamiUitOpen 6:38f7dce055d0 92 register uint32_t __regIPSR __ASM("ipsr");
MikamiUitOpen 6:38f7dce055d0 93 return(__regIPSR);
MikamiUitOpen 6:38f7dce055d0 94 }
MikamiUitOpen 6:38f7dce055d0 95
MikamiUitOpen 6:38f7dce055d0 96
MikamiUitOpen 6:38f7dce055d0 97 /** \brief Get APSR Register
MikamiUitOpen 6:38f7dce055d0 98
MikamiUitOpen 6:38f7dce055d0 99 This function returns the content of the APSR Register.
MikamiUitOpen 6:38f7dce055d0 100
MikamiUitOpen 6:38f7dce055d0 101 \return APSR Register value
MikamiUitOpen 6:38f7dce055d0 102 */
MikamiUitOpen 6:38f7dce055d0 103 __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 6:38f7dce055d0 104 {
MikamiUitOpen 6:38f7dce055d0 105 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 6:38f7dce055d0 106 return(__regAPSR);
MikamiUitOpen 6:38f7dce055d0 107 }
MikamiUitOpen 6:38f7dce055d0 108
MikamiUitOpen 6:38f7dce055d0 109
MikamiUitOpen 6:38f7dce055d0 110 /** \brief Get xPSR Register
MikamiUitOpen 6:38f7dce055d0 111
MikamiUitOpen 6:38f7dce055d0 112 This function returns the content of the xPSR Register.
MikamiUitOpen 6:38f7dce055d0 113
MikamiUitOpen 6:38f7dce055d0 114 \return xPSR Register value
MikamiUitOpen 6:38f7dce055d0 115 */
MikamiUitOpen 6:38f7dce055d0 116 __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 6:38f7dce055d0 117 {
MikamiUitOpen 6:38f7dce055d0 118 register uint32_t __regXPSR __ASM("xpsr");
MikamiUitOpen 6:38f7dce055d0 119 return(__regXPSR);
MikamiUitOpen 6:38f7dce055d0 120 }
MikamiUitOpen 6:38f7dce055d0 121
MikamiUitOpen 6:38f7dce055d0 122
MikamiUitOpen 6:38f7dce055d0 123 /** \brief Get Process Stack Pointer
MikamiUitOpen 6:38f7dce055d0 124
MikamiUitOpen 6:38f7dce055d0 125 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 6:38f7dce055d0 126
MikamiUitOpen 6:38f7dce055d0 127 \return PSP Register value
MikamiUitOpen 6:38f7dce055d0 128 */
MikamiUitOpen 6:38f7dce055d0 129 __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 6:38f7dce055d0 130 {
MikamiUitOpen 6:38f7dce055d0 131 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 6:38f7dce055d0 132 return(__regProcessStackPointer);
MikamiUitOpen 6:38f7dce055d0 133 }
MikamiUitOpen 6:38f7dce055d0 134
MikamiUitOpen 6:38f7dce055d0 135
MikamiUitOpen 6:38f7dce055d0 136 /** \brief Set Process Stack Pointer
MikamiUitOpen 6:38f7dce055d0 137
MikamiUitOpen 6:38f7dce055d0 138 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 6:38f7dce055d0 139
MikamiUitOpen 6:38f7dce055d0 140 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 6:38f7dce055d0 141 */
MikamiUitOpen 6:38f7dce055d0 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 6:38f7dce055d0 143 {
MikamiUitOpen 6:38f7dce055d0 144 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 6:38f7dce055d0 145 __regProcessStackPointer = topOfProcStack;
MikamiUitOpen 6:38f7dce055d0 146 }
MikamiUitOpen 6:38f7dce055d0 147
MikamiUitOpen 6:38f7dce055d0 148
MikamiUitOpen 6:38f7dce055d0 149 /** \brief Get Main Stack Pointer
MikamiUitOpen 6:38f7dce055d0 150
MikamiUitOpen 6:38f7dce055d0 151 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 6:38f7dce055d0 152
MikamiUitOpen 6:38f7dce055d0 153 \return MSP Register value
MikamiUitOpen 6:38f7dce055d0 154 */
MikamiUitOpen 6:38f7dce055d0 155 __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 6:38f7dce055d0 156 {
MikamiUitOpen 6:38f7dce055d0 157 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 6:38f7dce055d0 158 return(__regMainStackPointer);
MikamiUitOpen 6:38f7dce055d0 159 }
MikamiUitOpen 6:38f7dce055d0 160
MikamiUitOpen 6:38f7dce055d0 161
MikamiUitOpen 6:38f7dce055d0 162 /** \brief Set Main Stack Pointer
MikamiUitOpen 6:38f7dce055d0 163
MikamiUitOpen 6:38f7dce055d0 164 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 6:38f7dce055d0 165
MikamiUitOpen 6:38f7dce055d0 166 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 6:38f7dce055d0 167 */
MikamiUitOpen 6:38f7dce055d0 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 6:38f7dce055d0 169 {
MikamiUitOpen 6:38f7dce055d0 170 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 6:38f7dce055d0 171 __regMainStackPointer = topOfMainStack;
MikamiUitOpen 6:38f7dce055d0 172 }
MikamiUitOpen 6:38f7dce055d0 173
MikamiUitOpen 6:38f7dce055d0 174
MikamiUitOpen 6:38f7dce055d0 175 /** \brief Get Priority Mask
MikamiUitOpen 6:38f7dce055d0 176
MikamiUitOpen 6:38f7dce055d0 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 6:38f7dce055d0 178
MikamiUitOpen 6:38f7dce055d0 179 \return Priority Mask value
MikamiUitOpen 6:38f7dce055d0 180 */
MikamiUitOpen 6:38f7dce055d0 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 6:38f7dce055d0 182 {
MikamiUitOpen 6:38f7dce055d0 183 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 6:38f7dce055d0 184 return(__regPriMask);
MikamiUitOpen 6:38f7dce055d0 185 }
MikamiUitOpen 6:38f7dce055d0 186
MikamiUitOpen 6:38f7dce055d0 187
MikamiUitOpen 6:38f7dce055d0 188 /** \brief Set Priority Mask
MikamiUitOpen 6:38f7dce055d0 189
MikamiUitOpen 6:38f7dce055d0 190 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 6:38f7dce055d0 191
MikamiUitOpen 6:38f7dce055d0 192 \param [in] priMask Priority Mask
MikamiUitOpen 6:38f7dce055d0 193 */
MikamiUitOpen 6:38f7dce055d0 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 6:38f7dce055d0 195 {
MikamiUitOpen 6:38f7dce055d0 196 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 6:38f7dce055d0 197 __regPriMask = (priMask);
MikamiUitOpen 6:38f7dce055d0 198 }
MikamiUitOpen 6:38f7dce055d0 199
MikamiUitOpen 6:38f7dce055d0 200
MikamiUitOpen 6:38f7dce055d0 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 6:38f7dce055d0 202
MikamiUitOpen 6:38f7dce055d0 203 /** \brief Enable FIQ
MikamiUitOpen 6:38f7dce055d0 204
MikamiUitOpen 6:38f7dce055d0 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 6:38f7dce055d0 206 Can only be executed in Privileged modes.
MikamiUitOpen 6:38f7dce055d0 207 */
MikamiUitOpen 6:38f7dce055d0 208 #define __enable_fault_irq __enable_fiq
MikamiUitOpen 6:38f7dce055d0 209
MikamiUitOpen 6:38f7dce055d0 210
MikamiUitOpen 6:38f7dce055d0 211 /** \brief Disable FIQ
MikamiUitOpen 6:38f7dce055d0 212
MikamiUitOpen 6:38f7dce055d0 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 6:38f7dce055d0 214 Can only be executed in Privileged modes.
MikamiUitOpen 6:38f7dce055d0 215 */
MikamiUitOpen 6:38f7dce055d0 216 #define __disable_fault_irq __disable_fiq
MikamiUitOpen 6:38f7dce055d0 217
MikamiUitOpen 6:38f7dce055d0 218
MikamiUitOpen 6:38f7dce055d0 219 /** \brief Get Base Priority
MikamiUitOpen 6:38f7dce055d0 220
MikamiUitOpen 6:38f7dce055d0 221 This function returns the current value of the Base Priority register.
MikamiUitOpen 6:38f7dce055d0 222
MikamiUitOpen 6:38f7dce055d0 223 \return Base Priority register value
MikamiUitOpen 6:38f7dce055d0 224 */
MikamiUitOpen 6:38f7dce055d0 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 6:38f7dce055d0 226 {
MikamiUitOpen 6:38f7dce055d0 227 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 6:38f7dce055d0 228 return(__regBasePri);
MikamiUitOpen 6:38f7dce055d0 229 }
MikamiUitOpen 6:38f7dce055d0 230
MikamiUitOpen 6:38f7dce055d0 231
MikamiUitOpen 6:38f7dce055d0 232 /** \brief Set Base Priority
MikamiUitOpen 6:38f7dce055d0 233
MikamiUitOpen 6:38f7dce055d0 234 This function assigns the given value to the Base Priority register.
MikamiUitOpen 6:38f7dce055d0 235
MikamiUitOpen 6:38f7dce055d0 236 \param [in] basePri Base Priority value to set
MikamiUitOpen 6:38f7dce055d0 237 */
MikamiUitOpen 6:38f7dce055d0 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
MikamiUitOpen 6:38f7dce055d0 239 {
MikamiUitOpen 6:38f7dce055d0 240 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 6:38f7dce055d0 241 __regBasePri = (basePri & 0xff);
MikamiUitOpen 6:38f7dce055d0 242 }
MikamiUitOpen 6:38f7dce055d0 243
MikamiUitOpen 6:38f7dce055d0 244
MikamiUitOpen 6:38f7dce055d0 245 /** \brief Set Base Priority with condition
MikamiUitOpen 6:38f7dce055d0 246
MikamiUitOpen 6:38f7dce055d0 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 6:38f7dce055d0 248 or the new value increases the BASEPRI priority level.
MikamiUitOpen 6:38f7dce055d0 249
MikamiUitOpen 6:38f7dce055d0 250 \param [in] basePri Base Priority value to set
MikamiUitOpen 6:38f7dce055d0 251 */
MikamiUitOpen 6:38f7dce055d0 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
MikamiUitOpen 6:38f7dce055d0 253 {
MikamiUitOpen 6:38f7dce055d0 254 register uint32_t __regBasePriMax __ASM("basepri_max");
MikamiUitOpen 6:38f7dce055d0 255 __regBasePriMax = (basePri & 0xff);
MikamiUitOpen 6:38f7dce055d0 256 }
MikamiUitOpen 6:38f7dce055d0 257
MikamiUitOpen 6:38f7dce055d0 258
MikamiUitOpen 6:38f7dce055d0 259 /** \brief Get Fault Mask
MikamiUitOpen 6:38f7dce055d0 260
MikamiUitOpen 6:38f7dce055d0 261 This function returns the current value of the Fault Mask register.
MikamiUitOpen 6:38f7dce055d0 262
MikamiUitOpen 6:38f7dce055d0 263 \return Fault Mask register value
MikamiUitOpen 6:38f7dce055d0 264 */
MikamiUitOpen 6:38f7dce055d0 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 6:38f7dce055d0 266 {
MikamiUitOpen 6:38f7dce055d0 267 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 6:38f7dce055d0 268 return(__regFaultMask);
MikamiUitOpen 6:38f7dce055d0 269 }
MikamiUitOpen 6:38f7dce055d0 270
MikamiUitOpen 6:38f7dce055d0 271
MikamiUitOpen 6:38f7dce055d0 272 /** \brief Set Fault Mask
MikamiUitOpen 6:38f7dce055d0 273
MikamiUitOpen 6:38f7dce055d0 274 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 6:38f7dce055d0 275
MikamiUitOpen 6:38f7dce055d0 276 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 6:38f7dce055d0 277 */
MikamiUitOpen 6:38f7dce055d0 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 6:38f7dce055d0 279 {
MikamiUitOpen 6:38f7dce055d0 280 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 6:38f7dce055d0 281 __regFaultMask = (faultMask & (uint32_t)1);
MikamiUitOpen 6:38f7dce055d0 282 }
MikamiUitOpen 6:38f7dce055d0 283
MikamiUitOpen 6:38f7dce055d0 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 6:38f7dce055d0 285
MikamiUitOpen 6:38f7dce055d0 286
MikamiUitOpen 6:38f7dce055d0 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 6:38f7dce055d0 288
MikamiUitOpen 6:38f7dce055d0 289 /** \brief Get FPSCR
MikamiUitOpen 6:38f7dce055d0 290
MikamiUitOpen 6:38f7dce055d0 291 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 6:38f7dce055d0 292
MikamiUitOpen 6:38f7dce055d0 293 \return Floating Point Status/Control register value
MikamiUitOpen 6:38f7dce055d0 294 */
MikamiUitOpen 6:38f7dce055d0 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 6:38f7dce055d0 296 {
MikamiUitOpen 6:38f7dce055d0 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 6:38f7dce055d0 298 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 6:38f7dce055d0 299 return(__regfpscr);
MikamiUitOpen 6:38f7dce055d0 300 #else
MikamiUitOpen 6:38f7dce055d0 301 return(0);
MikamiUitOpen 6:38f7dce055d0 302 #endif
MikamiUitOpen 6:38f7dce055d0 303 }
MikamiUitOpen 6:38f7dce055d0 304
MikamiUitOpen 6:38f7dce055d0 305
MikamiUitOpen 6:38f7dce055d0 306 /** \brief Set FPSCR
MikamiUitOpen 6:38f7dce055d0 307
MikamiUitOpen 6:38f7dce055d0 308 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 6:38f7dce055d0 309
MikamiUitOpen 6:38f7dce055d0 310 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 6:38f7dce055d0 311 */
MikamiUitOpen 6:38f7dce055d0 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 6:38f7dce055d0 313 {
MikamiUitOpen 6:38f7dce055d0 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 6:38f7dce055d0 315 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 6:38f7dce055d0 316 __regfpscr = (fpscr);
MikamiUitOpen 6:38f7dce055d0 317 #endif
MikamiUitOpen 6:38f7dce055d0 318 }
MikamiUitOpen 6:38f7dce055d0 319
MikamiUitOpen 6:38f7dce055d0 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 6:38f7dce055d0 321
MikamiUitOpen 6:38f7dce055d0 322
MikamiUitOpen 6:38f7dce055d0 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 6:38f7dce055d0 324 /* GNU gcc specific functions */
MikamiUitOpen 6:38f7dce055d0 325
MikamiUitOpen 6:38f7dce055d0 326 /** \brief Enable IRQ Interrupts
MikamiUitOpen 6:38f7dce055d0 327
MikamiUitOpen 6:38f7dce055d0 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
MikamiUitOpen 6:38f7dce055d0 329 Can only be executed in Privileged modes.
MikamiUitOpen 6:38f7dce055d0 330 */
MikamiUitOpen 6:38f7dce055d0 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MikamiUitOpen 6:38f7dce055d0 332 {
MikamiUitOpen 6:38f7dce055d0 333 __ASM volatile ("cpsie i" : : : "memory");
MikamiUitOpen 6:38f7dce055d0 334 }
MikamiUitOpen 6:38f7dce055d0 335
MikamiUitOpen 6:38f7dce055d0 336
MikamiUitOpen 6:38f7dce055d0 337 /** \brief Disable IRQ Interrupts
MikamiUitOpen 6:38f7dce055d0 338
MikamiUitOpen 6:38f7dce055d0 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MikamiUitOpen 6:38f7dce055d0 340 Can only be executed in Privileged modes.
MikamiUitOpen 6:38f7dce055d0 341 */
MikamiUitOpen 6:38f7dce055d0 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
MikamiUitOpen 6:38f7dce055d0 343 {
MikamiUitOpen 6:38f7dce055d0 344 __ASM volatile ("cpsid i" : : : "memory");
MikamiUitOpen 6:38f7dce055d0 345 }
MikamiUitOpen 6:38f7dce055d0 346
MikamiUitOpen 6:38f7dce055d0 347
MikamiUitOpen 6:38f7dce055d0 348 /** \brief Get Control Register
MikamiUitOpen 6:38f7dce055d0 349
MikamiUitOpen 6:38f7dce055d0 350 This function returns the content of the Control Register.
MikamiUitOpen 6:38f7dce055d0 351
MikamiUitOpen 6:38f7dce055d0 352 \return Control Register value
MikamiUitOpen 6:38f7dce055d0 353 */
MikamiUitOpen 6:38f7dce055d0 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 6:38f7dce055d0 355 {
MikamiUitOpen 6:38f7dce055d0 356 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 357
MikamiUitOpen 6:38f7dce055d0 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 359 return(result);
MikamiUitOpen 6:38f7dce055d0 360 }
MikamiUitOpen 6:38f7dce055d0 361
MikamiUitOpen 6:38f7dce055d0 362
MikamiUitOpen 6:38f7dce055d0 363 /** \brief Set Control Register
MikamiUitOpen 6:38f7dce055d0 364
MikamiUitOpen 6:38f7dce055d0 365 This function writes the given value to the Control Register.
MikamiUitOpen 6:38f7dce055d0 366
MikamiUitOpen 6:38f7dce055d0 367 \param [in] control Control Register value to set
MikamiUitOpen 6:38f7dce055d0 368 */
MikamiUitOpen 6:38f7dce055d0 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 6:38f7dce055d0 370 {
MikamiUitOpen 6:38f7dce055d0 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
MikamiUitOpen 6:38f7dce055d0 372 }
MikamiUitOpen 6:38f7dce055d0 373
MikamiUitOpen 6:38f7dce055d0 374
MikamiUitOpen 6:38f7dce055d0 375 /** \brief Get IPSR Register
MikamiUitOpen 6:38f7dce055d0 376
MikamiUitOpen 6:38f7dce055d0 377 This function returns the content of the IPSR Register.
MikamiUitOpen 6:38f7dce055d0 378
MikamiUitOpen 6:38f7dce055d0 379 \return IPSR Register value
MikamiUitOpen 6:38f7dce055d0 380 */
MikamiUitOpen 6:38f7dce055d0 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 6:38f7dce055d0 382 {
MikamiUitOpen 6:38f7dce055d0 383 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 384
MikamiUitOpen 6:38f7dce055d0 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 386 return(result);
MikamiUitOpen 6:38f7dce055d0 387 }
MikamiUitOpen 6:38f7dce055d0 388
MikamiUitOpen 6:38f7dce055d0 389
MikamiUitOpen 6:38f7dce055d0 390 /** \brief Get APSR Register
MikamiUitOpen 6:38f7dce055d0 391
MikamiUitOpen 6:38f7dce055d0 392 This function returns the content of the APSR Register.
MikamiUitOpen 6:38f7dce055d0 393
MikamiUitOpen 6:38f7dce055d0 394 \return APSR Register value
MikamiUitOpen 6:38f7dce055d0 395 */
MikamiUitOpen 6:38f7dce055d0 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 6:38f7dce055d0 397 {
MikamiUitOpen 6:38f7dce055d0 398 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 399
MikamiUitOpen 6:38f7dce055d0 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 401 return(result);
MikamiUitOpen 6:38f7dce055d0 402 }
MikamiUitOpen 6:38f7dce055d0 403
MikamiUitOpen 6:38f7dce055d0 404
MikamiUitOpen 6:38f7dce055d0 405 /** \brief Get xPSR Register
MikamiUitOpen 6:38f7dce055d0 406
MikamiUitOpen 6:38f7dce055d0 407 This function returns the content of the xPSR Register.
MikamiUitOpen 6:38f7dce055d0 408
MikamiUitOpen 6:38f7dce055d0 409 \return xPSR Register value
MikamiUitOpen 6:38f7dce055d0 410 */
MikamiUitOpen 6:38f7dce055d0 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 6:38f7dce055d0 412 {
MikamiUitOpen 6:38f7dce055d0 413 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 414
MikamiUitOpen 6:38f7dce055d0 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 416 return(result);
MikamiUitOpen 6:38f7dce055d0 417 }
MikamiUitOpen 6:38f7dce055d0 418
MikamiUitOpen 6:38f7dce055d0 419
MikamiUitOpen 6:38f7dce055d0 420 /** \brief Get Process Stack Pointer
MikamiUitOpen 6:38f7dce055d0 421
MikamiUitOpen 6:38f7dce055d0 422 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 6:38f7dce055d0 423
MikamiUitOpen 6:38f7dce055d0 424 \return PSP Register value
MikamiUitOpen 6:38f7dce055d0 425 */
MikamiUitOpen 6:38f7dce055d0 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 6:38f7dce055d0 427 {
MikamiUitOpen 6:38f7dce055d0 428 register uint32_t result;
MikamiUitOpen 6:38f7dce055d0 429
MikamiUitOpen 6:38f7dce055d0 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 431 return(result);
MikamiUitOpen 6:38f7dce055d0 432 }
MikamiUitOpen 6:38f7dce055d0 433
MikamiUitOpen 6:38f7dce055d0 434
MikamiUitOpen 6:38f7dce055d0 435 /** \brief Set Process Stack Pointer
MikamiUitOpen 6:38f7dce055d0 436
MikamiUitOpen 6:38f7dce055d0 437 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 6:38f7dce055d0 438
MikamiUitOpen 6:38f7dce055d0 439 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 6:38f7dce055d0 440 */
MikamiUitOpen 6:38f7dce055d0 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 6:38f7dce055d0 442 {
MikamiUitOpen 6:38f7dce055d0 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
MikamiUitOpen 6:38f7dce055d0 444 }
MikamiUitOpen 6:38f7dce055d0 445
MikamiUitOpen 6:38f7dce055d0 446
MikamiUitOpen 6:38f7dce055d0 447 /** \brief Get Main Stack Pointer
MikamiUitOpen 6:38f7dce055d0 448
MikamiUitOpen 6:38f7dce055d0 449 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 6:38f7dce055d0 450
MikamiUitOpen 6:38f7dce055d0 451 \return MSP Register value
MikamiUitOpen 6:38f7dce055d0 452 */
MikamiUitOpen 6:38f7dce055d0 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 6:38f7dce055d0 454 {
MikamiUitOpen 6:38f7dce055d0 455 register uint32_t result;
MikamiUitOpen 6:38f7dce055d0 456
MikamiUitOpen 6:38f7dce055d0 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 458 return(result);
MikamiUitOpen 6:38f7dce055d0 459 }
MikamiUitOpen 6:38f7dce055d0 460
MikamiUitOpen 6:38f7dce055d0 461
MikamiUitOpen 6:38f7dce055d0 462 /** \brief Set Main Stack Pointer
MikamiUitOpen 6:38f7dce055d0 463
MikamiUitOpen 6:38f7dce055d0 464 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 6:38f7dce055d0 465
MikamiUitOpen 6:38f7dce055d0 466 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 6:38f7dce055d0 467 */
MikamiUitOpen 6:38f7dce055d0 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 6:38f7dce055d0 469 {
MikamiUitOpen 6:38f7dce055d0 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
MikamiUitOpen 6:38f7dce055d0 471 }
MikamiUitOpen 6:38f7dce055d0 472
MikamiUitOpen 6:38f7dce055d0 473
MikamiUitOpen 6:38f7dce055d0 474 /** \brief Get Priority Mask
MikamiUitOpen 6:38f7dce055d0 475
MikamiUitOpen 6:38f7dce055d0 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 6:38f7dce055d0 477
MikamiUitOpen 6:38f7dce055d0 478 \return Priority Mask value
MikamiUitOpen 6:38f7dce055d0 479 */
MikamiUitOpen 6:38f7dce055d0 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 6:38f7dce055d0 481 {
MikamiUitOpen 6:38f7dce055d0 482 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 483
MikamiUitOpen 6:38f7dce055d0 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 485 return(result);
MikamiUitOpen 6:38f7dce055d0 486 }
MikamiUitOpen 6:38f7dce055d0 487
MikamiUitOpen 6:38f7dce055d0 488
MikamiUitOpen 6:38f7dce055d0 489 /** \brief Set Priority Mask
MikamiUitOpen 6:38f7dce055d0 490
MikamiUitOpen 6:38f7dce055d0 491 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 6:38f7dce055d0 492
MikamiUitOpen 6:38f7dce055d0 493 \param [in] priMask Priority Mask
MikamiUitOpen 6:38f7dce055d0 494 */
MikamiUitOpen 6:38f7dce055d0 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 6:38f7dce055d0 496 {
MikamiUitOpen 6:38f7dce055d0 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
MikamiUitOpen 6:38f7dce055d0 498 }
MikamiUitOpen 6:38f7dce055d0 499
MikamiUitOpen 6:38f7dce055d0 500
MikamiUitOpen 6:38f7dce055d0 501 #if (__CORTEX_M >= 0x03)
MikamiUitOpen 6:38f7dce055d0 502
MikamiUitOpen 6:38f7dce055d0 503 /** \brief Enable FIQ
MikamiUitOpen 6:38f7dce055d0 504
MikamiUitOpen 6:38f7dce055d0 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 6:38f7dce055d0 506 Can only be executed in Privileged modes.
MikamiUitOpen 6:38f7dce055d0 507 */
MikamiUitOpen 6:38f7dce055d0 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
MikamiUitOpen 6:38f7dce055d0 509 {
MikamiUitOpen 6:38f7dce055d0 510 __ASM volatile ("cpsie f" : : : "memory");
MikamiUitOpen 6:38f7dce055d0 511 }
MikamiUitOpen 6:38f7dce055d0 512
MikamiUitOpen 6:38f7dce055d0 513
MikamiUitOpen 6:38f7dce055d0 514 /** \brief Disable FIQ
MikamiUitOpen 6:38f7dce055d0 515
MikamiUitOpen 6:38f7dce055d0 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 6:38f7dce055d0 517 Can only be executed in Privileged modes.
MikamiUitOpen 6:38f7dce055d0 518 */
MikamiUitOpen 6:38f7dce055d0 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
MikamiUitOpen 6:38f7dce055d0 520 {
MikamiUitOpen 6:38f7dce055d0 521 __ASM volatile ("cpsid f" : : : "memory");
MikamiUitOpen 6:38f7dce055d0 522 }
MikamiUitOpen 6:38f7dce055d0 523
MikamiUitOpen 6:38f7dce055d0 524
MikamiUitOpen 6:38f7dce055d0 525 /** \brief Get Base Priority
MikamiUitOpen 6:38f7dce055d0 526
MikamiUitOpen 6:38f7dce055d0 527 This function returns the current value of the Base Priority register.
MikamiUitOpen 6:38f7dce055d0 528
MikamiUitOpen 6:38f7dce055d0 529 \return Base Priority register value
MikamiUitOpen 6:38f7dce055d0 530 */
MikamiUitOpen 6:38f7dce055d0 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 6:38f7dce055d0 532 {
MikamiUitOpen 6:38f7dce055d0 533 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 534
MikamiUitOpen 6:38f7dce055d0 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 536 return(result);
MikamiUitOpen 6:38f7dce055d0 537 }
MikamiUitOpen 6:38f7dce055d0 538
MikamiUitOpen 6:38f7dce055d0 539
MikamiUitOpen 6:38f7dce055d0 540 /** \brief Set Base Priority
MikamiUitOpen 6:38f7dce055d0 541
MikamiUitOpen 6:38f7dce055d0 542 This function assigns the given value to the Base Priority register.
MikamiUitOpen 6:38f7dce055d0 543
MikamiUitOpen 6:38f7dce055d0 544 \param [in] basePri Base Priority value to set
MikamiUitOpen 6:38f7dce055d0 545 */
MikamiUitOpen 6:38f7dce055d0 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 547 {
MikamiUitOpen 6:38f7dce055d0 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
MikamiUitOpen 6:38f7dce055d0 549 }
MikamiUitOpen 6:38f7dce055d0 550
MikamiUitOpen 6:38f7dce055d0 551
MikamiUitOpen 6:38f7dce055d0 552 /** \brief Set Base Priority with condition
MikamiUitOpen 6:38f7dce055d0 553
MikamiUitOpen 6:38f7dce055d0 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 6:38f7dce055d0 555 or the new value increases the BASEPRI priority level.
MikamiUitOpen 6:38f7dce055d0 556
MikamiUitOpen 6:38f7dce055d0 557 \param [in] basePri Base Priority value to set
MikamiUitOpen 6:38f7dce055d0 558 */
MikamiUitOpen 6:38f7dce055d0 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
MikamiUitOpen 6:38f7dce055d0 560 {
MikamiUitOpen 6:38f7dce055d0 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
MikamiUitOpen 6:38f7dce055d0 562 }
MikamiUitOpen 6:38f7dce055d0 563
MikamiUitOpen 6:38f7dce055d0 564
MikamiUitOpen 6:38f7dce055d0 565 /** \brief Get Fault Mask
MikamiUitOpen 6:38f7dce055d0 566
MikamiUitOpen 6:38f7dce055d0 567 This function returns the current value of the Fault Mask register.
MikamiUitOpen 6:38f7dce055d0 568
MikamiUitOpen 6:38f7dce055d0 569 \return Fault Mask register value
MikamiUitOpen 6:38f7dce055d0 570 */
MikamiUitOpen 6:38f7dce055d0 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 6:38f7dce055d0 572 {
MikamiUitOpen 6:38f7dce055d0 573 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 574
MikamiUitOpen 6:38f7dce055d0 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 576 return(result);
MikamiUitOpen 6:38f7dce055d0 577 }
MikamiUitOpen 6:38f7dce055d0 578
MikamiUitOpen 6:38f7dce055d0 579
MikamiUitOpen 6:38f7dce055d0 580 /** \brief Set Fault Mask
MikamiUitOpen 6:38f7dce055d0 581
MikamiUitOpen 6:38f7dce055d0 582 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 6:38f7dce055d0 583
MikamiUitOpen 6:38f7dce055d0 584 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 6:38f7dce055d0 585 */
MikamiUitOpen 6:38f7dce055d0 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 6:38f7dce055d0 587 {
MikamiUitOpen 6:38f7dce055d0 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
MikamiUitOpen 6:38f7dce055d0 589 }
MikamiUitOpen 6:38f7dce055d0 590
MikamiUitOpen 6:38f7dce055d0 591 #endif /* (__CORTEX_M >= 0x03) */
MikamiUitOpen 6:38f7dce055d0 592
MikamiUitOpen 6:38f7dce055d0 593
MikamiUitOpen 6:38f7dce055d0 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 6:38f7dce055d0 595
MikamiUitOpen 6:38f7dce055d0 596 /** \brief Get FPSCR
MikamiUitOpen 6:38f7dce055d0 597
MikamiUitOpen 6:38f7dce055d0 598 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 6:38f7dce055d0 599
MikamiUitOpen 6:38f7dce055d0 600 \return Floating Point Status/Control register value
MikamiUitOpen 6:38f7dce055d0 601 */
MikamiUitOpen 6:38f7dce055d0 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 6:38f7dce055d0 603 {
MikamiUitOpen 6:38f7dce055d0 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 6:38f7dce055d0 605 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 606
MikamiUitOpen 6:38f7dce055d0 607 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 6:38f7dce055d0 608 __ASM volatile ("");
MikamiUitOpen 6:38f7dce055d0 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
MikamiUitOpen 6:38f7dce055d0 610 __ASM volatile ("");
MikamiUitOpen 6:38f7dce055d0 611 return(result);
MikamiUitOpen 6:38f7dce055d0 612 #else
MikamiUitOpen 6:38f7dce055d0 613 return(0);
MikamiUitOpen 6:38f7dce055d0 614 #endif
MikamiUitOpen 6:38f7dce055d0 615 }
MikamiUitOpen 6:38f7dce055d0 616
MikamiUitOpen 6:38f7dce055d0 617
MikamiUitOpen 6:38f7dce055d0 618 /** \brief Set FPSCR
MikamiUitOpen 6:38f7dce055d0 619
MikamiUitOpen 6:38f7dce055d0 620 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 6:38f7dce055d0 621
MikamiUitOpen 6:38f7dce055d0 622 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 6:38f7dce055d0 623 */
MikamiUitOpen 6:38f7dce055d0 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 6:38f7dce055d0 625 {
MikamiUitOpen 6:38f7dce055d0 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 6:38f7dce055d0 627 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 6:38f7dce055d0 628 __ASM volatile ("");
MikamiUitOpen 6:38f7dce055d0 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
MikamiUitOpen 6:38f7dce055d0 630 __ASM volatile ("");
MikamiUitOpen 6:38f7dce055d0 631 #endif
MikamiUitOpen 6:38f7dce055d0 632 }
MikamiUitOpen 6:38f7dce055d0 633
MikamiUitOpen 6:38f7dce055d0 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 6:38f7dce055d0 635
MikamiUitOpen 6:38f7dce055d0 636
MikamiUitOpen 6:38f7dce055d0 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 6:38f7dce055d0 638 /* IAR iccarm specific functions */
MikamiUitOpen 6:38f7dce055d0 639 #include <cmsis_iar.h>
MikamiUitOpen 6:38f7dce055d0 640
MikamiUitOpen 6:38f7dce055d0 641
MikamiUitOpen 6:38f7dce055d0 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 6:38f7dce055d0 643 /* TI CCS specific functions */
MikamiUitOpen 6:38f7dce055d0 644 #include <cmsis_ccs.h>
MikamiUitOpen 6:38f7dce055d0 645
MikamiUitOpen 6:38f7dce055d0 646
MikamiUitOpen 6:38f7dce055d0 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 6:38f7dce055d0 648 /* TASKING carm specific functions */
MikamiUitOpen 6:38f7dce055d0 649 /*
MikamiUitOpen 6:38f7dce055d0 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
MikamiUitOpen 6:38f7dce055d0 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
MikamiUitOpen 6:38f7dce055d0 652 * Including the CMSIS ones.
MikamiUitOpen 6:38f7dce055d0 653 */
MikamiUitOpen 6:38f7dce055d0 654
MikamiUitOpen 6:38f7dce055d0 655
MikamiUitOpen 6:38f7dce055d0 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 6:38f7dce055d0 657 /* Cosmic specific functions */
MikamiUitOpen 6:38f7dce055d0 658 #include <cmsis_csm.h>
MikamiUitOpen 6:38f7dce055d0 659
MikamiUitOpen 6:38f7dce055d0 660 #endif
MikamiUitOpen 6:38f7dce055d0 661
MikamiUitOpen 6:38f7dce055d0 662 /*@} end of CMSIS_Core_RegAccFunctions */
MikamiUitOpen 6:38f7dce055d0 663
MikamiUitOpen 6:38f7dce055d0 664 #endif /* __CORE_CMFUNC_H */