不韋 呂
Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．
Dependencies: F746_GUI F746_SAI_IO
mbed_src_STM32F7/targets/cmsis/core_caFunc.h@10:56f2f01df983, 2017-04-10 (annotated)
- Committer:
- MikamiUitOpen
- Date:
- Mon Apr 10 13:44:13 2017 +0000
- Revision:
- 10:56f2f01df983
- Parent:
- 6:38f7dce055d0
11
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| MikamiUitOpen | 6:38f7dce055d0 | 1 | /**************************************************************************//** |
| MikamiUitOpen | 6:38f7dce055d0 | 2 | * @file core_caFunc.h |
| MikamiUitOpen | 6:38f7dce055d0 | 3 | * @brief CMSIS Cortex-A Core Function Access Header File |
| MikamiUitOpen | 6:38f7dce055d0 | 4 | * @version V3.10 |
| MikamiUitOpen | 6:38f7dce055d0 | 5 | * @date 30 Oct 2013 |
| MikamiUitOpen | 6:38f7dce055d0 | 6 | * |
| MikamiUitOpen | 6:38f7dce055d0 | 7 | * @note |
| MikamiUitOpen | 6:38f7dce055d0 | 8 | * |
| MikamiUitOpen | 6:38f7dce055d0 | 9 | ******************************************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 10 | /* Copyright (c) 2009 - 2013 ARM LIMITED |
| MikamiUitOpen | 6:38f7dce055d0 | 11 | |
| MikamiUitOpen | 6:38f7dce055d0 | 12 | All rights reserved. |
| MikamiUitOpen | 6:38f7dce055d0 | 13 | Redistribution and use in source and binary forms, with or without |
| MikamiUitOpen | 6:38f7dce055d0 | 14 | modification, are permitted provided that the following conditions are met: |
| MikamiUitOpen | 6:38f7dce055d0 | 15 | - Redistributions of source code must retain the above copyright |
| MikamiUitOpen | 6:38f7dce055d0 | 16 | notice, this list of conditions and the following disclaimer. |
| MikamiUitOpen | 6:38f7dce055d0 | 17 | - Redistributions in binary form must reproduce the above copyright |
| MikamiUitOpen | 6:38f7dce055d0 | 18 | notice, this list of conditions and the following disclaimer in the |
| MikamiUitOpen | 6:38f7dce055d0 | 19 | documentation and/or other materials provided with the distribution. |
| MikamiUitOpen | 6:38f7dce055d0 | 20 | - Neither the name of ARM nor the names of its contributors may be used |
| MikamiUitOpen | 6:38f7dce055d0 | 21 | to endorse or promote products derived from this software without |
| MikamiUitOpen | 6:38f7dce055d0 | 22 | specific prior written permission. |
| MikamiUitOpen | 6:38f7dce055d0 | 23 | * |
| MikamiUitOpen | 6:38f7dce055d0 | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| MikamiUitOpen | 6:38f7dce055d0 | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| MikamiUitOpen | 6:38f7dce055d0 | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| MikamiUitOpen | 6:38f7dce055d0 | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
| MikamiUitOpen | 6:38f7dce055d0 | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| MikamiUitOpen | 6:38f7dce055d0 | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| MikamiUitOpen | 6:38f7dce055d0 | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| MikamiUitOpen | 6:38f7dce055d0 | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| MikamiUitOpen | 6:38f7dce055d0 | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| MikamiUitOpen | 6:38f7dce055d0 | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| MikamiUitOpen | 6:38f7dce055d0 | 34 | POSSIBILITY OF SUCH DAMAGE. |
| MikamiUitOpen | 6:38f7dce055d0 | 35 | ---------------------------------------------------------------------------*/ |
| MikamiUitOpen | 6:38f7dce055d0 | 36 | |
| MikamiUitOpen | 6:38f7dce055d0 | 37 | |
| MikamiUitOpen | 6:38f7dce055d0 | 38 | #ifndef __CORE_CAFUNC_H__ |
| MikamiUitOpen | 6:38f7dce055d0 | 39 | #define __CORE_CAFUNC_H__ |
| MikamiUitOpen | 6:38f7dce055d0 | 40 | |
| MikamiUitOpen | 6:38f7dce055d0 | 41 | |
| MikamiUitOpen | 6:38f7dce055d0 | 42 | /* ########################### Core Function Access ########################### */ |
| MikamiUitOpen | 6:38f7dce055d0 | 43 | /** \ingroup CMSIS_Core_FunctionInterface |
| MikamiUitOpen | 6:38f7dce055d0 | 44 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
| MikamiUitOpen | 6:38f7dce055d0 | 45 | @{ |
| MikamiUitOpen | 6:38f7dce055d0 | 46 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 47 | |
| MikamiUitOpen | 6:38f7dce055d0 | 48 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
| MikamiUitOpen | 6:38f7dce055d0 | 49 | /* ARM armcc specific functions */ |
| MikamiUitOpen | 6:38f7dce055d0 | 50 | |
| MikamiUitOpen | 6:38f7dce055d0 | 51 | #if (__ARMCC_VERSION < 400677) |
| MikamiUitOpen | 6:38f7dce055d0 | 52 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
| MikamiUitOpen | 6:38f7dce055d0 | 53 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 54 | |
| MikamiUitOpen | 6:38f7dce055d0 | 55 | #define MODE_USR 0x10 |
| MikamiUitOpen | 6:38f7dce055d0 | 56 | #define MODE_FIQ 0x11 |
| MikamiUitOpen | 6:38f7dce055d0 | 57 | #define MODE_IRQ 0x12 |
| MikamiUitOpen | 6:38f7dce055d0 | 58 | #define MODE_SVC 0x13 |
| MikamiUitOpen | 6:38f7dce055d0 | 59 | #define MODE_MON 0x16 |
| MikamiUitOpen | 6:38f7dce055d0 | 60 | #define MODE_ABT 0x17 |
| MikamiUitOpen | 6:38f7dce055d0 | 61 | #define MODE_HYP 0x1A |
| MikamiUitOpen | 6:38f7dce055d0 | 62 | #define MODE_UND 0x1B |
| MikamiUitOpen | 6:38f7dce055d0 | 63 | #define MODE_SYS 0x1F |
| MikamiUitOpen | 6:38f7dce055d0 | 64 | |
| MikamiUitOpen | 6:38f7dce055d0 | 65 | /** \brief Get APSR Register |
| MikamiUitOpen | 6:38f7dce055d0 | 66 | |
| MikamiUitOpen | 6:38f7dce055d0 | 67 | This function returns the content of the APSR Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 68 | |
| MikamiUitOpen | 6:38f7dce055d0 | 69 | \return APSR Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 70 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 71 | __STATIC_INLINE uint32_t __get_APSR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 72 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 73 | register uint32_t __regAPSR __ASM("apsr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 74 | return(__regAPSR); |
| MikamiUitOpen | 6:38f7dce055d0 | 75 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 76 | |
| MikamiUitOpen | 6:38f7dce055d0 | 77 | |
| MikamiUitOpen | 6:38f7dce055d0 | 78 | /** \brief Get CPSR Register |
| MikamiUitOpen | 6:38f7dce055d0 | 79 | |
| MikamiUitOpen | 6:38f7dce055d0 | 80 | This function returns the content of the CPSR Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 81 | |
| MikamiUitOpen | 6:38f7dce055d0 | 82 | \return CPSR Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 83 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 84 | __STATIC_INLINE uint32_t __get_CPSR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 85 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 86 | register uint32_t __regCPSR __ASM("cpsr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 87 | return(__regCPSR); |
| MikamiUitOpen | 6:38f7dce055d0 | 88 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 89 | |
| MikamiUitOpen | 6:38f7dce055d0 | 90 | /** \brief Set Stack Pointer |
| MikamiUitOpen | 6:38f7dce055d0 | 91 | |
| MikamiUitOpen | 6:38f7dce055d0 | 92 | This function assigns the given value to the current stack pointer. |
| MikamiUitOpen | 6:38f7dce055d0 | 93 | |
| MikamiUitOpen | 6:38f7dce055d0 | 94 | \param [in] topOfStack Stack Pointer value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 95 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 96 | register uint32_t __regSP __ASM("sp"); |
| MikamiUitOpen | 6:38f7dce055d0 | 97 | __STATIC_INLINE void __set_SP(uint32_t topOfStack) |
| MikamiUitOpen | 6:38f7dce055d0 | 98 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 99 | __regSP = topOfStack; |
| MikamiUitOpen | 6:38f7dce055d0 | 100 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 101 | |
| MikamiUitOpen | 6:38f7dce055d0 | 102 | |
| MikamiUitOpen | 6:38f7dce055d0 | 103 | /** \brief Get link register |
| MikamiUitOpen | 6:38f7dce055d0 | 104 | |
| MikamiUitOpen | 6:38f7dce055d0 | 105 | This function returns the value of the link register |
| MikamiUitOpen | 6:38f7dce055d0 | 106 | |
| MikamiUitOpen | 6:38f7dce055d0 | 107 | \return Value of link register |
| MikamiUitOpen | 6:38f7dce055d0 | 108 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 109 | register uint32_t __reglr __ASM("lr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 110 | __STATIC_INLINE uint32_t __get_LR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 111 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 112 | return(__reglr); |
| MikamiUitOpen | 6:38f7dce055d0 | 113 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 114 | |
| MikamiUitOpen | 6:38f7dce055d0 | 115 | /** \brief Set link register |
| MikamiUitOpen | 6:38f7dce055d0 | 116 | |
| MikamiUitOpen | 6:38f7dce055d0 | 117 | This function sets the value of the link register |
| MikamiUitOpen | 6:38f7dce055d0 | 118 | |
| MikamiUitOpen | 6:38f7dce055d0 | 119 | \param [in] lr LR value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 120 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 121 | __STATIC_INLINE void __set_LR(uint32_t lr) |
| MikamiUitOpen | 6:38f7dce055d0 | 122 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 123 | __reglr = lr; |
| MikamiUitOpen | 6:38f7dce055d0 | 124 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 125 | |
| MikamiUitOpen | 6:38f7dce055d0 | 126 | /** \brief Set Process Stack Pointer |
| MikamiUitOpen | 6:38f7dce055d0 | 127 | |
| MikamiUitOpen | 6:38f7dce055d0 | 128 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
| MikamiUitOpen | 6:38f7dce055d0 | 129 | |
| MikamiUitOpen | 6:38f7dce055d0 | 130 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 131 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 132 | __STATIC_ASM void __set_PSP(uint32_t topOfProcStack) |
| MikamiUitOpen | 6:38f7dce055d0 | 133 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 134 | ARM |
| MikamiUitOpen | 6:38f7dce055d0 | 135 | PRESERVE8 |
| MikamiUitOpen | 6:38f7dce055d0 | 136 | |
| MikamiUitOpen | 6:38f7dce055d0 | 137 | BIC R0, R0, #7 ;ensure stack is 8-byte aligned |
| MikamiUitOpen | 6:38f7dce055d0 | 138 | MRS R1, CPSR |
| MikamiUitOpen | 6:38f7dce055d0 | 139 | CPS #MODE_SYS ;no effect in USR mode |
| MikamiUitOpen | 6:38f7dce055d0 | 140 | MOV SP, R0 |
| MikamiUitOpen | 6:38f7dce055d0 | 141 | MSR CPSR_c, R1 ;no effect in USR mode |
| MikamiUitOpen | 6:38f7dce055d0 | 142 | ISB |
| MikamiUitOpen | 6:38f7dce055d0 | 143 | BX LR |
| MikamiUitOpen | 6:38f7dce055d0 | 144 | |
| MikamiUitOpen | 6:38f7dce055d0 | 145 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 146 | |
| MikamiUitOpen | 6:38f7dce055d0 | 147 | /** \brief Set User Mode |
| MikamiUitOpen | 6:38f7dce055d0 | 148 | |
| MikamiUitOpen | 6:38f7dce055d0 | 149 | This function changes the processor state to User Mode |
| MikamiUitOpen | 6:38f7dce055d0 | 150 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 151 | __STATIC_ASM void __set_CPS_USR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 152 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 153 | ARM |
| MikamiUitOpen | 6:38f7dce055d0 | 154 | |
| MikamiUitOpen | 6:38f7dce055d0 | 155 | CPS #MODE_USR |
| MikamiUitOpen | 6:38f7dce055d0 | 156 | BX LR |
| MikamiUitOpen | 6:38f7dce055d0 | 157 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 158 | |
| MikamiUitOpen | 6:38f7dce055d0 | 159 | |
| MikamiUitOpen | 6:38f7dce055d0 | 160 | /** \brief Enable FIQ |
| MikamiUitOpen | 6:38f7dce055d0 | 161 | |
| MikamiUitOpen | 6:38f7dce055d0 | 162 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
| MikamiUitOpen | 6:38f7dce055d0 | 163 | Can only be executed in Privileged modes. |
| MikamiUitOpen | 6:38f7dce055d0 | 164 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 165 | #define __enable_fault_irq __enable_fiq |
| MikamiUitOpen | 6:38f7dce055d0 | 166 | |
| MikamiUitOpen | 6:38f7dce055d0 | 167 | |
| MikamiUitOpen | 6:38f7dce055d0 | 168 | /** \brief Disable FIQ |
| MikamiUitOpen | 6:38f7dce055d0 | 169 | |
| MikamiUitOpen | 6:38f7dce055d0 | 170 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
| MikamiUitOpen | 6:38f7dce055d0 | 171 | Can only be executed in Privileged modes. |
| MikamiUitOpen | 6:38f7dce055d0 | 172 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 173 | #define __disable_fault_irq __disable_fiq |
| MikamiUitOpen | 6:38f7dce055d0 | 174 | |
| MikamiUitOpen | 6:38f7dce055d0 | 175 | |
| MikamiUitOpen | 6:38f7dce055d0 | 176 | /** \brief Get FPSCR |
| MikamiUitOpen | 6:38f7dce055d0 | 177 | |
| MikamiUitOpen | 6:38f7dce055d0 | 178 | This function returns the current value of the Floating Point Status/Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 179 | |
| MikamiUitOpen | 6:38f7dce055d0 | 180 | \return Floating Point Status/Control register value |
| MikamiUitOpen | 6:38f7dce055d0 | 181 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 182 | __STATIC_INLINE uint32_t __get_FPSCR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 183 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 184 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 185 | register uint32_t __regfpscr __ASM("fpscr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 186 | return(__regfpscr); |
| MikamiUitOpen | 6:38f7dce055d0 | 187 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 188 | return(0); |
| MikamiUitOpen | 6:38f7dce055d0 | 189 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 190 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 191 | |
| MikamiUitOpen | 6:38f7dce055d0 | 192 | |
| MikamiUitOpen | 6:38f7dce055d0 | 193 | /** \brief Set FPSCR |
| MikamiUitOpen | 6:38f7dce055d0 | 194 | |
| MikamiUitOpen | 6:38f7dce055d0 | 195 | This function assigns the given value to the Floating Point Status/Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 196 | |
| MikamiUitOpen | 6:38f7dce055d0 | 197 | \param [in] fpscr Floating Point Status/Control value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 198 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 199 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
| MikamiUitOpen | 6:38f7dce055d0 | 200 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 201 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 202 | register uint32_t __regfpscr __ASM("fpscr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 203 | __regfpscr = (fpscr); |
| MikamiUitOpen | 6:38f7dce055d0 | 204 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 205 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 206 | |
| MikamiUitOpen | 6:38f7dce055d0 | 207 | /** \brief Get FPEXC |
| MikamiUitOpen | 6:38f7dce055d0 | 208 | |
| MikamiUitOpen | 6:38f7dce055d0 | 209 | This function returns the current value of the Floating Point Exception Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 210 | |
| MikamiUitOpen | 6:38f7dce055d0 | 211 | \return Floating Point Exception Control register value |
| MikamiUitOpen | 6:38f7dce055d0 | 212 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 213 | __STATIC_INLINE uint32_t __get_FPEXC(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 214 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 215 | #if (__FPU_PRESENT == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 216 | register uint32_t __regfpexc __ASM("fpexc"); |
| MikamiUitOpen | 6:38f7dce055d0 | 217 | return(__regfpexc); |
| MikamiUitOpen | 6:38f7dce055d0 | 218 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 219 | return(0); |
| MikamiUitOpen | 6:38f7dce055d0 | 220 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 221 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 222 | |
| MikamiUitOpen | 6:38f7dce055d0 | 223 | |
| MikamiUitOpen | 6:38f7dce055d0 | 224 | /** \brief Set FPEXC |
| MikamiUitOpen | 6:38f7dce055d0 | 225 | |
| MikamiUitOpen | 6:38f7dce055d0 | 226 | This function assigns the given value to the Floating Point Exception Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 227 | |
| MikamiUitOpen | 6:38f7dce055d0 | 228 | \param [in] fpscr Floating Point Exception Control value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 229 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 230 | __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
| MikamiUitOpen | 6:38f7dce055d0 | 231 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 232 | #if (__FPU_PRESENT == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 233 | register uint32_t __regfpexc __ASM("fpexc"); |
| MikamiUitOpen | 6:38f7dce055d0 | 234 | __regfpexc = (fpexc); |
| MikamiUitOpen | 6:38f7dce055d0 | 235 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 236 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 237 | |
| MikamiUitOpen | 6:38f7dce055d0 | 238 | /** \brief Get CPACR |
| MikamiUitOpen | 6:38f7dce055d0 | 239 | |
| MikamiUitOpen | 6:38f7dce055d0 | 240 | This function returns the current value of the Coprocessor Access Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 241 | |
| MikamiUitOpen | 6:38f7dce055d0 | 242 | \return Coprocessor Access Control register value |
| MikamiUitOpen | 6:38f7dce055d0 | 243 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 244 | __STATIC_INLINE uint32_t __get_CPACR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 245 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 246 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
| MikamiUitOpen | 6:38f7dce055d0 | 247 | return __regCPACR; |
| MikamiUitOpen | 6:38f7dce055d0 | 248 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 249 | |
| MikamiUitOpen | 6:38f7dce055d0 | 250 | /** \brief Set CPACR |
| MikamiUitOpen | 6:38f7dce055d0 | 251 | |
| MikamiUitOpen | 6:38f7dce055d0 | 252 | This function assigns the given value to the Coprocessor Access Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 253 | |
| MikamiUitOpen | 6:38f7dce055d0 | 254 | \param [in] cpacr Coprocessor Acccess Control value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 255 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 256 | __STATIC_INLINE void __set_CPACR(uint32_t cpacr) |
| MikamiUitOpen | 6:38f7dce055d0 | 257 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 258 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
| MikamiUitOpen | 6:38f7dce055d0 | 259 | __regCPACR = cpacr; |
| MikamiUitOpen | 6:38f7dce055d0 | 260 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 261 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 262 | |
| MikamiUitOpen | 6:38f7dce055d0 | 263 | /** \brief Get CBAR |
| MikamiUitOpen | 6:38f7dce055d0 | 264 | |
| MikamiUitOpen | 6:38f7dce055d0 | 265 | This function returns the value of the Configuration Base Address register. |
| MikamiUitOpen | 6:38f7dce055d0 | 266 | |
| MikamiUitOpen | 6:38f7dce055d0 | 267 | \return Configuration Base Address register value |
| MikamiUitOpen | 6:38f7dce055d0 | 268 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 269 | __STATIC_INLINE uint32_t __get_CBAR() { |
| MikamiUitOpen | 6:38f7dce055d0 | 270 | register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 271 | return(__regCBAR); |
| MikamiUitOpen | 6:38f7dce055d0 | 272 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 273 | |
| MikamiUitOpen | 6:38f7dce055d0 | 274 | /** \brief Get TTBR0 |
| MikamiUitOpen | 6:38f7dce055d0 | 275 | |
| MikamiUitOpen | 6:38f7dce055d0 | 276 | This function returns the value of the Translation Table Base Register 0. |
| MikamiUitOpen | 6:38f7dce055d0 | 277 | |
| MikamiUitOpen | 6:38f7dce055d0 | 278 | \return Translation Table Base Register 0 value |
| MikamiUitOpen | 6:38f7dce055d0 | 279 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 280 | __STATIC_INLINE uint32_t __get_TTBR0() { |
| MikamiUitOpen | 6:38f7dce055d0 | 281 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 282 | return(__regTTBR0); |
| MikamiUitOpen | 6:38f7dce055d0 | 283 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 284 | |
| MikamiUitOpen | 6:38f7dce055d0 | 285 | /** \brief Set TTBR0 |
| MikamiUitOpen | 6:38f7dce055d0 | 286 | |
| MikamiUitOpen | 6:38f7dce055d0 | 287 | This function assigns the given value to the Translation Table Base Register 0. |
| MikamiUitOpen | 6:38f7dce055d0 | 288 | |
| MikamiUitOpen | 6:38f7dce055d0 | 289 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 290 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 291 | __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
| MikamiUitOpen | 6:38f7dce055d0 | 292 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 293 | __regTTBR0 = ttbr0; |
| MikamiUitOpen | 6:38f7dce055d0 | 294 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 295 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 296 | |
| MikamiUitOpen | 6:38f7dce055d0 | 297 | /** \brief Get DACR |
| MikamiUitOpen | 6:38f7dce055d0 | 298 | |
| MikamiUitOpen | 6:38f7dce055d0 | 299 | This function returns the value of the Domain Access Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 300 | |
| MikamiUitOpen | 6:38f7dce055d0 | 301 | \return Domain Access Control Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 302 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 303 | __STATIC_INLINE uint32_t __get_DACR() { |
| MikamiUitOpen | 6:38f7dce055d0 | 304 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 305 | return(__regDACR); |
| MikamiUitOpen | 6:38f7dce055d0 | 306 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 307 | |
| MikamiUitOpen | 6:38f7dce055d0 | 308 | /** \brief Set DACR |
| MikamiUitOpen | 6:38f7dce055d0 | 309 | |
| MikamiUitOpen | 6:38f7dce055d0 | 310 | This function assigns the given value to the Domain Access Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 311 | |
| MikamiUitOpen | 6:38f7dce055d0 | 312 | \param [in] dacr Domain Access Control Register value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 313 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 314 | __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
| MikamiUitOpen | 6:38f7dce055d0 | 315 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 316 | __regDACR = dacr; |
| MikamiUitOpen | 6:38f7dce055d0 | 317 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 318 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 319 | |
| MikamiUitOpen | 6:38f7dce055d0 | 320 | /******************************** Cache and BTAC enable ****************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 321 | |
| MikamiUitOpen | 6:38f7dce055d0 | 322 | /** \brief Set SCTLR |
| MikamiUitOpen | 6:38f7dce055d0 | 323 | |
| MikamiUitOpen | 6:38f7dce055d0 | 324 | This function assigns the given value to the System Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 325 | |
| MikamiUitOpen | 6:38f7dce055d0 | 326 | \param [in] sctlr System Control Register value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 327 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 328 | __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) |
| MikamiUitOpen | 6:38f7dce055d0 | 329 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 330 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 331 | __regSCTLR = sctlr; |
| MikamiUitOpen | 6:38f7dce055d0 | 332 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 333 | |
| MikamiUitOpen | 6:38f7dce055d0 | 334 | /** \brief Get SCTLR |
| MikamiUitOpen | 6:38f7dce055d0 | 335 | |
| MikamiUitOpen | 6:38f7dce055d0 | 336 | This function returns the value of the System Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 337 | |
| MikamiUitOpen | 6:38f7dce055d0 | 338 | \return System Control Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 339 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 340 | __STATIC_INLINE uint32_t __get_SCTLR() { |
| MikamiUitOpen | 6:38f7dce055d0 | 341 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 342 | return(__regSCTLR); |
| MikamiUitOpen | 6:38f7dce055d0 | 343 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 344 | |
| MikamiUitOpen | 6:38f7dce055d0 | 345 | /** \brief Enable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 346 | |
| MikamiUitOpen | 6:38f7dce055d0 | 347 | Enable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 348 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 349 | __STATIC_INLINE void __enable_caches(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 350 | // Set I bit 12 to enable I Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 351 | // Set C bit 2 to enable D Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 352 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
| MikamiUitOpen | 6:38f7dce055d0 | 353 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 354 | |
| MikamiUitOpen | 6:38f7dce055d0 | 355 | /** \brief Disable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 356 | |
| MikamiUitOpen | 6:38f7dce055d0 | 357 | Disable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 358 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 359 | __STATIC_INLINE void __disable_caches(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 360 | // Clear I bit 12 to disable I Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 361 | // Clear C bit 2 to disable D Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 362 | __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); |
| MikamiUitOpen | 6:38f7dce055d0 | 363 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 364 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 365 | |
| MikamiUitOpen | 6:38f7dce055d0 | 366 | /** \brief Enable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 367 | |
| MikamiUitOpen | 6:38f7dce055d0 | 368 | Enable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 369 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 370 | __STATIC_INLINE void __enable_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 371 | // Set Z bit 11 to enable branch prediction |
| MikamiUitOpen | 6:38f7dce055d0 | 372 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
| MikamiUitOpen | 6:38f7dce055d0 | 373 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 374 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 375 | |
| MikamiUitOpen | 6:38f7dce055d0 | 376 | /** \brief Disable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 377 | |
| MikamiUitOpen | 6:38f7dce055d0 | 378 | Disable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 379 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 380 | __STATIC_INLINE void __disable_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 381 | // Clear Z bit 11 to disable branch prediction |
| MikamiUitOpen | 6:38f7dce055d0 | 382 | __set_SCTLR( __get_SCTLR() & ~(1 << 11)); |
| MikamiUitOpen | 6:38f7dce055d0 | 383 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 384 | |
| MikamiUitOpen | 6:38f7dce055d0 | 385 | |
| MikamiUitOpen | 6:38f7dce055d0 | 386 | /** \brief Enable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 387 | |
| MikamiUitOpen | 6:38f7dce055d0 | 388 | Enable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 389 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 390 | __STATIC_INLINE void __enable_mmu(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 391 | // Set M bit 0 to enable the MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 392 | // Set AFE bit to enable simplified access permissions model |
| MikamiUitOpen | 6:38f7dce055d0 | 393 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
| MikamiUitOpen | 6:38f7dce055d0 | 394 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
| MikamiUitOpen | 6:38f7dce055d0 | 395 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 396 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 397 | |
| MikamiUitOpen | 6:38f7dce055d0 | 398 | /** \brief Disable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 399 | |
| MikamiUitOpen | 6:38f7dce055d0 | 400 | Disable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 401 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 402 | __STATIC_INLINE void __disable_mmu(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 403 | // Clear M bit 0 to disable the MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 404 | __set_SCTLR( __get_SCTLR() & ~1); |
| MikamiUitOpen | 6:38f7dce055d0 | 405 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 406 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 407 | |
| MikamiUitOpen | 6:38f7dce055d0 | 408 | /******************************** TLB maintenance operations ************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 409 | /** \brief Invalidate the whole tlb |
| MikamiUitOpen | 6:38f7dce055d0 | 410 | |
| MikamiUitOpen | 6:38f7dce055d0 | 411 | TLBIALL. Invalidate the whole tlb |
| MikamiUitOpen | 6:38f7dce055d0 | 412 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 413 | |
| MikamiUitOpen | 6:38f7dce055d0 | 414 | __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 415 | register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 416 | __TLBIALL = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 417 | __DSB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 418 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 419 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 420 | |
| MikamiUitOpen | 6:38f7dce055d0 | 421 | /******************************** BTB maintenance operations ************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 422 | /** \brief Invalidate entire branch predictor array |
| MikamiUitOpen | 6:38f7dce055d0 | 423 | |
| MikamiUitOpen | 6:38f7dce055d0 | 424 | BPIALL. Branch Predictor Invalidate All. |
| MikamiUitOpen | 6:38f7dce055d0 | 425 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 426 | |
| MikamiUitOpen | 6:38f7dce055d0 | 427 | __STATIC_INLINE void __v7_inv_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 428 | register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); |
| MikamiUitOpen | 6:38f7dce055d0 | 429 | __BPIALL = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 430 | __DSB(); //ensure completion of the invalidation |
| MikamiUitOpen | 6:38f7dce055d0 | 431 | __ISB(); //ensure instruction fetch path sees new state |
| MikamiUitOpen | 6:38f7dce055d0 | 432 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 433 | |
| MikamiUitOpen | 6:38f7dce055d0 | 434 | |
| MikamiUitOpen | 6:38f7dce055d0 | 435 | /******************************** L1 cache operations ******************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 436 | |
| MikamiUitOpen | 6:38f7dce055d0 | 437 | /** \brief Invalidate the whole I$ |
| MikamiUitOpen | 6:38f7dce055d0 | 438 | |
| MikamiUitOpen | 6:38f7dce055d0 | 439 | ICIALLU. Instruction Cache Invalidate All to PoU |
| MikamiUitOpen | 6:38f7dce055d0 | 440 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 441 | __STATIC_INLINE void __v7_inv_icache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 442 | register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 443 | __ICIALLU = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 444 | __DSB(); //ensure completion of the invalidation |
| MikamiUitOpen | 6:38f7dce055d0 | 445 | __ISB(); //ensure instruction fetch path sees new I cache state |
| MikamiUitOpen | 6:38f7dce055d0 | 446 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 447 | |
| MikamiUitOpen | 6:38f7dce055d0 | 448 | /** \brief Clean D$ by MVA |
| MikamiUitOpen | 6:38f7dce055d0 | 449 | |
| MikamiUitOpen | 6:38f7dce055d0 | 450 | DCCMVAC. Data cache clean by MVA to PoC |
| MikamiUitOpen | 6:38f7dce055d0 | 451 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 452 | __STATIC_INLINE void __v7_clean_dcache_mva(void *va) { |
| MikamiUitOpen | 6:38f7dce055d0 | 453 | register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); |
| MikamiUitOpen | 6:38f7dce055d0 | 454 | __DCCMVAC = (uint32_t)va; |
| MikamiUitOpen | 6:38f7dce055d0 | 455 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
| MikamiUitOpen | 6:38f7dce055d0 | 456 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 457 | |
| MikamiUitOpen | 6:38f7dce055d0 | 458 | /** \brief Invalidate D$ by MVA |
| MikamiUitOpen | 6:38f7dce055d0 | 459 | |
| MikamiUitOpen | 6:38f7dce055d0 | 460 | DCIMVAC. Data cache invalidate by MVA to PoC |
| MikamiUitOpen | 6:38f7dce055d0 | 461 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 462 | __STATIC_INLINE void __v7_inv_dcache_mva(void *va) { |
| MikamiUitOpen | 6:38f7dce055d0 | 463 | register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); |
| MikamiUitOpen | 6:38f7dce055d0 | 464 | __DCIMVAC = (uint32_t)va; |
| MikamiUitOpen | 6:38f7dce055d0 | 465 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
| MikamiUitOpen | 6:38f7dce055d0 | 466 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 467 | |
| MikamiUitOpen | 6:38f7dce055d0 | 468 | /** \brief Clean and Invalidate D$ by MVA |
| MikamiUitOpen | 6:38f7dce055d0 | 469 | |
| MikamiUitOpen | 6:38f7dce055d0 | 470 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
| MikamiUitOpen | 6:38f7dce055d0 | 471 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 472 | __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { |
| MikamiUitOpen | 6:38f7dce055d0 | 473 | register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); |
| MikamiUitOpen | 6:38f7dce055d0 | 474 | __DCCIMVAC = (uint32_t)va; |
| MikamiUitOpen | 6:38f7dce055d0 | 475 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
| MikamiUitOpen | 6:38f7dce055d0 | 476 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 477 | |
| MikamiUitOpen | 6:38f7dce055d0 | 478 | /** \brief Clean and Invalidate the entire data or unified cache |
| MikamiUitOpen | 6:38f7dce055d0 | 479 | |
| MikamiUitOpen | 6:38f7dce055d0 | 480 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. |
| MikamiUitOpen | 6:38f7dce055d0 | 481 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 482 | #pragma push |
| MikamiUitOpen | 6:38f7dce055d0 | 483 | #pragma arm |
| MikamiUitOpen | 6:38f7dce055d0 | 484 | __STATIC_ASM void __v7_all_cache(uint32_t op) { |
| MikamiUitOpen | 6:38f7dce055d0 | 485 | ARM |
| MikamiUitOpen | 6:38f7dce055d0 | 486 | |
| MikamiUitOpen | 6:38f7dce055d0 | 487 | PUSH {R4-R11} |
| MikamiUitOpen | 6:38f7dce055d0 | 488 | |
| MikamiUitOpen | 6:38f7dce055d0 | 489 | MRC p15, 1, R6, c0, c0, 1 // Read CLIDR |
| MikamiUitOpen | 6:38f7dce055d0 | 490 | ANDS R3, R6, #0x07000000 // Extract coherency level |
| MikamiUitOpen | 6:38f7dce055d0 | 491 | MOV R3, R3, LSR #23 // Total cache levels << 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 492 | BEQ Finished // If 0, no need to clean |
| MikamiUitOpen | 6:38f7dce055d0 | 493 | |
| MikamiUitOpen | 6:38f7dce055d0 | 494 | MOV R10, #0 // R10 holds current cache level << 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 495 | Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position |
| MikamiUitOpen | 6:38f7dce055d0 | 496 | MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level |
| MikamiUitOpen | 6:38f7dce055d0 | 497 | AND R1, R1, #7 // Isolate those lower 3 bits |
| MikamiUitOpen | 6:38f7dce055d0 | 498 | CMP R1, #2 |
| MikamiUitOpen | 6:38f7dce055d0 | 499 | BLT Skip // No cache or only instruction cache at this level |
| MikamiUitOpen | 6:38f7dce055d0 | 500 | |
| MikamiUitOpen | 6:38f7dce055d0 | 501 | MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register |
| MikamiUitOpen | 6:38f7dce055d0 | 502 | ISB // ISB to sync the change to the CacheSizeID reg |
| MikamiUitOpen | 6:38f7dce055d0 | 503 | MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register |
| MikamiUitOpen | 6:38f7dce055d0 | 504 | AND R2, R1, #7 // Extract the line length field |
| MikamiUitOpen | 6:38f7dce055d0 | 505 | ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) |
| MikamiUitOpen | 6:38f7dce055d0 | 506 | LDR R4, =0x3FF |
| MikamiUitOpen | 6:38f7dce055d0 | 507 | ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) |
| MikamiUitOpen | 6:38f7dce055d0 | 508 | CLZ R5, R4 // R5 is the bit position of the way size increment |
| MikamiUitOpen | 6:38f7dce055d0 | 509 | LDR R7, =0x7FFF |
| MikamiUitOpen | 6:38f7dce055d0 | 510 | ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) |
| MikamiUitOpen | 6:38f7dce055d0 | 511 | |
| MikamiUitOpen | 6:38f7dce055d0 | 512 | Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned) |
| MikamiUitOpen | 6:38f7dce055d0 | 513 | |
| MikamiUitOpen | 6:38f7dce055d0 | 514 | Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 |
| MikamiUitOpen | 6:38f7dce055d0 | 515 | ORR R11, R11, R7, LSL R2 // Factor in the Set number |
| MikamiUitOpen | 6:38f7dce055d0 | 516 | CMP R0, #0 |
| MikamiUitOpen | 6:38f7dce055d0 | 517 | BNE Dccsw |
| MikamiUitOpen | 6:38f7dce055d0 | 518 | MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 519 | B cont |
| MikamiUitOpen | 6:38f7dce055d0 | 520 | Dccsw CMP R0, #1 |
| MikamiUitOpen | 6:38f7dce055d0 | 521 | BNE Dccisw |
| MikamiUitOpen | 6:38f7dce055d0 | 522 | MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 523 | B cont |
| MikamiUitOpen | 6:38f7dce055d0 | 524 | Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 525 | cont SUBS R9, R9, #1 // Decrement the Way number |
| MikamiUitOpen | 6:38f7dce055d0 | 526 | BGE Loop3 |
| MikamiUitOpen | 6:38f7dce055d0 | 527 | SUBS R7, R7, #1 // Decrement the Set number |
| MikamiUitOpen | 6:38f7dce055d0 | 528 | BGE Loop2 |
| MikamiUitOpen | 6:38f7dce055d0 | 529 | Skip ADD R10, R10, #2 // Increment the cache number |
| MikamiUitOpen | 6:38f7dce055d0 | 530 | CMP R3, R10 |
| MikamiUitOpen | 6:38f7dce055d0 | 531 | BGT Loop1 |
| MikamiUitOpen | 6:38f7dce055d0 | 532 | |
| MikamiUitOpen | 6:38f7dce055d0 | 533 | Finished |
| MikamiUitOpen | 6:38f7dce055d0 | 534 | DSB |
| MikamiUitOpen | 6:38f7dce055d0 | 535 | POP {R4-R11} |
| MikamiUitOpen | 6:38f7dce055d0 | 536 | BX lr |
| MikamiUitOpen | 6:38f7dce055d0 | 537 | |
| MikamiUitOpen | 6:38f7dce055d0 | 538 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 539 | #pragma pop |
| MikamiUitOpen | 6:38f7dce055d0 | 540 | |
| MikamiUitOpen | 6:38f7dce055d0 | 541 | |
| MikamiUitOpen | 6:38f7dce055d0 | 542 | /** \brief Invalidate the whole D$ |
| MikamiUitOpen | 6:38f7dce055d0 | 543 | |
| MikamiUitOpen | 6:38f7dce055d0 | 544 | DCISW. Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 545 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 546 | |
| MikamiUitOpen | 6:38f7dce055d0 | 547 | __STATIC_INLINE void __v7_inv_dcache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 548 | __v7_all_cache(0); |
| MikamiUitOpen | 6:38f7dce055d0 | 549 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 550 | |
| MikamiUitOpen | 6:38f7dce055d0 | 551 | /** \brief Clean the whole D$ |
| MikamiUitOpen | 6:38f7dce055d0 | 552 | |
| MikamiUitOpen | 6:38f7dce055d0 | 553 | DCCSW. Clean by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 554 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 555 | |
| MikamiUitOpen | 6:38f7dce055d0 | 556 | __STATIC_INLINE void __v7_clean_dcache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 557 | __v7_all_cache(1); |
| MikamiUitOpen | 6:38f7dce055d0 | 558 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 559 | |
| MikamiUitOpen | 6:38f7dce055d0 | 560 | /** \brief Clean and invalidate the whole D$ |
| MikamiUitOpen | 6:38f7dce055d0 | 561 | |
| MikamiUitOpen | 6:38f7dce055d0 | 562 | DCCISW. Clean and Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 563 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 564 | |
| MikamiUitOpen | 6:38f7dce055d0 | 565 | __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 566 | __v7_all_cache(2); |
| MikamiUitOpen | 6:38f7dce055d0 | 567 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 568 | |
| MikamiUitOpen | 6:38f7dce055d0 | 569 | #include "core_ca_mmu.h" |
| MikamiUitOpen | 6:38f7dce055d0 | 570 | |
| MikamiUitOpen | 6:38f7dce055d0 | 571 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ |
| MikamiUitOpen | 6:38f7dce055d0 | 572 | |
| MikamiUitOpen | 6:38f7dce055d0 | 573 | #define __inline inline |
| MikamiUitOpen | 6:38f7dce055d0 | 574 | |
| MikamiUitOpen | 6:38f7dce055d0 | 575 | inline static uint32_t __disable_irq_iar() { |
| MikamiUitOpen | 6:38f7dce055d0 | 576 | int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I |
| MikamiUitOpen | 6:38f7dce055d0 | 577 | __disable_irq(); |
| MikamiUitOpen | 6:38f7dce055d0 | 578 | return irq_dis; |
| MikamiUitOpen | 6:38f7dce055d0 | 579 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 580 | |
| MikamiUitOpen | 6:38f7dce055d0 | 581 | #define MODE_USR 0x10 |
| MikamiUitOpen | 6:38f7dce055d0 | 582 | #define MODE_FIQ 0x11 |
| MikamiUitOpen | 6:38f7dce055d0 | 583 | #define MODE_IRQ 0x12 |
| MikamiUitOpen | 6:38f7dce055d0 | 584 | #define MODE_SVC 0x13 |
| MikamiUitOpen | 6:38f7dce055d0 | 585 | #define MODE_MON 0x16 |
| MikamiUitOpen | 6:38f7dce055d0 | 586 | #define MODE_ABT 0x17 |
| MikamiUitOpen | 6:38f7dce055d0 | 587 | #define MODE_HYP 0x1A |
| MikamiUitOpen | 6:38f7dce055d0 | 588 | #define MODE_UND 0x1B |
| MikamiUitOpen | 6:38f7dce055d0 | 589 | #define MODE_SYS 0x1F |
| MikamiUitOpen | 6:38f7dce055d0 | 590 | |
| MikamiUitOpen | 6:38f7dce055d0 | 591 | /** \brief Set Process Stack Pointer |
| MikamiUitOpen | 6:38f7dce055d0 | 592 | |
| MikamiUitOpen | 6:38f7dce055d0 | 593 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
| MikamiUitOpen | 6:38f7dce055d0 | 594 | |
| MikamiUitOpen | 6:38f7dce055d0 | 595 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 596 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 597 | // from rt_CMSIS.c |
| MikamiUitOpen | 6:38f7dce055d0 | 598 | __arm static inline void __set_PSP(uint32_t topOfProcStack) { |
| MikamiUitOpen | 6:38f7dce055d0 | 599 | __asm( |
| MikamiUitOpen | 6:38f7dce055d0 | 600 | " ARM\n" |
| MikamiUitOpen | 6:38f7dce055d0 | 601 | // " PRESERVE8\n" |
| MikamiUitOpen | 6:38f7dce055d0 | 602 | |
| MikamiUitOpen | 6:38f7dce055d0 | 603 | " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 604 | " MRS R1, CPSR \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 605 | " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS |
| MikamiUitOpen | 6:38f7dce055d0 | 606 | " MOV SP, R0 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 607 | " MSR CPSR_c, R1 ;no effect in USR mode \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 608 | " ISB \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 609 | " BX LR \n"); |
| MikamiUitOpen | 6:38f7dce055d0 | 610 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 611 | |
| MikamiUitOpen | 6:38f7dce055d0 | 612 | /** \brief Set User Mode |
| MikamiUitOpen | 6:38f7dce055d0 | 613 | |
| MikamiUitOpen | 6:38f7dce055d0 | 614 | This function changes the processor state to User Mode |
| MikamiUitOpen | 6:38f7dce055d0 | 615 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 616 | // from rt_CMSIS.c |
| MikamiUitOpen | 6:38f7dce055d0 | 617 | __arm static inline void __set_CPS_USR(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 618 | __asm( |
| MikamiUitOpen | 6:38f7dce055d0 | 619 | " ARM \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 620 | |
| MikamiUitOpen | 6:38f7dce055d0 | 621 | " CPS #0x10 \n" // MODE_USR |
| MikamiUitOpen | 6:38f7dce055d0 | 622 | " BX LR\n"); |
| MikamiUitOpen | 6:38f7dce055d0 | 623 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 624 | |
| MikamiUitOpen | 6:38f7dce055d0 | 625 | /** \brief Set TTBR0 |
| MikamiUitOpen | 6:38f7dce055d0 | 626 | |
| MikamiUitOpen | 6:38f7dce055d0 | 627 | This function assigns the given value to the Translation Table Base Register 0. |
| MikamiUitOpen | 6:38f7dce055d0 | 628 | |
| MikamiUitOpen | 6:38f7dce055d0 | 629 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 630 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 631 | // from mmu_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 632 | __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
| MikamiUitOpen | 6:38f7dce055d0 | 633 | __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 634 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 635 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 636 | |
| MikamiUitOpen | 6:38f7dce055d0 | 637 | /** \brief Set DACR |
| MikamiUitOpen | 6:38f7dce055d0 | 638 | |
| MikamiUitOpen | 6:38f7dce055d0 | 639 | This function assigns the given value to the Domain Access Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 640 | |
| MikamiUitOpen | 6:38f7dce055d0 | 641 | \param [in] dacr Domain Access Control Register value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 642 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 643 | // from mmu_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 644 | __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
| MikamiUitOpen | 6:38f7dce055d0 | 645 | __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 646 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 647 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 648 | |
| MikamiUitOpen | 6:38f7dce055d0 | 649 | |
| MikamiUitOpen | 6:38f7dce055d0 | 650 | /******************************** Cache and BTAC enable ****************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 651 | /** \brief Set SCTLR |
| MikamiUitOpen | 6:38f7dce055d0 | 652 | |
| MikamiUitOpen | 6:38f7dce055d0 | 653 | This function assigns the given value to the System Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 654 | |
| MikamiUitOpen | 6:38f7dce055d0 | 655 | \param [in] sctlr System Control Register value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 656 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 657 | // from __enable_mmu() |
| MikamiUitOpen | 6:38f7dce055d0 | 658 | __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) { |
| MikamiUitOpen | 6:38f7dce055d0 | 659 | __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 660 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 661 | |
| MikamiUitOpen | 6:38f7dce055d0 | 662 | /** \brief Get SCTLR |
| MikamiUitOpen | 6:38f7dce055d0 | 663 | |
| MikamiUitOpen | 6:38f7dce055d0 | 664 | This function returns the value of the System Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 665 | |
| MikamiUitOpen | 6:38f7dce055d0 | 666 | \return System Control Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 667 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 668 | // from __enable_mmu() |
| MikamiUitOpen | 6:38f7dce055d0 | 669 | __STATIC_INLINE uint32_t __get_SCTLR() { |
| MikamiUitOpen | 6:38f7dce055d0 | 670 | uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0); |
| MikamiUitOpen | 6:38f7dce055d0 | 671 | return __regSCTLR; |
| MikamiUitOpen | 6:38f7dce055d0 | 672 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 673 | |
| MikamiUitOpen | 6:38f7dce055d0 | 674 | /** \brief Enable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 675 | |
| MikamiUitOpen | 6:38f7dce055d0 | 676 | Enable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 677 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 678 | // from system_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 679 | __STATIC_INLINE void __enable_caches(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 680 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
| MikamiUitOpen | 6:38f7dce055d0 | 681 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 682 | |
| MikamiUitOpen | 6:38f7dce055d0 | 683 | /** \brief Enable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 684 | |
| MikamiUitOpen | 6:38f7dce055d0 | 685 | Enable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 686 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 687 | // from system_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 688 | __STATIC_INLINE void __enable_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 689 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
| MikamiUitOpen | 6:38f7dce055d0 | 690 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 691 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 692 | |
| MikamiUitOpen | 6:38f7dce055d0 | 693 | /** \brief Enable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 694 | |
| MikamiUitOpen | 6:38f7dce055d0 | 695 | Enable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 696 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 697 | // from system_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 698 | __STATIC_INLINE void __enable_mmu(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 699 | // Set M bit 0 to enable the MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 700 | // Set AFE bit to enable simplified access permissions model |
| MikamiUitOpen | 6:38f7dce055d0 | 701 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
| MikamiUitOpen | 6:38f7dce055d0 | 702 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
| MikamiUitOpen | 6:38f7dce055d0 | 703 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 704 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 705 | |
| MikamiUitOpen | 6:38f7dce055d0 | 706 | /******************************** TLB maintenance operations ************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 707 | /** \brief Invalidate the whole tlb |
| MikamiUitOpen | 6:38f7dce055d0 | 708 | |
| MikamiUitOpen | 6:38f7dce055d0 | 709 | TLBIALL. Invalidate the whole tlb |
| MikamiUitOpen | 6:38f7dce055d0 | 710 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 711 | // from system_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 712 | __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 713 | uint32_t val = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 714 | __MCR(15, 0, val, 8, 7, 0); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 715 | __MCR(15, 0, val, 8, 6, 0); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 716 | __MCR(15, 0, val, 8, 5, 0); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 717 | __DSB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 718 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 719 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 720 | |
| MikamiUitOpen | 6:38f7dce055d0 | 721 | /******************************** BTB maintenance operations ************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 722 | /** \brief Invalidate entire branch predictor array |
| MikamiUitOpen | 6:38f7dce055d0 | 723 | |
| MikamiUitOpen | 6:38f7dce055d0 | 724 | BPIALL. Branch Predictor Invalidate All. |
| MikamiUitOpen | 6:38f7dce055d0 | 725 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 726 | // from system_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 727 | __STATIC_INLINE void __v7_inv_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 728 | uint32_t val = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 729 | __MCR(15, 0, val, 7, 5, 6); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 730 | __DSB(); //ensure completion of the invalidation |
| MikamiUitOpen | 6:38f7dce055d0 | 731 | __ISB(); //ensure instruction fetch path sees new state |
| MikamiUitOpen | 6:38f7dce055d0 | 732 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 733 | |
| MikamiUitOpen | 6:38f7dce055d0 | 734 | |
| MikamiUitOpen | 6:38f7dce055d0 | 735 | /******************************** L1 cache operations ******************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 736 | |
| MikamiUitOpen | 6:38f7dce055d0 | 737 | /** \brief Invalidate the whole I$ |
| MikamiUitOpen | 6:38f7dce055d0 | 738 | |
| MikamiUitOpen | 6:38f7dce055d0 | 739 | ICIALLU. Instruction Cache Invalidate All to PoU |
| MikamiUitOpen | 6:38f7dce055d0 | 740 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 741 | // from system_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 742 | __STATIC_INLINE void __v7_inv_icache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 743 | uint32_t val = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 744 | __MCR(15, 0, val, 7, 5, 0); // reg to cp15 |
| MikamiUitOpen | 6:38f7dce055d0 | 745 | __DSB(); //ensure completion of the invalidation |
| MikamiUitOpen | 6:38f7dce055d0 | 746 | __ISB(); //ensure instruction fetch path sees new I cache state |
| MikamiUitOpen | 6:38f7dce055d0 | 747 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 748 | |
| MikamiUitOpen | 6:38f7dce055d0 | 749 | // from __v7_inv_dcache_all() |
| MikamiUitOpen | 6:38f7dce055d0 | 750 | __arm static inline void __v7_all_cache(uint32_t op) { |
| MikamiUitOpen | 6:38f7dce055d0 | 751 | __asm( |
| MikamiUitOpen | 6:38f7dce055d0 | 752 | " ARM \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 753 | |
| MikamiUitOpen | 6:38f7dce055d0 | 754 | " PUSH {R4-R11} \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 755 | |
| MikamiUitOpen | 6:38f7dce055d0 | 756 | " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR |
| MikamiUitOpen | 6:38f7dce055d0 | 757 | " ANDS R3, R6, #0x07000000\n" // Extract coherency level |
| MikamiUitOpen | 6:38f7dce055d0 | 758 | " MOV R3, R3, LSR #23\n" // Total cache levels << 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 759 | " BEQ Finished\n" // If 0, no need to clean |
| MikamiUitOpen | 6:38f7dce055d0 | 760 | |
| MikamiUitOpen | 6:38f7dce055d0 | 761 | " MOV R10, #0\n" // R10 holds current cache level << 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 762 | "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position |
| MikamiUitOpen | 6:38f7dce055d0 | 763 | " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level |
| MikamiUitOpen | 6:38f7dce055d0 | 764 | " AND R1, R1, #7 \n" // Isolate those lower 3 bits |
| MikamiUitOpen | 6:38f7dce055d0 | 765 | " CMP R1, #2 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 766 | " BLT Skip \n" // No cache or only instruction cache at this level |
| MikamiUitOpen | 6:38f7dce055d0 | 767 | |
| MikamiUitOpen | 6:38f7dce055d0 | 768 | " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register |
| MikamiUitOpen | 6:38f7dce055d0 | 769 | " ISB \n" // ISB to sync the change to the CacheSizeID reg |
| MikamiUitOpen | 6:38f7dce055d0 | 770 | " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register |
| MikamiUitOpen | 6:38f7dce055d0 | 771 | " AND R2, R1, #7 \n" // Extract the line length field |
| MikamiUitOpen | 6:38f7dce055d0 | 772 | " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes) |
| MikamiUitOpen | 6:38f7dce055d0 | 773 | " movw R4, #0x3FF \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 774 | " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned) |
| MikamiUitOpen | 6:38f7dce055d0 | 775 | " CLZ R5, R4 \n" // R5 is the bit position of the way size increment |
| MikamiUitOpen | 6:38f7dce055d0 | 776 | " movw R7, #0x7FFF \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 777 | " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned) |
| MikamiUitOpen | 6:38f7dce055d0 | 778 | |
| MikamiUitOpen | 6:38f7dce055d0 | 779 | "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned) |
| MikamiUitOpen | 6:38f7dce055d0 | 780 | |
| MikamiUitOpen | 6:38f7dce055d0 | 781 | "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11 |
| MikamiUitOpen | 6:38f7dce055d0 | 782 | " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number |
| MikamiUitOpen | 6:38f7dce055d0 | 783 | " CMP R0, #0 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 784 | " BNE Dccsw \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 785 | " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 786 | " B cont \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 787 | "Dccsw: CMP R0, #1 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 788 | " BNE Dccisw \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 789 | " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 790 | " B cont \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 791 | "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 792 | "cont: SUBS R9, R9, #1 \n" // Decrement the Way number |
| MikamiUitOpen | 6:38f7dce055d0 | 793 | " BGE Loop3 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 794 | " SUBS R7, R7, #1 \n" // Decrement the Set number |
| MikamiUitOpen | 6:38f7dce055d0 | 795 | " BGE Loop2 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 796 | "Skip: ADD R10, R10, #2 \n" // increment the cache number |
| MikamiUitOpen | 6:38f7dce055d0 | 797 | " CMP R3, R10 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 798 | " BGT Loop1 \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 799 | |
| MikamiUitOpen | 6:38f7dce055d0 | 800 | "Finished: \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 801 | " DSB \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 802 | " POP {R4-R11} \n" |
| MikamiUitOpen | 6:38f7dce055d0 | 803 | " BX lr \n" ); |
| MikamiUitOpen | 6:38f7dce055d0 | 804 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 805 | |
| MikamiUitOpen | 6:38f7dce055d0 | 806 | /** \brief Invalidate the whole D$ |
| MikamiUitOpen | 6:38f7dce055d0 | 807 | |
| MikamiUitOpen | 6:38f7dce055d0 | 808 | DCISW. Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 809 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 810 | // from system_Renesas_RZ_A1.c |
| MikamiUitOpen | 6:38f7dce055d0 | 811 | __STATIC_INLINE void __v7_inv_dcache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 812 | __v7_all_cache(0); |
| MikamiUitOpen | 6:38f7dce055d0 | 813 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 814 | /** \brief Clean and Invalidate D$ by MVA |
| MikamiUitOpen | 6:38f7dce055d0 | 815 | |
| MikamiUitOpen | 6:38f7dce055d0 | 816 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
| MikamiUitOpen | 6:38f7dce055d0 | 817 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 818 | __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { |
| MikamiUitOpen | 6:38f7dce055d0 | 819 | __MCR(15, 0, (uint32_t)va, 7, 14, 1); |
| MikamiUitOpen | 6:38f7dce055d0 | 820 | __DMB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 821 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 822 | |
| MikamiUitOpen | 6:38f7dce055d0 | 823 | #include "core_ca_mmu.h" |
| MikamiUitOpen | 6:38f7dce055d0 | 824 | |
| MikamiUitOpen | 6:38f7dce055d0 | 825 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
| MikamiUitOpen | 6:38f7dce055d0 | 826 | /* GNU gcc specific functions */ |
| MikamiUitOpen | 6:38f7dce055d0 | 827 | |
| MikamiUitOpen | 6:38f7dce055d0 | 828 | #define MODE_USR 0x10 |
| MikamiUitOpen | 6:38f7dce055d0 | 829 | #define MODE_FIQ 0x11 |
| MikamiUitOpen | 6:38f7dce055d0 | 830 | #define MODE_IRQ 0x12 |
| MikamiUitOpen | 6:38f7dce055d0 | 831 | #define MODE_SVC 0x13 |
| MikamiUitOpen | 6:38f7dce055d0 | 832 | #define MODE_MON 0x16 |
| MikamiUitOpen | 6:38f7dce055d0 | 833 | #define MODE_ABT 0x17 |
| MikamiUitOpen | 6:38f7dce055d0 | 834 | #define MODE_HYP 0x1A |
| MikamiUitOpen | 6:38f7dce055d0 | 835 | #define MODE_UND 0x1B |
| MikamiUitOpen | 6:38f7dce055d0 | 836 | #define MODE_SYS 0x1F |
| MikamiUitOpen | 6:38f7dce055d0 | 837 | |
| MikamiUitOpen | 6:38f7dce055d0 | 838 | |
| MikamiUitOpen | 6:38f7dce055d0 | 839 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 840 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 841 | __ASM volatile ("cpsie i"); |
| MikamiUitOpen | 6:38f7dce055d0 | 842 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 843 | |
| MikamiUitOpen | 6:38f7dce055d0 | 844 | /** \brief Disable IRQ Interrupts |
| MikamiUitOpen | 6:38f7dce055d0 | 845 | |
| MikamiUitOpen | 6:38f7dce055d0 | 846 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
| MikamiUitOpen | 6:38f7dce055d0 | 847 | Can only be executed in Privileged modes. |
| MikamiUitOpen | 6:38f7dce055d0 | 848 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 849 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 850 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 851 | uint32_t result; |
| MikamiUitOpen | 6:38f7dce055d0 | 852 | |
| MikamiUitOpen | 6:38f7dce055d0 | 853 | __ASM volatile ("mrs %0, cpsr" : "=r" (result)); |
| MikamiUitOpen | 6:38f7dce055d0 | 854 | __ASM volatile ("cpsid i"); |
| MikamiUitOpen | 6:38f7dce055d0 | 855 | return(result & 0x80); |
| MikamiUitOpen | 6:38f7dce055d0 | 856 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 857 | |
| MikamiUitOpen | 6:38f7dce055d0 | 858 | |
| MikamiUitOpen | 6:38f7dce055d0 | 859 | /** \brief Get APSR Register |
| MikamiUitOpen | 6:38f7dce055d0 | 860 | |
| MikamiUitOpen | 6:38f7dce055d0 | 861 | This function returns the content of the APSR Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 862 | |
| MikamiUitOpen | 6:38f7dce055d0 | 863 | \return APSR Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 864 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 865 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 866 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 867 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 868 | register uint32_t __regAPSR; |
| MikamiUitOpen | 6:38f7dce055d0 | 869 | __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) ); |
| MikamiUitOpen | 6:38f7dce055d0 | 870 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 871 | register uint32_t __regAPSR __ASM("apsr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 872 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 873 | return(__regAPSR); |
| MikamiUitOpen | 6:38f7dce055d0 | 874 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 875 | |
| MikamiUitOpen | 6:38f7dce055d0 | 876 | |
| MikamiUitOpen | 6:38f7dce055d0 | 877 | /** \brief Get CPSR Register |
| MikamiUitOpen | 6:38f7dce055d0 | 878 | |
| MikamiUitOpen | 6:38f7dce055d0 | 879 | This function returns the content of the CPSR Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 880 | |
| MikamiUitOpen | 6:38f7dce055d0 | 881 | \return CPSR Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 882 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 883 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 884 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 885 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 886 | register uint32_t __regCPSR; |
| MikamiUitOpen | 6:38f7dce055d0 | 887 | __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR)); |
| MikamiUitOpen | 6:38f7dce055d0 | 888 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 889 | register uint32_t __regCPSR __ASM("cpsr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 890 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 891 | return(__regCPSR); |
| MikamiUitOpen | 6:38f7dce055d0 | 892 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 893 | |
| MikamiUitOpen | 6:38f7dce055d0 | 894 | #if 0 |
| MikamiUitOpen | 6:38f7dce055d0 | 895 | /** \brief Set Stack Pointer |
| MikamiUitOpen | 6:38f7dce055d0 | 896 | |
| MikamiUitOpen | 6:38f7dce055d0 | 897 | This function assigns the given value to the current stack pointer. |
| MikamiUitOpen | 6:38f7dce055d0 | 898 | |
| MikamiUitOpen | 6:38f7dce055d0 | 899 | \param [in] topOfStack Stack Pointer value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 900 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 901 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack) |
| MikamiUitOpen | 6:38f7dce055d0 | 902 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 903 | register uint32_t __regSP __ASM("sp"); |
| MikamiUitOpen | 6:38f7dce055d0 | 904 | __regSP = topOfStack; |
| MikamiUitOpen | 6:38f7dce055d0 | 905 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 906 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 907 | |
| MikamiUitOpen | 6:38f7dce055d0 | 908 | /** \brief Get link register |
| MikamiUitOpen | 6:38f7dce055d0 | 909 | |
| MikamiUitOpen | 6:38f7dce055d0 | 910 | This function returns the value of the link register |
| MikamiUitOpen | 6:38f7dce055d0 | 911 | |
| MikamiUitOpen | 6:38f7dce055d0 | 912 | \return Value of link register |
| MikamiUitOpen | 6:38f7dce055d0 | 913 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 914 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 915 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 916 | register uint32_t __reglr __ASM("lr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 917 | return(__reglr); |
| MikamiUitOpen | 6:38f7dce055d0 | 918 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 919 | |
| MikamiUitOpen | 6:38f7dce055d0 | 920 | #if 0 |
| MikamiUitOpen | 6:38f7dce055d0 | 921 | /** \brief Set link register |
| MikamiUitOpen | 6:38f7dce055d0 | 922 | |
| MikamiUitOpen | 6:38f7dce055d0 | 923 | This function sets the value of the link register |
| MikamiUitOpen | 6:38f7dce055d0 | 924 | |
| MikamiUitOpen | 6:38f7dce055d0 | 925 | \param [in] lr LR value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 926 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 927 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr) |
| MikamiUitOpen | 6:38f7dce055d0 | 928 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 929 | register uint32_t __reglr __ASM("lr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 930 | __reglr = lr; |
| MikamiUitOpen | 6:38f7dce055d0 | 931 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 932 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 933 | |
| MikamiUitOpen | 6:38f7dce055d0 | 934 | /** \brief Set Process Stack Pointer |
| MikamiUitOpen | 6:38f7dce055d0 | 935 | |
| MikamiUitOpen | 6:38f7dce055d0 | 936 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
| MikamiUitOpen | 6:38f7dce055d0 | 937 | |
| MikamiUitOpen | 6:38f7dce055d0 | 938 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 939 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 940 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
| MikamiUitOpen | 6:38f7dce055d0 | 941 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 942 | __asm__ volatile ( |
| MikamiUitOpen | 6:38f7dce055d0 | 943 | ".ARM;" |
| MikamiUitOpen | 6:38f7dce055d0 | 944 | ".eabi_attribute Tag_ABI_align8_preserved,1;" |
| MikamiUitOpen | 6:38f7dce055d0 | 945 | |
| MikamiUitOpen | 6:38f7dce055d0 | 946 | "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */ |
| MikamiUitOpen | 6:38f7dce055d0 | 947 | "MRS R1, CPSR;" |
| MikamiUitOpen | 6:38f7dce055d0 | 948 | "CPS %0;" /* ;no effect in USR mode */ |
| MikamiUitOpen | 6:38f7dce055d0 | 949 | "MOV SP, R0;" |
| MikamiUitOpen | 6:38f7dce055d0 | 950 | "MSR CPSR_c, R1;" /* ;no effect in USR mode */ |
| MikamiUitOpen | 6:38f7dce055d0 | 951 | "ISB;" |
| MikamiUitOpen | 6:38f7dce055d0 | 952 | //"BX LR;" |
| MikamiUitOpen | 6:38f7dce055d0 | 953 | : |
| MikamiUitOpen | 6:38f7dce055d0 | 954 | : "i"(MODE_SYS) |
| MikamiUitOpen | 6:38f7dce055d0 | 955 | : "r0", "r1"); |
| MikamiUitOpen | 6:38f7dce055d0 | 956 | return; |
| MikamiUitOpen | 6:38f7dce055d0 | 957 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 958 | |
| MikamiUitOpen | 6:38f7dce055d0 | 959 | /** \brief Set User Mode |
| MikamiUitOpen | 6:38f7dce055d0 | 960 | |
| MikamiUitOpen | 6:38f7dce055d0 | 961 | This function changes the processor state to User Mode |
| MikamiUitOpen | 6:38f7dce055d0 | 962 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 963 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 964 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 965 | __asm__ volatile ( |
| MikamiUitOpen | 6:38f7dce055d0 | 966 | ".ARM;" |
| MikamiUitOpen | 6:38f7dce055d0 | 967 | |
| MikamiUitOpen | 6:38f7dce055d0 | 968 | "CPS %0;" |
| MikamiUitOpen | 6:38f7dce055d0 | 969 | //"BX LR;" |
| MikamiUitOpen | 6:38f7dce055d0 | 970 | : |
| MikamiUitOpen | 6:38f7dce055d0 | 971 | : "i"(MODE_USR) |
| MikamiUitOpen | 6:38f7dce055d0 | 972 | : ); |
| MikamiUitOpen | 6:38f7dce055d0 | 973 | return; |
| MikamiUitOpen | 6:38f7dce055d0 | 974 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 975 | |
| MikamiUitOpen | 6:38f7dce055d0 | 976 | |
| MikamiUitOpen | 6:38f7dce055d0 | 977 | /** \brief Enable FIQ |
| MikamiUitOpen | 6:38f7dce055d0 | 978 | |
| MikamiUitOpen | 6:38f7dce055d0 | 979 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
| MikamiUitOpen | 6:38f7dce055d0 | 980 | Can only be executed in Privileged modes. |
| MikamiUitOpen | 6:38f7dce055d0 | 981 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 982 | #define __enable_fault_irq() __asm__ volatile ("cpsie f") |
| MikamiUitOpen | 6:38f7dce055d0 | 983 | |
| MikamiUitOpen | 6:38f7dce055d0 | 984 | |
| MikamiUitOpen | 6:38f7dce055d0 | 985 | /** \brief Disable FIQ |
| MikamiUitOpen | 6:38f7dce055d0 | 986 | |
| MikamiUitOpen | 6:38f7dce055d0 | 987 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
| MikamiUitOpen | 6:38f7dce055d0 | 988 | Can only be executed in Privileged modes. |
| MikamiUitOpen | 6:38f7dce055d0 | 989 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 990 | #define __disable_fault_irq() __asm__ volatile ("cpsid f") |
| MikamiUitOpen | 6:38f7dce055d0 | 991 | |
| MikamiUitOpen | 6:38f7dce055d0 | 992 | |
| MikamiUitOpen | 6:38f7dce055d0 | 993 | /** \brief Get FPSCR |
| MikamiUitOpen | 6:38f7dce055d0 | 994 | |
| MikamiUitOpen | 6:38f7dce055d0 | 995 | This function returns the current value of the Floating Point Status/Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 996 | |
| MikamiUitOpen | 6:38f7dce055d0 | 997 | \return Floating Point Status/Control register value |
| MikamiUitOpen | 6:38f7dce055d0 | 998 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 999 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 1000 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 1001 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 1002 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1003 | uint32_t result; |
| MikamiUitOpen | 6:38f7dce055d0 | 1004 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1005 | __ASM volatile ("vmrs %0, fpscr" : "=r" (result) ); |
| MikamiUitOpen | 6:38f7dce055d0 | 1006 | return (result); |
| MikamiUitOpen | 6:38f7dce055d0 | 1007 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1008 | register uint32_t __regfpscr __ASM("fpscr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1009 | return(__regfpscr); |
| MikamiUitOpen | 6:38f7dce055d0 | 1010 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1011 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1012 | return(0); |
| MikamiUitOpen | 6:38f7dce055d0 | 1013 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1014 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1015 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1016 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1017 | /** \brief Set FPSCR |
| MikamiUitOpen | 6:38f7dce055d0 | 1018 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1019 | This function assigns the given value to the Floating Point Status/Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1020 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1021 | \param [in] fpscr Floating Point Status/Control value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 1022 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1023 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
| MikamiUitOpen | 6:38f7dce055d0 | 1024 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 1025 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 1026 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1027 | __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) ); |
| MikamiUitOpen | 6:38f7dce055d0 | 1028 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1029 | register uint32_t __regfpscr __ASM("fpscr"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1030 | __regfpscr = (fpscr); |
| MikamiUitOpen | 6:38f7dce055d0 | 1031 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1032 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1033 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1034 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1035 | /** \brief Get FPEXC |
| MikamiUitOpen | 6:38f7dce055d0 | 1036 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1037 | This function returns the current value of the Floating Point Exception Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1038 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1039 | \return Floating Point Exception Control register value |
| MikamiUitOpen | 6:38f7dce055d0 | 1040 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1041 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 1042 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 1043 | #if (__FPU_PRESENT == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 1044 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1045 | uint32_t result; |
| MikamiUitOpen | 6:38f7dce055d0 | 1046 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1047 | __ASM volatile ("vmrs %0, fpexc" : "=r" (result)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1048 | return (result); |
| MikamiUitOpen | 6:38f7dce055d0 | 1049 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1050 | register uint32_t __regfpexc __ASM("fpexc"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1051 | return(__regfpexc); |
| MikamiUitOpen | 6:38f7dce055d0 | 1052 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1053 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1054 | return(0); |
| MikamiUitOpen | 6:38f7dce055d0 | 1055 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1056 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1057 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1058 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1059 | /** \brief Set FPEXC |
| MikamiUitOpen | 6:38f7dce055d0 | 1060 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1061 | This function assigns the given value to the Floating Point Exception Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1062 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1063 | \param [in] fpscr Floating Point Exception Control value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 1064 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1065 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
| MikamiUitOpen | 6:38f7dce055d0 | 1066 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 1067 | #if (__FPU_PRESENT == 1) |
| MikamiUitOpen | 6:38f7dce055d0 | 1068 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1069 | __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1070 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1071 | register uint32_t __regfpexc __ASM("fpexc"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1072 | __regfpexc = (fpexc); |
| MikamiUitOpen | 6:38f7dce055d0 | 1073 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1074 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1075 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1076 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1077 | /** \brief Get CPACR |
| MikamiUitOpen | 6:38f7dce055d0 | 1078 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1079 | This function returns the current value of the Coprocessor Access Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1080 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1081 | \return Coprocessor Access Control register value |
| MikamiUitOpen | 6:38f7dce055d0 | 1082 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1083 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void) |
| MikamiUitOpen | 6:38f7dce055d0 | 1084 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 1085 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1086 | register uint32_t __regCPACR; |
| MikamiUitOpen | 6:38f7dce055d0 | 1087 | __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1088 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1089 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1090 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1091 | return __regCPACR; |
| MikamiUitOpen | 6:38f7dce055d0 | 1092 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1093 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1094 | /** \brief Set CPACR |
| MikamiUitOpen | 6:38f7dce055d0 | 1095 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1096 | This function assigns the given value to the Coprocessor Access Control register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1097 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1098 | \param [in] cpacr Coprocessor Acccess Control value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 1099 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1100 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr) |
| MikamiUitOpen | 6:38f7dce055d0 | 1101 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 1102 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1103 | __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1104 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1105 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1106 | __regCPACR = cpacr; |
| MikamiUitOpen | 6:38f7dce055d0 | 1107 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1108 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1109 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1110 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1111 | /** \brief Get CBAR |
| MikamiUitOpen | 6:38f7dce055d0 | 1112 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1113 | This function returns the value of the Configuration Base Address register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1114 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1115 | \return Configuration Base Address register value |
| MikamiUitOpen | 6:38f7dce055d0 | 1116 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1117 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() { |
| MikamiUitOpen | 6:38f7dce055d0 | 1118 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1119 | register uint32_t __regCBAR; |
| MikamiUitOpen | 6:38f7dce055d0 | 1120 | __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1121 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1122 | register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1123 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1124 | return(__regCBAR); |
| MikamiUitOpen | 6:38f7dce055d0 | 1125 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1126 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1127 | /** \brief Get TTBR0 |
| MikamiUitOpen | 6:38f7dce055d0 | 1128 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1129 | This function returns the value of the Translation Table Base Register 0. |
| MikamiUitOpen | 6:38f7dce055d0 | 1130 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1131 | \return Translation Table Base Register 0 value |
| MikamiUitOpen | 6:38f7dce055d0 | 1132 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1133 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() { |
| MikamiUitOpen | 6:38f7dce055d0 | 1134 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1135 | register uint32_t __regTTBR0; |
| MikamiUitOpen | 6:38f7dce055d0 | 1136 | __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1137 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1138 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1139 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1140 | return(__regTTBR0); |
| MikamiUitOpen | 6:38f7dce055d0 | 1141 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1142 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1143 | /** \brief Set TTBR0 |
| MikamiUitOpen | 6:38f7dce055d0 | 1144 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1145 | This function assigns the given value to the Translation Table Base Register 0. |
| MikamiUitOpen | 6:38f7dce055d0 | 1146 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1147 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 1148 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1149 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1150 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1151 | __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1152 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1153 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1154 | __regTTBR0 = ttbr0; |
| MikamiUitOpen | 6:38f7dce055d0 | 1155 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1156 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1157 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1158 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1159 | /** \brief Get DACR |
| MikamiUitOpen | 6:38f7dce055d0 | 1160 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1161 | This function returns the value of the Domain Access Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1162 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1163 | \return Domain Access Control Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 1164 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1165 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() { |
| MikamiUitOpen | 6:38f7dce055d0 | 1166 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1167 | register uint32_t __regDACR; |
| MikamiUitOpen | 6:38f7dce055d0 | 1168 | __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1169 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1170 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1171 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1172 | return(__regDACR); |
| MikamiUitOpen | 6:38f7dce055d0 | 1173 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1174 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1175 | /** \brief Set DACR |
| MikamiUitOpen | 6:38f7dce055d0 | 1176 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1177 | This function assigns the given value to the Domain Access Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1178 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1179 | \param [in] dacr Domain Access Control Register value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 1180 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1181 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1182 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1183 | __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1184 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1185 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1186 | __regDACR = dacr; |
| MikamiUitOpen | 6:38f7dce055d0 | 1187 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1188 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1189 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1190 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1191 | /******************************** Cache and BTAC enable ****************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 1192 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1193 | /** \brief Set SCTLR |
| MikamiUitOpen | 6:38f7dce055d0 | 1194 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1195 | This function assigns the given value to the System Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1196 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1197 | \param [in] sctlr System Control Register value to set |
| MikamiUitOpen | 6:38f7dce055d0 | 1198 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1199 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) |
| MikamiUitOpen | 6:38f7dce055d0 | 1200 | { |
| MikamiUitOpen | 6:38f7dce055d0 | 1201 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1202 | __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1203 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1204 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1205 | __regSCTLR = sctlr; |
| MikamiUitOpen | 6:38f7dce055d0 | 1206 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1207 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1208 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1209 | /** \brief Get SCTLR |
| MikamiUitOpen | 6:38f7dce055d0 | 1210 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1211 | This function returns the value of the System Control Register. |
| MikamiUitOpen | 6:38f7dce055d0 | 1212 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1213 | \return System Control Register value |
| MikamiUitOpen | 6:38f7dce055d0 | 1214 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1215 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() { |
| MikamiUitOpen | 6:38f7dce055d0 | 1216 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1217 | register uint32_t __regSCTLR; |
| MikamiUitOpen | 6:38f7dce055d0 | 1218 | __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1219 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1220 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1221 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1222 | return(__regSCTLR); |
| MikamiUitOpen | 6:38f7dce055d0 | 1223 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1224 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1225 | /** \brief Enable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 1226 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1227 | Enable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 1228 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1229 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1230 | // Set I bit 12 to enable I Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 1231 | // Set C bit 2 to enable D Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 1232 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1233 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1234 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1235 | /** \brief Disable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 1236 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1237 | Disable Caches |
| MikamiUitOpen | 6:38f7dce055d0 | 1238 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1239 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1240 | // Clear I bit 12 to disable I Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 1241 | // Clear C bit 2 to disable D Cache |
| MikamiUitOpen | 6:38f7dce055d0 | 1242 | __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1243 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1244 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1245 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1246 | /** \brief Enable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 1247 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1248 | Enable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 1249 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1250 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1251 | // Set Z bit 11 to enable branch prediction |
| MikamiUitOpen | 6:38f7dce055d0 | 1252 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1253 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1254 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1255 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1256 | /** \brief Disable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 1257 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1258 | Disable BTAC |
| MikamiUitOpen | 6:38f7dce055d0 | 1259 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1260 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1261 | // Clear Z bit 11 to disable branch prediction |
| MikamiUitOpen | 6:38f7dce055d0 | 1262 | __set_SCTLR( __get_SCTLR() & ~(1 << 11)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1263 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1264 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1265 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1266 | /** \brief Enable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 1267 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1268 | Enable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 1269 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1270 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1271 | // Set M bit 0 to enable the MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 1272 | // Set AFE bit to enable simplified access permissions model |
| MikamiUitOpen | 6:38f7dce055d0 | 1273 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
| MikamiUitOpen | 6:38f7dce055d0 | 1274 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1275 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1276 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1277 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1278 | /** \brief Disable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 1279 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1280 | Disable MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 1281 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1282 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1283 | // Clear M bit 0 to disable the MMU |
| MikamiUitOpen | 6:38f7dce055d0 | 1284 | __set_SCTLR( __get_SCTLR() & ~1); |
| MikamiUitOpen | 6:38f7dce055d0 | 1285 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1286 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1287 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1288 | /******************************** TLB maintenance operations ************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 1289 | /** \brief Invalidate the whole tlb |
| MikamiUitOpen | 6:38f7dce055d0 | 1290 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1291 | TLBIALL. Invalidate the whole tlb |
| MikamiUitOpen | 6:38f7dce055d0 | 1292 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1293 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1294 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1295 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1296 | __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1297 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1298 | register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1299 | __TLBIALL = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 1300 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1301 | __DSB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1302 | __ISB(); |
| MikamiUitOpen | 6:38f7dce055d0 | 1303 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1304 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1305 | /******************************** BTB maintenance operations ************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 1306 | /** \brief Invalidate entire branch predictor array |
| MikamiUitOpen | 6:38f7dce055d0 | 1307 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1308 | BPIALL. Branch Predictor Invalidate All. |
| MikamiUitOpen | 6:38f7dce055d0 | 1309 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1310 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1311 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1312 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1313 | __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1314 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1315 | register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1316 | __BPIALL = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 1317 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1318 | __DSB(); //ensure completion of the invalidation |
| MikamiUitOpen | 6:38f7dce055d0 | 1319 | __ISB(); //ensure instruction fetch path sees new state |
| MikamiUitOpen | 6:38f7dce055d0 | 1320 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1321 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1322 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1323 | /******************************** L1 cache operations ******************************************************/ |
| MikamiUitOpen | 6:38f7dce055d0 | 1324 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1325 | /** \brief Invalidate the whole I$ |
| MikamiUitOpen | 6:38f7dce055d0 | 1326 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1327 | ICIALLU. Instruction Cache Invalidate All to PoU |
| MikamiUitOpen | 6:38f7dce055d0 | 1328 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1329 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1330 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1331 | __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1332 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1333 | register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1334 | __ICIALLU = 0; |
| MikamiUitOpen | 6:38f7dce055d0 | 1335 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1336 | __DSB(); //ensure completion of the invalidation |
| MikamiUitOpen | 6:38f7dce055d0 | 1337 | __ISB(); //ensure instruction fetch path sees new I cache state |
| MikamiUitOpen | 6:38f7dce055d0 | 1338 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1339 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1340 | /** \brief Clean D$ by MVA |
| MikamiUitOpen | 6:38f7dce055d0 | 1341 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1342 | DCCMVAC. Data cache clean by MVA to PoC |
| MikamiUitOpen | 6:38f7dce055d0 | 1343 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1344 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1345 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1346 | __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1347 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1348 | register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1349 | __DCCMVAC = (uint32_t)va; |
| MikamiUitOpen | 6:38f7dce055d0 | 1350 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1351 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
| MikamiUitOpen | 6:38f7dce055d0 | 1352 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1353 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1354 | /** \brief Invalidate D$ by MVA |
| MikamiUitOpen | 6:38f7dce055d0 | 1355 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1356 | DCIMVAC. Data cache invalidate by MVA to PoC |
| MikamiUitOpen | 6:38f7dce055d0 | 1357 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1358 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1359 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1360 | __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1361 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1362 | register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1363 | __DCIMVAC = (uint32_t)va; |
| MikamiUitOpen | 6:38f7dce055d0 | 1364 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1365 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
| MikamiUitOpen | 6:38f7dce055d0 | 1366 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1367 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1368 | /** \brief Clean and Invalidate D$ by MVA |
| MikamiUitOpen | 6:38f7dce055d0 | 1369 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1370 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
| MikamiUitOpen | 6:38f7dce055d0 | 1371 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1372 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1373 | #if 1 |
| MikamiUitOpen | 6:38f7dce055d0 | 1374 | __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va)); |
| MikamiUitOpen | 6:38f7dce055d0 | 1375 | #else |
| MikamiUitOpen | 6:38f7dce055d0 | 1376 | register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); |
| MikamiUitOpen | 6:38f7dce055d0 | 1377 | __DCCIMVAC = (uint32_t)va; |
| MikamiUitOpen | 6:38f7dce055d0 | 1378 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1379 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
| MikamiUitOpen | 6:38f7dce055d0 | 1380 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1381 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1382 | /** \brief Clean and Invalidate the entire data or unified cache |
| MikamiUitOpen | 6:38f7dce055d0 | 1383 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1384 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. |
| MikamiUitOpen | 6:38f7dce055d0 | 1385 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1386 | extern void __v7_all_cache(uint32_t op); |
| MikamiUitOpen | 6:38f7dce055d0 | 1387 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1388 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1389 | /** \brief Invalidate the whole D$ |
| MikamiUitOpen | 6:38f7dce055d0 | 1390 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1391 | DCISW. Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 1392 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1393 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1394 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1395 | __v7_all_cache(0); |
| MikamiUitOpen | 6:38f7dce055d0 | 1396 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1397 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1398 | /** \brief Clean the whole D$ |
| MikamiUitOpen | 6:38f7dce055d0 | 1399 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1400 | DCCSW. Clean by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 1401 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1402 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1403 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1404 | __v7_all_cache(1); |
| MikamiUitOpen | 6:38f7dce055d0 | 1405 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1406 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1407 | /** \brief Clean and invalidate the whole D$ |
| MikamiUitOpen | 6:38f7dce055d0 | 1408 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1409 | DCCISW. Clean and Invalidate by Set/Way |
| MikamiUitOpen | 6:38f7dce055d0 | 1410 | */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1411 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1412 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { |
| MikamiUitOpen | 6:38f7dce055d0 | 1413 | __v7_all_cache(2); |
| MikamiUitOpen | 6:38f7dce055d0 | 1414 | } |
| MikamiUitOpen | 6:38f7dce055d0 | 1415 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1416 | #include "core_ca_mmu.h" |
| MikamiUitOpen | 6:38f7dce055d0 | 1417 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1418 | #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ |
| MikamiUitOpen | 6:38f7dce055d0 | 1419 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1420 | #error TASKING Compiler support not implemented for Cortex-A |
| MikamiUitOpen | 6:38f7dce055d0 | 1421 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1422 | #endif |
| MikamiUitOpen | 6:38f7dce055d0 | 1423 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1424 | /*@} end of CMSIS_Core_RegAccFunctions */ |
| MikamiUitOpen | 6:38f7dce055d0 | 1425 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1426 | |
| MikamiUitOpen | 6:38f7dce055d0 | 1427 | #endif /* __CORE_CAFUNC_H__ */ |