Teste Flash
Dependencies: pulga-lorawan-drv Si1133 BME280
SPI_MX25R.h@70:99b7a15c09da, 2021-09-13 (annotated)
- Committer:
- MatteusCarr
- Date:
- Mon Sep 13 18:55:32 2021 +0000
- Revision:
- 70:99b7a15c09da
Teste Flash
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
MatteusCarr | 70:99b7a15c09da | 1 | #ifndef _SPI_MX25R_H_ |
MatteusCarr | 70:99b7a15c09da | 2 | #define _SPI_MX25R_H_ |
MatteusCarr | 70:99b7a15c09da | 3 | |
MatteusCarr | 70:99b7a15c09da | 4 | #include "mbed.h" |
MatteusCarr | 70:99b7a15c09da | 5 | |
MatteusCarr | 70:99b7a15c09da | 6 | /** |
MatteusCarr | 70:99b7a15c09da | 7 | Page Defines, write read based on page size |
MatteusCarr | 70:99b7a15c09da | 8 | */ |
MatteusCarr | 70:99b7a15c09da | 9 | #define MX25R_PAGES 0x7FFF // total memory size - Addresses 0x7FFFFF |
MatteusCarr | 70:99b7a15c09da | 10 | /** |
MatteusCarr | 70:99b7a15c09da | 11 | * Macronix Serial Flash Low Power Memories |
MatteusCarr | 70:99b7a15c09da | 12 | * SPI_MX25R Series SPI-Flash Memory |
MatteusCarr | 70:99b7a15c09da | 13 | */ |
MatteusCarr | 70:99b7a15c09da | 14 | #define CS_LOW 0 // SPI CS# (Chip Select) Setting |
MatteusCarr | 70:99b7a15c09da | 15 | #define CS_HIGH 1 // SPI CS# (Chip Select) Setting |
MatteusCarr | 70:99b7a15c09da | 16 | #define DUMMY 0x00 // Dummy byte which can be changed to any value |
MatteusCarr | 70:99b7a15c09da | 17 | /** |
MatteusCarr | 70:99b7a15c09da | 18 | * MX25R Series Register Command Table. |
MatteusCarr | 70:99b7a15c09da | 19 | * x2 and x4 commands not currently supported with FRDM K64F platform |
MatteusCarr | 70:99b7a15c09da | 20 | */ |
MatteusCarr | 70:99b7a15c09da | 21 | #define CMD_READ 0x03 // x1 Normal Read Data Byte |
MatteusCarr | 70:99b7a15c09da | 22 | #define CMD_FREAD 0x0B // x1 Fast Read Data Byte |
MatteusCarr | 70:99b7a15c09da | 23 | #define CMD_2READ 0xBB // x2 2READ |
MatteusCarr | 70:99b7a15c09da | 24 | #define CMD_DREAD 0x3B // x2 DREAD |
MatteusCarr | 70:99b7a15c09da | 25 | #define CMD_4READ 0xEB // x4 4READ |
MatteusCarr | 70:99b7a15c09da | 26 | #define CMD_QREAD 0x6B // x4 QREAD |
MatteusCarr | 70:99b7a15c09da | 27 | #define CMD_PP 0x02 // Page Program |
MatteusCarr | 70:99b7a15c09da | 28 | #define CMD_4PP 0x38 // x4 PP |
MatteusCarr | 70:99b7a15c09da | 29 | #define CMD_SE 0x20 // 4KB Sector Erase |
MatteusCarr | 70:99b7a15c09da | 30 | #define CMD_32KBE 0x52 // 32KB Block Erase |
MatteusCarr | 70:99b7a15c09da | 31 | #define CMD_BE 0xD8 // 64KB Block Erase |
MatteusCarr | 70:99b7a15c09da | 32 | #define CMD_CE 0xC7 // Chip Erase |
MatteusCarr | 70:99b7a15c09da | 33 | #define CMD_RDSFDP 0x5A // Read SFDP |
MatteusCarr | 70:99b7a15c09da | 34 | #define CMD_WREN 0x06 // Write Enable |
MatteusCarr | 70:99b7a15c09da | 35 | #define CMD_WRDI 0x04 // Write Disable |
MatteusCarr | 70:99b7a15c09da | 36 | #define CMD_RDSR 0x05 // Read Status Register |
MatteusCarr | 70:99b7a15c09da | 37 | #define CMD_RDCR 0x15 // Read Configuration Register |
MatteusCarr | 70:99b7a15c09da | 38 | #define CMD_WRSR 0x01 // Write Status Register |
MatteusCarr | 70:99b7a15c09da | 39 | #define CMD_PESUS 0xB0 // Program/Erase Suspend |
MatteusCarr | 70:99b7a15c09da | 40 | #define CMD_PERES 0x30 // Program/Erase Resume |
MatteusCarr | 70:99b7a15c09da | 41 | #define CMD_DP 0xB9 // Enter Deep Power Down |
MatteusCarr | 70:99b7a15c09da | 42 | #define CMD_SBL 0xC0 // Set Burst Length |
MatteusCarr | 70:99b7a15c09da | 43 | #define CMD_RDID 0x9F // Read Manufacturer and JDEC Device ID |
MatteusCarr | 70:99b7a15c09da | 44 | #define CMD_REMS 0x90 // Read Electronic Manufacturer and Device ID |
MatteusCarr | 70:99b7a15c09da | 45 | #define CMD_RES 0xAB // Read Electronic ID |
MatteusCarr | 70:99b7a15c09da | 46 | #define CMD_ENSO 0xB1 // Enter Secure OTP |
MatteusCarr | 70:99b7a15c09da | 47 | #define CMD_EXSO 0xC1 // Exit Secure OTP |
MatteusCarr | 70:99b7a15c09da | 48 | #define CMD_RDSCUR 0x2B // Read Security Register |
MatteusCarr | 70:99b7a15c09da | 49 | #define CMD_WRSCUR 0x2F // Write Security Register |
MatteusCarr | 70:99b7a15c09da | 50 | #define CMD_NOP 0x00 // No Operation |
MatteusCarr | 70:99b7a15c09da | 51 | #define CMD_RSTEN 0x66 // Reset Enable |
MatteusCarr | 70:99b7a15c09da | 52 | #define CMD_RST 0x99 // Reset |
MatteusCarr | 70:99b7a15c09da | 53 | #define CMD_RRE 0xFF // Release Read Enhanced Mode |
MatteusCarr | 70:99b7a15c09da | 54 | |
MatteusCarr | 70:99b7a15c09da | 55 | |
MatteusCarr | 70:99b7a15c09da | 56 | class SPI_MX25R |
MatteusCarr | 70:99b7a15c09da | 57 | { |
MatteusCarr | 70:99b7a15c09da | 58 | public: |
MatteusCarr | 70:99b7a15c09da | 59 | /** |
MatteusCarr | 70:99b7a15c09da | 60 | * Macronix MX25R Low Power and Wide Vcc SPI-Flash Memory Family |
MatteusCarr | 70:99b7a15c09da | 61 | * |
MatteusCarr | 70:99b7a15c09da | 62 | * @param SI/SIO0 SPI_MOSI pin |
MatteusCarr | 70:99b7a15c09da | 63 | * @param SO/SI01 SPI_MISO pin |
MatteusCarr | 70:99b7a15c09da | 64 | * @param SCLK SPI_CLK pin |
MatteusCarr | 70:99b7a15c09da | 65 | * @param CSb SPI_CS pin |
MatteusCarr | 70:99b7a15c09da | 66 | */ |
MatteusCarr | 70:99b7a15c09da | 67 | SPI_MX25R(PinName mosi, PinName miso, PinName sclk, PinName cs) ; |
MatteusCarr | 70:99b7a15c09da | 68 | |
MatteusCarr | 70:99b7a15c09da | 69 | ~SPI_MX25R() ; |
MatteusCarr | 70:99b7a15c09da | 70 | |
MatteusCarr | 70:99b7a15c09da | 71 | SPI m_spi; |
MatteusCarr | 70:99b7a15c09da | 72 | DigitalOut m_cs ; |
MatteusCarr | 70:99b7a15c09da | 73 | int _mode ; |
MatteusCarr | 70:99b7a15c09da | 74 | |
MatteusCarr | 70:99b7a15c09da | 75 | /// Write Enable |
MatteusCarr | 70:99b7a15c09da | 76 | void writeEnable(void) ; |
MatteusCarr | 70:99b7a15c09da | 77 | |
MatteusCarr | 70:99b7a15c09da | 78 | /// Write Disable |
MatteusCarr | 70:99b7a15c09da | 79 | void writeDisable(void) ; |
MatteusCarr | 70:99b7a15c09da | 80 | |
MatteusCarr | 70:99b7a15c09da | 81 | /// Reset Enable |
MatteusCarr | 70:99b7a15c09da | 82 | void resetEnable(void) ; |
MatteusCarr | 70:99b7a15c09da | 83 | |
MatteusCarr | 70:99b7a15c09da | 84 | /// Reset |
MatteusCarr | 70:99b7a15c09da | 85 | void reset(void) ; |
MatteusCarr | 70:99b7a15c09da | 86 | |
MatteusCarr | 70:99b7a15c09da | 87 | /// Program or Erase Suspend |
MatteusCarr | 70:99b7a15c09da | 88 | void pgmersSuspend(void) ; |
MatteusCarr | 70:99b7a15c09da | 89 | |
MatteusCarr | 70:99b7a15c09da | 90 | /// Program or Erase Resume |
MatteusCarr | 70:99b7a15c09da | 91 | void pgmersResume(void) ; |
MatteusCarr | 70:99b7a15c09da | 92 | |
MatteusCarr | 70:99b7a15c09da | 93 | /// Enter Deep Power Down |
MatteusCarr | 70:99b7a15c09da | 94 | void deepPowerdown(void) ; |
MatteusCarr | 70:99b7a15c09da | 95 | |
MatteusCarr | 70:99b7a15c09da | 96 | /// Set Burst Length |
MatteusCarr | 70:99b7a15c09da | 97 | void setBurstlength(void) ; |
MatteusCarr | 70:99b7a15c09da | 98 | |
MatteusCarr | 70:99b7a15c09da | 99 | /// Release from Read Enhanced Mode |
MatteusCarr | 70:99b7a15c09da | 100 | void releaseReadenhaced(void) ; |
MatteusCarr | 70:99b7a15c09da | 101 | |
MatteusCarr | 70:99b7a15c09da | 102 | /// No Operation |
MatteusCarr | 70:99b7a15c09da | 103 | void noOperation(void) ; |
MatteusCarr | 70:99b7a15c09da | 104 | |
MatteusCarr | 70:99b7a15c09da | 105 | /// Enter OTP Area |
MatteusCarr | 70:99b7a15c09da | 106 | void enterSecureOTP(void) ; |
MatteusCarr | 70:99b7a15c09da | 107 | |
MatteusCarr | 70:99b7a15c09da | 108 | /// Exit OTP Area |
MatteusCarr | 70:99b7a15c09da | 109 | void exitSecureOTP(void) ; |
MatteusCarr | 70:99b7a15c09da | 110 | |
MatteusCarr | 70:99b7a15c09da | 111 | /// Chip Erase |
MatteusCarr | 70:99b7a15c09da | 112 | void chipErase(void) ; |
MatteusCarr | 70:99b7a15c09da | 113 | |
MatteusCarr | 70:99b7a15c09da | 114 | /// Write Status and Configuration Reg 1 and 2 |
MatteusCarr | 70:99b7a15c09da | 115 | void writeStatusreg(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 116 | |
MatteusCarr | 70:99b7a15c09da | 117 | /// Write Security Reg |
MatteusCarr | 70:99b7a15c09da | 118 | void writeSecurityreg(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 119 | |
MatteusCarr | 70:99b7a15c09da | 120 | /** Page Program |
MatteusCarr | 70:99b7a15c09da | 121 | * |
MatteusCarr | 70:99b7a15c09da | 122 | * @param int addr start address |
MatteusCarr | 70:99b7a15c09da | 123 | * @param uint8_t *data data buffer |
MatteusCarr | 70:99b7a15c09da | 124 | * @param int numData the number of data to be written |
MatteusCarr | 70:99b7a15c09da | 125 | */ |
MatteusCarr | 70:99b7a15c09da | 126 | void programPage(int addr, uint8_t *data, int numData) ; |
MatteusCarr | 70:99b7a15c09da | 127 | |
MatteusCarr | 70:99b7a15c09da | 128 | /** Sector Erase |
MatteusCarr | 70:99b7a15c09da | 129 | * |
MatteusCarr | 70:99b7a15c09da | 130 | * @param int addr specify the sector to be erased |
MatteusCarr | 70:99b7a15c09da | 131 | */ |
MatteusCarr | 70:99b7a15c09da | 132 | void sectorErase(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 133 | |
MatteusCarr | 70:99b7a15c09da | 134 | /** Block Erase |
MatteusCarr | 70:99b7a15c09da | 135 | * |
MatteusCarr | 70:99b7a15c09da | 136 | * @param int addr specify the sector to be erased |
MatteusCarr | 70:99b7a15c09da | 137 | */ |
MatteusCarr | 70:99b7a15c09da | 138 | void blockErase(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 139 | |
MatteusCarr | 70:99b7a15c09da | 140 | /** 32KB Block Erase |
MatteusCarr | 70:99b7a15c09da | 141 | * |
MatteusCarr | 70:99b7a15c09da | 142 | * @param int addr specify the sector to be erased |
MatteusCarr | 70:99b7a15c09da | 143 | */ |
MatteusCarr | 70:99b7a15c09da | 144 | void blockErase32KB(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 145 | |
MatteusCarr | 70:99b7a15c09da | 146 | /** Read Status Register |
MatteusCarr | 70:99b7a15c09da | 147 | * |
MatteusCarr | 70:99b7a15c09da | 148 | * @returns uint8_t status register value |
MatteusCarr | 70:99b7a15c09da | 149 | */ |
MatteusCarr | 70:99b7a15c09da | 150 | uint8_t readStatus(void) ; |
MatteusCarr | 70:99b7a15c09da | 151 | |
MatteusCarr | 70:99b7a15c09da | 152 | /** Read Security Register |
MatteusCarr | 70:99b7a15c09da | 153 | * |
MatteusCarr | 70:99b7a15c09da | 154 | * @returns uint8_t security register value |
MatteusCarr | 70:99b7a15c09da | 155 | */ |
MatteusCarr | 70:99b7a15c09da | 156 | uint8_t readSecurity(void) ; |
MatteusCarr | 70:99b7a15c09da | 157 | |
MatteusCarr | 70:99b7a15c09da | 158 | /** Read Manufacturer and JEDEC Device ID |
MatteusCarr | 70:99b7a15c09da | 159 | * |
MatteusCarr | 70:99b7a15c09da | 160 | * @returns uint32_t Manufacturer ID, Mem Type, Device ID |
MatteusCarr | 70:99b7a15c09da | 161 | */ |
MatteusCarr | 70:99b7a15c09da | 162 | uint32_t readID(void) ; |
MatteusCarr | 70:99b7a15c09da | 163 | |
MatteusCarr | 70:99b7a15c09da | 164 | /** Read Electronic Manufacturer and Device ID |
MatteusCarr | 70:99b7a15c09da | 165 | * |
MatteusCarr | 70:99b7a15c09da | 166 | * @returns uint32_t Manufacturer ID, Device ID |
MatteusCarr | 70:99b7a15c09da | 167 | */ |
MatteusCarr | 70:99b7a15c09da | 168 | uint32_t readREMS(void) ; |
MatteusCarr | 70:99b7a15c09da | 169 | |
MatteusCarr | 70:99b7a15c09da | 170 | /** Read Electronic ID |
MatteusCarr | 70:99b7a15c09da | 171 | * |
MatteusCarr | 70:99b7a15c09da | 172 | * @returns uint8_t Device ID |
MatteusCarr | 70:99b7a15c09da | 173 | */ |
MatteusCarr | 70:99b7a15c09da | 174 | uint8_t readRES(void) ; |
MatteusCarr | 70:99b7a15c09da | 175 | |
MatteusCarr | 70:99b7a15c09da | 176 | /** Read Configuration Register |
MatteusCarr | 70:99b7a15c09da | 177 | * |
MatteusCarr | 70:99b7a15c09da | 178 | * @returns uint32_t configuration register value |
MatteusCarr | 70:99b7a15c09da | 179 | */ |
MatteusCarr | 70:99b7a15c09da | 180 | uint32_t readConfig(void) ; |
MatteusCarr | 70:99b7a15c09da | 181 | uint8_t readSFDP(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 182 | uint8_t readFREAD(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 183 | uint8_t read8(int addr) ; |
MatteusCarr | 70:99b7a15c09da | 184 | void write8(int addr, uint8_t data) ; |
MatteusCarr | 70:99b7a15c09da | 185 | // read sequential n bytes |
MatteusCarr | 70:99b7a15c09da | 186 | void readNBytes(int addr, uint8_t *data, int nBytes); |
MatteusCarr | 70:99b7a15c09da | 187 | private: |
MatteusCarr | 70:99b7a15c09da | 188 | |
MatteusCarr | 70:99b7a15c09da | 189 | } ; |
MatteusCarr | 70:99b7a15c09da | 190 | #endif // _SPI_MX25R_H_ |