Martin Johnson / Colour_Video_Demo

Demo of low res colour vga video for stm32f3 discovery board

Dependencies:   STM32F3-Discovery-minimal

Fork of Space_Invaders_Demo by Martin Johnson

video.c@17:833f1b69e11d, 2019-04-03 (annotated)

Committer:
MartinJohnson
Date:
Wed Apr 03 22:05:56 2019 +0000
Revision:
17:833f1b69e11d
Parent:
16:915db2280bc4 
update library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MartinJohnson 0:404dae88af71 1 /***************************************************************************
MartinJohnson 0:404dae88af71 2 * STM32 VGA demo
MartinJohnson 0:404dae88af71 3 * Copyright (C) 2012 Artekit Italy
MartinJohnson 0:404dae88af71 4 * http://www.artekit.eu
MartinJohnson 14:3035b3271395 5 * Originally Written by Ruben H. Meleca
MartinJohnson 14:3035b3271395 6 * updated for STM32F3 discovery with colour VGA output
MartinJohnson 0:404dae88af71 7
MartinJohnson 0:404dae88af71 8 ### video.c
MartinJohnson 0:404dae88af71 9
MartinJohnson 0:404dae88af71 10 # This program is free software; you can redistribute it and/or modify
MartinJohnson 0:404dae88af71 11 # it under the terms of the GNU General Public License as published by
MartinJohnson 0:404dae88af71 12 # the Free Software Foundation; either version 2 of the License, or
MartinJohnson 0:404dae88af71 13 # (at your option) any later version.
MartinJohnson 0:404dae88af71 14 #
MartinJohnson 0:404dae88af71 15 # This program is distributed in the hope that it will be useful,
MartinJohnson 0:404dae88af71 16 # but WITHOUT ANY WARRANTY; without even the implied warranty of
MartinJohnson 0:404dae88af71 17 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
MartinJohnson 0:404dae88af71 18 # GNU General Public License for more details.
MartinJohnson 0:404dae88af71 19 #
MartinJohnson 0:404dae88af71 20 # You should have received a copy of the GNU General Public License
MartinJohnson 0:404dae88af71 21 # along with this program; if not, write to the Free Software
MartinJohnson 0:404dae88af71 22 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
MartinJohnson 0:404dae88af71 23
MartinJohnson 0:404dae88af71 24 ***************************************************************************/
MartinJohnson 0:404dae88af71 25
MartinJohnson 0:404dae88af71 26 // VGA connector
MartinJohnson 0:404dae88af71 27 // ---------------------
MartinJohnson 0:404dae88af71 28 // \ Ro Go Bo o Xo / X=Gnd
MartinJohnson 4:de45d218ed3c 29 // \ o o o o Xo / H=HSync=PA8 R=Red=PD0
MartinJohnson 4:de45d218ed3c 30 // \ o o Ho Vo o / V=Vsync=PA1 G=Green=PD1
MartinJohnson 4:de45d218ed3c 31 // -------------- B=Blue=PD2
MartinJohnson 14:3035b3271395 32 // 8x2 connector
MartinJohnson 4:de45d218ed3c 33 // R G B o o X X
MartinJohnson 1:1b37c4b989b4 34 // o o o o o H V o
MartinJohnson 1:1b37c4b989b4 35 //
MartinJohnson 0:404dae88af71 36 #include "stm32f30x.h"
MartinJohnson 0:404dae88af71 37 #include "video.h"
MartinJohnson 0:404dae88af71 38
MartinJohnson 3:93e488fbb8a2 39 __attribute__ ((aligned (4))) u8 volatile fba[VID_VSIZE*HTOTAL]; /* Frame buffer */
MartinJohnson 0:404dae88af71 40
MartinJohnson 16:915db2280bc4 41 __attribute__ ((section ("ccmram_data"))) u8 volatile *fb[VID_VSIZE];
MartinJohnson 0:404dae88af71 42
MartinJohnson 0:404dae88af71 43 int fboffset=0;
MartinJohnson 0:404dae88af71 44
MartinJohnson 16:915db2280bc4 45 __attribute__ ((section ("ccmram_data"))) static volatile u16 vline = 0; /* The current line being drawn */
MartinJohnson 16:915db2280bc4 46 __attribute__ ((section ("ccmram_data"))) static volatile u32 vflag = 0; /* When 1, the DMA request can draw on the screen */
MartinJohnson 16:915db2280bc4 47 __attribute__ ((section ("ccmram_data"))) static volatile u32 vdraw = 0; /* Used to increment vline every 3 drawn lines */
MartinJohnson 0:404dae88af71 48
MartinJohnson 3:93e488fbb8a2 49 #define GPIO_MODE_INPUT 0
MartinJohnson 3:93e488fbb8a2 50 #define GPIO_MODE_OUTPUT 1
MartinJohnson 3:93e488fbb8a2 51 #define GPIO_MODE_AF 2
MartinJohnson 3:93e488fbb8a2 52
MartinJohnson 3:93e488fbb8a2 53 #define GPIO_NO_PULL 0
MartinJohnson 3:93e488fbb8a2 54 #define GPIO_PULL_UP 1
MartinJohnson 3:93e488fbb8a2 55 #define GPIO_PULL_DOWN 2
MartinJohnson 3:93e488fbb8a2 56
MartinJohnson 3:93e488fbb8a2 57 #define GPIO_OUTPUT_PUSH_PULL 0
MartinJohnson 3:93e488fbb8a2 58
MartinJohnson 3:93e488fbb8a2 59
MartinJohnson 3:93e488fbb8a2 60 #define GPIO_SPEED_MEDIUM 1
MartinJohnson 3:93e488fbb8a2 61 #define GPIO_SPEED_LOW 0
MartinJohnson 3:93e488fbb8a2 62 #define GPIO_SPEED_HIGH 3
MartinJohnson 3:93e488fbb8a2 63
MartinJohnson 3:93e488fbb8a2 64
MartinJohnson 3:93e488fbb8a2 65 void gpio_set_mode(GPIO_TypeDef *g,int n,int mode) {
MartinJohnson 3:93e488fbb8a2 66 n=n<<1;
MartinJohnson 3:93e488fbb8a2 67 g->MODER = (g->MODER & ~(3<<n)) | (mode<<n);
MartinJohnson 3:93e488fbb8a2 68 }
MartinJohnson 3:93e488fbb8a2 69
MartinJohnson 3:93e488fbb8a2 70 void gpio_set_af(GPIO_TypeDef *g,int n,int af, int otype, int pupd, int speed) {
MartinJohnson 3:93e488fbb8a2 71 int reg=n>>3;
MartinJohnson 3:93e488fbb8a2 72 int pos=(n&7)*4;
MartinJohnson 3:93e488fbb8a2 73 g->AFR[reg] = (g->AFR[reg] & ~(0xf<<pos)) | (af<<pos); // alt func
MartinJohnson 3:93e488fbb8a2 74 pos=(n<<1);
MartinJohnson 3:93e488fbb8a2 75 g->OSPEEDR = (g->OSPEEDR & ~(3<<pos)) | (speed<<pos);
MartinJohnson 3:93e488fbb8a2 76 g->OTYPER = (g->OTYPER & ~(1<<n)) | (otype<<n);
MartinJohnson 3:93e488fbb8a2 77 gpio_set_mode(g,n,GPIO_MODE_AF);
MartinJohnson 3:93e488fbb8a2 78 g->PUPDR = (g->PUPDR & ~(3<<pos)) | (pupd<<pos);
MartinJohnson 3:93e488fbb8a2 79 }
MartinJohnson 3:93e488fbb8a2 80
MartinJohnson 3:93e488fbb8a2 81 void TIMER_Configuration(void) {
MartinJohnson 0:404dae88af71 82 u32 TimerPeriod = 0;
MartinJohnson 0:404dae88af71 83 u16 Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0;
MartinJohnson 0:404dae88af71 84
MartinJohnson 3:93e488fbb8a2 85 gpio_set_af(GPIOA,1,1,GPIO_OUTPUT_PUSH_PULL, GPIO_NO_PULL, GPIO_SPEED_LOW);
MartinJohnson 3:93e488fbb8a2 86 gpio_set_af(GPIOA,8,6,GPIO_OUTPUT_PUSH_PULL, GPIO_NO_PULL, GPIO_SPEED_LOW);
MartinJohnson 0:404dae88af71 87
MartinJohnson 0:404dae88af71 88 /*
MartinJohnson 14:3035b3271395 89 VGA 640x480 @ 60 Hz
MartinJohnson 14:3035b3271395 90 Vertical refresh 31.46875 kHz
MartinJohnson 0:404dae88af71 91 Pixel freq. 36.0 MHz
MartinJohnson 0:404dae88af71 92
MartinJohnson 0:404dae88af71 93 1 system tick @ 72Mhz = 0,0138 us
MartinJohnson 0:404dae88af71 94 */
MartinJohnson 0:404dae88af71 95
MartinJohnson 0:404dae88af71 96 /*
MartinJohnson 0:404dae88af71 97 Horizontal timing
MartinJohnson 0:404dae88af71 98 -----------------
MartinJohnson 0:404dae88af71 99
MartinJohnson 14:3035b3271395 100 Timer 1 period = 31468.53 Hz
MartinJohnson 0:404dae88af71 101
MartinJohnson 0:404dae88af71 102 Horizontal timing info
MartinJohnson 0:404dae88af71 103 ----------------------
MartinJohnson 0:404dae88af71 104
MartinJohnson 14:3035b3271395 105 Dots us ticks
MartinJohnson 14:3035b3271395 106 ----------------------------------------------------
MartinJohnson 14:3035b3271395 107 Visible area 640 25.422045680238 1830
MartinJohnson 14:3035b3271395 108 Front porch 16 0.6355511420059 46
MartinJohnson 14:3035b3271395 109 Sync pulse 96 3.8133068520357 275
MartinJohnson 14:3035b3271395 110 Back porch 48 1.9066534260179 137
MartinJohnson 14:3035b3271395 111 Whole line 800 31.777557100298 2288
MartinJohnson 14:3035b3271395 112 Sync + bp 144 5.7199602780536 412
MartinJohnson 0:404dae88af71 113
MartinJohnson 0:404dae88af71 114 */
MartinJohnson 0:404dae88af71 115
MartinJohnson 14:3035b3271395 116 TimerPeriod = 2288;//2303;
MartinJohnson 14:3035b3271395 117 Channel1Pulse = 275;//274;//274;//277; /* HSYNC */
MartinJohnson 14:3035b3271395 118 Channel3Pulse = 412;//412;//394;
MartinJohnson 0:404dae88af71 119
MartinJohnson 3:93e488fbb8a2 120 TIM1->CR1 &= ~TIM_CR1_CEN;
MartinJohnson 14:3035b3271395 121
MartinJohnson 3:93e488fbb8a2 122 TIM1->PSC=0;
MartinJohnson 3:93e488fbb8a2 123 TIM1->ARR=TimerPeriod;
MartinJohnson 3:93e488fbb8a2 124 TIM1->CNT=0;
MartinJohnson 0:404dae88af71 125
MartinJohnson 14:3035b3271395 126 // disable Capture and Compare
MartinJohnson 14:3035b3271395 127 TIM1->CCER &= ~(TIM_CCER_CC1E);
MartinJohnson 3:93e488fbb8a2 128 // set output compare 1 to PWM mode with preload
MartinJohnson 3:93e488fbb8a2 129 TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC1M | TIM_CCMR1_CC1S)) | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
MartinJohnson 3:93e488fbb8a2 130 TIM1->CCR1=Channel1Pulse;
MartinJohnson 3:93e488fbb8a2 131 // enable Capture and Compare 1
MartinJohnson 14:3035b3271395 132 TIM1->CCER |= TIM_CCER_CC1E | TIM_CCER_CC1P ; // output polarity low
MartinJohnson 3:93e488fbb8a2 133 // main output enable
MartinJohnson 3:93e488fbb8a2 134 TIM1->BDTR |= TIM_BDTR_MOE;
MartinJohnson 3:93e488fbb8a2 135
MartinJohnson 14:3035b3271395 136 TIM1->CR2 = (TIM1->CR2 & ~TIM_CR2_MMS) | (2<<4); // TIM_TRGOSource_Update mode
MartinJohnson 3:93e488fbb8a2 137
MartinJohnson 3:93e488fbb8a2 138 TIM8->CR1 &= ~TIM_CR1_CEN;
MartinJohnson 14:3035b3271395 139 TIM8->CR1 |= TIM_CR1_ARPE | TIM_CR1_URS;
MartinJohnson 5:594c9712697c 140 TIM8->PSC=0;
MartinJohnson 5:594c9712697c 141 TIM8->ARR=8;
MartinJohnson 3:93e488fbb8a2 142 TIM8->CNT=0;
MartinJohnson 3:93e488fbb8a2 143
MartinJohnson 3:93e488fbb8a2 144 TIM8->DIER |= TIM_DIER_UDE;
MartinJohnson 14:3035b3271395 145
MartinJohnson 14:3035b3271395 146 TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 6 | (3<<4); // trigger mode from itr3 (tim3)
MartinJohnson 0:404dae88af71 147
MartinJohnson 14:3035b3271395 148 TIM3->CR1 &= ~TIM_CR1_CEN;
MartinJohnson 14:3035b3271395 149 TIM3->PSC=0;
MartinJohnson 14:3035b3271395 150 TIM3->ARR=Channel3Pulse;
MartinJohnson 14:3035b3271395 151 TIM3->CNT=0;
MartinJohnson 14:3035b3271395 152 TIM3->CR1 |= TIM_CR1_ARPE | TIM_CR1_URS;
MartinJohnson 14:3035b3271395 153 TIM3->CR1 |= TIM_CR1_OPM;
MartinJohnson 14:3035b3271395 154 TIM3->SMCR=TIM3->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 6 ; // trigger mode from itr0 (tim1)
MartinJohnson 14:3035b3271395 155 TIM3->CR2 = (TIM3->CR2 & ~TIM_CR2_MMS) | (2<<4); ///*TIM_CR2_MMS_2 |*/ TIM_CR2_MMS_1 /*| TIM_CR2_MMS_0*/;// TIM_TRGOSource_Update mode
MartinJohnson 14:3035b3271395 156
MartinJohnson 0:404dae88af71 157 /*
MartinJohnson 0:404dae88af71 158 Vertical timing
MartinJohnson 0:404dae88af71 159 ---------------
MartinJohnson 0:404dae88af71 160
MartinJohnson 14:3035b3271395 161 Polarity of vertical sync pulse is negative.
MartinJohnson 0:404dae88af71 162
MartinJohnson 0:404dae88af71 163 Lines
MartinJohnson 0:404dae88af71 164 ------------------------------
MartinJohnson 14:3035b3271395 165 Visible area 480
MartinJohnson 14:3035b3271395 166 Front porch 10
MartinJohnson 0:404dae88af71 167 Sync pulse 2
MartinJohnson 14:3035b3271395 168 Back porch 33
MartinJohnson 14:3035b3271395 169 Whole frame 525
MartinJohnson 0:404dae88af71 170
MartinJohnson 0:404dae88af71 171 */
MartinJohnson 0:404dae88af71 172
MartinJohnson 0:404dae88af71 173 /* VSYNC (TIM2_CH2) and VSYNC_BACKPORCH (TIM2_CH3) */
MartinJohnson 0:404dae88af71 174 /* Channel 2 and 3 Configuration in PWM mode */
MartinJohnson 14:3035b3271395 175 TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// gated slave mode trigger source 0
MartinJohnson 14:3035b3271395 176
MartinJohnson 14:3035b3271395 177
MartinJohnson 12:f819427d0bec 178 TimerPeriod = 525; /* Vertical lines */
MartinJohnson 0:404dae88af71 179 Channel2Pulse = 2; /* Sync pulse */
MartinJohnson 12:f819427d0bec 180 Channel3Pulse = 35; /* Sync pulse + Back porch */
MartinJohnson 0:404dae88af71 181
MartinJohnson 3:93e488fbb8a2 182 TIM2->CR1 &= ~TIM_CR1_CEN;
MartinJohnson 14:3035b3271395 183 TIM2->PSC=0;
MartinJohnson 3:93e488fbb8a2 184 TIM2->ARR=TimerPeriod;
MartinJohnson 3:93e488fbb8a2 185 TIM2->CNT=0;
MartinJohnson 0:404dae88af71 186
MartinJohnson 3:93e488fbb8a2 187 // disable Capture and Compare 2 and 3
MartinJohnson 3:93e488fbb8a2 188 TIM2->CCER &= ~(TIM_CCER_CC2E | TIM_CCER_CC3E);
MartinJohnson 3:93e488fbb8a2 189 // set output compare 1 to PWM mode with preload
MartinJohnson 3:93e488fbb8a2 190 TIM2->CCMR1 = (TIM2->CCMR1 & ~(TIM_CCMR1_OC2M | TIM_CCMR1_CC2S)) | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1;
MartinJohnson 3:93e488fbb8a2 191 TIM2->CCR2=Channel2Pulse;
MartinJohnson 3:93e488fbb8a2 192 TIM2->CCR3=Channel3Pulse;
MartinJohnson 3:93e488fbb8a2 193
MartinJohnson 3:93e488fbb8a2 194 // enable Capture and Compare 2 and 3
MartinJohnson 3:93e488fbb8a2 195 TIM2->CCER |= TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
MartinJohnson 3:93e488fbb8a2 196
MartinJohnson 3:93e488fbb8a2 197 // main output enable
MartinJohnson 3:93e488fbb8a2 198 TIM2->BDTR |= TIM_BDTR_MOE;
MartinJohnson 0:404dae88af71 199
MartinJohnson 5:594c9712697c 200 NVIC->IP[TIM2_IRQn]=32; // Interrupt Priority, lower is higher priority
MartinJohnson 3:93e488fbb8a2 201 NVIC->ISER[TIM2_IRQn >> 0x05] = 1 << (TIM2_IRQn & 0x1F); // Interrupt enable
MartinJohnson 3:93e488fbb8a2 202
MartinJohnson 3:93e488fbb8a2 203 TIM2->DIER |= TIM_DIER_CC3IE;
MartinJohnson 3:93e488fbb8a2 204
MartinJohnson 3:93e488fbb8a2 205 TIM2->CR1 |= TIM_CR1_CEN;
MartinJohnson 3:93e488fbb8a2 206 TIM1->CR1 |= TIM_CR1_CEN;
MartinJohnson 0:404dae88af71 207 }
MartinJohnson 0:404dae88af71 208
MartinJohnson 14:3035b3271395 209 void DMA_Configuration(void) {
MartinJohnson 14:3035b3271395 210 RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN;
MartinJohnson 14:3035b3271395 211 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM8EN ;
MartinJohnson 14:3035b3271395 212 RCC->AHBENR |= RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIODEN;
MartinJohnson 14:3035b3271395 213
MartinJohnson 14:3035b3271395 214 GPIOD->MODER = (GPIOD->MODER&0xffff0000) | 0x5555; // output mode for PD0-7
MartinJohnson 14:3035b3271395 215 GPIOD->PUPDR = (GPIOD->PUPDR & ~0xffff);// | 0xaaaa; // pull down (1010)
MartinJohnson 14:3035b3271395 216 // GPIOD->OTYPER |= 0x8;
MartinJohnson 14:3035b3271395 217 GPIOD->OSPEEDR = (GPIOD->OSPEEDR & ~0xffff) | 0xffff;
MartinJohnson 0:404dae88af71 218
MartinJohnson 3:93e488fbb8a2 219 RCC->AHBENR |= RCC_AHBENR_DMA2EN;
MartinJohnson 3:93e488fbb8a2 220 // direction = peripheral dest, memory inc, peripheral size=halfword, memory size=byte, priority level=high, transmission complete interrupt enabled
MartinJohnson 3:93e488fbb8a2 221 DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;
MartinJohnson 3:93e488fbb8a2 222 // bytes to transfer
MartinJohnson 14:3035b3271395 223 DMA2_Channel1->CNDTR = HTOTAL;
MartinJohnson 3:93e488fbb8a2 224 // peripheral address
MartinJohnson 3:93e488fbb8a2 225 DMA2_Channel1->CPAR =(uint32_t) &GPIOD->ODR;
MartinJohnson 3:93e488fbb8a2 226 // memory address
MartinJohnson 3:93e488fbb8a2 227 DMA2_Channel1->CMAR =(u32) fba+fboffset;
MartinJohnson 3:93e488fbb8a2 228 // configure NVIC
MartinJohnson 3:93e488fbb8a2 229 NVIC->IP[DMA2_Channel1_IRQn]=16; // Interrupt Priority, lower is higher priority
MartinJohnson 3:93e488fbb8a2 230 NVIC->ISER[DMA2_Channel1_IRQn >> 0x05] = 1 << (DMA2_Channel1_IRQn & 0x1F); // Interrupt enable
MartinJohnson 0:404dae88af71 231
MartinJohnson 0:404dae88af71 232 }
MartinJohnson 0:404dae88af71 233
MartinJohnson 0:404dae88af71 234 //*****************************************************************************
MartinJohnson 0:404dae88af71 235 // This irq is generated at the end of the vertical back porch.
MartinJohnson 0:404dae88af71 236 // Sets the 'vflag' variable to 1 (valid vertical frame).
MartinJohnson 0:404dae88af71 237 //*****************************************************************************
MartinJohnson 14:3035b3271395 238
MartinJohnson 14:3035b3271395 239 uint32_t dummy=0;
MartinJohnson 3:93e488fbb8a2 240 __attribute__ ((section ("ccmram"))) void TIM2_IRQHandler(void) {
MartinJohnson 0:404dae88af71 241 vflag = 1;
MartinJohnson 0:404dae88af71 242 TIM2->SR = 0xFFF7; //~TIM_IT_CC3;
MartinJohnson 14:3035b3271395 243 TIM8->CR1 &= ~TIM_CR1_CEN;
MartinJohnson 14:3035b3271395 244 DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE ;
MartinJohnson 14:3035b3271395 245 DMA2_Channel1->CNDTR = HTOTAL;
MartinJohnson 14:3035b3271395 246 TIM8->CNT=0;
MartinJohnson 14:3035b3271395 247 DMA2_Channel1->CPAR=(uint32_t)&dummy;//(uint32_t) &GPIOD->ODR+1;
MartinJohnson 14:3035b3271395 248 GPIOD->ODR=0x00;
MartinJohnson 14:3035b3271395 249 DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;// | DMA_CCR_CIRC;
MartinJohnson 0:404dae88af71 250 }
MartinJohnson 0:404dae88af71 251
MartinJohnson 0:404dae88af71 252 //*****************************************************************************
MartinJohnson 0:404dae88af71 253 // This interrupt is generated at the end of every line.
MartinJohnson 0:404dae88af71 254 // It will increment the line number and set the corresponding line pointer
MartinJohnson 0:404dae88af71 255 // in the DMA register.
MartinJohnson 0:404dae88af71 256 //*****************************************************************************
MartinJohnson 14:3035b3271395 257
MartinJohnson 3:93e488fbb8a2 258 __attribute__ ((section ("ccmram"))) void DMA2_Channel1_IRQHandler(void) {
MartinJohnson 3:93e488fbb8a2 259 DMA2->IFCR = DMA_ISR_TCIF1;
MartinJohnson 5:594c9712697c 260 TIM8->CR1 &= ~TIM_CR1_CEN;
MartinJohnson 5:594c9712697c 261 TIM8->CNT=0;
MartinJohnson 14:3035b3271395 262 DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;
MartinJohnson 3:93e488fbb8a2 263 DMA2_Channel1->CNDTR = HTOTAL;
MartinJohnson 14:3035b3271395 264 DMA2_Channel1->CPAR=(uint32_t) &GPIOD->ODR;;
MartinJohnson 0:404dae88af71 265 vdraw++;
MartinJohnson 14:3035b3271395 266 if (vdraw == 3) {
MartinJohnson 0:404dae88af71 267 vdraw = 0;
MartinJohnson 0:404dae88af71 268 vline++;
MartinJohnson 3:93e488fbb8a2 269 if (vline == VID_VSIZE) {
MartinJohnson 0:404dae88af71 270 vdraw = vline = vflag = 0;
MartinJohnson 14:3035b3271395 271 DMA2_Channel1->CMAR = (u32)fba;
MartinJohnson 14:3035b3271395 272 DMA2_Channel1->CPAR=(uint32_t)&dummy;
MartinJohnson 14:3035b3271395 273 GPIOD->ODR=0x00;
MartinJohnson 0:404dae88af71 274 } else {
MartinJohnson 3:93e488fbb8a2 275 DMA2_Channel1->CMAR += HTOTAL;
MartinJohnson 0:404dae88af71 276 }
MartinJohnson 0:404dae88af71 277 }
MartinJohnson 14:3035b3271395 278 if(vflag)
MartinJohnson 14:3035b3271395 279 DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;
MartinJohnson 14:3035b3271395 280
MartinJohnson 5:594c9712697c 281
MartinJohnson 3:93e488fbb8a2 282 }
MartinJohnson 14:3035b3271395 283
MartinJohnson 3:93e488fbb8a2 284 __attribute__ ((section ("ccmram"))) void vidNextBuffer(void) {
MartinJohnson 14:3035b3271395 285 unsigned *fp=(unsigned *)fba;
MartinJohnson 14:3035b3271395 286 for(int i=0;i<VID_VSIZE*HTOTAL/4;i++)
MartinJohnson 14:3035b3271395 287 *fp++=(*fp>>4)&0xf0f0f0f;
MartinJohnson 0:404dae88af71 288 }
MartinJohnson 0:404dae88af71 289
MartinJohnson 3:93e488fbb8a2 290 __attribute__ ((section ("ccmram"))) void waitForRefresh(void) {
MartinJohnson 16:915db2280bc4 291 while(vflag) __WFI();
MartinJohnson 3:93e488fbb8a2 292 }
MartinJohnson 14:3035b3271395 293
MartinJohnson 3:93e488fbb8a2 294 void vidClearScreen(void) {
MartinJohnson 0:404dae88af71 295 u16 x, y;
MartinJohnson 0:404dae88af71 296
MartinJohnson 3:93e488fbb8a2 297 for (y = 0; y < VID_VSIZE; y++) {
MartinJohnson 3:93e488fbb8a2 298 for (x = 0; x < HTOTAL; x++) {
MartinJohnson 0:404dae88af71 299 fba[y*HTOTAL+x] = 0;
MartinJohnson 0:404dae88af71 300 }
MartinJohnson 0:404dae88af71 301 }
MartinJohnson 0:404dae88af71 302 }
MartinJohnson 0:404dae88af71 303
MartinJohnson 3:93e488fbb8a2 304 void vidDot(int x, int y, int col) {
MartinJohnson 3:93e488fbb8a2 305 fb[y][x]=col;
MartinJohnson 3:93e488fbb8a2 306 }
MartinJohnson 3:93e488fbb8a2 307
MartinJohnson 3:93e488fbb8a2 308 void vidLine(int x, int y, int col) {
MartinJohnson 3:93e488fbb8a2 309 fb[y][x]=col;
MartinJohnson 3:93e488fbb8a2 310 }
MartinJohnson 3:93e488fbb8a2 311
MartinJohnson 3:93e488fbb8a2 312 void vidInit(void) {
MartinJohnson 0:404dae88af71 313 int i;
MartinJohnson 3:93e488fbb8a2 314 DMA_Configuration();
MartinJohnson 0:404dae88af71 315 TIMER_Configuration();
MartinJohnson 3:93e488fbb8a2 316 for(i=0;i<VID_VSIZE;i++)
MartinJohnson 14:3035b3271395 317 fb[i]=fba+i*HTOTAL+2;
MartinJohnson 0:404dae88af71 318 vidClearScreen();
MartinJohnson 0:404dae88af71 319 }
MartinJohnson 0:404dae88af71 320