Sergeh Vartanian / Mbed 2 deprecated End_Device

WSN End Device

Dependencies:   mbed

Fork of I2C_HelloWorld_Mbed by mbed official

EthernetPowerControl.cpp@1:bc4ec3bf209e, 2014-06-16 (annotated)

Committer:
LAvtec818
Date:
Mon Jun 16 18:23:01 2014 +0000
Revision:
1:bc4ec3bf209e
End Device

Who changed what in which revision?

UserRevisionLine numberNew contents of line
LAvtec818 1:bc4ec3bf209e 1 #include "EthernetPowerControl.h"
LAvtec818 1:bc4ec3bf209e 2
LAvtec818 1:bc4ec3bf209e 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
LAvtec818 1:bc4ec3bf209e 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
LAvtec818 1:bc4ec3bf209e 5 unsigned int tout;
LAvtec818 1:bc4ec3bf209e 6 /* Hardware MII Management for LPC176x devices. */
LAvtec818 1:bc4ec3bf209e 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LAvtec818 1:bc4ec3bf209e 8 LPC_EMAC->MWTD = Value;
LAvtec818 1:bc4ec3bf209e 9
LAvtec818 1:bc4ec3bf209e 10 /* Wait utill operation completed */
LAvtec818 1:bc4ec3bf209e 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
LAvtec818 1:bc4ec3bf209e 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
LAvtec818 1:bc4ec3bf209e 13 break;
LAvtec818 1:bc4ec3bf209e 14 }
LAvtec818 1:bc4ec3bf209e 15 }
LAvtec818 1:bc4ec3bf209e 16 }
LAvtec818 1:bc4ec3bf209e 17
LAvtec818 1:bc4ec3bf209e 18 static unsigned short read_PHY (unsigned int PhyReg) {
LAvtec818 1:bc4ec3bf209e 19 /* Read a PHY register 'PhyReg'. */
LAvtec818 1:bc4ec3bf209e 20 unsigned int tout, val;
LAvtec818 1:bc4ec3bf209e 21
LAvtec818 1:bc4ec3bf209e 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LAvtec818 1:bc4ec3bf209e 23 LPC_EMAC->MCMD = MCMD_READ;
LAvtec818 1:bc4ec3bf209e 24
LAvtec818 1:bc4ec3bf209e 25 /* Wait until operation completed */
LAvtec818 1:bc4ec3bf209e 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
LAvtec818 1:bc4ec3bf209e 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
LAvtec818 1:bc4ec3bf209e 28 break;
LAvtec818 1:bc4ec3bf209e 29 }
LAvtec818 1:bc4ec3bf209e 30 }
LAvtec818 1:bc4ec3bf209e 31 LPC_EMAC->MCMD = 0;
LAvtec818 1:bc4ec3bf209e 32 val = LPC_EMAC->MRDD;
LAvtec818 1:bc4ec3bf209e 33
LAvtec818 1:bc4ec3bf209e 34 return (val);
LAvtec818 1:bc4ec3bf209e 35 }
LAvtec818 1:bc4ec3bf209e 36
LAvtec818 1:bc4ec3bf209e 37 void EMAC_Init()
LAvtec818 1:bc4ec3bf209e 38 {
LAvtec818 1:bc4ec3bf209e 39 unsigned int tout,regv;
LAvtec818 1:bc4ec3bf209e 40 /* Power Up the EMAC controller. */
LAvtec818 1:bc4ec3bf209e 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
LAvtec818 1:bc4ec3bf209e 42
LAvtec818 1:bc4ec3bf209e 43 LPC_PINCON->PINSEL2 = 0x50150105;
LAvtec818 1:bc4ec3bf209e 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
LAvtec818 1:bc4ec3bf209e 45 LPC_PINCON->PINSEL3 |= 0x00000005;
LAvtec818 1:bc4ec3bf209e 46
LAvtec818 1:bc4ec3bf209e 47 /* Reset all EMAC internal modules. */
LAvtec818 1:bc4ec3bf209e 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
LAvtec818 1:bc4ec3bf209e 49 MAC1_SIM_RES | MAC1_SOFT_RES;
LAvtec818 1:bc4ec3bf209e 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
LAvtec818 1:bc4ec3bf209e 51
LAvtec818 1:bc4ec3bf209e 52 /* A short delay after reset. */
LAvtec818 1:bc4ec3bf209e 53 for (tout = 100; tout; tout--);
LAvtec818 1:bc4ec3bf209e 54
LAvtec818 1:bc4ec3bf209e 55 /* Initialize MAC control registers. */
LAvtec818 1:bc4ec3bf209e 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
LAvtec818 1:bc4ec3bf209e 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LAvtec818 1:bc4ec3bf209e 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
LAvtec818 1:bc4ec3bf209e 59 LPC_EMAC->CLRT = CLRT_DEF;
LAvtec818 1:bc4ec3bf209e 60 LPC_EMAC->IPGR = IPGR_DEF;
LAvtec818 1:bc4ec3bf209e 61
LAvtec818 1:bc4ec3bf209e 62 /* Enable Reduced MII interface. */
LAvtec818 1:bc4ec3bf209e 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
LAvtec818 1:bc4ec3bf209e 64
LAvtec818 1:bc4ec3bf209e 65 /* Reset Reduced MII Logic. */
LAvtec818 1:bc4ec3bf209e 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
LAvtec818 1:bc4ec3bf209e 67 for (tout = 100; tout; tout--);
LAvtec818 1:bc4ec3bf209e 68 LPC_EMAC->SUPP = 0;
LAvtec818 1:bc4ec3bf209e 69
LAvtec818 1:bc4ec3bf209e 70 /* Put the DP83848C in reset mode */
LAvtec818 1:bc4ec3bf209e 71 write_PHY (PHY_REG_BMCR, 0x8000);
LAvtec818 1:bc4ec3bf209e 72
LAvtec818 1:bc4ec3bf209e 73 /* Wait for hardware reset to end. */
LAvtec818 1:bc4ec3bf209e 74 for (tout = 0; tout < 0x100000; tout++) {
LAvtec818 1:bc4ec3bf209e 75 regv = read_PHY (PHY_REG_BMCR);
LAvtec818 1:bc4ec3bf209e 76 if (!(regv & 0x8000)) {
LAvtec818 1:bc4ec3bf209e 77 /* Reset complete */
LAvtec818 1:bc4ec3bf209e 78 break;
LAvtec818 1:bc4ec3bf209e 79 }
LAvtec818 1:bc4ec3bf209e 80 }
LAvtec818 1:bc4ec3bf209e 81 }
LAvtec818 1:bc4ec3bf209e 82
LAvtec818 1:bc4ec3bf209e 83
LAvtec818 1:bc4ec3bf209e 84 void PHY_PowerDown()
LAvtec818 1:bc4ec3bf209e 85 {
LAvtec818 1:bc4ec3bf209e 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:bc4ec3bf209e 87 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:bc4ec3bf209e 88
LAvtec818 1:bc4ec3bf209e 89 unsigned int regv;
LAvtec818 1:bc4ec3bf209e 90 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:bc4ec3bf209e 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
LAvtec818 1:bc4ec3bf209e 92 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:bc4ec3bf209e 93
LAvtec818 1:bc4ec3bf209e 94 //shouldn't need the EMAC now.
LAvtec818 1:bc4ec3bf209e 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
LAvtec818 1:bc4ec3bf209e 96
LAvtec818 1:bc4ec3bf209e 97 //and turn off the PHY OSC
LAvtec818 1:bc4ec3bf209e 98 LPC_GPIO1->FIODIR |= 0x8000000;
LAvtec818 1:bc4ec3bf209e 99 LPC_GPIO1->FIOCLR = 0x8000000;
LAvtec818 1:bc4ec3bf209e 100 }
LAvtec818 1:bc4ec3bf209e 101
LAvtec818 1:bc4ec3bf209e 102 void PHY_PowerUp()
LAvtec818 1:bc4ec3bf209e 103 {
LAvtec818 1:bc4ec3bf209e 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:bc4ec3bf209e 105 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:bc4ec3bf209e 106
LAvtec818 1:bc4ec3bf209e 107 LPC_GPIO1->FIODIR |= 0x8000000;
LAvtec818 1:bc4ec3bf209e 108 LPC_GPIO1->FIOSET = 0x8000000;
LAvtec818 1:bc4ec3bf209e 109
LAvtec818 1:bc4ec3bf209e 110 //wait for osc to be stable
LAvtec818 1:bc4ec3bf209e 111 wait_ms(200);
LAvtec818 1:bc4ec3bf209e 112
LAvtec818 1:bc4ec3bf209e 113 unsigned int regv;
LAvtec818 1:bc4ec3bf209e 114 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:bc4ec3bf209e 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
LAvtec818 1:bc4ec3bf209e 116 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:bc4ec3bf209e 117 }
LAvtec818 1:bc4ec3bf209e 118
LAvtec818 1:bc4ec3bf209e 119 void PHY_EnergyDetect_Enable()
LAvtec818 1:bc4ec3bf209e 120 {
LAvtec818 1:bc4ec3bf209e 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:bc4ec3bf209e 122 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:bc4ec3bf209e 123
LAvtec818 1:bc4ec3bf209e 124 unsigned int regv;
LAvtec818 1:bc4ec3bf209e 125 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:bc4ec3bf209e 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
LAvtec818 1:bc4ec3bf209e 127 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:bc4ec3bf209e 128 }
LAvtec818 1:bc4ec3bf209e 129
LAvtec818 1:bc4ec3bf209e 130 void PHY_EnergyDetect_Disable()
LAvtec818 1:bc4ec3bf209e 131 {
LAvtec818 1:bc4ec3bf209e 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:bc4ec3bf209e 133 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:bc4ec3bf209e 134 unsigned int regv;
LAvtec818 1:bc4ec3bf209e 135 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:bc4ec3bf209e 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
LAvtec818 1:bc4ec3bf209e 137 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:bc4ec3bf209e 138 }