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PowerControl.h@1:f9ead8ebc68b, 2014-06-16 (annotated)

Committer:
LAvtec818
Date:
Mon Jun 16 18:17:19 2014 +0000
Revision:
1:f9ead8ebc68b
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LAvtec818 1:f9ead8ebc68b 1 /* mbed PowerControl Library
LAvtec818 1:f9ead8ebc68b 2 * Copyright (c) 2010 Michael Wei
LAvtec818 1:f9ead8ebc68b 3 */
LAvtec818 1:f9ead8ebc68b 4
LAvtec818 1:f9ead8ebc68b 5 #ifndef MBED_POWERCONTROL_H
LAvtec818 1:f9ead8ebc68b 6 #define MBED_POWERCONTROL_H
LAvtec818 1:f9ead8ebc68b 7
LAvtec818 1:f9ead8ebc68b 8 //shouldn't have to include, but fixes weird problems with defines
LAvtec818 1:f9ead8ebc68b 9 #include "LPC1768/LPC17xx.h"
LAvtec818 1:f9ead8ebc68b 10
LAvtec818 1:f9ead8ebc68b 11 //System Control Register
LAvtec818 1:f9ead8ebc68b 12 // bit 0: Reserved
LAvtec818 1:f9ead8ebc68b 13 // bit 1: Sleep on Exit
LAvtec818 1:f9ead8ebc68b 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
LAvtec818 1:f9ead8ebc68b 15 // bit 2: Deep Sleep
LAvtec818 1:f9ead8ebc68b 16 #define LPC1768_SCR_SLEEPDEEP 0x4
LAvtec818 1:f9ead8ebc68b 17 // bit 3: Resereved
LAvtec818 1:f9ead8ebc68b 18 // bit 4: Send on Pending
LAvtec818 1:f9ead8ebc68b 19 #define LPC1768_SCR_SEVONPEND 0x10
LAvtec818 1:f9ead8ebc68b 20 // bit 5-31: Reserved
LAvtec818 1:f9ead8ebc68b 21
LAvtec818 1:f9ead8ebc68b 22 //Power Control Register
LAvtec818 1:f9ead8ebc68b 23 // bit 0: Power mode control bit 0 (power-down mode)
LAvtec818 1:f9ead8ebc68b 24 #define LPC1768_PCON_PM0 0x1
LAvtec818 1:f9ead8ebc68b 25 // bit 1: Power mode control bit 1 (deep power-down mode)
LAvtec818 1:f9ead8ebc68b 26 #define LPC1768_PCON_PM1 0x2
LAvtec818 1:f9ead8ebc68b 27 // bit 2: Brown-out reduced power mode
LAvtec818 1:f9ead8ebc68b 28 #define LPC1768_PCON_BODRPM 0x4
LAvtec818 1:f9ead8ebc68b 29 // bit 3: Brown-out global disable
LAvtec818 1:f9ead8ebc68b 30 #define LPC1768_PCON_BOGD 0x8
LAvtec818 1:f9ead8ebc68b 31 // bit 4: Brown-out reset disable
LAvtec818 1:f9ead8ebc68b 32 #define LPC1768_PCON_BORD 0x10
LAvtec818 1:f9ead8ebc68b 33 // bit 5-7 : Reserved
LAvtec818 1:f9ead8ebc68b 34 // bit 8: Sleep Mode Entry Flag
LAvtec818 1:f9ead8ebc68b 35 #define LPC1768_PCON_SMFLAG 0x100
LAvtec818 1:f9ead8ebc68b 36 // bit 9: Deep Sleep Entry Flag
LAvtec818 1:f9ead8ebc68b 37 #define LPC1768_PCON_DSFLAG 0x200
LAvtec818 1:f9ead8ebc68b 38 // bit 10: Power Down Entry Flag
LAvtec818 1:f9ead8ebc68b 39 #define LPC1768_PCON_PDFLAG 0x400
LAvtec818 1:f9ead8ebc68b 40 // bit 11: Deep Power Down Entry Flag
LAvtec818 1:f9ead8ebc68b 41 #define LPC1768_PCON_DPDFLAG 0x800
LAvtec818 1:f9ead8ebc68b 42 // bit 12-31: Reserved
LAvtec818 1:f9ead8ebc68b 43
LAvtec818 1:f9ead8ebc68b 44 //"Sleep Mode" (WFI).
LAvtec818 1:f9ead8ebc68b 45 inline void Sleep(void)
LAvtec818 1:f9ead8ebc68b 46 {
LAvtec818 1:f9ead8ebc68b 47 __WFI();
LAvtec818 1:f9ead8ebc68b 48 }
LAvtec818 1:f9ead8ebc68b 49
LAvtec818 1:f9ead8ebc68b 50 //"Deep Sleep" Mode
LAvtec818 1:f9ead8ebc68b 51 inline void DeepSleep(void)
LAvtec818 1:f9ead8ebc68b 52 {
LAvtec818 1:f9ead8ebc68b 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
LAvtec818 1:f9ead8ebc68b 54 __WFI();
LAvtec818 1:f9ead8ebc68b 55 }
LAvtec818 1:f9ead8ebc68b 56
LAvtec818 1:f9ead8ebc68b 57 //"Power-Down" Mode
LAvtec818 1:f9ead8ebc68b 58 inline void PowerDown(void)
LAvtec818 1:f9ead8ebc68b 59 {
LAvtec818 1:f9ead8ebc68b 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
LAvtec818 1:f9ead8ebc68b 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
LAvtec818 1:f9ead8ebc68b 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
LAvtec818 1:f9ead8ebc68b 63 __WFI();
LAvtec818 1:f9ead8ebc68b 64 //reset back to normal
LAvtec818 1:f9ead8ebc68b 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
LAvtec818 1:f9ead8ebc68b 66 }
LAvtec818 1:f9ead8ebc68b 67
LAvtec818 1:f9ead8ebc68b 68 //"Deep Power-Down" Mode
LAvtec818 1:f9ead8ebc68b 69 inline void DeepPowerDown(void)
LAvtec818 1:f9ead8ebc68b 70 {
LAvtec818 1:f9ead8ebc68b 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
LAvtec818 1:f9ead8ebc68b 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
LAvtec818 1:f9ead8ebc68b 73 __WFI();
LAvtec818 1:f9ead8ebc68b 74 //reset back to normal
LAvtec818 1:f9ead8ebc68b 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
LAvtec818 1:f9ead8ebc68b 76 }
LAvtec818 1:f9ead8ebc68b 77
LAvtec818 1:f9ead8ebc68b 78 //shut down BOD during power-down/deep sleep
LAvtec818 1:f9ead8ebc68b 79 inline void BrownOut_ReducedPowerMode_Enable(void)
LAvtec818 1:f9ead8ebc68b 80 {
LAvtec818 1:f9ead8ebc68b 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
LAvtec818 1:f9ead8ebc68b 82 }
LAvtec818 1:f9ead8ebc68b 83
LAvtec818 1:f9ead8ebc68b 84 //turn on BOD during power-down/deep sleep
LAvtec818 1:f9ead8ebc68b 85 inline void BrownOut_ReducedPowerMode_Disable(void)
LAvtec818 1:f9ead8ebc68b 86 {
LAvtec818 1:f9ead8ebc68b 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
LAvtec818 1:f9ead8ebc68b 88 }
LAvtec818 1:f9ead8ebc68b 89
LAvtec818 1:f9ead8ebc68b 90 //turn off brown out circutry
LAvtec818 1:f9ead8ebc68b 91 inline void BrownOut_Global_Disable(void)
LAvtec818 1:f9ead8ebc68b 92 {
LAvtec818 1:f9ead8ebc68b 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
LAvtec818 1:f9ead8ebc68b 94 }
LAvtec818 1:f9ead8ebc68b 95
LAvtec818 1:f9ead8ebc68b 96 //turn on brown out circutry
LAvtec818 1:f9ead8ebc68b 97 inline void BrownOut_Global_Enable(void)
LAvtec818 1:f9ead8ebc68b 98 {
LAvtec818 1:f9ead8ebc68b 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
LAvtec818 1:f9ead8ebc68b 100 }
LAvtec818 1:f9ead8ebc68b 101
LAvtec818 1:f9ead8ebc68b 102 //turn off brown out reset circutry
LAvtec818 1:f9ead8ebc68b 103 inline void BrownOut_Reset_Disable(void)
LAvtec818 1:f9ead8ebc68b 104 {
LAvtec818 1:f9ead8ebc68b 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
LAvtec818 1:f9ead8ebc68b 106 }
LAvtec818 1:f9ead8ebc68b 107
LAvtec818 1:f9ead8ebc68b 108 //turn on brown outreset circutry
LAvtec818 1:f9ead8ebc68b 109 inline void BrownOut_Reset_Enable(void)
LAvtec818 1:f9ead8ebc68b 110 {
LAvtec818 1:f9ead8ebc68b 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
LAvtec818 1:f9ead8ebc68b 112 }
LAvtec818 1:f9ead8ebc68b 113 //Peripheral Control Register
LAvtec818 1:f9ead8ebc68b 114 // bit 0: Reserved
LAvtec818 1:f9ead8ebc68b 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
LAvtec818 1:f9ead8ebc68b 116 #define LPC1768_PCONP_PCTIM0 0x2
LAvtec818 1:f9ead8ebc68b 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
LAvtec818 1:f9ead8ebc68b 118 #define LPC1768_PCONP_PCTIM1 0x4
LAvtec818 1:f9ead8ebc68b 119 // bit 3: PCUART0: UART 0 power/clock enable
LAvtec818 1:f9ead8ebc68b 120 #define LPC1768_PCONP_PCUART0 0x8
LAvtec818 1:f9ead8ebc68b 121 // bit 4: PCUART1: UART 1 power/clock enable
LAvtec818 1:f9ead8ebc68b 122 #define LPC1768_PCONP_PCUART1 0x10
LAvtec818 1:f9ead8ebc68b 123 // bit 5: Reserved
LAvtec818 1:f9ead8ebc68b 124 // bit 6: PCPWM1: PWM 1 power/clock enable
LAvtec818 1:f9ead8ebc68b 125 #define LPC1768_PCONP_PCPWM1 0x40
LAvtec818 1:f9ead8ebc68b 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
LAvtec818 1:f9ead8ebc68b 127 #define LPC1768_PCONP_PCI2C0 0x80
LAvtec818 1:f9ead8ebc68b 128 // bit 8: PCSPI: SPI interface power/clock enable
LAvtec818 1:f9ead8ebc68b 129 #define LPC1768_PCONP_PCSPI 0x100
LAvtec818 1:f9ead8ebc68b 130 // bit 9: PCRTC: RTC power/clock enable
LAvtec818 1:f9ead8ebc68b 131 #define LPC1768_PCONP_PCRTC 0x200
LAvtec818 1:f9ead8ebc68b 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
LAvtec818 1:f9ead8ebc68b 133 #define LPC1768_PCONP_PCSSP1 0x400
LAvtec818 1:f9ead8ebc68b 134 // bit 11: Reserved
LAvtec818 1:f9ead8ebc68b 135 // bit 12: PCADC: A/D converter power/clock enable
LAvtec818 1:f9ead8ebc68b 136 #define LPC1768_PCONP_PCADC 0x1000
LAvtec818 1:f9ead8ebc68b 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
LAvtec818 1:f9ead8ebc68b 138 #define LPC1768_PCONP_PCCAN1 0x2000
LAvtec818 1:f9ead8ebc68b 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
LAvtec818 1:f9ead8ebc68b 140 #define LPC1768_PCONP_PCCAN2 0x4000
LAvtec818 1:f9ead8ebc68b 141 // bit 15: PCGPIO: GPIOs power/clock enable
LAvtec818 1:f9ead8ebc68b 142 #define LPC1768_PCONP_PCGPIO 0x8000
LAvtec818 1:f9ead8ebc68b 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
LAvtec818 1:f9ead8ebc68b 144 #define LPC1768_PCONP_PCRIT 0x10000
LAvtec818 1:f9ead8ebc68b 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
LAvtec818 1:f9ead8ebc68b 146 #define LPC1768_PCONP_PCMCPWM 0x20000
LAvtec818 1:f9ead8ebc68b 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
LAvtec818 1:f9ead8ebc68b 148 #define LPC1768_PCONP_PCQEI 0x40000
LAvtec818 1:f9ead8ebc68b 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
LAvtec818 1:f9ead8ebc68b 150 #define LPC1768_PCONP_PCI2C1 0x80000
LAvtec818 1:f9ead8ebc68b 151 // bit 20: Reserved
LAvtec818 1:f9ead8ebc68b 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
LAvtec818 1:f9ead8ebc68b 153 #define LPC1768_PCONP_PCSSP0 0x200000
LAvtec818 1:f9ead8ebc68b 154 // bit 22: PCTIM2: Timer 2 power/clock enable
LAvtec818 1:f9ead8ebc68b 155 #define LPC1768_PCONP_PCTIM2 0x400000
LAvtec818 1:f9ead8ebc68b 156 // bit 23: PCTIM3: Timer 3 power/clock enable
LAvtec818 1:f9ead8ebc68b 157 #define LPC1768_PCONP_PCQTIM3 0x800000
LAvtec818 1:f9ead8ebc68b 158 // bit 24: PCUART2: UART 2 power/clock enable
LAvtec818 1:f9ead8ebc68b 159 #define LPC1768_PCONP_PCUART2 0x1000000
LAvtec818 1:f9ead8ebc68b 160 // bit 25: PCUART3: UART 3 power/clock enable
LAvtec818 1:f9ead8ebc68b 161 #define LPC1768_PCONP_PCUART3 0x2000000
LAvtec818 1:f9ead8ebc68b 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
LAvtec818 1:f9ead8ebc68b 163 #define LPC1768_PCONP_PCI2C2 0x4000000
LAvtec818 1:f9ead8ebc68b 164 // bit 27: PCI2S: I2S interface power/clock enable
LAvtec818 1:f9ead8ebc68b 165 #define LPC1768_PCONP_PCI2S 0x8000000
LAvtec818 1:f9ead8ebc68b 166 // bit 28: Reserved
LAvtec818 1:f9ead8ebc68b 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
LAvtec818 1:f9ead8ebc68b 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
LAvtec818 1:f9ead8ebc68b 169 // bit 30: PCENET: Ethernet block power/clock enable
LAvtec818 1:f9ead8ebc68b 170 #define LPC1768_PCONP_PCENET 0x40000000
LAvtec818 1:f9ead8ebc68b 171 // bit 31: PCUSB: USB interface power/clock enable
LAvtec818 1:f9ead8ebc68b 172 #define LPC1768_PCONP_PCUSB 0x80000000
LAvtec818 1:f9ead8ebc68b 173
LAvtec818 1:f9ead8ebc68b 174 //Powers Up specified Peripheral(s)
LAvtec818 1:f9ead8ebc68b 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
LAvtec818 1:f9ead8ebc68b 176 {
LAvtec818 1:f9ead8ebc68b 177 return LPC_SC->PCONP |= bitMask;
LAvtec818 1:f9ead8ebc68b 178 }
LAvtec818 1:f9ead8ebc68b 179
LAvtec818 1:f9ead8ebc68b 180 //Powers Down specified Peripheral(s)
LAvtec818 1:f9ead8ebc68b 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
LAvtec818 1:f9ead8ebc68b 182 {
LAvtec818 1:f9ead8ebc68b 183 return LPC_SC->PCONP &= ~bitMask;
LAvtec818 1:f9ead8ebc68b 184 }
LAvtec818 1:f9ead8ebc68b 185
LAvtec818 1:f9ead8ebc68b 186 //returns if the peripheral is on or off
LAvtec818 1:f9ead8ebc68b 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
LAvtec818 1:f9ead8ebc68b 188 {
LAvtec818 1:f9ead8ebc68b 189 return (LPC_SC->PCONP & peripheral) ? true : false;
LAvtec818 1:f9ead8ebc68b 190 }
LAvtec818 1:f9ead8ebc68b 191
LAvtec818 1:f9ead8ebc68b 192 #endif