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EthernetPowerControl.cpp@1:f9ead8ebc68b, 2014-06-16 (annotated)

Committer:
LAvtec818
Date:
Mon Jun 16 18:17:19 2014 +0000
Revision:
1:f9ead8ebc68b
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UserRevisionLine numberNew contents of line
LAvtec818 1:f9ead8ebc68b 1 #include "EthernetPowerControl.h"
LAvtec818 1:f9ead8ebc68b 2
LAvtec818 1:f9ead8ebc68b 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
LAvtec818 1:f9ead8ebc68b 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
LAvtec818 1:f9ead8ebc68b 5 unsigned int tout;
LAvtec818 1:f9ead8ebc68b 6 /* Hardware MII Management for LPC176x devices. */
LAvtec818 1:f9ead8ebc68b 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LAvtec818 1:f9ead8ebc68b 8 LPC_EMAC->MWTD = Value;
LAvtec818 1:f9ead8ebc68b 9
LAvtec818 1:f9ead8ebc68b 10 /* Wait utill operation completed */
LAvtec818 1:f9ead8ebc68b 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
LAvtec818 1:f9ead8ebc68b 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
LAvtec818 1:f9ead8ebc68b 13 break;
LAvtec818 1:f9ead8ebc68b 14 }
LAvtec818 1:f9ead8ebc68b 15 }
LAvtec818 1:f9ead8ebc68b 16 }
LAvtec818 1:f9ead8ebc68b 17
LAvtec818 1:f9ead8ebc68b 18 static unsigned short read_PHY (unsigned int PhyReg) {
LAvtec818 1:f9ead8ebc68b 19 /* Read a PHY register 'PhyReg'. */
LAvtec818 1:f9ead8ebc68b 20 unsigned int tout, val;
LAvtec818 1:f9ead8ebc68b 21
LAvtec818 1:f9ead8ebc68b 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LAvtec818 1:f9ead8ebc68b 23 LPC_EMAC->MCMD = MCMD_READ;
LAvtec818 1:f9ead8ebc68b 24
LAvtec818 1:f9ead8ebc68b 25 /* Wait until operation completed */
LAvtec818 1:f9ead8ebc68b 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
LAvtec818 1:f9ead8ebc68b 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
LAvtec818 1:f9ead8ebc68b 28 break;
LAvtec818 1:f9ead8ebc68b 29 }
LAvtec818 1:f9ead8ebc68b 30 }
LAvtec818 1:f9ead8ebc68b 31 LPC_EMAC->MCMD = 0;
LAvtec818 1:f9ead8ebc68b 32 val = LPC_EMAC->MRDD;
LAvtec818 1:f9ead8ebc68b 33
LAvtec818 1:f9ead8ebc68b 34 return (val);
LAvtec818 1:f9ead8ebc68b 35 }
LAvtec818 1:f9ead8ebc68b 36
LAvtec818 1:f9ead8ebc68b 37 void EMAC_Init()
LAvtec818 1:f9ead8ebc68b 38 {
LAvtec818 1:f9ead8ebc68b 39 unsigned int tout,regv;
LAvtec818 1:f9ead8ebc68b 40 /* Power Up the EMAC controller. */
LAvtec818 1:f9ead8ebc68b 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
LAvtec818 1:f9ead8ebc68b 42
LAvtec818 1:f9ead8ebc68b 43 LPC_PINCON->PINSEL2 = 0x50150105;
LAvtec818 1:f9ead8ebc68b 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
LAvtec818 1:f9ead8ebc68b 45 LPC_PINCON->PINSEL3 |= 0x00000005;
LAvtec818 1:f9ead8ebc68b 46
LAvtec818 1:f9ead8ebc68b 47 /* Reset all EMAC internal modules. */
LAvtec818 1:f9ead8ebc68b 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
LAvtec818 1:f9ead8ebc68b 49 MAC1_SIM_RES | MAC1_SOFT_RES;
LAvtec818 1:f9ead8ebc68b 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
LAvtec818 1:f9ead8ebc68b 51
LAvtec818 1:f9ead8ebc68b 52 /* A short delay after reset. */
LAvtec818 1:f9ead8ebc68b 53 for (tout = 100; tout; tout--);
LAvtec818 1:f9ead8ebc68b 54
LAvtec818 1:f9ead8ebc68b 55 /* Initialize MAC control registers. */
LAvtec818 1:f9ead8ebc68b 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
LAvtec818 1:f9ead8ebc68b 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LAvtec818 1:f9ead8ebc68b 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
LAvtec818 1:f9ead8ebc68b 59 LPC_EMAC->CLRT = CLRT_DEF;
LAvtec818 1:f9ead8ebc68b 60 LPC_EMAC->IPGR = IPGR_DEF;
LAvtec818 1:f9ead8ebc68b 61
LAvtec818 1:f9ead8ebc68b 62 /* Enable Reduced MII interface. */
LAvtec818 1:f9ead8ebc68b 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
LAvtec818 1:f9ead8ebc68b 64
LAvtec818 1:f9ead8ebc68b 65 /* Reset Reduced MII Logic. */
LAvtec818 1:f9ead8ebc68b 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
LAvtec818 1:f9ead8ebc68b 67 for (tout = 100; tout; tout--);
LAvtec818 1:f9ead8ebc68b 68 LPC_EMAC->SUPP = 0;
LAvtec818 1:f9ead8ebc68b 69
LAvtec818 1:f9ead8ebc68b 70 /* Put the DP83848C in reset mode */
LAvtec818 1:f9ead8ebc68b 71 write_PHY (PHY_REG_BMCR, 0x8000);
LAvtec818 1:f9ead8ebc68b 72
LAvtec818 1:f9ead8ebc68b 73 /* Wait for hardware reset to end. */
LAvtec818 1:f9ead8ebc68b 74 for (tout = 0; tout < 0x100000; tout++) {
LAvtec818 1:f9ead8ebc68b 75 regv = read_PHY (PHY_REG_BMCR);
LAvtec818 1:f9ead8ebc68b 76 if (!(regv & 0x8000)) {
LAvtec818 1:f9ead8ebc68b 77 /* Reset complete */
LAvtec818 1:f9ead8ebc68b 78 break;
LAvtec818 1:f9ead8ebc68b 79 }
LAvtec818 1:f9ead8ebc68b 80 }
LAvtec818 1:f9ead8ebc68b 81 }
LAvtec818 1:f9ead8ebc68b 82
LAvtec818 1:f9ead8ebc68b 83
LAvtec818 1:f9ead8ebc68b 84 void PHY_PowerDown()
LAvtec818 1:f9ead8ebc68b 85 {
LAvtec818 1:f9ead8ebc68b 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:f9ead8ebc68b 87 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:f9ead8ebc68b 88
LAvtec818 1:f9ead8ebc68b 89 unsigned int regv;
LAvtec818 1:f9ead8ebc68b 90 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:f9ead8ebc68b 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
LAvtec818 1:f9ead8ebc68b 92 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:f9ead8ebc68b 93
LAvtec818 1:f9ead8ebc68b 94 //shouldn't need the EMAC now.
LAvtec818 1:f9ead8ebc68b 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
LAvtec818 1:f9ead8ebc68b 96
LAvtec818 1:f9ead8ebc68b 97 //and turn off the PHY OSC
LAvtec818 1:f9ead8ebc68b 98 LPC_GPIO1->FIODIR |= 0x8000000;
LAvtec818 1:f9ead8ebc68b 99 LPC_GPIO1->FIOCLR = 0x8000000;
LAvtec818 1:f9ead8ebc68b 100 }
LAvtec818 1:f9ead8ebc68b 101
LAvtec818 1:f9ead8ebc68b 102 void PHY_PowerUp()
LAvtec818 1:f9ead8ebc68b 103 {
LAvtec818 1:f9ead8ebc68b 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:f9ead8ebc68b 105 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:f9ead8ebc68b 106
LAvtec818 1:f9ead8ebc68b 107 LPC_GPIO1->FIODIR |= 0x8000000;
LAvtec818 1:f9ead8ebc68b 108 LPC_GPIO1->FIOSET = 0x8000000;
LAvtec818 1:f9ead8ebc68b 109
LAvtec818 1:f9ead8ebc68b 110 //wait for osc to be stable
LAvtec818 1:f9ead8ebc68b 111 wait_ms(200);
LAvtec818 1:f9ead8ebc68b 112
LAvtec818 1:f9ead8ebc68b 113 unsigned int regv;
LAvtec818 1:f9ead8ebc68b 114 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:f9ead8ebc68b 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
LAvtec818 1:f9ead8ebc68b 116 regv = read_PHY(PHY_REG_BMCR);
LAvtec818 1:f9ead8ebc68b 117 }
LAvtec818 1:f9ead8ebc68b 118
LAvtec818 1:f9ead8ebc68b 119 void PHY_EnergyDetect_Enable()
LAvtec818 1:f9ead8ebc68b 120 {
LAvtec818 1:f9ead8ebc68b 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:f9ead8ebc68b 122 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:f9ead8ebc68b 123
LAvtec818 1:f9ead8ebc68b 124 unsigned int regv;
LAvtec818 1:f9ead8ebc68b 125 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:f9ead8ebc68b 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
LAvtec818 1:f9ead8ebc68b 127 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:f9ead8ebc68b 128 }
LAvtec818 1:f9ead8ebc68b 129
LAvtec818 1:f9ead8ebc68b 130 void PHY_EnergyDetect_Disable()
LAvtec818 1:f9ead8ebc68b 131 {
LAvtec818 1:f9ead8ebc68b 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
LAvtec818 1:f9ead8ebc68b 133 EMAC_Init(); //init EMAC if it is not already init'd
LAvtec818 1:f9ead8ebc68b 134 unsigned int regv;
LAvtec818 1:f9ead8ebc68b 135 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:f9ead8ebc68b 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
LAvtec818 1:f9ead8ebc68b 137 regv = read_PHY(PHY_REG_EDCR);
LAvtec818 1:f9ead8ebc68b 138 }