Dmitry Kovalev / Mbed 2 deprecated LG2

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Dependencies:   mbed

Fork of LG by igor Apu

system_LPC17xx.c@219:2d3475d0dd1b, 2017-09-27 (annotated)

Committer:
Kovalev_D
Date:
Wed Sep 27 13:09:24 2017 +0000
Revision:
219:2d3475d0dd1b
Parent:
214:4c70e452c491 
hnjtfgyy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 2:2d0b80ed9216 1 /**************************************************************************//**
igor_v 2:2d0b80ed9216 2 * @file system_LPC17xx.c
igor_v 2:2d0b80ed9216 3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
igor_v 2:2d0b80ed9216 4 * for the NXP LPC17xx Device Series
igor_v 2:2d0b80ed9216 5 * @version V1.03
igor_v 2:2d0b80ed9216 6 * @date 07. October 2009
igor_v 2:2d0b80ed9216 7 *
igor_v 2:2d0b80ed9216 8 * @note
igor_v 2:2d0b80ed9216 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
igor_v 2:2d0b80ed9216 10 *
igor_v 2:2d0b80ed9216 11 * @par
Kovalev_D 135:c1e30e0e8949 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Kovalev_D 135:c1e30e0e8949 13 * processor based microcontrollers. This file can be freely distributed
Kovalev_D 135:c1e30e0e8949 14 * within development tools that are supporting such ARM based processors.
igor_v 2:2d0b80ed9216 15 *
igor_v 2:2d0b80ed9216 16 * @par
igor_v 2:2d0b80ed9216 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
igor_v 2:2d0b80ed9216 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
igor_v 2:2d0b80ed9216 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
igor_v 2:2d0b80ed9216 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
igor_v 2:2d0b80ed9216 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
igor_v 2:2d0b80ed9216 22 *
igor_v 2:2d0b80ed9216 23 ******************************************************************************/
igor_v 2:2d0b80ed9216 24
igor_v 2:2d0b80ed9216 25
igor_v 2:2d0b80ed9216 26 #include <stdint.h>
igor_v 2:2d0b80ed9216 27 #include "LPC17xx.h"
igor_v 2:2d0b80ed9216 28
igor_v 2:2d0b80ed9216 29 /*
igor_v 2:2d0b80ed9216 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
igor_v 2:2d0b80ed9216 31 */
igor_v 2:2d0b80ed9216 32
igor_v 2:2d0b80ed9216 33 /*--------------------- Clock Configuration ----------------------------------
igor_v 2:2d0b80ed9216 34 //
igor_v 2:2d0b80ed9216 35 // <e> Clock Configuration
igor_v 2:2d0b80ed9216 36 // <h> System Controls and Status Register (SCS)
igor_v 2:2d0b80ed9216 37 // <o1.4> OSCRANGE: Main Oscillator Range Select
igor_v 2:2d0b80ed9216 38 // <0=> 1 MHz to 20 MHz
igor_v 2:2d0b80ed9216 39 // <1=> 15 MHz to 24 MHz
igor_v 2:2d0b80ed9216 40 // <e1.5> OSCEN: Main Oscillator Enable
igor_v 2:2d0b80ed9216 41 // </e>
igor_v 2:2d0b80ed9216 42 // </h>
igor_v 2:2d0b80ed9216 43 //
igor_v 2:2d0b80ed9216 44 // <h> Clock Source Select Register (CLKSRCSEL)
igor_v 2:2d0b80ed9216 45 // <o2.0..1> CLKSRC: PLL Clock Source Selection
igor_v 2:2d0b80ed9216 46 // <0=> Internal RC oscillator
igor_v 2:2d0b80ed9216 47 // <1=> Main oscillator
igor_v 2:2d0b80ed9216 48 // <2=> RTC oscillator
igor_v 2:2d0b80ed9216 49 // </h>
igor_v 2:2d0b80ed9216 50 //
igor_v 2:2d0b80ed9216 51 // <e3> PLL0 Configuration (Main PLL)
igor_v 2:2d0b80ed9216 52 // <h> PLL0 Configuration Register (PLL0CFG)
igor_v 2:2d0b80ed9216 53 // <i> F_cco0 = (2 * M * F_in) / N
igor_v 2:2d0b80ed9216 54 // <i> F_in must be in the range of 32 kHz to 50 MHz
igor_v 2:2d0b80ed9216 55 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
igor_v 2:2d0b80ed9216 56 // <o4.0..14> MSEL: PLL Multiplier Selection
igor_v 2:2d0b80ed9216 57 // <6-32768><#-1>
igor_v 2:2d0b80ed9216 58 // <i> M Value
igor_v 2:2d0b80ed9216 59 // <o4.16..23> NSEL: PLL Divider Selection
igor_v 2:2d0b80ed9216 60 // <1-256><#-1>
igor_v 2:2d0b80ed9216 61 // <i> N Value
igor_v 2:2d0b80ed9216 62 // </h>
igor_v 2:2d0b80ed9216 63 // </e>
igor_v 2:2d0b80ed9216 64 //
igor_v 2:2d0b80ed9216 65 // <e5> PLL1 Configuration (USB PLL)
igor_v 2:2d0b80ed9216 66 // <h> PLL1 Configuration Register (PLL1CFG)
igor_v 2:2d0b80ed9216 67 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
igor_v 2:2d0b80ed9216 68 // <i> F_cco1 = F_osc * M * 2 * P
igor_v 2:2d0b80ed9216 69 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
igor_v 2:2d0b80ed9216 70 // <o6.0..4> MSEL: PLL Multiplier Selection
igor_v 2:2d0b80ed9216 71 // <1-32><#-1>
igor_v 2:2d0b80ed9216 72 // <i> M Value (for USB maximum value is 4)
igor_v 2:2d0b80ed9216 73 // <o6.5..6> PSEL: PLL Divider Selection
igor_v 2:2d0b80ed9216 74 // <0=> 1
igor_v 2:2d0b80ed9216 75 // <1=> 2
igor_v 2:2d0b80ed9216 76 // <2=> 4
igor_v 2:2d0b80ed9216 77 // <3=> 8
igor_v 2:2d0b80ed9216 78 // <i> P Value
igor_v 2:2d0b80ed9216 79 // </h>
igor_v 2:2d0b80ed9216 80 // </e>
igor_v 2:2d0b80ed9216 81 //
igor_v 2:2d0b80ed9216 82 // <h> CPU Clock Configuration Register (CCLKCFG)
igor_v 2:2d0b80ed9216 83 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
igor_v 2:2d0b80ed9216 84 // <3-256><#-1>
igor_v 2:2d0b80ed9216 85 // </h>
igor_v 2:2d0b80ed9216 86 //
igor_v 2:2d0b80ed9216 87 // <h> USB Clock Configuration Register (USBCLKCFG)
igor_v 2:2d0b80ed9216 88 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
igor_v 2:2d0b80ed9216 89 // <0-15>
igor_v 2:2d0b80ed9216 90 // <i> Divide is USBSEL + 1
igor_v 2:2d0b80ed9216 91 // </h>
igor_v 2:2d0b80ed9216 92 //
igor_v 2:2d0b80ed9216 93 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
igor_v 2:2d0b80ed9216 94 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
igor_v 2:2d0b80ed9216 95 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 96 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 97 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 98 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 99 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
igor_v 2:2d0b80ed9216 100 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 101 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 102 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 103 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 104 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
igor_v 2:2d0b80ed9216 105 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 106 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 107 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 108 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 109 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
igor_v 2:2d0b80ed9216 110 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 111 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 112 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 113 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 114 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
igor_v 2:2d0b80ed9216 115 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 116 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 117 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 118 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 119 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
igor_v 2:2d0b80ed9216 120 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 121 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 122 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 123 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 124 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
igor_v 2:2d0b80ed9216 125 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 126 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 127 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 128 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 129 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
igor_v 2:2d0b80ed9216 130 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 131 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 132 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 133 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 134 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
igor_v 2:2d0b80ed9216 135 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 136 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 137 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 138 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 139 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
igor_v 2:2d0b80ed9216 140 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 141 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 142 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 143 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 144 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
igor_v 2:2d0b80ed9216 145 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 146 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 147 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 148 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 149 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
igor_v 2:2d0b80ed9216 150 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 151 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 152 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 153 // <3=> Pclk = Hclk / 6
igor_v 2:2d0b80ed9216 154 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
igor_v 2:2d0b80ed9216 155 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 156 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 157 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 158 // <3=> Pclk = Hclk / 6
igor_v 2:2d0b80ed9216 159 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
igor_v 2:2d0b80ed9216 160 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 161 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 162 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 163 // <3=> Pclk = Hclk / 6
igor_v 2:2d0b80ed9216 164 // </h>
igor_v 2:2d0b80ed9216 165 //
igor_v 2:2d0b80ed9216 166 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
igor_v 2:2d0b80ed9216 167 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
igor_v 2:2d0b80ed9216 168 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 169 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 170 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 171 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 172 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
igor_v 2:2d0b80ed9216 173 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 174 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 175 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 176 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 177 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
igor_v 2:2d0b80ed9216 178 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 179 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 180 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 181 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 182 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
igor_v 2:2d0b80ed9216 183 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 184 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 185 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 186 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 187 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
igor_v 2:2d0b80ed9216 188 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 189 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 190 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 191 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 192 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
igor_v 2:2d0b80ed9216 193 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 194 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 195 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 196 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 197 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
igor_v 2:2d0b80ed9216 198 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 199 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 200 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 201 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 202 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
igor_v 2:2d0b80ed9216 203 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 204 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 205 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 206 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 207 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
igor_v 2:2d0b80ed9216 208 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 209 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 210 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 211 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 212 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
igor_v 2:2d0b80ed9216 213 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 214 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 215 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 216 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 217 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
igor_v 2:2d0b80ed9216 218 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 219 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 220 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 221 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 222 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
igor_v 2:2d0b80ed9216 223 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 224 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 225 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 226 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 227 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
igor_v 2:2d0b80ed9216 228 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 229 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 230 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 231 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 232 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
igor_v 2:2d0b80ed9216 233 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 234 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 235 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 236 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 237 // </h>
igor_v 2:2d0b80ed9216 238 //
igor_v 2:2d0b80ed9216 239 // <h> Power Control for Peripherals Register (PCONP)
igor_v 2:2d0b80ed9216 240 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
igor_v 2:2d0b80ed9216 241 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
igor_v 2:2d0b80ed9216 242 // <o11.3> PCUART0: UART 0 power/clock enable
igor_v 2:2d0b80ed9216 243 // <o11.4> PCUART1: UART 1 power/clock enable
igor_v 2:2d0b80ed9216 244 // <o11.6> PCPWM1: PWM 1 power/clock enable
igor_v 2:2d0b80ed9216 245 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
igor_v 2:2d0b80ed9216 246 // <o11.8> PCSPI: SPI interface power/clock enable
igor_v 2:2d0b80ed9216 247 // <o11.9> PCRTC: RTC power/clock enable
igor_v 2:2d0b80ed9216 248 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
igor_v 2:2d0b80ed9216 249 // <o11.12> PCAD: A/D converter power/clock enable
igor_v 2:2d0b80ed9216 250 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
igor_v 2:2d0b80ed9216 251 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
igor_v 2:2d0b80ed9216 252 // <o11.15> PCGPIO: GPIOs power/clock enable
igor_v 2:2d0b80ed9216 253 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
igor_v 2:2d0b80ed9216 254 // <o11.17> PCMC: Motor control PWM power/clock enable
igor_v 2:2d0b80ed9216 255 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
igor_v 2:2d0b80ed9216 256 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
igor_v 2:2d0b80ed9216 257 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
igor_v 2:2d0b80ed9216 258 // <o11.22> PCTIM2: Timer 2 power/clock enable
igor_v 2:2d0b80ed9216 259 // <o11.23> PCTIM3: Timer 3 power/clock enable
igor_v 2:2d0b80ed9216 260 // <o11.24> PCUART2: UART 2 power/clock enable
igor_v 2:2d0b80ed9216 261 // <o11.25> PCUART3: UART 3 power/clock enable
igor_v 2:2d0b80ed9216 262 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
igor_v 2:2d0b80ed9216 263 // <o11.27> PCI2S: I2S interface power/clock enable
igor_v 2:2d0b80ed9216 264 // <o11.29> PCGPDMA: GP DMA function power/clock enable
igor_v 2:2d0b80ed9216 265 // <o11.30> PCENET: Ethernet block power/clock enable
igor_v 2:2d0b80ed9216 266 // <o11.31> PCUSB: USB interface power/clock enable
igor_v 2:2d0b80ed9216 267 // </h>
igor_v 2:2d0b80ed9216 268 //
igor_v 2:2d0b80ed9216 269 // <h> Clock Output Configuration Register (CLKOUTCFG)
igor_v 2:2d0b80ed9216 270 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
igor_v 2:2d0b80ed9216 271 // <0=> CPU clock
igor_v 2:2d0b80ed9216 272 // <1=> Main oscillator
igor_v 2:2d0b80ed9216 273 // <2=> Internal RC oscillator
igor_v 2:2d0b80ed9216 274 // <3=> USB clock
igor_v 2:2d0b80ed9216 275 // <4=> RTC oscillator
igor_v 2:2d0b80ed9216 276 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
igor_v 2:2d0b80ed9216 277 // <1-16><#-1>
igor_v 2:2d0b80ed9216 278 // <o12.8> CLKOUT_EN: CLKOUT enable control
igor_v 2:2d0b80ed9216 279 // </h>
igor_v 2:2d0b80ed9216 280 //
igor_v 2:2d0b80ed9216 281 // </e>
igor_v 2:2d0b80ed9216 282 */
Diletant 44:80289a836583 283
igor_v 123:6dd1df6230e9 284 // сейчас получается частота 100 Mhz
igor_v 123:6dd1df6230e9 285 //12 * 2 * (99+1) / (5+1) = 400 (должна быть в пределах 275...550)
igor_v 123:6dd1df6230e9 286 //потом еше делится на 4 = 100
igor_v 123:6dd1df6230e9 287 //нам нужно 921600* 16 = 14 745 000, теперб выбираем делитель уартовский 7 = 103 219 200, дибо 8 = 117 964 800
igor_v 123:6dd1df6230e9 288
igor_v 123:6dd1df6230e9 289 //1 выбираем второе 117 964 800 округляем до 100 000 (для второго таймера) 118 000. таку. частоту нужно на входе УАРТА.
Kovalev_D 135:c1e30e0e8949 290 //118 * 3 = 354, 118 * 4 = 472.
igor_v 123:6dd1df6230e9 291
igor_v 123:6dd1df6230e9 292 // 354 / "3" = 118
igor_v 123:6dd1df6230e9 293 //попробуем с 474 >> умножитель на 59 и делитель на 3 => 12 * 2 * ("58" + 1) / ("2" + 1) = 472.
igor_v 123:6dd1df6230e9 294 // 472 / "4" = 118
Kovalev_D 135:c1e30e0e8949 295
igor_v 123:6dd1df6230e9 296 // с другой стороны не рекомендуют частоты выше 100 (120 только для 1769 или чото там еще )
igor_v 123:6dd1df6230e9 297 // 103,200 => *3 = 309.6; * 4 = 412,8.
igor_v 123:6dd1df6230e9 298 // 412,8 умножитель на 86 и делитель на 5 => 12 * 2 * ("85" + 1) / ("4" + 1) = 412,8. !!!!!наверно можно остоновиься и попробовать!!!!!!!!
igor_v 123:6dd1df6230e9 299 // 412,8 / "4" = 103,2
igor_v 123:6dd1df6230e9 300
igor_v 2:2d0b80ed9216 301 #define CLOCK_SETUP 1
Kovalev_D 133:90d0bf0e2996 302
Diletant 44:80289a836583 303 //System control - system control and status register:
Diletant 44:80289a836583 304 // bit 4 - main oscillator range:
Diletant 44:80289a836583 305 // 0 - 1...20MHz
Diletant 44:80289a836583 306 // 1 - 15...25MHz
Diletant 44:80289a836583 307 // bit 5 - main oscillator enable
Diletant 44:80289a836583 308 // 0 - disabled
Diletant 44:80289a836583 309 // 1 - enabled
Diletant 44:80289a836583 310 // bit 6 - main oscillator status
Diletant 44:80289a836583 311 // 0 - not ready
Diletant 44:80289a836583 312 // 1 - ready
Diletant 44:80289a836583 313 #define SCS_Val 0x00000020 //Enable main oscillator,1...20MHz
Diletant 44:80289a836583 314 //Clock Source Select register
Diletant 44:80289a836583 315 // bits 0-1:
Diletant 44:80289a836583 316 // 00 - Selects the Internal RC oscillator as the PLL0 clock source (default)
Diletant 44:80289a836583 317 // 01 - Selects the main oscillator as the PLL0 clock source
Diletant 44:80289a836583 318 // 10 - Selects the RTC oscillator as the PLL0 clock source
Diletant 44:80289a836583 319 // 11 - Reserved, do not use this setting
Diletant 44:80289a836583 320 #define CLKSRCSEL_Val 0x00000001//Select the main oscillator as the PLL0 clock source
igor_v 2:2d0b80ed9216 321 #define PLL0_SETUP 1
Diletant 44:80289a836583 322 //PLL0 Configuration register
Diletant 44:80289a836583 323 // bits 0...14 - PLL0 multiplier value minus 1. Supported multiplier M range 6...512
Diletant 44:80289a836583 324 // bits 16...23 - PLL0 Pre-Divider value minus 1. Supported divider N range 1...32
Diletant 44:80289a836583 325 // Fcc0 = (2 * M * Fin) / N
Kovalev_D 164:6f43f85fdd8d 326 #define PLL0CFG_Val 0x00040055//M - 86, N - 5, output = 2 * 86 * 12MHz / 5 = 400MHz
Kovalev_D 164:6f43f85fdd8d 327 // #define PLL0CFG_Val 0x0003003d//M - 86, N - 5, output = 2 * 86 * 12MHz / 5 = 400MHz
igor_v 2:2d0b80ed9216 328 #define PLL1_SETUP 1
Diletant 44:80289a836583 329 #define PLL1CFG_Val 0x00000023//M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz?
Diletant 44:80289a836583 330 //CPU Clock Configure Register
Diletant 44:80289a836583 331 #define CCLKCFG_Val 0x00000003 //Divide by 4
igor_v 123:6dd1df6230e9 332
Diletant 44:80289a836583 333 //USB Clock Configuration register
Diletant 44:80289a836583 334 // bits 0...3
Diletant 44:80289a836583 335 // 5 - PLL0 output is divided by 6. PLL0 output must be 288 MHz
Diletant 44:80289a836583 336 // 7 - PLL0 output is divided by 8. PLL0 output must be 384 MHz
Diletant 44:80289a836583 337 // 9 - PLL0 output is divided by 10. PLL0 output must be 480 MHz
Diletant 44:80289a836583 338 #define USBCLKCFG_Val 0x00000000//default
Diletant 44:80289a836583 339 //Peripheral Clock Selection register 0
Diletant 44:80289a836583 340 // 1:0 PCLK_WDT Peripheral clock selection for WDT. 00
Diletant 44:80289a836583 341 // 3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00
Diletant 44:80289a836583 342 // 5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00
Diletant 44:80289a836583 343 // 7:6 PCLK_UART0 Peripheral clock selection for UART0. 00
Diletant 44:80289a836583 344 // 9:8 PCLK_UART1 Peripheral clock selection for UART1. 00
Diletant 44:80289a836583 345 // 11:10 - Reserved. NA
Diletant 44:80289a836583 346 // 13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00
Diletant 44:80289a836583 347 // 15:14 PCLK_I2C0 Peripheral clock selection for I2C0. 00
Diletant 44:80289a836583 348 // 17:16 PCLK_SPI Peripheral clock selection for SPI. 00
Diletant 44:80289a836583 349 // 19:18 - Reserved. NA
Diletant 44:80289a836583 350 // 21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00
Diletant 44:80289a836583 351 // 23:22 PCLK_DAC Peripheral clock selection for DAC. 00
Diletant 44:80289a836583 352 // 25:24 PCLK_ADC Peripheral clock selection for ADC. 00
Diletant 44:80289a836583 353 // 27:26 PCLK_CAN1 Peripheral clock selection for CAN1.[1] 00
Diletant 44:80289a836583 354 // 29:28 PCLK_CAN2 Peripheral clock selection for CAN2.[1] 00
Diletant 44:80289a836583 355 // 31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering
Diletant 44:80289a836583 356 // bits values:
Diletant 44:80289a836583 357 // 00 PCLK_peripheral = CCLK/4
Diletant 44:80289a836583 358 // 01 PCLK_peripheral = CCLK
Diletant 44:80289a836583 359 // 10 PCLK_peripheral = CCLK/2
Diletant 44:80289a836583 360 // 11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6.
Kovalev_D 117:eefe61968528 361 //#define PCLKSEL0_Val 0x00000010//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
Kovalev_D 214:4c70e452c491 362 #define PCLKSEL0_Val 0x40000150//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
Kovalev_D 164:6f43f85fdd8d 363 //#define PCLKSEL0_Val 0x000003d0//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
Diletant 44:80289a836583 364 //Peripheral Clock Selection register 1
Diletant 44:80289a836583 365 // 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface.00
Diletant 44:80289a836583 366 // 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00
Diletant 44:80289a836583 367 // 5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00
Diletant 44:80289a836583 368 // 7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00
Diletant 44:80289a836583 369 // 9:8 - Reserved. NA
Diletant 44:80289a836583 370 // 11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00
Diletant 44:80289a836583 371 // 13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00
Diletant 44:80289a836583 372 // 15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00
Diletant 44:80289a836583 373 // 17:16 PCLK_UART2 Peripheral clock selection for UART2. 00
Diletant 44:80289a836583 374 // 19:18 PCLK_UART3 Peripheral clock selection for UART3. 00
Diletant 44:80289a836583 375 // 21:20 PCLK_I2C2 Peripheral clock selection for I2C2. 00
Diletant 44:80289a836583 376 // 23:22 PCLK_I2S Peripheral clock selection for I2S. 00
Diletant 44:80289a836583 377 // 25:24 - Reserved. NA
Diletant 44:80289a836583 378 // 27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00
Diletant 44:80289a836583 379 // 29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00
Diletant 44:80289a836583 380 // 31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM
Diletant 49:53277d871197 381 #define PCLKSEL1_Val 0x00000000//CCLK/4
Diletant 49:53277d871197 382 //Power Control for Peripherals register
Diletant 49:53277d871197 383 //0 - Reserved. NA
Diletant 49:53277d871197 384 //1 PCTIM0 Timer/Counter 0 power/clock control bit. 1
Diletant 49:53277d871197 385 //2 PCTIM1 Timer/Counter 1 power/clock control bit. 1
Diletant 49:53277d871197 386 //3 PCUART0 UART0 power/clock control bit. 1
Diletant 49:53277d871197 387 //4 PCUART1 UART1 power/clock control bit. 1
Diletant 49:53277d871197 388 //5 - Reserved. NA
Diletant 49:53277d871197 389 //6 PCPWM1 PWM1 power/clock control bit. 1
Diletant 49:53277d871197 390 //7 PCI2C0 The I2C0 interface power/clock control bit. 1
Diletant 49:53277d871197 391 //8 PCSPI The SPI interface power/clock control bit. 1
Diletant 49:53277d871197 392 //9 PCRTC The RTC power/clock control bit. 1
Diletant 49:53277d871197 393 //10 PCSSP1 The SSP 1 interface power/clock control bit. 1
Diletant 49:53277d871197 394 //11 - Reserved. NA
Diletant 49:53277d871197 395 //12 PCADC A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. 0
Diletant 49:53277d871197 396 //13 PCCAN1 CAN Controller 1 power/clock control bit. 0
Diletant 49:53277d871197 397 //14 PCCAN2 CAN Controller 2 power/clock control bit. 0
Diletant 49:53277d871197 398 //15 PCGPIO Power/clock control bit for IOCON, GPIO, and GPIO interrupts. 1
Diletant 49:53277d871197 399 //16 PCRIT Repetitive Interrupt Timer power/clock control bit. 0
Diletant 49:53277d871197 400 //17 PCMCPWM Motor Control PWM 0
Diletant 49:53277d871197 401 //18 PCQEI Quadrature Encoder Interface power/clock control bit. 0
Diletant 49:53277d871197 402 //19 PCI2C1 The I2C1 interface power/clock control bit. 1
Diletant 49:53277d871197 403 //20 - Reserved. NA
Diletant 49:53277d871197 404 //21 PCSSP0 The SSP0 interface power/clock control bit. 1
Diletant 49:53277d871197 405 //22 PCTIM2 Timer 2 power/clock control bit. 0
Diletant 49:53277d871197 406 //23 PCTIM3 Timer 3 power/clock control bit. 0
Diletant 49:53277d871197 407 //24 PCUART2 UART 2 power/clock control bit. 0
Diletant 49:53277d871197 408 //25 PCUART3 UART 3 power/clock control bit. 0
Diletant 49:53277d871197 409 //26 PCI2C2 I2C interface 2 power/clock control bit. 1
Kovalev_D 116:66f1f0ff2dab 410 #define PCONP_Val 0x046887DE//ADC,CAN1/2,RIT,Timer3,UART2,UART3 disabled
Diletant 49:53277d871197 411 //Clock Output Configuration register
Diletant 49:53277d871197 412 // 3:0 CLKOUTSEL Selects the clock source for the CLKOUT function. 0
Diletant 49:53277d871197 413 // 0000 Selects the CPU clock as the CLKOUT source.
Diletant 49:53277d871197 414 // 0001 Selects the main oscillator as the CLKOUT source.
Diletant 49:53277d871197 415 // 0010 Selects the Internal RC oscillator as the CLKOUT source.
Diletant 49:53277d871197 416 // 0011 Selects the USB clock as the CLKOUT source.
Diletant 49:53277d871197 417 // 0100 Selects the RTC oscillator as the CLKOUT source.
Diletant 49:53277d871197 418 // Others Reserved, do not use these settings.
Diletant 49:53277d871197 419 // 7:4 CLKOUTDIV Integer value to divide the output clock by, minus one. 0
Diletant 49:53277d871197 420 // 0000 Clock is divided by 1.
Diletant 49:53277d871197 421 // 0001 Clock is divided by 2.
Diletant 49:53277d871197 422 // 0010 Clock is divided by 3.
Diletant 49:53277d871197 423 // ... ...
Diletant 49:53277d871197 424 // 1111 Clock is divided by 16.
Diletant 49:53277d871197 425 // 8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. 0
Diletant 49:53277d871197 426 // 9 CLKOUT_ACT CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped.
Diletant 49:53277d871197 427 #define CLKOUTCFG_Val 0x00000000//Host4: CLKOUT pin not used
igor_v 2:2d0b80ed9216 428
igor_v 2:2d0b80ed9216 429
igor_v 2:2d0b80ed9216 430 /*--------------------- Flash Accelerator Configuration ----------------------
igor_v 2:2d0b80ed9216 431 //
igor_v 2:2d0b80ed9216 432 // <e> Flash Accelerator Configuration
igor_v 2:2d0b80ed9216 433 // <o1.0..1> FETCHCFG: Fetch Configuration
igor_v 2:2d0b80ed9216 434 // <0=> Instruction fetches from flash are not buffered
igor_v 2:2d0b80ed9216 435 // <1=> One buffer is used for all instruction fetch buffering
igor_v 2:2d0b80ed9216 436 // <2=> All buffers may be used for instruction fetch buffering
igor_v 2:2d0b80ed9216 437 // <3=> Reserved (do not use this setting)
igor_v 2:2d0b80ed9216 438 // <o1.2..3> DATACFG: Data Configuration
igor_v 2:2d0b80ed9216 439 // <0=> Data accesses from flash are not buffered
igor_v 2:2d0b80ed9216 440 // <1=> One buffer is used for all data access buffering
igor_v 2:2d0b80ed9216 441 // <2=> All buffers may be used for data access buffering
igor_v 2:2d0b80ed9216 442 // <3=> Reserved (do not use this setting)
igor_v 2:2d0b80ed9216 443 // <o1.4> ACCEL: Acceleration Enable
igor_v 2:2d0b80ed9216 444 // <o1.5> PREFEN: Prefetch Enable
igor_v 2:2d0b80ed9216 445 // <o1.6> PREFOVR: Prefetch Override
igor_v 2:2d0b80ed9216 446 // <o1.12..15> FLASHTIM: Flash Access Time
igor_v 2:2d0b80ed9216 447 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
igor_v 2:2d0b80ed9216 448 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
igor_v 2:2d0b80ed9216 449 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
igor_v 2:2d0b80ed9216 450 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
igor_v 2:2d0b80ed9216 451 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
igor_v 2:2d0b80ed9216 452 // <5=> 6 CPU clocks (for any CPU clock)
igor_v 2:2d0b80ed9216 453 // </e>
igor_v 2:2d0b80ed9216 454 */
igor_v 2:2d0b80ed9216 455 #define FLASH_SETUP 1
Diletant 46:2670fa0fcebc 456 //Flash Accelerator Configuration Register
Diletant 46:2670fa0fcebc 457 // 11:0 - - Reserved, user software should not change these bits from the reset value. 0x03A
Diletant 46:2670fa0fcebc 458 // 15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. 0x3
Diletant 46:2670fa0fcebc 459 // 0000 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.
Diletant 46:2670fa0fcebc 460 // 0001 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.
Diletant 46:2670fa0fcebc 461 // 0010 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.
Diletant 46:2670fa0fcebc 462 // 0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.
Diletant 46:2670fa0fcebc 463 // 0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only.
Diletant 46:2670fa0fcebc 464 // 0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions. Other Intended for potential future higher speed devices.
Kovalev_D 135:c1e30e0e8949 465
Diletant 46:2670fa0fcebc 466 // 31:16 - Reserved. The value read from a reserved bit is not defined. NA
Kovalev_D 136:19b9e6abb86f 467 #define FLASHCFG_Val 0x0000303A//5 CPU clocks required for flash access
igor_v 2:2d0b80ed9216 468
igor_v 2:2d0b80ed9216 469 /*
igor_v 2:2d0b80ed9216 470 //-------- <<< end of configuration section >>> ------------------------------
igor_v 2:2d0b80ed9216 471 */
igor_v 2:2d0b80ed9216 472
igor_v 2:2d0b80ed9216 473 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 474 Check the register settings
igor_v 2:2d0b80ed9216 475 *----------------------------------------------------------------------------*/
igor_v 2:2d0b80ed9216 476 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
igor_v 2:2d0b80ed9216 477 #define CHECK_RSVD(val, mask) (val & mask)
igor_v 2:2d0b80ed9216 478
igor_v 2:2d0b80ed9216 479 /* Clock Configuration -------------------------------------------------------*/
igor_v 2:2d0b80ed9216 480 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
Kovalev_D 135:c1e30e0e8949 481 #error "SCS: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 482 #endif
igor_v 2:2d0b80ed9216 483
igor_v 2:2d0b80ed9216 484 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
Kovalev_D 135:c1e30e0e8949 485 #error "CLKSRCSEL: Value out of range!"
igor_v 2:2d0b80ed9216 486 #endif
igor_v 2:2d0b80ed9216 487
igor_v 2:2d0b80ed9216 488 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
Kovalev_D 135:c1e30e0e8949 489 #error "PLL0CFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 490 #endif
igor_v 2:2d0b80ed9216 491
igor_v 2:2d0b80ed9216 492 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
Kovalev_D 135:c1e30e0e8949 493 #error "PLL1CFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 494 #endif
igor_v 2:2d0b80ed9216 495
igor_v 2:2d0b80ed9216 496 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
Kovalev_D 135:c1e30e0e8949 497 #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
igor_v 2:2d0b80ed9216 498 #endif
igor_v 2:2d0b80ed9216 499
igor_v 2:2d0b80ed9216 500 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
Kovalev_D 135:c1e30e0e8949 501 #error "USBCLKCFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 502 #endif
igor_v 2:2d0b80ed9216 503
igor_v 2:2d0b80ed9216 504 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
Kovalev_D 135:c1e30e0e8949 505 #error "PCLKSEL0: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 506 #endif
igor_v 2:2d0b80ed9216 507
igor_v 2:2d0b80ed9216 508 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
Kovalev_D 135:c1e30e0e8949 509 #error "PCLKSEL1: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 510 #endif
igor_v 2:2d0b80ed9216 511
igor_v 2:2d0b80ed9216 512 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
Kovalev_D 135:c1e30e0e8949 513 #error "PCONP: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 514 #endif
igor_v 2:2d0b80ed9216 515
igor_v 2:2d0b80ed9216 516 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
Kovalev_D 135:c1e30e0e8949 517 #error "CLKOUTCFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 518 #endif
igor_v 2:2d0b80ed9216 519
igor_v 2:2d0b80ed9216 520 /* Flash Accelerator Configuration -------------------------------------------*/
igor_v 2:2d0b80ed9216 521 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
Kovalev_D 135:c1e30e0e8949 522 #error "FLASHCFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 523 #endif
igor_v 2:2d0b80ed9216 524
igor_v 2:2d0b80ed9216 525
igor_v 2:2d0b80ed9216 526 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 527 DEFINES
igor_v 2:2d0b80ed9216 528 *----------------------------------------------------------------------------*/
Kovalev_D 135:c1e30e0e8949 529
igor_v 2:2d0b80ed9216 530 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 531 Define clocks
igor_v 2:2d0b80ed9216 532 *----------------------------------------------------------------------------*/
igor_v 2:2d0b80ed9216 533 #define XTAL (12000000UL) /* Oscillator frequency */
igor_v 2:2d0b80ed9216 534 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
igor_v 2:2d0b80ed9216 535 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
igor_v 2:2d0b80ed9216 536 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
igor_v 2:2d0b80ed9216 537
igor_v 2:2d0b80ed9216 538
igor_v 2:2d0b80ed9216 539 /* F_cco0 = (2 * M * F_in) / N */
igor_v 2:2d0b80ed9216 540 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
igor_v 2:2d0b80ed9216 541 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
Kovalev_D 135:c1e30e0e8949 542 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
igor_v 2:2d0b80ed9216 543 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
igor_v 2:2d0b80ed9216 544
igor_v 2:2d0b80ed9216 545 /* Determine core clock frequency according to settings */
Kovalev_D 135:c1e30e0e8949 546 #if (PLL0_SETUP)
Kovalev_D 135:c1e30e0e8949 547 #if ((CLKSRCSEL_Val & 0x03) == 1)
Kovalev_D 135:c1e30e0e8949 548 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
Kovalev_D 135:c1e30e0e8949 549 #elif ((CLKSRCSEL_Val & 0x03) == 2)
Kovalev_D 135:c1e30e0e8949 550 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
Kovalev_D 135:c1e30e0e8949 551 #else
Kovalev_D 135:c1e30e0e8949 552 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
Kovalev_D 135:c1e30e0e8949 553 #endif
Kovalev_D 135:c1e30e0e8949 554 #else
Kovalev_D 135:c1e30e0e8949 555 #if ((CLKSRCSEL_Val & 0x03) == 1)
Kovalev_D 135:c1e30e0e8949 556 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
Kovalev_D 135:c1e30e0e8949 557 #elif ((CLKSRCSEL_Val & 0x03) == 2)
Kovalev_D 135:c1e30e0e8949 558 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
Kovalev_D 135:c1e30e0e8949 559 #else
Kovalev_D 135:c1e30e0e8949 560 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
Kovalev_D 135:c1e30e0e8949 561 #endif
Kovalev_D 135:c1e30e0e8949 562 #endif
igor_v 2:2d0b80ed9216 563
igor_v 2:2d0b80ed9216 564
igor_v 2:2d0b80ed9216 565 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 566 Clock Variable definitions
igor_v 2:2d0b80ed9216 567 *----------------------------------------------------------------------------*/
Kovalev_D 132:2c7bec5cf6fe 568 uint32_t SystemFrequency = IRC_OSC;
igor_v 12:74bd0ecf7f83 569 uint32_t SystemCoreClock1 = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
igor_v 2:2d0b80ed9216 570
igor_v 2:2d0b80ed9216 571
igor_v 2:2d0b80ed9216 572 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 573 Clock functions
igor_v 2:2d0b80ed9216 574 *----------------------------------------------------------------------------*/
igor_v 12:74bd0ecf7f83 575 void SystemCoreClockUpdate1 (void) /* Get Core Clock Frequency */
igor_v 2:2d0b80ed9216 576 {
Kovalev_D 135:c1e30e0e8949 577 /* Determine clock frequency according to clock register values */
Kovalev_D 135:c1e30e0e8949 578 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
Kovalev_D 135:c1e30e0e8949 579 switch (LPC_SC->CLKSRCSEL & 0x03) {
Kovalev_D 135:c1e30e0e8949 580 case 0: /* Int. RC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 581 case 3: /* Reserved, default to Int. RC */
Kovalev_D 135:c1e30e0e8949 582 SystemCoreClock1 = (IRC_OSC *
Kovalev_D 135:c1e30e0e8949 583 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
Kovalev_D 135:c1e30e0e8949 584 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
Kovalev_D 135:c1e30e0e8949 585 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
Kovalev_D 135:c1e30e0e8949 586 break;
Kovalev_D 135:c1e30e0e8949 587 case 1: /* Main oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 588 SystemCoreClock1 = (OSC_CLK * //it is our case osc_clk = 12 MHz
Kovalev_D 135:c1e30e0e8949 589 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / //PLL0 multiplier value
Kovalev_D 135:c1e30e0e8949 590 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / //PLL0 pre-divider
Kovalev_D 135:c1e30e0e8949 591 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); //divider for CCLK (SystemCoreClock)
Kovalev_D 135:c1e30e0e8949 592 break;
Kovalev_D 135:c1e30e0e8949 593 case 2: /* RTC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 594 SystemCoreClock1 = (RTC_CLK *
Kovalev_D 135:c1e30e0e8949 595 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
Kovalev_D 135:c1e30e0e8949 596 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
Kovalev_D 135:c1e30e0e8949 597 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
Kovalev_D 135:c1e30e0e8949 598 break;
Kovalev_D 135:c1e30e0e8949 599 }
Kovalev_D 135:c1e30e0e8949 600 } else {
Kovalev_D 135:c1e30e0e8949 601 switch (LPC_SC->CLKSRCSEL & 0x03) {
Kovalev_D 135:c1e30e0e8949 602 case 0: /* Int. RC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 603 case 3: /* Reserved, default to Int. RC */
Kovalev_D 135:c1e30e0e8949 604 SystemCoreClock1 = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
Kovalev_D 135:c1e30e0e8949 605 break;
Kovalev_D 135:c1e30e0e8949 606 case 1: /* Main oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 607 SystemCoreClock1 = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
Kovalev_D 135:c1e30e0e8949 608 break;
Kovalev_D 135:c1e30e0e8949 609 case 2: /* RTC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 610 SystemCoreClock1 = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
Kovalev_D 135:c1e30e0e8949 611 break;
Kovalev_D 135:c1e30e0e8949 612 }
igor_v 2:2d0b80ed9216 613 }
igor_v 2:2d0b80ed9216 614
igor_v 2:2d0b80ed9216 615 }
igor_v 2:2d0b80ed9216 616
igor_v 2:2d0b80ed9216 617 /**
igor_v 2:2d0b80ed9216 618 * Initialize the system
igor_v 2:2d0b80ed9216 619 *
igor_v 2:2d0b80ed9216 620 * @param none
igor_v 2:2d0b80ed9216 621 * @return none
igor_v 2:2d0b80ed9216 622 *
igor_v 2:2d0b80ed9216 623 * @brief Setup the microcontroller system.
igor_v 2:2d0b80ed9216 624 * Initialize the System.
igor_v 2:2d0b80ed9216 625 */
igor_v 12:74bd0ecf7f83 626 void SystemInit1 (void)
igor_v 2:2d0b80ed9216 627 {
Kovalev_D 135:c1e30e0e8949 628 #if (CLOCK_SETUP) /* Clock Setup */
Kovalev_D 135:c1e30e0e8949 629 //Init system control and status register
Kovalev_D 135:c1e30e0e8949 630 LPC_SC->SCS = SCS_Val;//0x20 - enable main oscillator,1...20MHz (12MHz)
Kovalev_D 135:c1e30e0e8949 631 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
Kovalev_D 135:c1e30e0e8949 632 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
Kovalev_D 135:c1e30e0e8949 633 }
Kovalev_D 134:caf4c9cd5052 634
Kovalev_D 135:c1e30e0e8949 635 //Init CPU Clock Configure Register - select the divide value for creating the CPU clock (CCLK) from the PLL0 output
Kovalev_D 135:c1e30e0e8949 636 LPC_SC->CCLKCFG = CCLKCFG_Val; //3 - divide to 4 (3MHz)
igor_v 2:2d0b80ed9216 637
igor_v 2:2d0b80ed9216 638 #if (PLL0_SETUP)
Kovalev_D 135:c1e30e0e8949 639 //Init Clock Source Select register
Kovalev_D 135:c1e30e0e8949 640 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;//1 - Select the main oscillator as the PLL0 clock source
Kovalev_D 135:c1e30e0e8949 641 //Init PLL0 Configuration register
Kovalev_D 135:c1e30e0e8949 642 LPC_SC->PLL0CFG = PLL0CFG_Val;//0x00050063: M - 100, N - 6, PLL0output = 2 * 100 * 12MHz / 6 = 400MHz, CPU clock 100MHz
Kovalev_D 135:c1e30e0e8949 643 //Init PLL0 Feed Register. This register enables loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG
Kovalev_D 135:c1e30e0e8949 644 //registers into the shadow registers that actually affect PLL0 operation.
Kovalev_D 135:c1e30e0e8949 645 //Write 0xAA and 0x55 sequentially to update shadow registers and settings to take effect
Kovalev_D 135:c1e30e0e8949 646 LPC_SC->PLL0FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 647 LPC_SC->PLL0FEED = 0x55;
Kovalev_D 135:c1e30e0e8949 648 //Init PLL0 Control register
Kovalev_D 135:c1e30e0e8949 649 // bit 0 - PLL0 Enable
Kovalev_D 135:c1e30e0e8949 650 // bit 1 - PLL0 connect
Kovalev_D 135:c1e30e0e8949 651 LPC_SC->PLL0CON = 0x01;//PLL0 Enable
Kovalev_D 135:c1e30e0e8949 652 //Update shadow registers to settings take effect
Kovalev_D 135:c1e30e0e8949 653 LPC_SC->PLL0FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 654 LPC_SC->PLL0FEED = 0x55;
Kovalev_D 135:c1e30e0e8949 655 //PLL0 Status register
Kovalev_D 135:c1e30e0e8949 656 // bits 0...14 - Read-back for the PLL0 Multiplier value
Kovalev_D 135:c1e30e0e8949 657 // bits 16...23 - Read-back for the PLL0 Pre-Divider value
Kovalev_D 135:c1e30e0e8949 658 // bit 24 - Read-back for the PLL0 Enable bit
Kovalev_D 135:c1e30e0e8949 659 // bit 25 - Read-back for the PLL0 Connect bit
Kovalev_D 135:c1e30e0e8949 660 // bit 26 - Reflects the PLL0 Lock status: 1 - locked
Kovalev_D 135:c1e30e0e8949 661 while (!(LPC_SC->PLL0STAT & (1<<26)));//Wait while PLL0 locked (PLOCK0)
igor_v 2:2d0b80ed9216 662
Kovalev_D 135:c1e30e0e8949 663 LPC_SC->PLL0CON = 0x03;//PLL0 Enable & Connect
Kovalev_D 135:c1e30e0e8949 664 LPC_SC->PLL0FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 665 LPC_SC->PLL0FEED = 0x55;
Kovalev_D 135:c1e30e0e8949 666 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait while PLL0 connected (PLLC0_STAT & PLLE0_STAT)
igor_v 2:2d0b80ed9216 667 #endif
igor_v 2:2d0b80ed9216 668
igor_v 2:2d0b80ed9216 669 #if (PLL1_SETUP)
Kovalev_D 135:c1e30e0e8949 670 LPC_SC->PLL1CFG = PLL1CFG_Val;//0x23 M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz?
Kovalev_D 135:c1e30e0e8949 671 LPC_SC->PLL1FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 672 LPC_SC->PLL1FEED = 0x55;
igor_v 2:2d0b80ed9216 673
Kovalev_D 135:c1e30e0e8949 674 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
Kovalev_D 135:c1e30e0e8949 675 LPC_SC->PLL1FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 676 LPC_SC->PLL1FEED = 0x55;
Kovalev_D 135:c1e30e0e8949 677 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
igor_v 2:2d0b80ed9216 678
Kovalev_D 135:c1e30e0e8949 679 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
Kovalev_D 135:c1e30e0e8949 680 LPC_SC->PLL1FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 681 LPC_SC->PLL1FEED = 0x55;
Kovalev_D 135:c1e30e0e8949 682 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
igor_v 2:2d0b80ed9216 683 #else
Kovalev_D 135:c1e30e0e8949 684 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
igor_v 2:2d0b80ed9216 685 #endif
igor_v 2:2d0b80ed9216 686
Kovalev_D 135:c1e30e0e8949 687 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
Kovalev_D 135:c1e30e0e8949 688 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
igor_v 2:2d0b80ed9216 689
Kovalev_D 135:c1e30e0e8949 690 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
igor_v 2:2d0b80ed9216 691
Kovalev_D 135:c1e30e0e8949 692 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
igor_v 2:2d0b80ed9216 693 #endif
igor_v 2:2d0b80ed9216 694
igor_v 2:2d0b80ed9216 695 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
Kovalev_D 135:c1e30e0e8949 696 LPC_SC->FLASHCFG = FLASHCFG_Val;
igor_v 2:2d0b80ed9216 697 #endif
igor_v 2:2d0b80ed9216 698 }
igor_v 2:2d0b80ed9216 699
Kovalev_D 134:caf4c9cd5052 700
Kovalev_D 134:caf4c9cd5052 701
Kovalev_D 134:caf4c9cd5052 702
Kovalev_D 134:caf4c9cd5052 703
Kovalev_D 134:caf4c9cd5052 704
Kovalev_D 134:caf4c9cd5052 705
Kovalev_D 134:caf4c9cd5052 706 void SystemInitDef (void)
Kovalev_D 134:caf4c9cd5052 707 {
Kovalev_D 135:c1e30e0e8949 708
Kovalev_D 134:caf4c9cd5052 709
Kovalev_D 134:caf4c9cd5052 710 #if (CLOCK_SETUP) /* Clock Setup */
Kovalev_D 135:c1e30e0e8949 711 LPC_SC->SCS = SCS_Val;
Kovalev_D 135:c1e30e0e8949 712 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
Kovalev_D 135:c1e30e0e8949 713 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
Kovalev_D 135:c1e30e0e8949 714 }
Kovalev_D 134:caf4c9cd5052 715
Kovalev_D 135:c1e30e0e8949 716 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
Kovalev_D 134:caf4c9cd5052 717
Kovalev_D 135:c1e30e0e8949 718 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
Kovalev_D 135:c1e30e0e8949 719 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
Kovalev_D 134:caf4c9cd5052 720
Kovalev_D 134:caf4c9cd5052 721 #if (PLL0_SETUP)
Kovalev_D 136:19b9e6abb86f 722 LPC_SC->CLKSRCSEL = 0;// CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
Kovalev_D 135:c1e30e0e8949 723 LPC_SC->PLL0CFG = PLL0CFG_Val;
Kovalev_D 135:c1e30e0e8949 724 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
Kovalev_D 135:c1e30e0e8949 725 LPC_SC->PLL0FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 726 LPC_SC->PLL0FEED = 0x55;
Kovalev_D 135:c1e30e0e8949 727 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
Kovalev_D 134:caf4c9cd5052 728
Kovalev_D 135:c1e30e0e8949 729 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
Kovalev_D 135:c1e30e0e8949 730 LPC_SC->PLL0FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 731 LPC_SC->PLL0FEED = 0x55;
Kovalev_D 134:caf4c9cd5052 732 #endif
Kovalev_D 134:caf4c9cd5052 733
Kovalev_D 134:caf4c9cd5052 734 #if (PLL1_SETUP)
Kovalev_D 135:c1e30e0e8949 735 LPC_SC->PLL1CFG = PLL1CFG_Val;
Kovalev_D 135:c1e30e0e8949 736 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
Kovalev_D 135:c1e30e0e8949 737 LPC_SC->PLL1FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 738 LPC_SC->PLL1FEED = 0x55;
Kovalev_D 135:c1e30e0e8949 739 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
Kovalev_D 134:caf4c9cd5052 740
Kovalev_D 135:c1e30e0e8949 741 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
Kovalev_D 135:c1e30e0e8949 742 LPC_SC->PLL1FEED = 0xAA;
Kovalev_D 135:c1e30e0e8949 743 LPC_SC->PLL1FEED = 0x55;
Kovalev_D 134:caf4c9cd5052 744 #else
Kovalev_D 135:c1e30e0e8949 745 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
Kovalev_D 134:caf4c9cd5052 746 #endif
Kovalev_D 133:90d0bf0e2996 747
Kovalev_D 135:c1e30e0e8949 748 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
Kovalev_D 134:caf4c9cd5052 749
Kovalev_D 135:c1e30e0e8949 750 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
Kovalev_D 134:caf4c9cd5052 751 #endif
Kovalev_D 133:90d0bf0e2996 752
Kovalev_D 135:c1e30e0e8949 753 /* Determine clock frequency according to clock register values */
Kovalev_D 135:c1e30e0e8949 754 if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */
Kovalev_D 135:c1e30e0e8949 755 switch (LPC_SC->CLKSRCSEL & 0x03) {
Kovalev_D 135:c1e30e0e8949 756 case 0: /* Internal RC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 757 case 3: /* Reserved, default to Internal RC */
Kovalev_D 135:c1e30e0e8949 758 SystemFrequency = (IRC_OSC *
Kovalev_D 135:c1e30e0e8949 759 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
Kovalev_D 136:19b9e6abb86f 760 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
Kovalev_D 136:19b9e6abb86f 761 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
Kovalev_D 135:c1e30e0e8949 762 break;
Kovalev_D 135:c1e30e0e8949 763 case 1: /* Main oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 764 SystemFrequency = (OSC_CLK *
Kovalev_D 135:c1e30e0e8949 765 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
Kovalev_D 135:c1e30e0e8949 766 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
Kovalev_D 135:c1e30e0e8949 767 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
Kovalev_D 135:c1e30e0e8949 768 break;
Kovalev_D 135:c1e30e0e8949 769 case 2: /* RTC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 770 SystemFrequency = (RTC_CLK *
Kovalev_D 135:c1e30e0e8949 771 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
Kovalev_D 135:c1e30e0e8949 772 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
Kovalev_D 135:c1e30e0e8949 773 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
Kovalev_D 135:c1e30e0e8949 774 break;
Kovalev_D 135:c1e30e0e8949 775 }
Kovalev_D 135:c1e30e0e8949 776 } else {
Kovalev_D 135:c1e30e0e8949 777 switch (LPC_SC->CLKSRCSEL & 0x03) {
Kovalev_D 135:c1e30e0e8949 778 case 0: /* Internal RC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 779 case 3: /* Reserved, default to Internal RC */
Kovalev_D 135:c1e30e0e8949 780 SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
Kovalev_D 135:c1e30e0e8949 781 break;
Kovalev_D 135:c1e30e0e8949 782 case 1: /* Main oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 783 SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
Kovalev_D 135:c1e30e0e8949 784 break;
Kovalev_D 135:c1e30e0e8949 785 case 2: /* RTC oscillator => PLL0 */
Kovalev_D 135:c1e30e0e8949 786 SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
Kovalev_D 135:c1e30e0e8949 787 break;
Kovalev_D 135:c1e30e0e8949 788 }
Kovalev_D 134:caf4c9cd5052 789 }
Kovalev_D 133:90d0bf0e2996 790
Kovalev_D 134:caf4c9cd5052 791 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
Kovalev_D 135:c1e30e0e8949 792 LPC_SC->FLASHCFG = FLASHCFG_Val;
Kovalev_D 134:caf4c9cd5052 793 #endif
Kovalev_D 133:90d0bf0e2996 794
Kovalev_D 133:90d0bf0e2996 795
Kovalev_D 133:90d0bf0e2996 796 }
Kovalev_D 133:90d0bf0e2996 797