Dmitry Kovalev / Mbed 2 deprecated LG2

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Fork of LG by igor Apu

LPC17xx.h@219:2d3475d0dd1b, 2017-09-27 (annotated)

Committer:
Kovalev_D
Date:
Wed Sep 27 13:09:24 2017 +0000
Revision:
219:2d3475d0dd1b
Parent:
197:7a05523bf588 
hnjtfgyy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 0:8ad47e2b6f00 1 /******************************************************************************
igor_v 0:8ad47e2b6f00 2 * @file: LPC17xx.h
igor_v 0:8ad47e2b6f00 3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
igor_v 0:8ad47e2b6f00 4 * NXP LPC17xx Device Series
igor_v 0:8ad47e2b6f00 5 * @version: V1.10
igor_v 0:8ad47e2b6f00 6 * @date: 24. September 2010
igor_v 0:8ad47e2b6f00 7 *----------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 8 *
igor_v 0:8ad47e2b6f00 9 * @note
igor_v 0:8ad47e2b6f00 10 * Copyright (C) 2010 ARM Limited. All rights reserved.
igor_v 0:8ad47e2b6f00 11 *
igor_v 0:8ad47e2b6f00 12 * @par
igor_v 0:8ad47e2b6f00 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
igor_v 0:8ad47e2b6f00 14 * processor based microcontrollers. This file can be freely distributed
igor_v 0:8ad47e2b6f00 15 * within development tools that are supporting such ARM based processors.
igor_v 0:8ad47e2b6f00 16 *
igor_v 0:8ad47e2b6f00 17 * @par
igor_v 0:8ad47e2b6f00 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
igor_v 0:8ad47e2b6f00 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
igor_v 0:8ad47e2b6f00 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
igor_v 0:8ad47e2b6f00 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
igor_v 0:8ad47e2b6f00 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
igor_v 0:8ad47e2b6f00 23 *
igor_v 0:8ad47e2b6f00 24 ******************************************************************************/
igor_v 0:8ad47e2b6f00 25
igor_v 0:8ad47e2b6f00 26
igor_v 0:8ad47e2b6f00 27 #ifndef __LPC17xx_H__
igor_v 0:8ad47e2b6f00 28 #define __LPC17xx_H__
igor_v 0:8ad47e2b6f00 29
igor_v 0:8ad47e2b6f00 30 /*
igor_v 0:8ad47e2b6f00 31 * ==========================================================================
igor_v 0:8ad47e2b6f00 32 * ---------- Interrupt Number Definition -----------------------------------
igor_v 0:8ad47e2b6f00 33 * ==========================================================================
igor_v 0:8ad47e2b6f00 34 */
igor_v 0:8ad47e2b6f00 35
igor_v 0:8ad47e2b6f00 36 /** @addtogroup LPC17xx_System
igor_v 0:8ad47e2b6f00 37 * @{
igor_v 0:8ad47e2b6f00 38 */
igor_v 0:8ad47e2b6f00 39 #define rISER0 (*(volatile unsigned *)0xE000E100)
igor_v 0:8ad47e2b6f00 40 #define rICER0 (*(volatile unsigned *)0xE000E180)
igor_v 0:8ad47e2b6f00 41 #define rISPR0 (*(volatile unsigned *)0xE000E200)
igor_v 0:8ad47e2b6f00 42 #define rICPR0 (*(volatile unsigned *)0xE000E280)
igor_v 0:8ad47e2b6f00 43 #define rIABR0 (*(volatile unsigned *)0xE000E300)
igor_v 0:8ad47e2b6f00 44
igor_v 0:8ad47e2b6f00 45
igor_v 0:8ad47e2b6f00 46 /** @brief IRQ interrupt source definition */
igor_v 0:8ad47e2b6f00 47 typedef enum IRQn
igor_v 0:8ad47e2b6f00 48 {
igor_v 0:8ad47e2b6f00 49 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
igor_v 0:8ad47e2b6f00 50 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
igor_v 0:8ad47e2b6f00 51 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
igor_v 0:8ad47e2b6f00 52 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
igor_v 0:8ad47e2b6f00 53 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
igor_v 0:8ad47e2b6f00 54 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
igor_v 0:8ad47e2b6f00 55 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
igor_v 0:8ad47e2b6f00 56 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
igor_v 0:8ad47e2b6f00 57 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
igor_v 0:8ad47e2b6f00 58
igor_v 0:8ad47e2b6f00 59 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
igor_v 0:8ad47e2b6f00 60 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
igor_v 0:8ad47e2b6f00 61 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
igor_v 0:8ad47e2b6f00 62 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
igor_v 0:8ad47e2b6f00 63 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
igor_v 0:8ad47e2b6f00 64 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
igor_v 0:8ad47e2b6f00 65 UART0_IRQn = 5, /*!< UART0 Interrupt */
igor_v 0:8ad47e2b6f00 66 UART1_IRQn = 6, /*!< UART1 Interrupt */
igor_v 0:8ad47e2b6f00 67 UART2_IRQn = 7, /*!< UART2 Interrupt */
igor_v 0:8ad47e2b6f00 68 UART3_IRQn = 8, /*!< UART3 Interrupt */
igor_v 0:8ad47e2b6f00 69 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
igor_v 0:8ad47e2b6f00 70 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
igor_v 0:8ad47e2b6f00 71 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
igor_v 0:8ad47e2b6f00 72 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
igor_v 0:8ad47e2b6f00 73 SPI_IRQn = 13, /*!< SPI Interrupt */
igor_v 0:8ad47e2b6f00 74 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
igor_v 0:8ad47e2b6f00 75 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
igor_v 0:8ad47e2b6f00 76 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
igor_v 0:8ad47e2b6f00 77 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
igor_v 0:8ad47e2b6f00 78 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
igor_v 0:8ad47e2b6f00 79 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
igor_v 0:8ad47e2b6f00 80 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
igor_v 0:8ad47e2b6f00 81 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
igor_v 0:8ad47e2b6f00 82 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
igor_v 0:8ad47e2b6f00 83 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
igor_v 0:8ad47e2b6f00 84 USB_IRQn = 24, /*!< USB Interrupt */
igor_v 0:8ad47e2b6f00 85 CAN_IRQn = 25, /*!< CAN Interrupt */
igor_v 0:8ad47e2b6f00 86 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
igor_v 0:8ad47e2b6f00 87 I2S_IRQn = 27, /*!< I2S Interrupt */
igor_v 0:8ad47e2b6f00 88 ENET_IRQn = 28, /*!< Ethernet Interrupt */
igor_v 0:8ad47e2b6f00 89 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
igor_v 0:8ad47e2b6f00 90 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
igor_v 0:8ad47e2b6f00 91 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
igor_v 0:8ad47e2b6f00 92 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
igor_v 0:8ad47e2b6f00 93 USBActivity_IRQn = 33, /*!< USB Activity Interrupt(For wakeup only) */
igor_v 0:8ad47e2b6f00 94 CANActivity_IRQn = 34 /*!< CAN Activity Interrupt(For wakeup only) */
igor_v 0:8ad47e2b6f00 95 } IRQn_Type;
igor_v 0:8ad47e2b6f00 96
igor_v 0:8ad47e2b6f00 97
igor_v 0:8ad47e2b6f00 98 /*
igor_v 0:8ad47e2b6f00 99 * ==========================================================================
igor_v 0:8ad47e2b6f00 100 * ----------- Processor and Core Peripheral Section ------------------------
igor_v 0:8ad47e2b6f00 101 * ==========================================================================
igor_v 0:8ad47e2b6f00 102 */
igor_v 0:8ad47e2b6f00 103
igor_v 0:8ad47e2b6f00 104 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
igor_v 0:8ad47e2b6f00 105 #define __MPU_PRESENT 1 /*!< MPU present or not */
igor_v 0:8ad47e2b6f00 106 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
igor_v 0:8ad47e2b6f00 107 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
igor_v 0:8ad47e2b6f00 108
igor_v 0:8ad47e2b6f00 109
igor_v 0:8ad47e2b6f00 110 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
igor_v 0:8ad47e2b6f00 111 #include "system_LPC17xx.h" /* System Header */
igor_v 0:8ad47e2b6f00 112
igor_v 0:8ad47e2b6f00 113
igor_v 0:8ad47e2b6f00 114 /******************************************************************************/
igor_v 0:8ad47e2b6f00 115 /* Device Specific Peripheral registers structures */
igor_v 0:8ad47e2b6f00 116 /******************************************************************************/
igor_v 0:8ad47e2b6f00 117
igor_v 0:8ad47e2b6f00 118 #if defined ( __CC_ARM )
igor_v 0:8ad47e2b6f00 119 #pragma anon_unions
igor_v 0:8ad47e2b6f00 120 #endif
igor_v 0:8ad47e2b6f00 121
igor_v 0:8ad47e2b6f00 122 /*------------- System Control (SC) ------------------------------------------*/
igor_v 0:8ad47e2b6f00 123 /** @brief System Control (SC) register structure definition */
igor_v 0:8ad47e2b6f00 124 typedef struct
igor_v 0:8ad47e2b6f00 125 {
igor_v 0:8ad47e2b6f00 126 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
igor_v 0:8ad47e2b6f00 127 uint32_t RESERVED0[31];
igor_v 0:8ad47e2b6f00 128 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
igor_v 0:8ad47e2b6f00 129 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
igor_v 0:8ad47e2b6f00 130 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
igor_v 0:8ad47e2b6f00 131 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
igor_v 0:8ad47e2b6f00 132 uint32_t RESERVED1[4];
igor_v 0:8ad47e2b6f00 133 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
igor_v 0:8ad47e2b6f00 134 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
igor_v 0:8ad47e2b6f00 135 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
igor_v 0:8ad47e2b6f00 136 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
igor_v 0:8ad47e2b6f00 137 uint32_t RESERVED2[4];
igor_v 0:8ad47e2b6f00 138 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
igor_v 0:8ad47e2b6f00 139 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
igor_v 0:8ad47e2b6f00 140 uint32_t RESERVED3[15];
igor_v 0:8ad47e2b6f00 141 __IO uint32_t CCLKCFG; /*!< Offset: 0x104 (R/W) CPU Clock Configure Register */
igor_v 0:8ad47e2b6f00 142 __IO uint32_t USBCLKCFG; /*!< Offset: 0x108 (R/W) USB Clock Configure Register */
igor_v 0:8ad47e2b6f00 143 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
igor_v 0:8ad47e2b6f00 144 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
igor_v 0:8ad47e2b6f00 145 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
igor_v 0:8ad47e2b6f00 146 uint32_t RESERVED4[10];
igor_v 0:8ad47e2b6f00 147 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
igor_v 0:8ad47e2b6f00 148 uint32_t RESERVED5[1];
igor_v 0:8ad47e2b6f00 149 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
igor_v 0:8ad47e2b6f00 150 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
igor_v 0:8ad47e2b6f00 151 uint32_t RESERVED6[12];
igor_v 0:8ad47e2b6f00 152 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
igor_v 0:8ad47e2b6f00 153 uint32_t RESERVED7[7];
igor_v 0:8ad47e2b6f00 154 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
igor_v 0:8ad47e2b6f00 155 __IO uint32_t IRCTRIM; /* Clock Dividers */
igor_v 0:8ad47e2b6f00 156 __IO uint32_t PCLKSEL0; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Select 0 Register */
igor_v 0:8ad47e2b6f00 157 __IO uint32_t PCLKSEL1; /*!< Offset: 0x1AC (R/W) Peripheral Clock Select 1 Register */
igor_v 0:8ad47e2b6f00 158 uint32_t RESERVED8[4];
igor_v 0:8ad47e2b6f00 159 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
igor_v 0:8ad47e2b6f00 160 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
igor_v 0:8ad47e2b6f00 161 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
igor_v 0:8ad47e2b6f00 162
igor_v 0:8ad47e2b6f00 163 } LPC_SC_TypeDef;
igor_v 0:8ad47e2b6f00 164
igor_v 0:8ad47e2b6f00 165
igor_v 0:8ad47e2b6f00 166 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
igor_v 0:8ad47e2b6f00 167 /** @brief Pin Connect Block (PINCON) register structure definition */
igor_v 0:8ad47e2b6f00 168 typedef struct
igor_v 0:8ad47e2b6f00 169 {
igor_v 0:8ad47e2b6f00 170 __IO uint32_t PINSEL0; /* !< Offset: 0x000 PIN Select0 (R/W) */
igor_v 0:8ad47e2b6f00 171 __IO uint32_t PINSEL1; /* !< Offset: 0x004 PIN Select1 (R/W) */
igor_v 0:8ad47e2b6f00 172 __IO uint32_t PINSEL2; /* !< Offset: 0x008 PIN Select2 (R/W) */
igor_v 0:8ad47e2b6f00 173 __IO uint32_t PINSEL3; /* !< Offset: 0x00C PIN Select3 (R/W) */
igor_v 0:8ad47e2b6f00 174 __IO uint32_t PINSEL4; /* !< Offset: 0x010 PIN Select4 (R/W) */
igor_v 0:8ad47e2b6f00 175 __IO uint32_t PINSEL5; /* !< Offset: 0x014 PIN Select5 (R/W) */
igor_v 0:8ad47e2b6f00 176 __IO uint32_t PINSEL6; /* !< Offset: 0x018 PIN Select6 (R/W) */
igor_v 0:8ad47e2b6f00 177 __IO uint32_t PINSEL7; /* !< Offset: 0x01C PIN Select7 (R/W) */
igor_v 0:8ad47e2b6f00 178 __IO uint32_t PINSEL8; /* !< Offset: 0x020 PIN Select8 (R/W) */
igor_v 0:8ad47e2b6f00 179 __IO uint32_t PINSEL9; /* !< Offset: 0x024 PIN Select9 (R/W) */
igor_v 0:8ad47e2b6f00 180 __IO uint32_t PINSEL10; /* !< Offset: 0x028 PIN Select20 (R/W) */
igor_v 0:8ad47e2b6f00 181 uint32_t RESERVED0[5];
igor_v 0:8ad47e2b6f00 182 __IO uint32_t PINMODE0; /* !< Offset: 0x040 PIN Mode0 (R/W) */
igor_v 0:8ad47e2b6f00 183 __IO uint32_t PINMODE1; /* !< Offset: 0x044 PIN Mode1 (R/W) */
igor_v 0:8ad47e2b6f00 184 __IO uint32_t PINMODE2; /* !< Offset: 0x048 PIN Mode2 (R/W) */
igor_v 0:8ad47e2b6f00 185 __IO uint32_t PINMODE3; /* !< Offset: 0x04C PIN Mode3 (R/W) */
igor_v 0:8ad47e2b6f00 186 __IO uint32_t PINMODE4; /* !< Offset: 0x050 PIN Mode4 (R/W) */
igor_v 0:8ad47e2b6f00 187 __IO uint32_t PINMODE5; /* !< Offset: 0x054 PIN Mode5 (R/W) */
igor_v 0:8ad47e2b6f00 188 __IO uint32_t PINMODE6; /* !< Offset: 0x058 PIN Mode6 (R/W) */
igor_v 0:8ad47e2b6f00 189 __IO uint32_t PINMODE7; /* !< Offset: 0x05C PIN Mode7 (R/W) */
igor_v 0:8ad47e2b6f00 190 __IO uint32_t PINMODE8; /* !< Offset: 0x060 PIN Mode8 (R/W) */
igor_v 0:8ad47e2b6f00 191 __IO uint32_t PINMODE9; /* !< Offset: 0x064 PIN Mode9 (R/W) */
igor_v 0:8ad47e2b6f00 192 __IO uint32_t PINMODE_OD0; /* !< Offset: 0x068 Open Drain PIN Mode0 (R/W) */
igor_v 0:8ad47e2b6f00 193 __IO uint32_t PINMODE_OD1; /* !< Offset: 0x06C Open Drain PIN Mode1 (R/W) */
igor_v 0:8ad47e2b6f00 194 __IO uint32_t PINMODE_OD2; /* !< Offset: 0x070 Open Drain PIN Mode2 (R/W) */
igor_v 0:8ad47e2b6f00 195 __IO uint32_t PINMODE_OD3; /* !< Offset: 0x074 Open Drain PIN Mode3 (R/W) */
igor_v 0:8ad47e2b6f00 196 __IO uint32_t PINMODE_OD4; /* !< Offset: 0x078 Open Drain PIN Mode4 (R/W) */
igor_v 0:8ad47e2b6f00 197 __IO uint32_t I2CPADCFG; /* !< Offset: 0x07C I2C Pad Configure (R/W) */
igor_v 0:8ad47e2b6f00 198 } LPC_PINCON_TypeDef;
igor_v 0:8ad47e2b6f00 199
igor_v 0:8ad47e2b6f00 200 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
igor_v 0:8ad47e2b6f00 201 /** @brief General Purpose Input/Output (GPIO) register structure definition */
igor_v 0:8ad47e2b6f00 202 typedef struct
igor_v 0:8ad47e2b6f00 203 {
igor_v 0:8ad47e2b6f00 204 union {
igor_v 0:8ad47e2b6f00 205 __IO uint32_t FIODIR; /* !< Offset: 0x00 Port direction (R/W) */
igor_v 0:8ad47e2b6f00 206 struct {
igor_v 0:8ad47e2b6f00 207 __IO uint16_t FIODIRL;
igor_v 0:8ad47e2b6f00 208 __IO uint16_t FIODIRH;
igor_v 0:8ad47e2b6f00 209 };
igor_v 0:8ad47e2b6f00 210 struct {
igor_v 0:8ad47e2b6f00 211 __IO uint8_t FIODIR0;
igor_v 0:8ad47e2b6f00 212 __IO uint8_t FIODIR1;
igor_v 0:8ad47e2b6f00 213 __IO uint8_t FIODIR2;
igor_v 0:8ad47e2b6f00 214 __IO uint8_t FIODIR3;
igor_v 0:8ad47e2b6f00 215 };
igor_v 0:8ad47e2b6f00 216 };
igor_v 0:8ad47e2b6f00 217 uint32_t RESERVED0[3];
igor_v 0:8ad47e2b6f00 218 union {
igor_v 0:8ad47e2b6f00 219 __IO uint32_t FIOMASK; /* !< Offset: 0x10 Port mask (R/W) */
igor_v 0:8ad47e2b6f00 220 struct {
igor_v 0:8ad47e2b6f00 221 __IO uint16_t FIOMASKL;
igor_v 0:8ad47e2b6f00 222 __IO uint16_t FIOMASKH;
igor_v 0:8ad47e2b6f00 223 };
igor_v 0:8ad47e2b6f00 224 struct {
igor_v 0:8ad47e2b6f00 225 __IO uint8_t FIOMASK0;
igor_v 0:8ad47e2b6f00 226 __IO uint8_t FIOMASK1;
igor_v 0:8ad47e2b6f00 227 __IO uint8_t FIOMASK2;
igor_v 0:8ad47e2b6f00 228 __IO uint8_t FIOMASK3;
igor_v 0:8ad47e2b6f00 229 };
igor_v 0:8ad47e2b6f00 230 };
igor_v 0:8ad47e2b6f00 231 union {
igor_v 0:8ad47e2b6f00 232 __IO uint32_t FIOPIN; /* !< Offset: 0x14 Port value (R/W) */
igor_v 0:8ad47e2b6f00 233 struct {
igor_v 0:8ad47e2b6f00 234 __IO uint16_t FIOPINL;
igor_v 0:8ad47e2b6f00 235 __IO uint16_t FIOPINH;
igor_v 0:8ad47e2b6f00 236 };
igor_v 0:8ad47e2b6f00 237 struct {
igor_v 0:8ad47e2b6f00 238 __IO uint8_t FIOPIN0;
igor_v 0:8ad47e2b6f00 239 __IO uint8_t FIOPIN1;
igor_v 0:8ad47e2b6f00 240 __IO uint8_t FIOPIN2;
igor_v 0:8ad47e2b6f00 241 __IO uint8_t FIOPIN3;
igor_v 0:8ad47e2b6f00 242 };
igor_v 0:8ad47e2b6f00 243 };
igor_v 0:8ad47e2b6f00 244 union {
igor_v 0:8ad47e2b6f00 245 __IO uint32_t FIOSET; /* !< Offset: 0x18 Port output set (R/W) */
igor_v 0:8ad47e2b6f00 246 struct {
igor_v 0:8ad47e2b6f00 247 __IO uint16_t FIOSETL;
igor_v 0:8ad47e2b6f00 248 __IO uint16_t FIOSETH;
igor_v 0:8ad47e2b6f00 249 };
igor_v 0:8ad47e2b6f00 250 struct {
igor_v 0:8ad47e2b6f00 251 __IO uint8_t FIOSET0;
igor_v 0:8ad47e2b6f00 252 __IO uint8_t FIOSET1;
igor_v 0:8ad47e2b6f00 253 __IO uint8_t FIOSET2;
igor_v 0:8ad47e2b6f00 254 __IO uint8_t FIOSET3;
igor_v 0:8ad47e2b6f00 255 };
igor_v 0:8ad47e2b6f00 256 };
igor_v 0:8ad47e2b6f00 257 union {
igor_v 0:8ad47e2b6f00 258 __O uint32_t FIOCLR; /* !< Offset: 0x1C Port output clear (R/W) */
igor_v 0:8ad47e2b6f00 259 struct {
igor_v 0:8ad47e2b6f00 260 __O uint16_t FIOCLRL;
igor_v 0:8ad47e2b6f00 261 __O uint16_t FIOCLRH;
igor_v 0:8ad47e2b6f00 262 };
igor_v 0:8ad47e2b6f00 263 struct {
igor_v 0:8ad47e2b6f00 264 __O uint8_t FIOCLR0;
igor_v 0:8ad47e2b6f00 265 __O uint8_t FIOCLR1;
igor_v 0:8ad47e2b6f00 266 __O uint8_t FIOCLR2;
igor_v 0:8ad47e2b6f00 267 __O uint8_t FIOCLR3;
igor_v 0:8ad47e2b6f00 268 };
igor_v 0:8ad47e2b6f00 269 };
igor_v 0:8ad47e2b6f00 270 } LPC_GPIO_TypeDef;
igor_v 0:8ad47e2b6f00 271
igor_v 0:8ad47e2b6f00 272 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
igor_v 0:8ad47e2b6f00 273 typedef struct
igor_v 0:8ad47e2b6f00 274 {
igor_v 0:8ad47e2b6f00 275 __I uint32_t IntStatus; /*!< Offset: 0x000 (R/ ) GPIO overall Interrupt Status Register */
igor_v 0:8ad47e2b6f00 276 __I uint32_t IO0IntStatR; /*!< Offset: 0x004 (R/ ) GPIO Interrupt Status Register 0 for Rising edge */
igor_v 0:8ad47e2b6f00 277 __I uint32_t IO0IntStatF; /*!< Offset: 0x008 (R/ ) GPIO Interrupt Status Register 0 for Falling edge */
igor_v 0:8ad47e2b6f00 278 __O uint32_t IO0IntClr; /*!< Offset: 0x00C (R/W) GPIO Interrupt Clear Register 0 */
igor_v 0:8ad47e2b6f00 279 __IO uint32_t IO0IntEnR; /*!< Offset: 0x010 ( /W) GPIO Interrupt Enable Register 0 for Rising edge */
igor_v 0:8ad47e2b6f00 280 __IO uint32_t IO0IntEnF; /*!< Offset: 0x014 (R/W) GPIO Interrupt Enable Register 0 for Falling edge */
igor_v 0:8ad47e2b6f00 281 uint32_t RESERVED0[3];
igor_v 0:8ad47e2b6f00 282 __I uint32_t IO2IntStatR; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Rising edge */
igor_v 0:8ad47e2b6f00 283 __I uint32_t IO2IntStatF; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Falling edge */
igor_v 0:8ad47e2b6f00 284 __O uint32_t IO2IntClr; /*!< Offset: 0x000 ( /W) GPIO Interrupt Clear Register 2 */
igor_v 0:8ad47e2b6f00 285 __IO uint32_t IO2IntEnR; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Rising edge */
igor_v 0:8ad47e2b6f00 286 __IO uint32_t IO2IntEnF; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Falling edge */
igor_v 0:8ad47e2b6f00 287 } LPC_GPIOINT_TypeDef;
igor_v 0:8ad47e2b6f00 288
igor_v 0:8ad47e2b6f00 289 /*------------- Timer (TIM) --------------------------------------------------*/
igor_v 0:8ad47e2b6f00 290 /** @brief Timer (TIM) register structure definition */
igor_v 0:8ad47e2b6f00 291 typedef struct
igor_v 0:8ad47e2b6f00 292 {
igor_v 0:8ad47e2b6f00 293 __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */
igor_v 0:8ad47e2b6f00 294 __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */
igor_v 0:8ad47e2b6f00 295 __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */
igor_v 0:8ad47e2b6f00 296 __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */
igor_v 0:8ad47e2b6f00 297 __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */
igor_v 0:8ad47e2b6f00 298 __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */
igor_v 0:8ad47e2b6f00 299 __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */
igor_v 0:8ad47e2b6f00 300 __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */
igor_v 0:8ad47e2b6f00 301 __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */
igor_v 0:8ad47e2b6f00 302 __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */
igor_v 0:8ad47e2b6f00 303 __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */
igor_v 0:8ad47e2b6f00 304 __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */
igor_v 0:8ad47e2b6f00 305 __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register */
igor_v 0:8ad47e2b6f00 306 uint32_t RESERVED0[2];
igor_v 0:8ad47e2b6f00 307 __IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */
igor_v 0:8ad47e2b6f00 308 uint32_t RESERVED1[12];
igor_v 0:8ad47e2b6f00 309 __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */
igor_v 0:8ad47e2b6f00 310 } LPC_TIM_TypeDef;
igor_v 0:8ad47e2b6f00 311
igor_v 0:8ad47e2b6f00 312 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
igor_v 0:8ad47e2b6f00 313 /** @brief Pulse-Width Modulation (PWM) register structure definition */
igor_v 0:8ad47e2b6f00 314 typedef struct
igor_v 0:8ad47e2b6f00 315 {
igor_v 0:8ad47e2b6f00 316 __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */
igor_v 0:8ad47e2b6f00 317 __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register. Register */
igor_v 0:8ad47e2b6f00 318 __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */
igor_v 0:8ad47e2b6f00 319 __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */
igor_v 0:8ad47e2b6f00 320 __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */
igor_v 0:8ad47e2b6f00 321 __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */
igor_v 0:8ad47e2b6f00 322 __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */
igor_v 0:8ad47e2b6f00 323 __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */
igor_v 0:8ad47e2b6f00 324 __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */
igor_v 0:8ad47e2b6f00 325 __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */
igor_v 0:8ad47e2b6f00 326 __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */
igor_v 0:8ad47e2b6f00 327 __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */
igor_v 0:8ad47e2b6f00 328 __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register 1 */
igor_v 0:8ad47e2b6f00 329 __I uint32_t CR2; /*!< Offset: 0x034 (R/ ) Capture Register 2 */
igor_v 0:8ad47e2b6f00 330 __I uint32_t CR3; /*!< Offset: 0x038 (R/ ) Capture Register 3 */
igor_v 0:8ad47e2b6f00 331 uint32_t RESERVED0;
igor_v 0:8ad47e2b6f00 332 __IO uint32_t MR4; /*!< Offset: 0x040 (R/W) Match Register 4 */
igor_v 0:8ad47e2b6f00 333 __IO uint32_t MR5; /*!< Offset: 0x044 (R/W) Match Register 5 */
igor_v 0:8ad47e2b6f00 334 __IO uint32_t MR6; /*!< Offset: 0x048 (R/W) Match Register 6 */
igor_v 0:8ad47e2b6f00 335 __IO uint32_t PCR; /*!< Offset: 0x04C (R/W) PWM Control Register */
igor_v 0:8ad47e2b6f00 336 __IO uint32_t LER; /*!< Offset: 0x050 (R/W) Load Enable Register */
igor_v 0:8ad47e2b6f00 337 uint32_t RESERVED1[7];
igor_v 0:8ad47e2b6f00 338 __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */
igor_v 0:8ad47e2b6f00 339 } LPC_PWM_TypeDef;
igor_v 0:8ad47e2b6f00 340
igor_v 0:8ad47e2b6f00 341 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
igor_v 0:8ad47e2b6f00 342 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
igor_v 0:8ad47e2b6f00 343 typedef struct
igor_v 0:8ad47e2b6f00 344 {
igor_v 0:8ad47e2b6f00 345 union {
igor_v 0:8ad47e2b6f00 346 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
igor_v 0:8ad47e2b6f00 347 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
igor_v 0:8ad47e2b6f00 348 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
igor_v 0:8ad47e2b6f00 349 };
igor_v 0:8ad47e2b6f00 350 union {
igor_v 0:8ad47e2b6f00 351 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
igor_v 0:8ad47e2b6f00 352 __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register (R/W) */
igor_v 0:8ad47e2b6f00 353 };
igor_v 0:8ad47e2b6f00 354 union {
igor_v 0:8ad47e2b6f00 355 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
igor_v 0:8ad47e2b6f00 356 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
igor_v 0:8ad47e2b6f00 357 };
igor_v 0:8ad47e2b6f00 358 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
igor_v 0:8ad47e2b6f00 359 uint32_t RESERVED0;
igor_v 0:8ad47e2b6f00 360 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
igor_v 0:8ad47e2b6f00 361 uint32_t RESERVED1;
igor_v 0:8ad47e2b6f00 362 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
igor_v 0:8ad47e2b6f00 363 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
igor_v 0:8ad47e2b6f00 364 __IO uint32_t ICR; /*!< Offset: 0x024 IrDA Control Register (R/W) */
igor_v 0:8ad47e2b6f00 365 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
igor_v 0:8ad47e2b6f00 366 uint32_t RESERVED2;
igor_v 0:8ad47e2b6f00 367 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
igor_v 0:8ad47e2b6f00 368 } LPC_UART_TypeDef;
igor_v 0:8ad47e2b6f00 369
igor_v 0:8ad47e2b6f00 370 /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
igor_v 0:8ad47e2b6f00 371 typedef struct
igor_v 0:8ad47e2b6f00 372 {
igor_v 0:8ad47e2b6f00 373 union {
igor_v 0:8ad47e2b6f00 374 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
igor_v 0:8ad47e2b6f00 375 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
igor_v 0:8ad47e2b6f00 376 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
igor_v 0:8ad47e2b6f00 377 };
igor_v 0:8ad47e2b6f00 378 union {
igor_v 0:8ad47e2b6f00 379 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
igor_v 0:8ad47e2b6f00 380 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
igor_v 0:8ad47e2b6f00 381 };
igor_v 0:8ad47e2b6f00 382 union {
igor_v 0:8ad47e2b6f00 383 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
igor_v 0:8ad47e2b6f00 384 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
igor_v 0:8ad47e2b6f00 385 };
igor_v 0:8ad47e2b6f00 386 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
igor_v 0:8ad47e2b6f00 387 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
igor_v 0:8ad47e2b6f00 388 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
igor_v 0:8ad47e2b6f00 389 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
igor_v 0:8ad47e2b6f00 390 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
igor_v 0:8ad47e2b6f00 391 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
igor_v 0:8ad47e2b6f00 392 uint32_t RESERVED0;
igor_v 0:8ad47e2b6f00 393 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
igor_v 0:8ad47e2b6f00 394 uint32_t RESERVED1;
igor_v 0:8ad47e2b6f00 395 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
igor_v 0:8ad47e2b6f00 396 uint32_t RESERVED2[6];
igor_v 0:8ad47e2b6f00 397 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
igor_v 0:8ad47e2b6f00 398 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
igor_v 0:8ad47e2b6f00 399 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
igor_v 0:8ad47e2b6f00 400 } LPC_UART1_TypeDef;
igor_v 0:8ad47e2b6f00 401
igor_v 0:8ad47e2b6f00 402 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
igor_v 0:8ad47e2b6f00 403 /** @brief Serial Peripheral Interface (SPI) register structure definition */
igor_v 0:8ad47e2b6f00 404 typedef struct
igor_v 0:8ad47e2b6f00 405 {
igor_v 0:8ad47e2b6f00 406 __IO uint32_t SPCR; /*!< Offset: 0x000 SPI Control Register (R/W) */
igor_v 0:8ad47e2b6f00 407 __I uint32_t SPSR; /*!< Offset: 0x004 SPI Status Register (R/) */
igor_v 0:8ad47e2b6f00 408 __IO uint32_t SPDR; /*!< Offset: 0x008 SPI Data Register (R/W) */
igor_v 0:8ad47e2b6f00 409 __IO uint32_t SPCCR; /*!< Offset: 0x00C SPI Clock Counter Register (R/W) */
igor_v 0:8ad47e2b6f00 410 uint32_t RESERVED0[3];
igor_v 0:8ad47e2b6f00 411 __IO uint32_t SPINT; /*!< Offset: 0x01C SPI Interrupt Flag Register (R/W) */
igor_v 0:8ad47e2b6f00 412 } LPC_SPI_TypeDef;
igor_v 0:8ad47e2b6f00 413
igor_v 0:8ad47e2b6f00 414 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
igor_v 0:8ad47e2b6f00 415 /** @brief Synchronous Serial Communication (SSP) register structure definition */
igor_v 0:8ad47e2b6f00 416 typedef struct
igor_v 0:8ad47e2b6f00 417 {
igor_v 0:8ad47e2b6f00 418 __IO uint32_t CR0; /*!< Offset: 0x000 (R/W) Control Register 0 */
igor_v 0:8ad47e2b6f00 419 __IO uint32_t CR1; /*!< Offset: 0x004 (R/W) Control Register 1 */
igor_v 0:8ad47e2b6f00 420 __IO uint32_t DR; /*!< Offset: 0x008 (R/W) Data Register */
igor_v 0:8ad47e2b6f00 421 __I uint32_t SR; /*!< Offset: 0x00C (R/ ) Status Register */
igor_v 0:8ad47e2b6f00 422 __IO uint32_t CPSR; /*!< Offset: 0x010 (R/W) Clock Prescale Register */
igor_v 0:8ad47e2b6f00 423 __IO uint32_t IMSC; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */
igor_v 0:8ad47e2b6f00 424 __IO uint32_t RIS; /*!< Offset: 0x018 (R/W) Raw Interrupt Status Register */
igor_v 0:8ad47e2b6f00 425 __IO uint32_t MIS; /*!< Offset: 0x01C (R/W) Masked Interrupt Status Register */
igor_v 0:8ad47e2b6f00 426 __IO uint32_t ICR; /*!< Offset: 0x020 (R/W) SSPICR Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 427 __IO uint32_t DMACR; /*!< Offset: 0x024 (R/W) DMA Control Register */
igor_v 0:8ad47e2b6f00 428 } LPC_SSP_TypeDef;
igor_v 0:8ad47e2b6f00 429
igor_v 0:8ad47e2b6f00 430 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
igor_v 0:8ad47e2b6f00 431 /** @brief Inter-Integrated Circuit (I2C) register structure definition */
igor_v 0:8ad47e2b6f00 432 typedef struct
igor_v 0:8ad47e2b6f00 433 {
igor_v 0:8ad47e2b6f00 434 __IO uint32_t CONSET; /*!< Offset: 0x000 (R/W) I2C Control Set Register */
igor_v 0:8ad47e2b6f00 435 __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) I2C Status Register */
igor_v 0:8ad47e2b6f00 436 __IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C Data Register */
igor_v 0:8ad47e2b6f00 437 __IO uint32_t ADR0; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */
igor_v 0:8ad47e2b6f00 438 __IO uint32_t SCLH; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */
igor_v 0:8ad47e2b6f00 439 __IO uint32_t SCLL; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */
igor_v 0:8ad47e2b6f00 440 __O uint32_t CONCLR; /*!< Offset: 0x018 (R/W) I2C Control Clear Register */
igor_v 0:8ad47e2b6f00 441 __IO uint32_t MMCTRL; /*!< Offset: 0x01C (R/W) Monitor mode control register */
igor_v 0:8ad47e2b6f00 442 __IO uint32_t ADR1; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */
igor_v 0:8ad47e2b6f00 443 __IO uint32_t ADR2; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */
igor_v 0:8ad47e2b6f00 444 __IO uint32_t ADR3; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */
igor_v 0:8ad47e2b6f00 445 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C (R/ ) Data buffer Register */
igor_v 0:8ad47e2b6f00 446 __IO uint32_t MASK0; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */
igor_v 0:8ad47e2b6f00 447 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */
igor_v 0:8ad47e2b6f00 448 __IO uint32_t MASK2; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */
igor_v 0:8ad47e2b6f00 449 __IO uint32_t MASK3; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */
igor_v 0:8ad47e2b6f00 450 } LPC_I2C_TypeDef;
igor_v 0:8ad47e2b6f00 451
igor_v 0:8ad47e2b6f00 452 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
igor_v 0:8ad47e2b6f00 453 /** @brief Inter IC Sound (I2S) register structure definition */
igor_v 0:8ad47e2b6f00 454 typedef struct
igor_v 0:8ad47e2b6f00 455 {
igor_v 0:8ad47e2b6f00 456 __IO uint32_t DAO; /*!< Offset: 0x000 (R/W) Digital Audio Output Register */
igor_v 0:8ad47e2b6f00 457 __IO uint32_t DAI; /*!< Offset: 0x004 (R/W) Digital Audio Input Register */
igor_v 0:8ad47e2b6f00 458 __O uint32_t TXFIFO; /*!< Offset: 0x008 ( /W) Transmit FIFO */
igor_v 0:8ad47e2b6f00 459 __I uint32_t RXFIFO; /*!< Offset: 0x00C (R/ ) Receive FIFO */
igor_v 0:8ad47e2b6f00 460 __I uint32_t STATE; /*!< Offset: 0x010 (R/W) Status Feedback Register */
igor_v 0:8ad47e2b6f00 461 __IO uint32_t DMA1; /*!< Offset: 0x014 (R/W) DMA Configuration Register 1 */
igor_v 0:8ad47e2b6f00 462 __IO uint32_t DMA2; /*!< Offset: 0x018 (R/W) DMA Configuration Register 2 */
igor_v 0:8ad47e2b6f00 463 __IO uint32_t IRQ; /*!< Offset: 0x01C (R/W) Interrupt Request Control Register */
igor_v 0:8ad47e2b6f00 464 __IO uint32_t TXRATE; /*!< Offset: 0x020 (R/W) Transmit reference clock divider Register */
igor_v 0:8ad47e2b6f00 465 __IO uint32_t RXRATE; /*!< Offset: 0x024 (R/W) Receive reference clock divider Register */
igor_v 0:8ad47e2b6f00 466 __IO uint32_t TXBITRATE; /*!< Offset: 0x028 (R/W) Transmit bit rate divider Register */
igor_v 0:8ad47e2b6f00 467 __IO uint32_t RXBITRATE; /*!< Offset: 0x02C (R/W) Receive bit rate divider Register */
igor_v 0:8ad47e2b6f00 468 __IO uint32_t TXMODE; /*!< Offset: 0x030 (R/W) Transmit mode control Register */
igor_v 0:8ad47e2b6f00 469 __IO uint32_t RXMODE; /*!< Offset: 0x034 (R/W) Receive mode control Register */
igor_v 0:8ad47e2b6f00 470 } LPC_I2S_TypeDef;
igor_v 0:8ad47e2b6f00 471
igor_v 0:8ad47e2b6f00 472 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
igor_v 0:8ad47e2b6f00 473 /** @brief Repetitive Interrupt Timer (RIT) register structure definition */
igor_v 0:8ad47e2b6f00 474 typedef struct
igor_v 0:8ad47e2b6f00 475 {
igor_v 0:8ad47e2b6f00 476 __IO uint32_t RICOMPVAL;
igor_v 0:8ad47e2b6f00 477 __IO uint32_t RIMASK;
igor_v 0:8ad47e2b6f00 478 __IO uint32_t RICTRL;
igor_v 0:8ad47e2b6f00 479 __IO uint32_t RICOUNTER;
igor_v 0:8ad47e2b6f00 480 } LPC_RIT_TypeDef;
igor_v 0:8ad47e2b6f00 481
igor_v 0:8ad47e2b6f00 482 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
igor_v 0:8ad47e2b6f00 483 /** @brief Real-Time Clock (RTC) register structure definition */
igor_v 0:8ad47e2b6f00 484 typedef struct
igor_v 0:8ad47e2b6f00 485 {
igor_v 0:8ad47e2b6f00 486 __IO uint32_t ILR; /*!< Offset: 0x000 (R/W) Interrupt Location Register */
igor_v 0:8ad47e2b6f00 487 uint32_t RESERVED0;
igor_v 0:8ad47e2b6f00 488 __IO uint32_t CCR; /*!< Offset: 0x008 (R/W) Clock Control Register */
igor_v 0:8ad47e2b6f00 489 __IO uint32_t CIIR; /*!< Offset: 0x00C (R/W) Counter Increment Interrupt Register */
igor_v 0:8ad47e2b6f00 490 __IO uint32_t AMR; /*!< Offset: 0x010 (R/W) Alarm Mask Register */
igor_v 0:8ad47e2b6f00 491 __I uint32_t CTIME0; /*!< Offset: 0x014 (R/ ) Consolidated Time Register 0 */
igor_v 0:8ad47e2b6f00 492 __I uint32_t CTIME1; /*!< Offset: 0x018 (R/ ) Consolidated Time Register 1 */
igor_v 0:8ad47e2b6f00 493 __I uint32_t CTIME2; /*!< Offset: 0x01C (R/ ) Consolidated Time Register 2 */
igor_v 0:8ad47e2b6f00 494 __IO uint32_t SEC; /*!< Offset: 0x020 (R/W) Seconds Counter Register */
igor_v 0:8ad47e2b6f00 495 __IO uint32_t MIN; /*!< Offset: 0x024 (R/W) Minutes Register */
igor_v 0:8ad47e2b6f00 496 __IO uint32_t HOUR; /*!< Offset: 0x028 (R/W) Hours Register */
igor_v 0:8ad47e2b6f00 497 __IO uint32_t DOM; /*!< Offset: 0x02C (R/W) Day of Month Register */
igor_v 0:8ad47e2b6f00 498 __IO uint32_t DOW; /*!< Offset: 0x030 (R/W) Day of Week Register */
igor_v 0:8ad47e2b6f00 499 __IO uint32_t DOY; /*!< Offset: 0x034 (R/W) Day of Year Register */
igor_v 0:8ad47e2b6f00 500 __IO uint32_t MONTH; /*!< Offset: 0x038 (R/W) Months Register */
igor_v 0:8ad47e2b6f00 501 __IO uint32_t YEAR; /*!< Offset: 0x03C (R/W) Years Register */
igor_v 0:8ad47e2b6f00 502 __IO uint32_t CALIBRATION; /*!< Offset: 0x040 (R/W) Calibration Value Register */
igor_v 0:8ad47e2b6f00 503 __IO uint32_t GPREG0; /*!< Offset: 0x044 (R/W) General Purpose Register 0 */
igor_v 0:8ad47e2b6f00 504 __IO uint32_t GPREG1; /*!< Offset: 0x048 (R/W) General Purpose Register 1 */
igor_v 0:8ad47e2b6f00 505 __IO uint32_t GPREG2; /*!< Offset: 0x04C (R/W) General Purpose Register 2 */
igor_v 0:8ad47e2b6f00 506 __IO uint32_t GPREG3; /*!< Offset: 0x050 (R/W) General Purpose Register 3 */
igor_v 0:8ad47e2b6f00 507 __IO uint32_t GPREG4; /*!< Offset: 0x054 (R/W) General Purpose Register 4 */
igor_v 0:8ad47e2b6f00 508 __IO uint32_t RTC_AUXEN; /*!< Offset: 0x058 (R/W) RTC Auxiliary Enable Register */
igor_v 0:8ad47e2b6f00 509 __IO uint32_t RTC_AUX; /*!< Offset: 0x05C (R/W) RTC Auxiliary Control Register */
igor_v 0:8ad47e2b6f00 510 __IO uint32_t ALSEC; /*!< Offset: 0x060 (R/W) Alarm value for Seconds */
igor_v 0:8ad47e2b6f00 511 __IO uint32_t ALMIN; /*!< Offset: 0x064 (R/W) Alarm value for Minutes */
igor_v 0:8ad47e2b6f00 512 __IO uint32_t ALHOUR; /*!< Offset: 0x068 (R/W) Alarm value for Hours */
igor_v 0:8ad47e2b6f00 513 __IO uint32_t ALDOM; /*!< Offset: 0x06C (R/W) Alarm value for Day of Month */
igor_v 0:8ad47e2b6f00 514 __IO uint32_t ALDOW; /*!< Offset: 0x070 (R/W) Alarm value for Day of Week */
igor_v 0:8ad47e2b6f00 515 __IO uint32_t ALDOY; /*!< Offset: 0x074 (R/W) Alarm value for Day of Year */
igor_v 0:8ad47e2b6f00 516 __IO uint32_t ALMON; /*!< Offset: 0x078 (R/W) Alarm value for Months */
igor_v 0:8ad47e2b6f00 517 __IO uint32_t ALYEAR; /*!< Offset: 0x07C (R/W) Alarm value for Year */
igor_v 0:8ad47e2b6f00 518 } LPC_RTC_TypeDef;
igor_v 0:8ad47e2b6f00 519
igor_v 0:8ad47e2b6f00 520 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
igor_v 0:8ad47e2b6f00 521 /** @brief Watchdog Timer (WDT) register structure definition */
igor_v 0:8ad47e2b6f00 522 typedef struct
igor_v 0:8ad47e2b6f00 523 {
igor_v 0:8ad47e2b6f00 524 __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) Watchdog mode Register */
igor_v 0:8ad47e2b6f00 525 __IO uint32_t TC; /*!< Offset: 0x004 (R/W) Watchdog timer constant Register */
igor_v 0:8ad47e2b6f00 526 __O uint32_t FEED; /*!< Offset: 0x008 ( /W) Watchdog feed sequence Register */
igor_v 0:8ad47e2b6f00 527 __I uint32_t TV; /*!< Offset: 0x00C (R/ ) Watchdog timer value Register */
igor_v 0:8ad47e2b6f00 528 __IO uint32_t WDCLKSEL;
igor_v 0:8ad47e2b6f00 529 } LPC_WDT_TypeDef;
igor_v 0:8ad47e2b6f00 530
igor_v 0:8ad47e2b6f00 531 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
igor_v 0:8ad47e2b6f00 532 /** @brief Analog-to-Digital Converter (ADC) register structure definition */
igor_v 0:8ad47e2b6f00 533 typedef struct
igor_v 0:8ad47e2b6f00 534 {
igor_v 0:8ad47e2b6f00 535 __IO uint32_t CR; /*!< Offset: 0x000 (R/W) A/D Control Register */
igor_v 0:8ad47e2b6f00 536 __IO uint32_t GDR; /*!< Offset: 0x004 (R/W) A/D Global Data Register */
igor_v 0:8ad47e2b6f00 537 uint32_t RESERVED0;
igor_v 0:8ad47e2b6f00 538 __IO uint32_t INTEN; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 539 __I uint32_t DR[8]; /*!< Offset: 0x010 (R/ ) A/D Channel # Data Register */
igor_v 0:8ad47e2b6f00 540 __I uint32_t STAT; /*!< Offset: 0x030 (R/ ) A/D Status Register */
igor_v 0:8ad47e2b6f00 541 __IO uint32_t ADTRM; /*!< Offset: 0x034 (R/W) ADC trim Register */
igor_v 0:8ad47e2b6f00 542 } LPC_ADC_TypeDef;
igor_v 0:8ad47e2b6f00 543
igor_v 0:8ad47e2b6f00 544 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
igor_v 0:8ad47e2b6f00 545 /** @brief Digital-to-Analog Converter (DAC) register structure definition */
igor_v 0:8ad47e2b6f00 546 typedef struct
igor_v 0:8ad47e2b6f00 547 {
Kovalev_D 197:7a05523bf588 548 __IO uint32_t DACR; /*!< Offset: 0x000 (R/W) D/A Converter Register */
igor_v 0:8ad47e2b6f00 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) DAC Control register */
igor_v 0:8ad47e2b6f00 550 __IO uint32_t CNTVAL; /*!< Offset: 0x008 (R/W) DAC Counter Value Register */
igor_v 0:8ad47e2b6f00 551 } LPC_DAC_TypeDef;
igor_v 0:8ad47e2b6f00 552
igor_v 0:8ad47e2b6f00 553 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
igor_v 0:8ad47e2b6f00 554 /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
igor_v 0:8ad47e2b6f00 555 typedef struct
igor_v 0:8ad47e2b6f00 556 {
igor_v 0:8ad47e2b6f00 557 __I uint32_t CON; /*!< Offset: 0x000 (R/ ) PWM Control read address Register */
igor_v 0:8ad47e2b6f00 558 __O uint32_t CON_SET; /*!< Offset: 0x004 ( /W) PWM Control set address Register */
igor_v 0:8ad47e2b6f00 559 __O uint32_t CON_CLR; /*!< Offset: 0x008 ( /W) PWM Control clear address Register */
igor_v 0:8ad47e2b6f00 560 __I uint32_t CAPCON; /*!< Offset: 0x00C (R/ ) Capture Control read address Register */
igor_v 0:8ad47e2b6f00 561 __O uint32_t CAPCON_SET; /*!< Offset: 0x010 ( /W) Capture Control set address Register */
igor_v 0:8ad47e2b6f00 562 __O uint32_t CAPCON_CLR; /*!< Offset: 0x014 ( /W) Event Control clear address Register */
igor_v 0:8ad47e2b6f00 563 __IO uint32_t TC0; /*!< Offset: 0x018 (R/W) Timer Counter Register, channel 0 */
igor_v 0:8ad47e2b6f00 564 __IO uint32_t TC1; /*!< Offset: 0x01C (R/W) Timer Counter Register, channel 1 */
igor_v 0:8ad47e2b6f00 565 __IO uint32_t TC2; /*!< Offset: 0x020 (R/W) Timer Counter Register, channel 2 */
igor_v 0:8ad47e2b6f00 566 __IO uint32_t LIM0; /*!< Offset: 0x024 (R/W) Limit Register, channel 0 */
igor_v 0:8ad47e2b6f00 567 __IO uint32_t LIM1; /*!< Offset: 0x028 (R/W) Limit Register, channel 1 */
igor_v 0:8ad47e2b6f00 568 __IO uint32_t LIM2; /*!< Offset: 0x02C (R/W) Limit Register, channel 2 */
igor_v 0:8ad47e2b6f00 569 __IO uint32_t MAT0; /*!< Offset: 0x030 (R/W) Match Register, channel 0 */
igor_v 0:8ad47e2b6f00 570 __IO uint32_t MAT1; /*!< Offset: 0x034 (R/W) Match Register, channel 1 */
igor_v 0:8ad47e2b6f00 571 __IO uint32_t MAT2; /*!< Offset: 0x038 (R/W) Match Register, channel 2 */
igor_v 0:8ad47e2b6f00 572 __IO uint32_t DT; /*!< Offset: 0x03C (R/W) Dead time Register */
igor_v 0:8ad47e2b6f00 573 __IO uint32_t CP; /*!< Offset: 0x040 (R/W) Commutation Pattern Register */
igor_v 0:8ad47e2b6f00 574 __IO uint32_t CAP0; /*!< Offset: 0x044 (R/W) Capture Register, channel 0 */
igor_v 0:8ad47e2b6f00 575 __IO uint32_t CAP1; /*!< Offset: 0x048 (R/W) Capture Register, channel 1 */
igor_v 0:8ad47e2b6f00 576 __IO uint32_t CAP2; /*!< Offset: 0x04C (R/W) Capture Register, channel 2 */
igor_v 0:8ad47e2b6f00 577 __I uint32_t INTEN; /*!< Offset: 0x050 (R/ ) Interrupt Enable read Register */
igor_v 0:8ad47e2b6f00 578 __O uint32_t INTEN_SET; /*!< Offset: 0x054 ( /W) Interrupt Enable set address Register */
igor_v 0:8ad47e2b6f00 579 __O uint32_t INTEN_CLR; /*!< Offset: 0x058 ( /W) Interrupt Enable clear address Register */
igor_v 0:8ad47e2b6f00 580 __I uint32_t CNTCON; /*!< Offset: 0x05C (R/ ) Count Control read address Register */
igor_v 0:8ad47e2b6f00 581 __O uint32_t CNTCON_SET; /*!< Offset: 0x060 ( /W) Count Control set address Register */
igor_v 0:8ad47e2b6f00 582 __O uint32_t CNTCON_CLR; /*!< Offset: 0x064 ( /W) Count Control clear address Register */
igor_v 0:8ad47e2b6f00 583 __I uint32_t INTF; /*!< Offset: 0x068 (R/ ) Interrupt flags read address Register */
igor_v 0:8ad47e2b6f00 584 __O uint32_t INTF_SET; /*!< Offset: 0x06C ( /W) Interrupt flags set address Register */
igor_v 0:8ad47e2b6f00 585 __O uint32_t INTF_CLR; /*!< Offset: 0x070 ( /W) Interrupt flags clear address Register */
igor_v 0:8ad47e2b6f00 586 __O uint32_t CAP_CLR; /*!< Offset: 0x074 ( /W) Capture clear address Register */
igor_v 0:8ad47e2b6f00 587 } LPC_MCPWM_TypeDef;
igor_v 0:8ad47e2b6f00 588
igor_v 0:8ad47e2b6f00 589 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
igor_v 0:8ad47e2b6f00 590 /** @brief Quadrature Encoder Interface (QEI) register structure definition */
igor_v 0:8ad47e2b6f00 591 typedef struct
igor_v 0:8ad47e2b6f00 592 {
igor_v 0:8ad47e2b6f00 593 __O uint32_t CON; /*!< Offset: 0x000 ( /W) Control Register */
igor_v 0:8ad47e2b6f00 594 __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) Encoder Status Register */
igor_v 0:8ad47e2b6f00 595 __IO uint32_t CONF; /*!< Offset: 0x008 (R/W) Configuration Register */
igor_v 0:8ad47e2b6f00 596 __I uint32_t POS; /*!< Offset: 0x00C (R/ ) Position Register */
igor_v 0:8ad47e2b6f00 597 __IO uint32_t MAXPOS; /*!< Offset: 0x010 (R/W) Maximum position Register */
igor_v 0:8ad47e2b6f00 598 __IO uint32_t CMPOS0; /*!< Offset: 0x014 (R/W) Position compare Register 0 */
igor_v 0:8ad47e2b6f00 599 __IO uint32_t CMPOS1; /*!< Offset: 0x018 (R/W) Position compare Register 1 */
igor_v 0:8ad47e2b6f00 600 __IO uint32_t CMPOS2; /*!< Offset: 0x01C (R/W) Position compare Register 2 */
igor_v 0:8ad47e2b6f00 601 __I uint32_t INXCNT; /*!< Offset: 0x020 (R/ ) Index count Register */
igor_v 0:8ad47e2b6f00 602 __IO uint32_t INXCMP0; /*!< Offset: 0x024 (R/W) Index compare Register 0 */
igor_v 0:8ad47e2b6f00 603 __IO uint32_t LOAD; /*!< Offset: 0x028 (R/W) Velocity timer reload Register */
igor_v 0:8ad47e2b6f00 604 __I uint32_t TIME; /*!< Offset: 0x02C (R/ ) Velocity timer Register */
igor_v 0:8ad47e2b6f00 605 __I uint32_t VEL; /*!< Offset: 0x030 (R/ ) Velocity counter Register */
igor_v 0:8ad47e2b6f00 606 __I uint32_t CAP; /*!< Offset: 0x034 (R/ ) Velocity capture Register */
igor_v 0:8ad47e2b6f00 607 __IO uint32_t VELCOMP; /*!< Offset: 0x038 (R/W) Velocity compare Register */
igor_v 0:8ad47e2b6f00 608 __IO uint32_t FILTER;
igor_v 0:8ad47e2b6f00 609 uint32_t RESERVED0[998];
igor_v 0:8ad47e2b6f00 610 __O uint32_t IEC; /*!< Offset: 0xFD8 ( /W) Interrupt enable clear Register */
igor_v 0:8ad47e2b6f00 611 __O uint32_t IES; /*!< Offset: 0xFDC ( /W) Interrupt enable set Register */
igor_v 0:8ad47e2b6f00 612 __I uint32_t INTSTAT; /*!< Offset: 0xFE0 (R/ ) Interrupt status Register */
igor_v 0:8ad47e2b6f00 613 __I uint32_t IE; /*!< Offset: 0xFE4 (R/ ) Interrupt enable Register */
igor_v 0:8ad47e2b6f00 614 __O uint32_t CLR; /*!< Offset: 0xFE8 ( /W) Interrupt status clear Register */
igor_v 0:8ad47e2b6f00 615 __O uint32_t SET; /*!< Offset: 0xFEC ( /W) Interrupt status set Register */
igor_v 0:8ad47e2b6f00 616 } LPC_QEI_TypeDef;
igor_v 0:8ad47e2b6f00 617
igor_v 0:8ad47e2b6f00 618 /*------------- Controller Area Network (CAN) --------------------------------*/
igor_v 0:8ad47e2b6f00 619 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
igor_v 0:8ad47e2b6f00 620 typedef struct
igor_v 0:8ad47e2b6f00 621 {
igor_v 0:8ad47e2b6f00 622 __IO uint32_t mask[512]; /*!< Offset: 0x000 (R/W) Acceptance Filter RAM */
igor_v 0:8ad47e2b6f00 623 } LPC_CANAF_RAM_TypeDef;
igor_v 0:8ad47e2b6f00 624
igor_v 0:8ad47e2b6f00 625 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
igor_v 0:8ad47e2b6f00 626 typedef struct /* Acceptance Filter Registers */
igor_v 0:8ad47e2b6f00 627 {
igor_v 0:8ad47e2b6f00 628 __IO uint32_t AFMR; /*!< Offset: 0x000 (R/W) Acceptance Filter Register */
igor_v 0:8ad47e2b6f00 629 __IO uint32_t SFF_sa; /*!< Offset: 0x004 (R/W) Standard Frame Individual Start Address Register */
igor_v 0:8ad47e2b6f00 630 __IO uint32_t SFF_GRP_sa; /*!< Offset: 0x008 (R/W) Standard Frame Group Start Address Register */
igor_v 0:8ad47e2b6f00 631 __IO uint32_t EFF_sa; /*!< Offset: 0x00C (R/W) Extended Frame Start Address Register */
igor_v 0:8ad47e2b6f00 632 __IO uint32_t EFF_GRP_sa; /*!< Offset: 0x010 (R/W) Extended Frame Group Start Address Register */
igor_v 0:8ad47e2b6f00 633 __IO uint32_t ENDofTable; /*!< Offset: 0x014 (R/W) End of AF Tables Register */
igor_v 0:8ad47e2b6f00 634 __I uint32_t LUTerrAd; /*!< Offset: 0x018 (R/ ) LUT Error Address Register */
igor_v 0:8ad47e2b6f00 635 __I uint32_t LUTerr; /*!< Offset: 0x01C (R/ ) LUT Error Register */
igor_v 0:8ad47e2b6f00 636 __IO uint32_t FCANIE; /*!< Offset: 0x020 (R/W) Global FullCANInterrupt Enable Register */
igor_v 0:8ad47e2b6f00 637 __IO uint32_t FCANIC0; /*!< Offset: 0x024 (R/W) FullCAN Interrupt and Capture Register 0 */
igor_v 0:8ad47e2b6f00 638 __IO uint32_t FCANIC1; /*!< Offset: 0x028 (R/W) FullCAN Interrupt and Capture Register 1 */
igor_v 0:8ad47e2b6f00 639 } LPC_CANAF_TypeDef;
igor_v 0:8ad47e2b6f00 640
igor_v 0:8ad47e2b6f00 641 /** @brief Controller Area Network Central (CANCR) register structure definition */
igor_v 0:8ad47e2b6f00 642 typedef struct /* Central Registers */
igor_v 0:8ad47e2b6f00 643 {
igor_v 0:8ad47e2b6f00 644 __I uint32_t TxSR; /*!< Offset: 0x000 (R/ ) CAN Central Transmit Status Register */
igor_v 0:8ad47e2b6f00 645 __I uint32_t RxSR; /*!< Offset: 0x004 (R/ ) CAN Central Receive Status Register */
igor_v 0:8ad47e2b6f00 646 __I uint32_t MSR; /*!< Offset: 0x008 (R/ ) CAN Central Miscellaneous Register */
igor_v 0:8ad47e2b6f00 647 } LPC_CANCR_TypeDef;
igor_v 0:8ad47e2b6f00 648
igor_v 0:8ad47e2b6f00 649 /** @brief Controller Area Network Controller (CAN) register structure definition */
igor_v 0:8ad47e2b6f00 650 typedef struct /* Controller Registers */
igor_v 0:8ad47e2b6f00 651 {
igor_v 0:8ad47e2b6f00 652 __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) CAN Mode Register */
igor_v 0:8ad47e2b6f00 653 __O uint32_t CMR; /*!< Offset: 0x004 ( /W) CAN Command Register */
igor_v 0:8ad47e2b6f00 654 __IO uint32_t GSR; /*!< Offset: 0x008 (R/W) CAN Global Status Register */
igor_v 0:8ad47e2b6f00 655 __I uint32_t ICR; /*!< Offset: 0x00C (R/ ) CAN Interrupt and Capture Register */
igor_v 0:8ad47e2b6f00 656 __IO uint32_t IER; /*!< Offset: 0x010 (R/W) CAN Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 657 __IO uint32_t BTR; /*!< Offset: 0x014 (R/W) CAN Bus Timing Register */
igor_v 0:8ad47e2b6f00 658 __IO uint32_t EWL; /*!< Offset: 0x018 (R/W) CAN Error Warning Limit Register */
igor_v 0:8ad47e2b6f00 659 __I uint32_t SR; /*!< Offset: 0x01C (R/ ) CAN Status Register */
igor_v 0:8ad47e2b6f00 660 __IO uint32_t RFS; /*!< Offset: 0x020 (R/W) CAN Receive Frame Status Register */
igor_v 0:8ad47e2b6f00 661 __IO uint32_t RID; /*!< Offset: 0x024 (R/W) CAN Receive Identifier Register */
igor_v 0:8ad47e2b6f00 662 __IO uint32_t RDA; /*!< Offset: 0x028 (R/W) CAN Receive Data Register A */
igor_v 0:8ad47e2b6f00 663 __IO uint32_t RDB; /*!< Offset: 0x02C (R/W) CAN Receive Data Register B */
igor_v 0:8ad47e2b6f00 664 __IO uint32_t TFI1; /*!< Offset: 0x030 (R/W) CAN Transmit Frame Information Register 1 */
igor_v 0:8ad47e2b6f00 665 __IO uint32_t TID1; /*!< Offset: 0x034 (R/W) CAN Transmit Identifier Register 1 */
igor_v 0:8ad47e2b6f00 666 __IO uint32_t TDA1; /*!< Offset: 0x038 (R/W) CAN Transmit Data Register A 1 */
igor_v 0:8ad47e2b6f00 667 __IO uint32_t TDB1; /*!< Offset: 0x03C (R/W) CAN Transmit Data Register B 1 */
igor_v 0:8ad47e2b6f00 668 __IO uint32_t TFI2; /*!< Offset: 0x040 (R/W) CAN Transmit Frame Information Register 2 */
igor_v 0:8ad47e2b6f00 669 __IO uint32_t TID2; /*!< Offset: 0x044 (R/W) CAN Transmit Identifier Register 2 */
igor_v 0:8ad47e2b6f00 670 __IO uint32_t TDA2; /*!< Offset: 0x048 (R/W) CAN Transmit Data Register A 2 */
igor_v 0:8ad47e2b6f00 671 __IO uint32_t TDB2; /*!< Offset: 0x04C (R/W) CAN Transmit Data Register B 2 */
igor_v 0:8ad47e2b6f00 672 __IO uint32_t TFI3; /*!< Offset: 0x050 (R/W) CAN Transmit Frame Information Register 3 */
igor_v 0:8ad47e2b6f00 673 __IO uint32_t TID3; /*!< Offset: 0x054 (R/W) CAN Transmit Identifier Register 3 */
igor_v 0:8ad47e2b6f00 674 __IO uint32_t TDA3; /*!< Offset: 0x058 (R/W) CAN Transmit Data Register A 3 */
igor_v 0:8ad47e2b6f00 675 __IO uint32_t TDB3; /*!< Offset: 0x05C (R/W) CAN Transmit Data Register B 3 */
igor_v 0:8ad47e2b6f00 676 } LPC_CAN_TypeDef;
igor_v 0:8ad47e2b6f00 677
igor_v 0:8ad47e2b6f00 678 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
igor_v 0:8ad47e2b6f00 679 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
igor_v 0:8ad47e2b6f00 680 typedef struct /* Common Registers */
igor_v 0:8ad47e2b6f00 681 {
igor_v 0:8ad47e2b6f00 682 __I uint32_t IntStat; /*!< Offset: 0x000 (R/ ) DMA Interrupt Status Register */
igor_v 0:8ad47e2b6f00 683 __I uint32_t IntTCStat; /*!< Offset: 0x004 (R/ ) DMA Interrupt Terminal Count Request Status Register */
igor_v 0:8ad47e2b6f00 684 __O uint32_t IntTCClear; /*!< Offset: 0x008 ( /W) DMA Interrupt Terminal Count Request Clear Register */
igor_v 0:8ad47e2b6f00 685 __I uint32_t IntErrStat; /*!< Offset: 0x00C (R/ ) DMA Interrupt Error Status Register */
igor_v 0:8ad47e2b6f00 686 __O uint32_t IntErrClr; /*!< Offset: 0x010 ( /W) DMA Interrupt Error Clear Register */
igor_v 0:8ad47e2b6f00 687 __I uint32_t RawIntTCStat; /*!< Offset: 0x014 (R/ ) DMA Raw Interrupt Terminal Count Status Register */
igor_v 0:8ad47e2b6f00 688 __I uint32_t RawIntErrStat; /*!< Offset: 0x018 (R/ ) DMA Raw Error Interrupt Status Register */
igor_v 0:8ad47e2b6f00 689 __I uint32_t EnbldChns; /*!< Offset: 0x01C (R/ ) DMA Enabled Channel Register */
igor_v 0:8ad47e2b6f00 690 __IO uint32_t SoftBReq; /*!< Offset: 0x020 (R/W) DMA Software Burst Request Register */
igor_v 0:8ad47e2b6f00 691 __IO uint32_t SoftSReq; /*!< Offset: 0x024 (R/W) DMA Software Single Request Register */
igor_v 0:8ad47e2b6f00 692 __IO uint32_t SoftLBReq; /*!< Offset: 0x028 (R/W) DMA Software Last Burst Request Register */
igor_v 0:8ad47e2b6f00 693 __IO uint32_t SoftLSReq; /*!< Offset: 0x02C (R/W) DMA Software Last Single Request Register */
igor_v 0:8ad47e2b6f00 694 __IO uint32_t Config; /*!< Offset: 0x030 (R/W) DMA Configuration Register */
igor_v 0:8ad47e2b6f00 695 __IO uint32_t Sync; /*!< Offset: 0x034 (R/W) DMA Synchronization Register */
igor_v 0:8ad47e2b6f00 696 } LPC_GPDMA_TypeDef;
igor_v 0:8ad47e2b6f00 697
igor_v 0:8ad47e2b6f00 698 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
igor_v 0:8ad47e2b6f00 699 typedef struct /* Channel Registers */
igor_v 0:8ad47e2b6f00 700 {
igor_v 0:8ad47e2b6f00 701 __IO uint32_t CSrcAddr; /*!< Offset: 0x000 (R/W) DMA Channel # Source Address Register */
igor_v 0:8ad47e2b6f00 702 __IO uint32_t CDestAddr; /*!< Offset: 0x004 (R/W) DMA Channel # Destination Address Register */
igor_v 0:8ad47e2b6f00 703 __IO uint32_t CLLI; /*!< Offset: 0x008 (R/W) DMA Channel # Linked List Item Register */
igor_v 0:8ad47e2b6f00 704 __IO uint32_t CControl; /*!< Offset: 0x00C (R/W) DMA Channel # Control Register */
igor_v 0:8ad47e2b6f00 705 __IO uint32_t CConfig; /*!< Offset: 0x010 (R/W) DMA Channel # Configuration Register */
igor_v 0:8ad47e2b6f00 706 } LPC_GPDMACH_TypeDef;
igor_v 0:8ad47e2b6f00 707
igor_v 0:8ad47e2b6f00 708 /*------------- Universal Serial Bus (USB) -----------------------------------*/
igor_v 0:8ad47e2b6f00 709 /** @brief Universal Serial Bus (USB) register structure definition */
igor_v 0:8ad47e2b6f00 710 typedef struct
igor_v 0:8ad47e2b6f00 711 {
igor_v 0:8ad47e2b6f00 712 __I uint32_t Revision; /*!< Offset: 0x000 (R/ ) Revision Register */
igor_v 0:8ad47e2b6f00 713 __IO uint32_t Control; /*!< Offset: 0x004 (R/W) Control Register */
igor_v 0:8ad47e2b6f00 714 __IO uint32_t CommandStatus; /*!< Offset: 0x008 (R/W) Command / Status Register */
igor_v 0:8ad47e2b6f00 715 __IO uint32_t InterruptStatus; /*!< Offset: 0x00C (R/W) Interrupt Status Register */
igor_v 0:8ad47e2b6f00 716 __IO uint32_t InterruptEnable; /*!< Offset: 0x010 (R/W) Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 717 __IO uint32_t InterruptDisable; /*!< Offset: 0x014 (R/W) Interrupt Disable Register */
igor_v 0:8ad47e2b6f00 718 __IO uint32_t HCCA; /*!< Offset: 0x018 (R/W) Host Controller communication Area Register */
igor_v 0:8ad47e2b6f00 719 __I uint32_t PeriodCurrentED; /*!< Offset: 0x01C (R/ ) Register */
igor_v 0:8ad47e2b6f00 720 __IO uint32_t ControlHeadED; /*!< Offset: 0x020 (R/W) Register */
igor_v 0:8ad47e2b6f00 721 __IO uint32_t ControlCurrentED; /*!< Offset: 0x024 (R/W) Register */
igor_v 0:8ad47e2b6f00 722 __IO uint32_t BulkHeadED; /*!< Offset: 0x028 (R/W) Register */
igor_v 0:8ad47e2b6f00 723 __IO uint32_t BulkCurrentED; /*!< Offset: 0x02C (R/W) Register */
igor_v 0:8ad47e2b6f00 724 __I uint32_t DoneHead; /*!< Offset: 0x030 (R/ ) Register */
igor_v 0:8ad47e2b6f00 725 __IO uint32_t FmInterval; /*!< Offset: 0x034 (R/W) Register */
igor_v 0:8ad47e2b6f00 726 __I uint32_t FmRemaining; /*!< Offset: 0x038 (R/ ) Register */
igor_v 0:8ad47e2b6f00 727 __I uint32_t FmNumber; /*!< Offset: 0x03C (R/ ) Register */
igor_v 0:8ad47e2b6f00 728 __IO uint32_t PeriodicStart; /*!< Offset: 0x040 (R/W) Register */
igor_v 0:8ad47e2b6f00 729 __IO uint32_t LSTreshold; /*!< Offset: 0x044 (R/W) Register */
igor_v 0:8ad47e2b6f00 730 __IO uint32_t RhDescriptorA; /*!< Offset: 0x048 (R/W) Register */
igor_v 0:8ad47e2b6f00 731 __IO uint32_t RhDescriptorB; /*!< Offset: 0x04C (R/W) Register */
igor_v 0:8ad47e2b6f00 732 __IO uint32_t RhStatus; /*!< Offset: 0x050 (R/W) Register */
igor_v 0:8ad47e2b6f00 733 __IO uint32_t RhPortStatus1; /*!< Offset: 0x054 (R/W) Register */
igor_v 0:8ad47e2b6f00 734 __IO uint32_t RhPortStatus2; /*!< Offset: 0x05C (R/W) Register */
igor_v 0:8ad47e2b6f00 735 uint32_t RESERVED0[40];
igor_v 0:8ad47e2b6f00 736 __I uint32_t Module_ID; /*!< Offset: 0x0FC (R/ ) Module ID / Version Reverence ID Register */
igor_v 0:8ad47e2b6f00 737 /* USB On-The-Go Registers */
igor_v 0:8ad47e2b6f00 738 __I uint32_t IntSt; /*!< Offset: 0x100 (R/ ) OTG Interrupt Status Register */
igor_v 0:8ad47e2b6f00 739 __IO uint32_t IntEn; /*!< Offset: 0x104 (R/W) OTG Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 740 __O uint32_t IntSet; /*!< Offset: 0x108 ( /W) OTG Interrupt Set Register */
igor_v 0:8ad47e2b6f00 741 __O uint32_t IntClr; /*!< Offset: 0x10C ( /W) OTG Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 742 __IO uint32_t StCtrl; /*!< Offset: 0x110 (R/W) OTG Status and Control Register */
igor_v 0:8ad47e2b6f00 743 __IO uint32_t Tmr; /*!< Offset: 0x114 (R/W) OTG Timer Register */
igor_v 0:8ad47e2b6f00 744 uint32_t RESERVED1[58];
igor_v 0:8ad47e2b6f00 745 /* USB Device Interrupt Registers */
igor_v 0:8ad47e2b6f00 746 __I uint32_t DevIntSt; /*!< Offset: 0x200 (R/ ) USB Device Interrupt Status Register */
igor_v 0:8ad47e2b6f00 747 __IO uint32_t DevIntEn; /*!< Offset: 0x204 (R/W) USB Device Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 748 __O uint32_t DevIntClr; /*!< Offset: 0x208 ( /W) USB Device Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 749 __O uint32_t DevIntSet; /*!< Offset: 0x20C ( /W) USB Device Interrupt Set Register */
igor_v 0:8ad47e2b6f00 750 /* USB Device SIE Command Registers */
igor_v 0:8ad47e2b6f00 751 __O uint32_t CmdCode; /*!< Offset: 0x210 (R/W) USB Command Code Register */
igor_v 0:8ad47e2b6f00 752 __I uint32_t CmdData; /*!< Offset: 0x214 (R/W) USB Command Data Register */
igor_v 0:8ad47e2b6f00 753 /* USB Device Transfer Registers */
igor_v 0:8ad47e2b6f00 754 __I uint32_t RxData; /*!< Offset: 0x218 (R/ ) USB Receive Data Register */
igor_v 0:8ad47e2b6f00 755 __O uint32_t TxData; /*!< Offset: 0x21C ( /W) USB Transmit Data Register */
igor_v 0:8ad47e2b6f00 756 __I uint32_t RxPLen; /*!< Offset: 0x220 (R/ ) USB Receive Packet Length Register */
igor_v 0:8ad47e2b6f00 757 __O uint32_t TxPLen; /*!< Offset: 0x224 ( /W) USB Transmit Packet Length Register */
igor_v 0:8ad47e2b6f00 758 __IO uint32_t Ctrl; /*!< Offset: 0x228 (R/W) USB Control Register */
igor_v 0:8ad47e2b6f00 759 __O uint32_t DevIntPri; /*!< Offset: 0x22C (R/W) USB Device Interrupt Priority Register */
igor_v 0:8ad47e2b6f00 760 /* USB Device Endpoint Interrupt Regs */
igor_v 0:8ad47e2b6f00 761 __I uint32_t EpIntSt; /*!< Offset: 0x230 (R/ ) USB Endpoint Interrupt Status Register */
igor_v 0:8ad47e2b6f00 762 __IO uint32_t EpIntEn; /*!< Offset: 0x234 (R/W) USB Endpoint Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 763 __O uint32_t EpIntClr; /*!< Offset: 0x238 ( /W) USB Endpoint Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 764 __O uint32_t EpIntSet; /*!< Offset: 0x23C ( /W) USB Endpoint Interrupt Set Register */
igor_v 0:8ad47e2b6f00 765 __O uint32_t EpIntPri; /*!< Offset: 0x240 ( /W) USB Endpoint Interrupt Priority Register */
igor_v 0:8ad47e2b6f00 766 /* USB Device Endpoint Realization Reg*/
igor_v 0:8ad47e2b6f00 767 __IO uint32_t ReEp; /*!< Offset: 0x244 (R/W) USB Realize Endpoint Register */
igor_v 0:8ad47e2b6f00 768 __O uint32_t EpInd; /*!< Offset: 0x248 ( /W) USB Endpoint Index Register */
igor_v 0:8ad47e2b6f00 769 __IO uint32_t MaxPSize; /*!< Offset: 0x24C (R/W) USB MaxPacketSize Register */
igor_v 0:8ad47e2b6f00 770 /* USB Device DMA Registers */
igor_v 0:8ad47e2b6f00 771 __I uint32_t DMARSt; /*!< Offset: 0x250 (R/ ) USB DMA Request Status Register */
igor_v 0:8ad47e2b6f00 772 __O uint32_t DMARClr; /*!< Offset: 0x254 ( /W) USB DMA Request Clear Register */
igor_v 0:8ad47e2b6f00 773 __O uint32_t DMARSet; /*!< Offset: 0x258 ( /W) USB DMA Request Set Register */
igor_v 0:8ad47e2b6f00 774 uint32_t RESERVED2[9];
igor_v 0:8ad47e2b6f00 775 __IO uint32_t UDCAH; /*!< Offset: 0x280 (R/W) USB UDCA Head Register */
igor_v 0:8ad47e2b6f00 776 __I uint32_t EpDMASt; /*!< Offset: 0x284 (R/ ) USB EP DMA Status Register */
igor_v 0:8ad47e2b6f00 777 __O uint32_t EpDMAEn; /*!< Offset: 0x288 ( /W) USB EP DMA Enable Register */
igor_v 0:8ad47e2b6f00 778 __O uint32_t EpDMADis; /*!< Offset: 0x28C ( /W) USB EP DMA Disable Register */
igor_v 0:8ad47e2b6f00 779 __I uint32_t DMAIntSt; /*!< Offset: 0x290 (R/ ) USB DMA Interrupt Status Register */
igor_v 0:8ad47e2b6f00 780 __IO uint32_t DMAIntEn; /*!< Offset: 0x294 (R/W) USB DMA Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 781 uint32_t RESERVED3[2];
igor_v 0:8ad47e2b6f00 782 __I uint32_t EoTIntSt; /*!< Offset: 0x2A0 (R/ ) USB End of Transfer Interrupt Status Register */
igor_v 0:8ad47e2b6f00 783 __O uint32_t EoTIntClr; /*!< Offset: 0x2A4 ( /W) USB End of Transfer Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 784 __O uint32_t EoTIntSet; /*!< Offset: 0x2A8 ( /W) USB End of Transfer Interrupt Set Register */
igor_v 0:8ad47e2b6f00 785 __I uint32_t NDDRIntSt; /*!< Offset: 0x2AC (R/ ) USB New DD Request Interrupt Status Register */
igor_v 0:8ad47e2b6f00 786 __O uint32_t NDDRIntClr; /*!< Offset: 0x2B0 ( /W) USB New DD Request Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 787 __O uint32_t NDDRIntSet; /*!< Offset: 0x2B4 ( /W) USB New DD Request Interrupt Set Register */
igor_v 0:8ad47e2b6f00 788 __I uint32_t SysErrIntSt; /*!< Offset: 0x2B8 (R/ ) USB System Error Interrupt Status Register */
igor_v 0:8ad47e2b6f00 789 __O uint32_t SysErrIntClr; /*!< Offset: 0x2BC ( /W) USB System Error Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 790 __O uint32_t SysErrIntSet; /*!< Offset: 0x2C0 ( /W) USB System Error Interrupt Set Register */
igor_v 0:8ad47e2b6f00 791 uint32_t RESERVED4[15];
igor_v 0:8ad47e2b6f00 792 /* USB OTG I2C Registers */
igor_v 0:8ad47e2b6f00 793 union {
igor_v 0:8ad47e2b6f00 794 __I uint32_t I2C_RX; /*!< Offset: 0x300 (R/ ) OTG I2C Receive Register */
igor_v 0:8ad47e2b6f00 795 __O uint32_t I2C_TX; /*!< Offset: 0x300 ( /W) OTG I2C Transmit Register */
igor_v 0:8ad47e2b6f00 796 };
igor_v 0:8ad47e2b6f00 797 __I uint32_t I2C_STS; /*!< Offset: 0x304 (R/ ) OTG I2C Status Register */
igor_v 0:8ad47e2b6f00 798 __IO uint32_t I2C_CTL; /*!< Offset: 0x308 (R/W) OTG I2C Control Register */
igor_v 0:8ad47e2b6f00 799 __IO uint32_t I2C_CLKHI; /*!< Offset: 0x30C (R/W) OTG I2C Clock High Register */
igor_v 0:8ad47e2b6f00 800 __O uint32_t I2C_CLKLO; /*!< Offset: 0x310 ( /W) OTG I2C Clock Low Register */
igor_v 0:8ad47e2b6f00 801 uint32_t RESERVED5[824];
igor_v 0:8ad47e2b6f00 802 /* USB Clock Control Registers */
igor_v 0:8ad47e2b6f00 803 union {
igor_v 0:8ad47e2b6f00 804 __IO uint32_t USBClkCtrl; /*!< Offset: 0xFF4 (R/W) OTG clock controller Register */
igor_v 0:8ad47e2b6f00 805 __IO uint32_t OTGClkCtrl; /*!< Offset: 0xFF4 (R/W) USB clock controller Register */
igor_v 0:8ad47e2b6f00 806 };
igor_v 0:8ad47e2b6f00 807 union {
igor_v 0:8ad47e2b6f00 808 __I uint32_t USBClkSt; /*!< Offset: 0xFF8 (R/ ) OTG clock status Register */
igor_v 0:8ad47e2b6f00 809 __I uint32_t OTGClkSt; /*!< Offset: 0xFF8 (R/ ) USB clock status Register */
igor_v 0:8ad47e2b6f00 810 };
igor_v 0:8ad47e2b6f00 811 } LPC_USB_TypeDef;
igor_v 0:8ad47e2b6f00 812
igor_v 0:8ad47e2b6f00 813 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
igor_v 0:8ad47e2b6f00 814 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */
igor_v 0:8ad47e2b6f00 815 typedef struct
igor_v 0:8ad47e2b6f00 816 {
igor_v 0:8ad47e2b6f00 817 __IO uint32_t MAC1; /*!< Offset: 0x000 (R/W) MAC Configuration Register 1 */
igor_v 0:8ad47e2b6f00 818 __IO uint32_t MAC2; /*!< Offset: 0x004 (R/W) MAC Configuration Register 2 */
igor_v 0:8ad47e2b6f00 819 __IO uint32_t IPGT; /*!< Offset: 0x008 (R/W) Back-to-Back Inter-Packet-Gap Register */
igor_v 0:8ad47e2b6f00 820 __IO uint32_t IPGR; /*!< Offset: 0x00C (R/W) Non Back-to-Back Inter-Packet-Gap Register */
igor_v 0:8ad47e2b6f00 821 __IO uint32_t CLRT; /*!< Offset: 0x010 (R/W) Collision Window / Retry Register */
igor_v 0:8ad47e2b6f00 822 __IO uint32_t MAXF; /*!< Offset: 0x014 (R/W) Maximum Frame Register */
igor_v 0:8ad47e2b6f00 823 __IO uint32_t SUPP; /*!< Offset: 0x018 (R/W) PHY Support Register */
igor_v 0:8ad47e2b6f00 824 __IO uint32_t TEST; /*!< Offset: 0x01C (R/W) Test Register */
igor_v 0:8ad47e2b6f00 825 __IO uint32_t MCFG; /*!< Offset: 0x020 (R/W) MII Mgmt Configuration Register */
igor_v 0:8ad47e2b6f00 826 __IO uint32_t MCMD; /*!< Offset: 0x024 (R/W) MII Mgmt Command Register */
igor_v 0:8ad47e2b6f00 827 __IO uint32_t MADR; /*!< Offset: 0x028 (R/W) MII Mgmt Address Register */
igor_v 0:8ad47e2b6f00 828 __O uint32_t MWTD; /*!< Offset: 0x02C ( /W) MII Mgmt Write Data Register */
igor_v 0:8ad47e2b6f00 829 __I uint32_t MRDD; /*!< Offset: 0x030 (R/ ) MII Mgmt Read Data Register */
igor_v 0:8ad47e2b6f00 830 __I uint32_t MIND; /*!< Offset: 0x034 (R/ ) MII Mgmt Indicators Register */
igor_v 0:8ad47e2b6f00 831 uint32_t RESERVED0[2];
igor_v 0:8ad47e2b6f00 832 __IO uint32_t SA0; /*!< Offset: 0x040 (R/W) Station Address 0 Register */
igor_v 0:8ad47e2b6f00 833 __IO uint32_t SA1; /*!< Offset: 0x044 (R/W) Station Address 1 Register */
igor_v 0:8ad47e2b6f00 834 __IO uint32_t SA2; /*!< Offset: 0x048 (R/W) Station Address 2 Register */
igor_v 0:8ad47e2b6f00 835 uint32_t RESERVED1[45];
igor_v 0:8ad47e2b6f00 836 __IO uint32_t Command; /*!< Offset: 0x100 (R/W) Command Register */
igor_v 0:8ad47e2b6f00 837 __I uint32_t Status; /*!< Offset: 0x104 (R/ ) Status Register */
igor_v 0:8ad47e2b6f00 838 __IO uint32_t RxDescriptor; /*!< Offset: 0x108 (R/W) Receive Descriptor Base Address Register */
igor_v 0:8ad47e2b6f00 839 __IO uint32_t RxStatus; /*!< Offset: 0x10C (R/W) Receive Status Base Address Register */
igor_v 0:8ad47e2b6f00 840 __IO uint32_t RxDescriptorNumber; /*!< Offset: 0x110 (R/W) Receive Number of Descriptors Register */
igor_v 0:8ad47e2b6f00 841 __I uint32_t RxProduceIndex; /*!< Offset: 0x114 (R/ ) Receive Produce Index Register */
igor_v 0:8ad47e2b6f00 842 __IO uint32_t RxConsumeIndex; /*!< Offset: 0x118 (R/W) Receive Consume Index Register */
igor_v 0:8ad47e2b6f00 843 __IO uint32_t TxDescriptor; /*!< Offset: 0x11C (R/W) Transmit Descriptor Base Address Register */
igor_v 0:8ad47e2b6f00 844 __IO uint32_t TxStatus; /*!< Offset: 0x120 (R/W) Transmit Status Base Address Register */
igor_v 0:8ad47e2b6f00 845 __IO uint32_t TxDescriptorNumber; /*!< Offset: 0x124 (R/W) Transmit Number of Descriptors Register */
igor_v 0:8ad47e2b6f00 846 __IO uint32_t TxProduceIndex; /*!< Offset: 0x128 (R/W) Transmit Produce Index Register */
igor_v 0:8ad47e2b6f00 847 __I uint32_t TxConsumeIndex; /*!< Offset: 0x12C (R/ ) Transmit Consume Index Register */
igor_v 0:8ad47e2b6f00 848 uint32_t RESERVED2[10];
igor_v 0:8ad47e2b6f00 849 __I uint32_t TSV0; /*!< Offset: 0x158 (R/ ) Transmit Status Vector 0 Register */
igor_v 0:8ad47e2b6f00 850 __I uint32_t TSV1; /*!< Offset: 0x15C (R/ ) Transmit Status Vector 1 Register */
igor_v 0:8ad47e2b6f00 851 __I uint32_t RSV; /*!< Offset: 0x160 (R/ ) Receive Status Vector Register */
igor_v 0:8ad47e2b6f00 852 uint32_t RESERVED3[3];
igor_v 0:8ad47e2b6f00 853 __IO uint32_t FlowControlCounter; /*!< Offset: 0x170 (R/W) Flow Control Counter Register */
igor_v 0:8ad47e2b6f00 854 __I uint32_t FlowControlStatus; /*!< Offset: 0x174 (R/ ) Flow Control Status egister */
igor_v 0:8ad47e2b6f00 855 uint32_t RESERVED4[34];
igor_v 0:8ad47e2b6f00 856 __IO uint32_t RxFilterCtrl; /*!< Offset: 0x200 (R/W) Receive Filter Control Register */
igor_v 0:8ad47e2b6f00 857 __I uint32_t RxFilterWoLStatus; /*!< Offset: 0x204 (R/ ) Receive Filter WoL Status Register */
igor_v 0:8ad47e2b6f00 858 __O uint32_t RxFilterWoLClear; /*!< Offset: 0x208 ( /W) Receive Filter WoL Clear Register */
igor_v 0:8ad47e2b6f00 859 uint32_t RESERVED5;
igor_v 0:8ad47e2b6f00 860 __IO uint32_t HashFilterL; /*!< Offset: 0x210 (R/W) Hash Filter Table LSBs Register */
igor_v 0:8ad47e2b6f00 861 __IO uint32_t HashFilterH; /*!< Offset: 0x214 (R/W) Hash Filter Table MSBs Register */
igor_v 0:8ad47e2b6f00 862 uint32_t RESERVED6[882];
igor_v 0:8ad47e2b6f00 863 __I uint32_t IntStatus; /*!< Offset: 0xFE0 (R/ ) Interrupt Status Register */
igor_v 0:8ad47e2b6f00 864 __IO uint32_t IntEnable; /*!< Offset: 0xFE4 (R/W) Interrupt Enable Register */
igor_v 0:8ad47e2b6f00 865 __O uint32_t IntClear; /*!< Offset: 0xFE8 ( /W) Interrupt Clear Register */
igor_v 0:8ad47e2b6f00 866 __O uint32_t IntSet; /*!< Offset: 0xFEC ( /W) Interrupt Set Register */
igor_v 0:8ad47e2b6f00 867 uint32_t RESERVED7;
igor_v 0:8ad47e2b6f00 868 __IO uint32_t PowerDown; /*!< Offset: 0xFF4 (R/W) Power-Down Register */
igor_v 0:8ad47e2b6f00 869 } LPC_EMAC_TypeDef;
igor_v 0:8ad47e2b6f00 870
igor_v 0:8ad47e2b6f00 871 #if defined ( __CC_ARM )
igor_v 0:8ad47e2b6f00 872 #pragma no_anon_unions
igor_v 0:8ad47e2b6f00 873 #endif
igor_v 0:8ad47e2b6f00 874
igor_v 0:8ad47e2b6f00 875
igor_v 0:8ad47e2b6f00 876 /******************************************************************************/
igor_v 0:8ad47e2b6f00 877 /* Peripheral memory map */
igor_v 0:8ad47e2b6f00 878 /******************************************************************************/
igor_v 0:8ad47e2b6f00 879 /* Base addresses */
igor_v 0:8ad47e2b6f00 880 #define LPC_FLASH_BASE (0x00000000UL)
igor_v 0:8ad47e2b6f00 881 #define LPC_RAM_BASE (0x10000000UL)
igor_v 0:8ad47e2b6f00 882 #ifdef __LPC17XX_REV00
igor_v 0:8ad47e2b6f00 883 #define LPC_AHBRAM0_BASE (0x20000000UL)
igor_v 0:8ad47e2b6f00 884 #define LPC_AHBRAM1_BASE (0x20004000UL)
igor_v 0:8ad47e2b6f00 885 #else
igor_v 0:8ad47e2b6f00 886 #define LPC_AHBRAM0_BASE (0x2007C000UL)
igor_v 0:8ad47e2b6f00 887 #define LPC_AHBRAM1_BASE (0x20080000UL)
igor_v 0:8ad47e2b6f00 888 #endif
igor_v 0:8ad47e2b6f00 889 #define LPC_GPIO_BASE (0x2009C000UL)
igor_v 0:8ad47e2b6f00 890 #define LPC_APB0_BASE (0x40000000UL)
igor_v 0:8ad47e2b6f00 891 #define LPC_APB1_BASE (0x40080000UL)
igor_v 0:8ad47e2b6f00 892 #define LPC_AHB_BASE (0x50000000UL)
igor_v 0:8ad47e2b6f00 893 #define LPC_CM3_BASE (0xE0000000UL)
igor_v 0:8ad47e2b6f00 894
igor_v 0:8ad47e2b6f00 895 /* APB0 peripherals */
igor_v 0:8ad47e2b6f00 896 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
igor_v 0:8ad47e2b6f00 897 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
igor_v 0:8ad47e2b6f00 898 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
igor_v 0:8ad47e2b6f00 899 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
igor_v 0:8ad47e2b6f00 900 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
igor_v 0:8ad47e2b6f00 901 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
igor_v 0:8ad47e2b6f00 902 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
igor_v 0:8ad47e2b6f00 903 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
igor_v 0:8ad47e2b6f00 904 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
igor_v 0:8ad47e2b6f00 905 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
igor_v 0:8ad47e2b6f00 906 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
igor_v 0:8ad47e2b6f00 907 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
igor_v 0:8ad47e2b6f00 908 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
igor_v 0:8ad47e2b6f00 909 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
igor_v 0:8ad47e2b6f00 910 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
igor_v 0:8ad47e2b6f00 911 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
igor_v 0:8ad47e2b6f00 912 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
igor_v 0:8ad47e2b6f00 913 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
igor_v 0:8ad47e2b6f00 914 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
igor_v 0:8ad47e2b6f00 915
igor_v 0:8ad47e2b6f00 916 /* APB1 peripherals */
igor_v 0:8ad47e2b6f00 917 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
igor_v 0:8ad47e2b6f00 918 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
igor_v 0:8ad47e2b6f00 919 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
igor_v 0:8ad47e2b6f00 920 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
igor_v 0:8ad47e2b6f00 921 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
igor_v 0:8ad47e2b6f00 922 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
igor_v 0:8ad47e2b6f00 923 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
igor_v 0:8ad47e2b6f00 924 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
igor_v 0:8ad47e2b6f00 925 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
igor_v 0:8ad47e2b6f00 926 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
igor_v 0:8ad47e2b6f00 927 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
igor_v 0:8ad47e2b6f00 928 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
igor_v 0:8ad47e2b6f00 929
igor_v 0:8ad47e2b6f00 930 /* AHB peripherals */
igor_v 0:8ad47e2b6f00 931 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
igor_v 0:8ad47e2b6f00 932 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
igor_v 0:8ad47e2b6f00 933 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
igor_v 0:8ad47e2b6f00 934 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
igor_v 0:8ad47e2b6f00 935 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
igor_v 0:8ad47e2b6f00 936 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
igor_v 0:8ad47e2b6f00 937 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
igor_v 0:8ad47e2b6f00 938 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
igor_v 0:8ad47e2b6f00 939 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
igor_v 0:8ad47e2b6f00 940 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
igor_v 0:8ad47e2b6f00 941 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
igor_v 0:8ad47e2b6f00 942
igor_v 0:8ad47e2b6f00 943 /* GPIOs */
igor_v 0:8ad47e2b6f00 944 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
igor_v 0:8ad47e2b6f00 945 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
igor_v 0:8ad47e2b6f00 946 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
igor_v 0:8ad47e2b6f00 947 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
igor_v 0:8ad47e2b6f00 948 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
igor_v 0:8ad47e2b6f00 949
igor_v 0:8ad47e2b6f00 950
igor_v 0:8ad47e2b6f00 951 /******************************************************************************/
igor_v 0:8ad47e2b6f00 952 /* Peripheral declaration */
igor_v 0:8ad47e2b6f00 953 /******************************************************************************/
igor_v 0:8ad47e2b6f00 954 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
igor_v 0:8ad47e2b6f00 955 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
igor_v 0:8ad47e2b6f00 956 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
igor_v 0:8ad47e2b6f00 957 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
igor_v 0:8ad47e2b6f00 958 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
igor_v 0:8ad47e2b6f00 959 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
igor_v 0:8ad47e2b6f00 960 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
igor_v 0:8ad47e2b6f00 961 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
igor_v 0:8ad47e2b6f00 962 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
igor_v 0:8ad47e2b6f00 963 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
igor_v 0:8ad47e2b6f00 964 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
igor_v 0:8ad47e2b6f00 965 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
igor_v 0:8ad47e2b6f00 966 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
igor_v 0:8ad47e2b6f00 967 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
igor_v 0:8ad47e2b6f00 968 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
igor_v 0:8ad47e2b6f00 969 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
igor_v 0:8ad47e2b6f00 970 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
igor_v 0:8ad47e2b6f00 971 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
igor_v 0:8ad47e2b6f00 972 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
igor_v 0:8ad47e2b6f00 973 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
igor_v 0:8ad47e2b6f00 974 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
igor_v 0:8ad47e2b6f00 975 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
igor_v 0:8ad47e2b6f00 976 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
igor_v 0:8ad47e2b6f00 977 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
igor_v 0:8ad47e2b6f00 978 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
igor_v 0:8ad47e2b6f00 979 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
igor_v 0:8ad47e2b6f00 980 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
igor_v 0:8ad47e2b6f00 981 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
igor_v 0:8ad47e2b6f00 982 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
igor_v 0:8ad47e2b6f00 983 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
igor_v 0:8ad47e2b6f00 984 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
igor_v 0:8ad47e2b6f00 985 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
igor_v 0:8ad47e2b6f00 986 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
igor_v 0:8ad47e2b6f00 987 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
igor_v 0:8ad47e2b6f00 988 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
igor_v 0:8ad47e2b6f00 989 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
igor_v 0:8ad47e2b6f00 990 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
igor_v 0:8ad47e2b6f00 991 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
igor_v 0:8ad47e2b6f00 992 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
igor_v 0:8ad47e2b6f00 993 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
igor_v 0:8ad47e2b6f00 994 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
igor_v 0:8ad47e2b6f00 995 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
igor_v 0:8ad47e2b6f00 996 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
igor_v 0:8ad47e2b6f00 997 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
igor_v 0:8ad47e2b6f00 998 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
igor_v 0:8ad47e2b6f00 999 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
igor_v 0:8ad47e2b6f00 1000 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
igor_v 0:8ad47e2b6f00 1001
igor_v 0:8ad47e2b6f00 1002
igor_v 0:8ad47e2b6f00 1003 /**
igor_v 0:8ad47e2b6f00 1004 * @}
igor_v 0:8ad47e2b6f00 1005 */
igor_v 0:8ad47e2b6f00 1006
igor_v 0:8ad47e2b6f00 1007 #endif // __LPC17xx_H__
igor_v 0:8ad47e2b6f00 1008