Dmitry Kovalev / Mbed 2 deprecated LG2

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Dependencies:   mbed

Fork of LG by igor Apu

CyclesSync.h@219:2d3475d0dd1b, 2017-09-27 (annotated)

Committer:
Kovalev_D
Date:
Wed Sep 27 13:09:24 2017 +0000
Revision:
219:2d3475d0dd1b
Parent:
21:bc8c1cec3da6 
hnjtfgyy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 0:8ad47e2b6f00 1 /**--------------File Info---------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 2 ** File name: CycleSync.h
igor_v 0:8ad47e2b6f00 3 ** Last modified Date: 2011-09-06
igor_v 0:8ad47e2b6f00 4 ** Last Version: V1.00
igor_v 21:bc8c1cec3da6 5 ** Descriptions:
igor_v 0:8ad47e2b6f00 6 **
igor_v 0:8ad47e2b6f00 7 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 8 ** Created by: Electrooptica Inc.
igor_v 0:8ad47e2b6f00 9 ** Created date: 2011-09-06
igor_v 0:8ad47e2b6f00 10 ** Version: V1.00
igor_v 0:8ad47e2b6f00 11 ** Descriptions: There is the routines for device synchronization
igor_v 0:8ad47e2b6f00 12 **
igor_v 21:bc8c1cec3da6 13 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 14 *********************************************************************************************************/
igor_v 0:8ad47e2b6f00 15 #include "LPC17xx.h"
igor_v 0:8ad47e2b6f00 16 #include "CntrlGLD.h"
igor_v 0:8ad47e2b6f00 17
igor_v 0:8ad47e2b6f00 18 //#define PERFOMANCE
igor_v 0:8ad47e2b6f00 19
igor_v 21:bc8c1cec3da6 20 //#define PERFOMANCE
igor_v 21:bc8c1cec3da6 21
igor_v 21:bc8c1cec3da6 22 #define DEVICE_SAMPLE_RATE_HZ 10000 //e. sampling frequency 10 kHz //r. частота дискретизации 10 кГц
igor_v 21:bc8c1cec3da6 23 #define DEVICE_SAMPLE_RATE_uks 100000000 //e. sampling frequency 10 kHz //r. частота дискретизации 10 кГц
igor_v 0:8ad47e2b6f00 24 #define DELAY_UART_ENBL 4000 //e. delay = DELAY_UART_ENBL*8/CLCK
igor_v 0:8ad47e2b6f00 25 #define DELAY_UART_DISBL 2500 //e. delay = DELAY_UART_ENBL*8/CLCK
igor_v 21:bc8c1cec3da6 26 #define RATE_REPER_OR_REFMEANDR 0x0000 //e. difference of general counters (not dither counters), latched by Reper or by Sign Meander //r. разность обычных счетчиков (не вибросч), защелкнутых по Reper`у или по RefMeandr`у
igor_v 21:bc8c1cec3da6 27 #define RATE_VIBRO_1 0x0001 //e. difference of dither counters after the filter of moving average //r. разность вибросчетчиков после фильтра скольз.среднего
igor_v 0:8ad47e2b6f00 28
igor_v 0:8ad47e2b6f00 29 #define HALF_PERIOD 0x00000004
igor_v 0:8ad47e2b6f00 30 #define WHOLE_PERIOD 0x00000008
igor_v 0:8ad47e2b6f00 31 #define RESET_PERIOD 0x0000000C
igor_v 0:8ad47e2b6f00 32 //-----------------------------PWM Registers----------------------------------------
igor_v 0:8ad47e2b6f00 33
igor_v 0:8ad47e2b6f00 34 #define TCR_CNT_EN 0x00000001
igor_v 0:8ad47e2b6f00 35 #define TCR_RESET 0x00000002
igor_v 0:8ad47e2b6f00 36 #define TCR_PWM_EN 0x00000008
igor_v 0:8ad47e2b6f00 37
igor_v 0:8ad47e2b6f00 38 #define PWMMR0I (1 << 0)
igor_v 0:8ad47e2b6f00 39 #define PWMMR0R (1 << 1)
igor_v 0:8ad47e2b6f00 40 #define PWMMR0S (1 << 2)
igor_v 0:8ad47e2b6f00 41 #define PWMENA1 (1 << 9)
igor_v 0:8ad47e2b6f00 42 #define LER0_EN (1 << 0)
igor_v 0:8ad47e2b6f00 43
igor_v 0:8ad47e2b6f00 44 //-----------------------Drive cycle registers------------------------------------
igor_v 0:8ad47e2b6f00 45 #define MR0_RESET 0x00000002
igor_v 0:8ad47e2b6f00 46 #define MR1_RESET 0x00000010
igor_v 0:8ad47e2b6f00 47 #define MR1_STOP 0x00000020
igor_v 0:8ad47e2b6f00 48 #define MR0_STOP 0x00000004
igor_v 0:8ad47e2b6f00 49 #define MR0_NO_STOP 0x00000000
igor_v 0:8ad47e2b6f00 50 #define MR0_INT_EN 0x00000001
igor_v 0:8ad47e2b6f00 51 #define SYNC_CLCK4 0xffff3fff
igor_v 0:8ad47e2b6f00 52 #define SYNC_CLCK 0xfffffff
igor_v 0:8ad47e2b6f00 53
igor_v 0:8ad47e2b6f00 54 //------------------------WDT registers--------------------------------------------
igor_v 0:8ad47e2b6f00 55 #define WDEN (0x1<<0)
igor_v 0:8ad47e2b6f00 56 #define WDRESET (0x1<<1)
igor_v 0:8ad47e2b6f00 57 #define WDTOF (0x1<<2)
igor_v 0:8ad47e2b6f00 58 #define WDINT (0x1<<3)
igor_v 0:8ad47e2b6f00 59 #define WDT_FEED_VALUE 0x003FFFFF
igor_v 0:8ad47e2b6f00 60
igor_v 0:8ad47e2b6f00 61 extern uint32_t WDTInit( void );
igor_v 0:8ad47e2b6f00 62 extern void WDTFeed( void );
igor_v 21:bc8c1cec3da6 63 extern uint32_t Sys_Clock;
igor_v 0:8ad47e2b6f00 64 extern int32_t time_1_Sec;
igor_v 0:8ad47e2b6f00 65 extern uint32_t trm_cycl;
igor_v 21:bc8c1cec3da6 66 extern int32_t PrevPeriod;
igor_v 0:8ad47e2b6f00 67 extern uint32_t Ext_Latch_ResetEnable;
igor_v 0:8ad47e2b6f00 68 extern volatile uint32_t Latch_Rdy;
igor_v 0:8ad47e2b6f00 69 extern volatile uint32_t data_Rdy;
igor_v 0:8ad47e2b6f00 70 extern int32_t LatchPhase;
igor_v 0:8ad47e2b6f00 71 extern uint32_t PeriodElapsed;
igor_v 0:8ad47e2b6f00 72 extern uint32_t count;
igor_v 21:bc8c1cec3da6 73 extern uint32_t main_cycle_latch;
igor_v 0:8ad47e2b6f00 74 extern uint32_t Out_main_cycle_latch; //e. counter of main cycles between external latch pulse appearence
igor_v 0:8ad47e2b6f00 75 extern uint32_t T_latch, Out_T_latch, temp_T_latch;
igor_v 0:8ad47e2b6f00 76
igor_v 0:8ad47e2b6f00 77 extern void CounterIquiryCycle_Init(uint32_t);
igor_v 0:8ad47e2b6f00 78 extern void ExtLatch_Init(void);
igor_v 0:8ad47e2b6f00 79 extern void IntLatch_Init(void);
igor_v 0:8ad47e2b6f00 80 extern void Latch_Event(void);
igor_v 0:8ad47e2b6f00 81 extern void SetIntLatch(uint32_t);
igor_v 0:8ad47e2b6f00 82 extern void SwitchRefMeandInt(uint32_t);
igor_v 0:8ad47e2b6f00 83 extern int SwitchMode(void);
igor_v 0:8ad47e2b6f00 84
igor_v 0:8ad47e2b6f00 85 #if defined PERFOMANCE
igor_v 21:bc8c1cec3da6 86 void IntLatch(void);
igor_v 0:8ad47e2b6f00 87 #endif
igor_v 0:8ad47e2b6f00 88
igor_v 0:8ad47e2b6f00 89 void ServiceTime(void);
igor_v 0:8ad47e2b6f00 90
igor_v 0:8ad47e2b6f00 91 /*****************************************************************************
igor_v 0:8ad47e2b6f00 92 ** End Of File
igor_v 0:8ad47e2b6f00 93 ******************************************************************************/