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core_cm3.h@217:15cd8752bb6c, 2017-09-04 (annotated)

Committer:: Kovalev_D
Date:: Mon Sep 04 12:55:13 2017 +0000
Revision:: 217:15cd8752bb6c
Parent:: 21:bc8c1cec3da6

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User	Revision	Line number	New contents of line
igor_v	0:8ad47e2b6f00	1	/************************************************************************//
igor_v	0:8ad47e2b6f00	2	* @file core_cm3.h
igor_v	0:8ad47e2b6f00	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
igor_v	11:af609f6dee46	4	* @version V1.30
igor_v	11:af609f6dee46	5	* @date 30. October 2009
igor_v	0:8ad47e2b6f00	6	*
igor_v	0:8ad47e2b6f00	7	* @note
igor_v	11:af609f6dee46	8	* Copyright (C) 2009 ARM Limited. All rights reserved.
igor_v	0:8ad47e2b6f00	9	*
igor_v	0:8ad47e2b6f00	10	* @par
igor_v	21:bc8c1cec3da6	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
igor_v	21:bc8c1cec3da6	12	* processor based microcontrollers. This file can be freely distributed
igor_v	21:bc8c1cec3da6	13	* within development tools that are supporting such ARM based processors.
igor_v	0:8ad47e2b6f00	14	*
igor_v	0:8ad47e2b6f00	15	* @par
igor_v	0:8ad47e2b6f00	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
igor_v	0:8ad47e2b6f00	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
igor_v	0:8ad47e2b6f00	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
igor_v	0:8ad47e2b6f00	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
igor_v	0:8ad47e2b6f00	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
igor_v	0:8ad47e2b6f00	21	*
igor_v	0:8ad47e2b6f00	22	******************************************************************************/
igor_v	11:af609f6dee46	23
igor_v	11:af609f6dee46	24	#ifndef __CM3_CORE_H__
igor_v	11:af609f6dee46	25	#define __CM3_CORE_H__
igor_v	11:af609f6dee46	26
igor_v	11:af609f6dee46	27	/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
igor_v	11:af609f6dee46	28	*
igor_v	11:af609f6dee46	29	* List of Lint messages which will be suppressed and not shown:
igor_v	11:af609f6dee46	30	* - Error 10: \n
igor_v	11:af609f6dee46	31	* register uint32_t __regBasePri __asm("basepri"); \n
igor_v	11:af609f6dee46	32	* Error 10: Expecting ';'
igor_v	11:af609f6dee46	33	* .
igor_v	11:af609f6dee46	34	* - Error 530: \n
igor_v	11:af609f6dee46	35	* return(__regBasePri); \n
igor_v	11:af609f6dee46	36	* Warning 530: Symbol '__regBasePri' (line 264) not initialized
igor_v	21:bc8c1cec3da6	37	* .
igor_v	11:af609f6dee46	38	* - Error 550: \n
igor_v	11:af609f6dee46	39	* __regBasePri = (basePri & 0x1ff); \n
igor_v	11:af609f6dee46	40	* Warning 550: Symbol '__regBasePri' (line 271) not accessed
igor_v	11:af609f6dee46	41	* .
igor_v	11:af609f6dee46	42	* - Error 754: \n
igor_v	11:af609f6dee46	43	* uint32_t RESERVED0[24]; \n
igor_v	11:af609f6dee46	44	* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
igor_v	11:af609f6dee46	45	* .
igor_v	11:af609f6dee46	46	* - Error 750: \n
igor_v	11:af609f6dee46	47	* #define __CM3_CORE_H__ \n
igor_v	11:af609f6dee46	48	* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
igor_v	11:af609f6dee46	49	* .
igor_v	11:af609f6dee46	50	* - Error 528: \n
igor_v	11:af609f6dee46	51	* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
igor_v	11:af609f6dee46	52	* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
igor_v	11:af609f6dee46	53	* .
igor_v	11:af609f6dee46	54	* - Error 751: \n
igor_v	11:af609f6dee46	55	* } InterruptType_Type; \n
igor_v	11:af609f6dee46	56	* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
igor_v	11:af609f6dee46	57	* .
igor_v	11:af609f6dee46	58	* Note: To re-enable a Message, insert a space before 'lint' *
igor_v	11:af609f6dee46	59	*
igor_v	11:af609f6dee46	60	*/
igor_v	11:af609f6dee46	61
igor_v	11:af609f6dee46	62	/lint -save /
igor_v	11:af609f6dee46	63	/lint -e10 /
igor_v	11:af609f6dee46	64	/lint -e530 /
igor_v	11:af609f6dee46	65	/lint -e550 /
igor_v	11:af609f6dee46	66	/lint -e754 /
igor_v	11:af609f6dee46	67	/lint -e750 /
igor_v	11:af609f6dee46	68	/lint -e528 /
igor_v	11:af609f6dee46	69	/lint -e751 /
igor_v	11:af609f6dee46	70
igor_v	11:af609f6dee46	71
igor_v	11:af609f6dee46	72	/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
igor_v	11:af609f6dee46	73	This file defines all structures and symbols for CMSIS core:
igor_v	11:af609f6dee46	74	- CMSIS version number
igor_v	11:af609f6dee46	75	- Cortex-M core registers and bitfields
igor_v	11:af609f6dee46	76	- Cortex-M core peripheral base address
igor_v	11:af609f6dee46	77	@{
igor_v	11:af609f6dee46	78	*/
igor_v	0:8ad47e2b6f00	79
igor_v	0:8ad47e2b6f00	80	#ifdef __cplusplus
igor_v	21:bc8c1cec3da6	81	extern "C" {
igor_v	21:bc8c1cec3da6	82	#endif
igor_v	0:8ad47e2b6f00	83
igor_v	11:af609f6dee46	84	#define __CM3_CMSIS_VERSION_MAIN (0x01) /!< [31:16] CMSIS HAL main version /
igor_v	11:af609f6dee46	85	#define __CM3_CMSIS_VERSION_SUB (0x30) /!< [15:0] CMSIS HAL sub version /
igor_v	0:8ad47e2b6f00	86	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| __CM3_CMSIS_VERSION_SUB) /!< CMSIS HAL version number /
igor_v	0:8ad47e2b6f00	87
igor_v	0:8ad47e2b6f00	88	#define __CORTEX_M (0x03) /!< Cortex core /
igor_v	0:8ad47e2b6f00	89
igor_v	11:af609f6dee46	90	#include <stdint.h> /* Include standard types */
igor_v	11:af609f6dee46	91
igor_v	11:af609f6dee46	92	#if defined (__ICCARM__)
igor_v	21:bc8c1cec3da6	93	#include <intrinsics.h> /* IAR Intrinsics */
igor_v	11:af609f6dee46	94	#endif
igor_v	11:af609f6dee46	95
igor_v	11:af609f6dee46	96
igor_v	11:af609f6dee46	97	#ifndef __NVIC_PRIO_BITS
igor_v	21:bc8c1cec3da6	98	#define __NVIC_PRIO_BITS 4 /!< standard definition for NVIC Priority Bits /
igor_v	11:af609f6dee46	99	#endif
igor_v	11:af609f6dee46	100
igor_v	11:af609f6dee46	101
igor_v	11:af609f6dee46	102
igor_v	11:af609f6dee46	103
igor_v	21:bc8c1cec3da6	104	/**
igor_v	21:bc8c1cec3da6	105	* IO definitions
igor_v	21:bc8c1cec3da6	106	*
igor_v	21:bc8c1cec3da6	107	* define access restrictions to peripheral registers
igor_v	21:bc8c1cec3da6	108	*/
igor_v	11:af609f6dee46	109
igor_v	11:af609f6dee46	110	#ifdef __cplusplus
igor_v	21:bc8c1cec3da6	111	#define __I volatile /!< defines 'read only' permissions /
igor_v	11:af609f6dee46	112	#else
igor_v	21:bc8c1cec3da6	113	#define __I volatile const /!< defines 'read only' permissions /
igor_v	11:af609f6dee46	114	#endif
igor_v	11:af609f6dee46	115	#define __O volatile /!< defines 'write only' permissions /
igor_v	11:af609f6dee46	116	#define __IO volatile /!< defines 'read / write' permissions /
igor_v	11:af609f6dee46	117
igor_v	11:af609f6dee46	118
igor_v	11:af609f6dee46	119
igor_v	21:bc8c1cec3da6	120	/*******************************************************************************
igor_v	21:bc8c1cec3da6	121	* Register Abstraction
igor_v	21:bc8c1cec3da6	122	******************************************************************************/
igor_v	21:bc8c1cec3da6	123	/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
igor_v	21:bc8c1cec3da6	124	@{
igor_v	21:bc8c1cec3da6	125	*/
igor_v	11:af609f6dee46	126
igor_v	11:af609f6dee46	127
igor_v	21:bc8c1cec3da6	128	/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
igor_v	21:bc8c1cec3da6	129	memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
igor_v	21:bc8c1cec3da6	130	@{
igor_v	21:bc8c1cec3da6	131	*/
igor_v	21:bc8c1cec3da6	132	typedef struct {
igor_v	21:bc8c1cec3da6	133	__IO uint32_t ISER[8]; /!< Offset: 0x000 Interrupt Set Enable Register /
igor_v	21:bc8c1cec3da6	134	uint32_t RESERVED0[24];
igor_v	21:bc8c1cec3da6	135	__IO uint32_t ICER[8]; /!< Offset: 0x080 Interrupt Clear Enable Register /
igor_v	21:bc8c1cec3da6	136	uint32_t RSERVED1[24];
igor_v	21:bc8c1cec3da6	137	__IO uint32_t ISPR[8]; /!< Offset: 0x100 Interrupt Set Pending Register /
igor_v	21:bc8c1cec3da6	138	uint32_t RESERVED2[24];
igor_v	21:bc8c1cec3da6	139	__IO uint32_t ICPR[8]; /!< Offset: 0x180 Interrupt Clear Pending Register /
igor_v	21:bc8c1cec3da6	140	uint32_t RESERVED3[24];
igor_v	21:bc8c1cec3da6	141	__IO uint32_t IABR[8]; /!< Offset: 0x200 Interrupt Active bit Register /
igor_v	21:bc8c1cec3da6	142	uint32_t RESERVED4[56];
igor_v	21:bc8c1cec3da6	143	__IO uint8_t IP[240]; /!< Offset: 0x300 Interrupt Priority Register (8Bit wide) /
igor_v	21:bc8c1cec3da6	144	uint32_t RESERVED5[644];
igor_v	21:bc8c1cec3da6	145	__O uint32_t STIR; /!< Offset: 0xE00 Software Trigger Interrupt Register /
igor_v	21:bc8c1cec3da6	146	} NVIC_Type;
igor_v	21:bc8c1cec3da6	147	/@}/ /* end of group CMSIS_CM3_NVIC */
igor_v	11:af609f6dee46	148
igor_v	11:af609f6dee46	149
igor_v	21:bc8c1cec3da6	150	/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
igor_v	21:bc8c1cec3da6	151	memory mapped structure for System Control Block (SCB)
igor_v	21:bc8c1cec3da6	152	@{
igor_v	21:bc8c1cec3da6	153	*/
igor_v	21:bc8c1cec3da6	154	typedef struct {
igor_v	21:bc8c1cec3da6	155	__I uint32_t CPUID; /!< Offset: 0x00 CPU ID Base Register /
igor_v	21:bc8c1cec3da6	156	__IO uint32_t ICSR; /!< Offset: 0x04 Interrupt Control State Register /
igor_v	21:bc8c1cec3da6	157	__IO uint32_t VTOR; /!< Offset: 0x08 Vector Table Offset Register /
igor_v	21:bc8c1cec3da6	158	__IO uint32_t AIRCR; /!< Offset: 0x0C Application Interrupt / Reset Control Register /
igor_v	21:bc8c1cec3da6	159	__IO uint32_t SCR; /!< Offset: 0x10 System Control Register /
igor_v	21:bc8c1cec3da6	160	__IO uint32_t CCR; /!< Offset: 0x14 Configuration Control Register /
igor_v	21:bc8c1cec3da6	161	__IO uint8_t SHP[12]; /!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) /
igor_v	21:bc8c1cec3da6	162	__IO uint32_t SHCSR; /!< Offset: 0x24 System Handler Control and State Register /
igor_v	21:bc8c1cec3da6	163	__IO uint32_t CFSR; /!< Offset: 0x28 Configurable Fault Status Register /
igor_v	21:bc8c1cec3da6	164	__IO uint32_t HFSR; /!< Offset: 0x2C Hard Fault Status Register /
igor_v	21:bc8c1cec3da6	165	__IO uint32_t DFSR; /!< Offset: 0x30 Debug Fault Status Register /
igor_v	21:bc8c1cec3da6	166	__IO uint32_t MMFAR; /!< Offset: 0x34 Mem Manage Address Register /
igor_v	21:bc8c1cec3da6	167	__IO uint32_t BFAR; /!< Offset: 0x38 Bus Fault Address Register /
igor_v	21:bc8c1cec3da6	168	__IO uint32_t AFSR; /!< Offset: 0x3C Auxiliary Fault Status Register /
igor_v	21:bc8c1cec3da6	169	__I uint32_t PFR[2]; /!< Offset: 0x40 Processor Feature Register /
igor_v	21:bc8c1cec3da6	170	__I uint32_t DFR; /!< Offset: 0x48 Debug Feature Register /
igor_v	21:bc8c1cec3da6	171	__I uint32_t ADR; /!< Offset: 0x4C Auxiliary Feature Register /
igor_v	21:bc8c1cec3da6	172	__I uint32_t MMFR[4]; /!< Offset: 0x50 Memory Model Feature Register /
igor_v	21:bc8c1cec3da6	173	__I uint32_t ISAR[5]; /!< Offset: 0x60 ISA Feature Register /
igor_v	21:bc8c1cec3da6	174	} SCB_Type;
igor_v	11:af609f6dee46	175
igor_v	21:bc8c1cec3da6	176	/* SCB CPUID Register Definitions */
igor_v	11:af609f6dee46	177	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
igor_v	11:af609f6dee46	178	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
igor_v	11:af609f6dee46	179
igor_v	11:af609f6dee46	180	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
igor_v	11:af609f6dee46	181	#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
igor_v	11:af609f6dee46	182
igor_v	11:af609f6dee46	183	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
igor_v	11:af609f6dee46	184	#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
igor_v	11:af609f6dee46	185
igor_v	11:af609f6dee46	186	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
igor_v	11:af609f6dee46	187	#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
igor_v	11:af609f6dee46	188
igor_v	21:bc8c1cec3da6	189	/* SCB Interrupt Control State Register Definitions */
igor_v	11:af609f6dee46	190	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
igor_v	11:af609f6dee46	191	#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
igor_v	11:af609f6dee46	192
igor_v	11:af609f6dee46	193	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
igor_v	11:af609f6dee46	194	#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
igor_v	11:af609f6dee46	195
igor_v	11:af609f6dee46	196	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
igor_v	11:af609f6dee46	197	#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
igor_v	11:af609f6dee46	198
igor_v	11:af609f6dee46	199	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
igor_v	11:af609f6dee46	200	#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
igor_v	11:af609f6dee46	201
igor_v	11:af609f6dee46	202	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
igor_v	11:af609f6dee46	203	#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
igor_v	11:af609f6dee46	204
igor_v	11:af609f6dee46	205	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
igor_v	11:af609f6dee46	206	#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
igor_v	11:af609f6dee46	207
igor_v	11:af609f6dee46	208	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
igor_v	11:af609f6dee46	209	#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
igor_v	11:af609f6dee46	210
igor_v	11:af609f6dee46	211	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
igor_v	11:af609f6dee46	212	#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
igor_v	11:af609f6dee46	213
igor_v	11:af609f6dee46	214	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
igor_v	11:af609f6dee46	215	#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
igor_v	11:af609f6dee46	216
igor_v	11:af609f6dee46	217	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
igor_v	11:af609f6dee46	218	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
igor_v	11:af609f6dee46	219
igor_v	21:bc8c1cec3da6	220	/* SCB Interrupt Control State Register Definitions */
igor_v	11:af609f6dee46	221	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
igor_v	11:af609f6dee46	222	#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
igor_v	11:af609f6dee46	223
igor_v	11:af609f6dee46	224	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
igor_v	11:af609f6dee46	225	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
igor_v	11:af609f6dee46	226
igor_v	21:bc8c1cec3da6	227	/* SCB Application Interrupt and Reset Control Register Definitions */
igor_v	11:af609f6dee46	228	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
igor_v	11:af609f6dee46	229	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
igor_v	11:af609f6dee46	230
igor_v	11:af609f6dee46	231	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
igor_v	11:af609f6dee46	232	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
igor_v	11:af609f6dee46	233
igor_v	11:af609f6dee46	234	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
igor_v	11:af609f6dee46	235	#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
igor_v	11:af609f6dee46	236
igor_v	11:af609f6dee46	237	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
igor_v	11:af609f6dee46	238	#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
igor_v	11:af609f6dee46	239
igor_v	11:af609f6dee46	240	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
igor_v	11:af609f6dee46	241	#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
igor_v	11:af609f6dee46	242
igor_v	11:af609f6dee46	243	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
igor_v	11:af609f6dee46	244	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
igor_v	11:af609f6dee46	245
igor_v	11:af609f6dee46	246	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
igor_v	11:af609f6dee46	247	#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
igor_v	11:af609f6dee46	248
igor_v	21:bc8c1cec3da6	249	/* SCB System Control Register Definitions */
igor_v	11:af609f6dee46	250	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
igor_v	11:af609f6dee46	251	#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
igor_v	11:af609f6dee46	252
igor_v	11:af609f6dee46	253	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
igor_v	11:af609f6dee46	254	#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
igor_v	11:af609f6dee46	255
igor_v	11:af609f6dee46	256	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
igor_v	11:af609f6dee46	257	#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
igor_v	11:af609f6dee46	258
igor_v	21:bc8c1cec3da6	259	/* SCB Configuration Control Register Definitions */
igor_v	11:af609f6dee46	260	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
igor_v	11:af609f6dee46	261	#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
igor_v	11:af609f6dee46	262
igor_v	11:af609f6dee46	263	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
igor_v	11:af609f6dee46	264	#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
igor_v	11:af609f6dee46	265
igor_v	11:af609f6dee46	266	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
igor_v	11:af609f6dee46	267	#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
igor_v	11:af609f6dee46	268
igor_v	11:af609f6dee46	269	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
igor_v	11:af609f6dee46	270	#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
igor_v	11:af609f6dee46	271
igor_v	11:af609f6dee46	272	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
igor_v	11:af609f6dee46	273	#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
igor_v	11:af609f6dee46	274
igor_v	11:af609f6dee46	275	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
igor_v	11:af609f6dee46	276	#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
igor_v	11:af609f6dee46	277
igor_v	21:bc8c1cec3da6	278	/* SCB System Handler Control and State Register Definitions */
igor_v	11:af609f6dee46	279	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
igor_v	11:af609f6dee46	280	#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
igor_v	11:af609f6dee46	281
igor_v	11:af609f6dee46	282	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
igor_v	11:af609f6dee46	283	#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
igor_v	11:af609f6dee46	284
igor_v	11:af609f6dee46	285	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
igor_v	11:af609f6dee46	286	#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
igor_v	11:af609f6dee46	287
igor_v	11:af609f6dee46	288	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
igor_v	11:af609f6dee46	289	#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
igor_v	11:af609f6dee46	290
igor_v	11:af609f6dee46	291	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
igor_v	11:af609f6dee46	292	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
igor_v	11:af609f6dee46	293
igor_v	11:af609f6dee46	294	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
igor_v	11:af609f6dee46	295	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
igor_v	11:af609f6dee46	296
igor_v	11:af609f6dee46	297	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
igor_v	11:af609f6dee46	298	#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
igor_v	11:af609f6dee46	299
igor_v	11:af609f6dee46	300	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
igor_v	11:af609f6dee46	301	#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
igor_v	11:af609f6dee46	302
igor_v	11:af609f6dee46	303	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
igor_v	11:af609f6dee46	304	#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
igor_v	11:af609f6dee46	305
igor_v	11:af609f6dee46	306	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
igor_v	11:af609f6dee46	307	#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
igor_v	11:af609f6dee46	308
igor_v	11:af609f6dee46	309	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
igor_v	11:af609f6dee46	310	#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
igor_v	21:bc8c1cec3da6	311
igor_v	11:af609f6dee46	312	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
igor_v	11:af609f6dee46	313	#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
igor_v	11:af609f6dee46	314
igor_v	11:af609f6dee46	315	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
igor_v	11:af609f6dee46	316	#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
igor_v	11:af609f6dee46	317
igor_v	11:af609f6dee46	318	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
igor_v	11:af609f6dee46	319	#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
igor_v	11:af609f6dee46	320
igor_v	21:bc8c1cec3da6	321	/* SCB Configurable Fault Status Registers Definitions */
igor_v	11:af609f6dee46	322	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
igor_v	11:af609f6dee46	323	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
igor_v	11:af609f6dee46	324
igor_v	11:af609f6dee46	325	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
igor_v	11:af609f6dee46	326	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
igor_v	11:af609f6dee46	327
igor_v	11:af609f6dee46	328	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
igor_v	11:af609f6dee46	329	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
igor_v	11:af609f6dee46	330
igor_v	21:bc8c1cec3da6	331	/* SCB Hard Fault Status Registers Definitions */
igor_v	11:af609f6dee46	332	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
igor_v	11:af609f6dee46	333	#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
igor_v	11:af609f6dee46	334
igor_v	11:af609f6dee46	335	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
igor_v	11:af609f6dee46	336	#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
igor_v	11:af609f6dee46	337
igor_v	11:af609f6dee46	338	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
igor_v	11:af609f6dee46	339	#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
igor_v	11:af609f6dee46	340
igor_v	21:bc8c1cec3da6	341	/* SCB Debug Fault Status Register Definitions */
igor_v	11:af609f6dee46	342	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
igor_v	11:af609f6dee46	343	#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
igor_v	11:af609f6dee46	344
igor_v	11:af609f6dee46	345	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
igor_v	11:af609f6dee46	346	#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
igor_v	11:af609f6dee46	347
igor_v	11:af609f6dee46	348	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
igor_v	11:af609f6dee46	349	#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
igor_v	11:af609f6dee46	350
igor_v	11:af609f6dee46	351	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
igor_v	11:af609f6dee46	352	#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
igor_v	11:af609f6dee46	353
igor_v	11:af609f6dee46	354	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
igor_v	11:af609f6dee46	355	#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
igor_v	21:bc8c1cec3da6	356	/@}/ /* end of group CMSIS_CM3_SCB */
igor_v	11:af609f6dee46	357
igor_v	11:af609f6dee46	358
igor_v	21:bc8c1cec3da6	359	/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
igor_v	21:bc8c1cec3da6	360	memory mapped structure for SysTick
igor_v	21:bc8c1cec3da6	361	@{
igor_v	21:bc8c1cec3da6	362	*/
igor_v	21:bc8c1cec3da6	363	typedef struct {
igor_v	21:bc8c1cec3da6	364	__IO uint32_t CTRL; /!< Offset: 0x00 SysTick Control and Status Register /
igor_v	21:bc8c1cec3da6	365	__IO uint32_t LOAD; /!< Offset: 0x04 SysTick Reload Value Register /
igor_v	21:bc8c1cec3da6	366	__IO uint32_t VAL; /!< Offset: 0x08 SysTick Current Value Register /
igor_v	21:bc8c1cec3da6	367	__I uint32_t CALIB; /!< Offset: 0x0C SysTick Calibration Register /
igor_v	21:bc8c1cec3da6	368	} SysTick_Type;
igor_v	11:af609f6dee46	369
igor_v	21:bc8c1cec3da6	370	/* SysTick Control / Status Register Definitions */
igor_v	11:af609f6dee46	371	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
igor_v	11:af609f6dee46	372	#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
igor_v	11:af609f6dee46	373
igor_v	11:af609f6dee46	374	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
igor_v	11:af609f6dee46	375	#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
igor_v	11:af609f6dee46	376
igor_v	11:af609f6dee46	377	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
igor_v	11:af609f6dee46	378	#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
igor_v	11:af609f6dee46	379
igor_v	11:af609f6dee46	380	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
igor_v	11:af609f6dee46	381	#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
igor_v	11:af609f6dee46	382
igor_v	21:bc8c1cec3da6	383	/* SysTick Reload Register Definitions */
igor_v	11:af609f6dee46	384	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
igor_v	11:af609f6dee46	385	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
igor_v	11:af609f6dee46	386
igor_v	21:bc8c1cec3da6	387	/* SysTick Current Register Definitions */
igor_v	11:af609f6dee46	388	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
igor_v	11:af609f6dee46	389	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
igor_v	11:af609f6dee46	390
igor_v	21:bc8c1cec3da6	391	/* SysTick Calibration Register Definitions */
igor_v	11:af609f6dee46	392	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
igor_v	11:af609f6dee46	393	#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
igor_v	11:af609f6dee46	394
igor_v	11:af609f6dee46	395	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
igor_v	11:af609f6dee46	396	#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
igor_v	11:af609f6dee46	397
igor_v	11:af609f6dee46	398	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
igor_v	11:af609f6dee46	399	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
igor_v	21:bc8c1cec3da6	400	/@}/ /* end of group CMSIS_CM3_SysTick */
igor_v	11:af609f6dee46	401
igor_v	11:af609f6dee46	402
igor_v	21:bc8c1cec3da6	403	/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
igor_v	21:bc8c1cec3da6	404	memory mapped structure for Instrumentation Trace Macrocell (ITM)
igor_v	21:bc8c1cec3da6	405	@{
igor_v	21:bc8c1cec3da6	406	*/
igor_v	21:bc8c1cec3da6	407	typedef struct {
igor_v	21:bc8c1cec3da6	408	__O union {
igor_v	21:bc8c1cec3da6	409	__O uint8_t u8; /!< Offset: ITM Stimulus Port 8-bit /
igor_v	21:bc8c1cec3da6	410	__O uint16_t u16; /!< Offset: ITM Stimulus Port 16-bit /
igor_v	21:bc8c1cec3da6	411	__O uint32_t u32; /!< Offset: ITM Stimulus Port 32-bit /
igor_v	21:bc8c1cec3da6	412	} PORT [32]; /!< Offset: 0x00 ITM Stimulus Port Registers /
igor_v	21:bc8c1cec3da6	413	uint32_t RESERVED0[864];
igor_v	21:bc8c1cec3da6	414	__IO uint32_t TER; /!< Offset: ITM Trace Enable Register /
igor_v	21:bc8c1cec3da6	415	uint32_t RESERVED1[15];
igor_v	21:bc8c1cec3da6	416	__IO uint32_t TPR; /!< Offset: ITM Trace Privilege Register /
igor_v	21:bc8c1cec3da6	417	uint32_t RESERVED2[15];
igor_v	21:bc8c1cec3da6	418	__IO uint32_t TCR; /!< Offset: ITM Trace Control Register /
igor_v	21:bc8c1cec3da6	419	uint32_t RESERVED3[29];
igor_v	21:bc8c1cec3da6	420	__IO uint32_t IWR; /!< Offset: ITM Integration Write Register /
igor_v	21:bc8c1cec3da6	421	__IO uint32_t IRR; /!< Offset: ITM Integration Read Register /
igor_v	21:bc8c1cec3da6	422	__IO uint32_t IMCR; /!< Offset: ITM Integration Mode Control Register /
igor_v	21:bc8c1cec3da6	423	uint32_t RESERVED4[43];
igor_v	21:bc8c1cec3da6	424	__IO uint32_t LAR; /!< Offset: ITM Lock Access Register /
igor_v	21:bc8c1cec3da6	425	__IO uint32_t LSR; /!< Offset: ITM Lock Status Register /
igor_v	21:bc8c1cec3da6	426	uint32_t RESERVED5[6];
igor_v	21:bc8c1cec3da6	427	__I uint32_t PID4; /!< Offset: ITM Peripheral Identification Register #4 /
igor_v	21:bc8c1cec3da6	428	__I uint32_t PID5; /!< Offset: ITM Peripheral Identification Register #5 /
igor_v	21:bc8c1cec3da6	429	__I uint32_t PID6; /!< Offset: ITM Peripheral Identification Register #6 /
igor_v	21:bc8c1cec3da6	430	__I uint32_t PID7; /!< Offset: ITM Peripheral Identification Register #7 /
igor_v	21:bc8c1cec3da6	431	__I uint32_t PID0; /!< Offset: ITM Peripheral Identification Register #0 /
igor_v	21:bc8c1cec3da6	432	__I uint32_t PID1; /!< Offset: ITM Peripheral Identification Register #1 /
igor_v	21:bc8c1cec3da6	433	__I uint32_t PID2; /!< Offset: ITM Peripheral Identification Register #2 /
igor_v	21:bc8c1cec3da6	434	__I uint32_t PID3; /!< Offset: ITM Peripheral Identification Register #3 /
igor_v	21:bc8c1cec3da6	435	__I uint32_t CID0; /!< Offset: ITM Component Identification Register #0 /
igor_v	21:bc8c1cec3da6	436	__I uint32_t CID1; /!< Offset: ITM Component Identification Register #1 /
igor_v	21:bc8c1cec3da6	437	__I uint32_t CID2; /!< Offset: ITM Component Identification Register #2 /
igor_v	21:bc8c1cec3da6	438	__I uint32_t CID3; /!< Offset: ITM Component Identification Register #3 /
igor_v	21:bc8c1cec3da6	439	} ITM_Type;
igor_v	11:af609f6dee46	440
igor_v	21:bc8c1cec3da6	441	/* ITM Trace Privilege Register Definitions */
igor_v	11:af609f6dee46	442	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
igor_v	11:af609f6dee46	443	#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
igor_v	11:af609f6dee46	444
igor_v	21:bc8c1cec3da6	445	/* ITM Trace Control Register Definitions */
igor_v	11:af609f6dee46	446	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
igor_v	11:af609f6dee46	447	#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
igor_v	11:af609f6dee46	448
igor_v	11:af609f6dee46	449	#define ITM_TCR_ATBID_Pos 16 /!< ITM TCR: ATBID Position /
igor_v	11:af609f6dee46	450	#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /!< ITM TCR: ATBID Mask /
igor_v	11:af609f6dee46	451
igor_v	11:af609f6dee46	452	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
igor_v	11:af609f6dee46	453	#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
igor_v	11:af609f6dee46	454
igor_v	11:af609f6dee46	455	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
igor_v	11:af609f6dee46	456	#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
igor_v	11:af609f6dee46	457
igor_v	11:af609f6dee46	458	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
igor_v	11:af609f6dee46	459	#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
igor_v	11:af609f6dee46	460
igor_v	11:af609f6dee46	461	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
igor_v	11:af609f6dee46	462	#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
igor_v	11:af609f6dee46	463
igor_v	11:af609f6dee46	464	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
igor_v	11:af609f6dee46	465	#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
igor_v	11:af609f6dee46	466
igor_v	11:af609f6dee46	467	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
igor_v	11:af609f6dee46	468	#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
igor_v	11:af609f6dee46	469
igor_v	21:bc8c1cec3da6	470	/* ITM Integration Write Register Definitions */
igor_v	11:af609f6dee46	471	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
igor_v	11:af609f6dee46	472	#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
igor_v	11:af609f6dee46	473
igor_v	21:bc8c1cec3da6	474	/* ITM Integration Read Register Definitions */
igor_v	11:af609f6dee46	475	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
igor_v	11:af609f6dee46	476	#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
igor_v	11:af609f6dee46	477
igor_v	21:bc8c1cec3da6	478	/* ITM Integration Mode Control Register Definitions */
igor_v	11:af609f6dee46	479	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
igor_v	11:af609f6dee46	480	#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
igor_v	11:af609f6dee46	481
igor_v	21:bc8c1cec3da6	482	/* ITM Lock Status Register Definitions */
igor_v	11:af609f6dee46	483	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
igor_v	11:af609f6dee46	484	#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
igor_v	11:af609f6dee46	485
igor_v	11:af609f6dee46	486	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
igor_v	11:af609f6dee46	487	#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
igor_v	11:af609f6dee46	488
igor_v	11:af609f6dee46	489	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
igor_v	11:af609f6dee46	490	#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
igor_v	21:bc8c1cec3da6	491	/@}/ /* end of group CMSIS_CM3_ITM */
igor_v	11:af609f6dee46	492
igor_v	11:af609f6dee46	493
igor_v	21:bc8c1cec3da6	494	/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
igor_v	21:bc8c1cec3da6	495	memory mapped structure for Interrupt Type
igor_v	21:bc8c1cec3da6	496	@{
igor_v	21:bc8c1cec3da6	497	*/
igor_v	21:bc8c1cec3da6	498	typedef struct {
igor_v	21:bc8c1cec3da6	499	uint32_t RESERVED0;
igor_v	21:bc8c1cec3da6	500	__I uint32_t ICTR; /!< Offset: 0x04 Interrupt Control Type Register /
igor_v	11:af609f6dee46	501	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
igor_v	21:bc8c1cec3da6	502	__IO uint32_t ACTLR; /!< Offset: 0x08 Auxiliary Control Register /
igor_v	11:af609f6dee46	503	#else
igor_v	21:bc8c1cec3da6	504	uint32_t RESERVED1;
igor_v	11:af609f6dee46	505	#endif
igor_v	21:bc8c1cec3da6	506	} InterruptType_Type;
igor_v	11:af609f6dee46	507
igor_v	21:bc8c1cec3da6	508	/* Interrupt Controller Type Register Definitions */
igor_v	11:af609f6dee46	509	#define InterruptType_ICTR_INTLINESNUM_Pos 0 /!< InterruptType ICTR: INTLINESNUM Position /
igor_v	11:af609f6dee46	510	#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /!< InterruptType ICTR: INTLINESNUM Mask /
igor_v	11:af609f6dee46	511
igor_v	21:bc8c1cec3da6	512	/* Auxiliary Control Register Definitions */
igor_v	11:af609f6dee46	513	#define InterruptType_ACTLR_DISFOLD_Pos 2 /!< InterruptType ACTLR: DISFOLD Position /
igor_v	11:af609f6dee46	514	#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /!< InterruptType ACTLR: DISFOLD Mask /
igor_v	11:af609f6dee46	515
igor_v	11:af609f6dee46	516	#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /!< InterruptType ACTLR: DISDEFWBUF Position /
igor_v	11:af609f6dee46	517	#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /!< InterruptType ACTLR: DISDEFWBUF Mask /
igor_v	11:af609f6dee46	518
igor_v	11:af609f6dee46	519	#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /!< InterruptType ACTLR: DISMCYCINT Position /
igor_v	11:af609f6dee46	520	#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /!< InterruptType ACTLR: DISMCYCINT Mask /
igor_v	21:bc8c1cec3da6	521	/@}/ /* end of group CMSIS_CM3_InterruptType */
igor_v	11:af609f6dee46	522
igor_v	11:af609f6dee46	523
igor_v	11:af609f6dee46	524	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
igor_v	21:bc8c1cec3da6	525	/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
igor_v	21:bc8c1cec3da6	526	memory mapped structure for Memory Protection Unit (MPU)
igor_v	21:bc8c1cec3da6	527	@{
igor_v	21:bc8c1cec3da6	528	*/
igor_v	21:bc8c1cec3da6	529	typedef struct {
igor_v	21:bc8c1cec3da6	530	__I uint32_t TYPE; /!< Offset: 0x00 MPU Type Register /
igor_v	21:bc8c1cec3da6	531	__IO uint32_t CTRL; /!< Offset: 0x04 MPU Control Register /
igor_v	21:bc8c1cec3da6	532	__IO uint32_t RNR; /!< Offset: 0x08 MPU Region RNRber Register /
igor_v	21:bc8c1cec3da6	533	__IO uint32_t RBAR; /!< Offset: 0x0C MPU Region Base Address Register /
igor_v	21:bc8c1cec3da6	534	__IO uint32_t RASR; /!< Offset: 0x10 MPU Region Attribute and Size Register /
igor_v	21:bc8c1cec3da6	535	__IO uint32_t RBAR_A1; /!< Offset: 0x14 MPU Alias 1 Region Base Address Register /
igor_v	21:bc8c1cec3da6	536	__IO uint32_t RASR_A1; /!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register /
igor_v	21:bc8c1cec3da6	537	__IO uint32_t RBAR_A2; /!< Offset: 0x1C MPU Alias 2 Region Base Address Register /
igor_v	21:bc8c1cec3da6	538	__IO uint32_t RASR_A2; /!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register /
igor_v	21:bc8c1cec3da6	539	__IO uint32_t RBAR_A3; /!< Offset: 0x24 MPU Alias 3 Region Base Address Register /
igor_v	21:bc8c1cec3da6	540	__IO uint32_t RASR_A3; /!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register /
igor_v	21:bc8c1cec3da6	541	} MPU_Type;
igor_v	11:af609f6dee46	542
igor_v	21:bc8c1cec3da6	543	/* MPU Type Register */
igor_v	11:af609f6dee46	544	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
igor_v	11:af609f6dee46	545	#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
igor_v	11:af609f6dee46	546
igor_v	11:af609f6dee46	547	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
igor_v	11:af609f6dee46	548	#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
igor_v	11:af609f6dee46	549
igor_v	11:af609f6dee46	550	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
igor_v	11:af609f6dee46	551	#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
igor_v	11:af609f6dee46	552
igor_v	21:bc8c1cec3da6	553	/* MPU Control Register */
igor_v	11:af609f6dee46	554	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
igor_v	11:af609f6dee46	555	#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
igor_v	11:af609f6dee46	556
igor_v	11:af609f6dee46	557	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
igor_v	11:af609f6dee46	558	#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
igor_v	11:af609f6dee46	559
igor_v	11:af609f6dee46	560	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
igor_v	11:af609f6dee46	561	#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
igor_v	11:af609f6dee46	562
igor_v	21:bc8c1cec3da6	563	/* MPU Region Number Register */
igor_v	11:af609f6dee46	564	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
igor_v	11:af609f6dee46	565	#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
igor_v	11:af609f6dee46	566
igor_v	21:bc8c1cec3da6	567	/* MPU Region Base Address Register */
igor_v	11:af609f6dee46	568	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
igor_v	11:af609f6dee46	569	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
igor_v	11:af609f6dee46	570
igor_v	11:af609f6dee46	571	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
igor_v	11:af609f6dee46	572	#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
igor_v	11:af609f6dee46	573
igor_v	11:af609f6dee46	574	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
igor_v	11:af609f6dee46	575	#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
igor_v	11:af609f6dee46	576
igor_v	21:bc8c1cec3da6	577	/* MPU Region Attribute and Size Register */
igor_v	11:af609f6dee46	578	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: XN Position /
igor_v	11:af609f6dee46	579	#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /!< MPU RASR: XN Mask /
igor_v	11:af609f6dee46	580
igor_v	11:af609f6dee46	581	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: AP Position /
igor_v	11:af609f6dee46	582	#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /!< MPU RASR: AP Mask /
igor_v	11:af609f6dee46	583
igor_v	11:af609f6dee46	584	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: TEX Position /
igor_v	11:af609f6dee46	585	#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /!< MPU RASR: TEX Mask /
igor_v	11:af609f6dee46	586
igor_v	11:af609f6dee46	587	#define MPU_RASR_S_Pos 18 /!< MPU RASR: Shareable bit Position /
igor_v	11:af609f6dee46	588	#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /!< MPU RASR: Shareable bit Mask /
igor_v	11:af609f6dee46	589
igor_v	11:af609f6dee46	590	#define MPU_RASR_C_Pos 17 /!< MPU RASR: Cacheable bit Position /
igor_v	11:af609f6dee46	591	#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /!< MPU RASR: Cacheable bit Mask /
igor_v	11:af609f6dee46	592
igor_v	11:af609f6dee46	593	#define MPU_RASR_B_Pos 16 /!< MPU RASR: Bufferable bit Position /
igor_v	11:af609f6dee46	594	#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /!< MPU RASR: Bufferable bit Mask /
igor_v	11:af609f6dee46	595
igor_v	11:af609f6dee46	596	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
igor_v	11:af609f6dee46	597	#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
igor_v	11:af609f6dee46	598
igor_v	11:af609f6dee46	599	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
igor_v	11:af609f6dee46	600	#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
igor_v	11:af609f6dee46	601
igor_v	11:af609f6dee46	602	#define MPU_RASR_ENA_Pos 0 /!< MPU RASR: Region enable bit Position /
igor_v	11:af609f6dee46	603	#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /!< MPU RASR: Region enable bit Disable Mask /
igor_v	11:af609f6dee46	604
igor_v	21:bc8c1cec3da6	605	/@}/ /* end of group CMSIS_CM3_MPU */
igor_v	11:af609f6dee46	606	#endif
igor_v	11:af609f6dee46	607
igor_v	11:af609f6dee46	608
igor_v	21:bc8c1cec3da6	609	/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
igor_v	21:bc8c1cec3da6	610	memory mapped structure for Core Debug Register
igor_v	21:bc8c1cec3da6	611	@{
igor_v	21:bc8c1cec3da6	612	*/
igor_v	21:bc8c1cec3da6	613	typedef struct {
igor_v	21:bc8c1cec3da6	614	__IO uint32_t DHCSR; /!< Offset: 0x00 Debug Halting Control and Status Register /
igor_v	21:bc8c1cec3da6	615	__O uint32_t DCRSR; /!< Offset: 0x04 Debug Core Register Selector Register /
igor_v	21:bc8c1cec3da6	616	__IO uint32_t DCRDR; /!< Offset: 0x08 Debug Core Register Data Register /
igor_v	21:bc8c1cec3da6	617	__IO uint32_t DEMCR; /!< Offset: 0x0C Debug Exception and Monitor Control Register /
igor_v	21:bc8c1cec3da6	618	} CoreDebug_Type;
igor_v	11:af609f6dee46	619
igor_v	21:bc8c1cec3da6	620	/* Debug Halting Control and Status Register */
igor_v	11:af609f6dee46	621	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
igor_v	11:af609f6dee46	622	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
igor_v	11:af609f6dee46	623
igor_v	11:af609f6dee46	624	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
igor_v	11:af609f6dee46	625	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
igor_v	11:af609f6dee46	626
igor_v	11:af609f6dee46	627	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
igor_v	11:af609f6dee46	628	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
igor_v	11:af609f6dee46	629
igor_v	11:af609f6dee46	630	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
igor_v	11:af609f6dee46	631	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
igor_v	11:af609f6dee46	632
igor_v	11:af609f6dee46	633	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
igor_v	11:af609f6dee46	634	#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
igor_v	11:af609f6dee46	635
igor_v	11:af609f6dee46	636	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
igor_v	11:af609f6dee46	637	#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
igor_v	11:af609f6dee46	638
igor_v	11:af609f6dee46	639	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
igor_v	11:af609f6dee46	640	#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
igor_v	11:af609f6dee46	641
igor_v	11:af609f6dee46	642	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
igor_v	11:af609f6dee46	643	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
igor_v	11:af609f6dee46	644
igor_v	11:af609f6dee46	645	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
igor_v	11:af609f6dee46	646	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
igor_v	11:af609f6dee46	647
igor_v	11:af609f6dee46	648	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
igor_v	11:af609f6dee46	649	#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
igor_v	11:af609f6dee46	650
igor_v	11:af609f6dee46	651	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
igor_v	11:af609f6dee46	652	#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
igor_v	11:af609f6dee46	653
igor_v	11:af609f6dee46	654	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
igor_v	11:af609f6dee46	655	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
igor_v	11:af609f6dee46	656
igor_v	21:bc8c1cec3da6	657	/* Debug Core Register Selector Register */
igor_v	11:af609f6dee46	658	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
igor_v	11:af609f6dee46	659	#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
igor_v	11:af609f6dee46	660
igor_v	11:af609f6dee46	661	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
igor_v	11:af609f6dee46	662	#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
igor_v	11:af609f6dee46	663
igor_v	21:bc8c1cec3da6	664	/* Debug Exception and Monitor Control Register */
igor_v	11:af609f6dee46	665	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
igor_v	11:af609f6dee46	666	#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
igor_v	11:af609f6dee46	667
igor_v	11:af609f6dee46	668	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
igor_v	11:af609f6dee46	669	#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
igor_v	11:af609f6dee46	670
igor_v	11:af609f6dee46	671	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
igor_v	11:af609f6dee46	672	#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
igor_v	11:af609f6dee46	673
igor_v	11:af609f6dee46	674	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
igor_v	11:af609f6dee46	675	#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
igor_v	11:af609f6dee46	676
igor_v	11:af609f6dee46	677	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
igor_v	11:af609f6dee46	678	#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
igor_v	11:af609f6dee46	679
igor_v	11:af609f6dee46	680	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
igor_v	11:af609f6dee46	681	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
igor_v	11:af609f6dee46	682
igor_v	11:af609f6dee46	683	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
igor_v	11:af609f6dee46	684	#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
igor_v	11:af609f6dee46	685
igor_v	11:af609f6dee46	686	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
igor_v	11:af609f6dee46	687	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
igor_v	11:af609f6dee46	688
igor_v	11:af609f6dee46	689	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
igor_v	11:af609f6dee46	690	#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
igor_v	11:af609f6dee46	691
igor_v	11:af609f6dee46	692	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
igor_v	11:af609f6dee46	693	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
igor_v	11:af609f6dee46	694
igor_v	11:af609f6dee46	695	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
igor_v	11:af609f6dee46	696	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
igor_v	11:af609f6dee46	697
igor_v	11:af609f6dee46	698	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
igor_v	11:af609f6dee46	699	#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
igor_v	11:af609f6dee46	700
igor_v	11:af609f6dee46	701	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
igor_v	11:af609f6dee46	702	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
igor_v	21:bc8c1cec3da6	703	/@}/ /* end of group CMSIS_CM3_CoreDebug */
igor_v	11:af609f6dee46	704
igor_v	11:af609f6dee46	705
igor_v	21:bc8c1cec3da6	706	/* Memory mapping of Cortex-M3 Hardware */
igor_v	11:af609f6dee46	707	#define SCS_BASE (0xE000E000) /!< System Control Space Base Address /
igor_v	11:af609f6dee46	708	#define ITM_BASE (0xE0000000) /!< ITM Base Address /
igor_v	11:af609f6dee46	709	#define CoreDebug_BASE (0xE000EDF0) /!< Core Debug Base Address /
igor_v	11:af609f6dee46	710	#define SysTick_BASE (SCS_BASE + 0x0010) /!< SysTick Base Address /
igor_v	11:af609f6dee46	711	#define NVIC_BASE (SCS_BASE + 0x0100) /!< NVIC Base Address /
igor_v	11:af609f6dee46	712	#define SCB_BASE (SCS_BASE + 0x0D00) /!< System Control Block Base Address /
igor_v	11:af609f6dee46	713
igor_v	11:af609f6dee46	714	#define InterruptType ((InterruptType_Type ) SCS_BASE) /!< Interrupt Type Register */
igor_v	11:af609f6dee46	715	#define SCB ((SCB_Type ) SCB_BASE) /!< SCB configuration struct */
igor_v	11:af609f6dee46	716	#define SysTick ((SysTick_Type ) SysTick_BASE) /!< SysTick configuration struct */
igor_v	11:af609f6dee46	717	#define NVIC ((NVIC_Type ) NVIC_BASE) /!< NVIC configuration struct */
igor_v	11:af609f6dee46	718	#define ITM ((ITM_Type ) ITM_BASE) /!< ITM configuration struct */
igor_v	11:af609f6dee46	719	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
igor_v	11:af609f6dee46	720
igor_v	11:af609f6dee46	721	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
igor_v	21:bc8c1cec3da6	722	#define MPU_BASE (SCS_BASE + 0x0D90) /!< Memory Protection Unit /
igor_v	21:bc8c1cec3da6	723	#define MPU ((MPU_Type) MPU_BASE) /!< Memory Protection Unit */
igor_v	11:af609f6dee46	724	#endif
igor_v	11:af609f6dee46	725
igor_v	21:bc8c1cec3da6	726	/@}/ /* end of group CMSIS_CM3_core_register */
igor_v	11:af609f6dee46	727
igor_v	11:af609f6dee46	728
igor_v	21:bc8c1cec3da6	729	/*******************************************************************************
igor_v	21:bc8c1cec3da6	730	* Hardware Abstraction Layer
igor_v	21:bc8c1cec3da6	731	******************************************************************************/
igor_v	0:8ad47e2b6f00	732
igor_v	0:8ad47e2b6f00	733	#if defined ( __CC_ARM )
igor_v	21:bc8c1cec3da6	734	#define __ASM __asm /!< asm keyword for ARM Compiler /
igor_v	21:bc8c1cec3da6	735	#define __INLINE __inline /!< inline keyword for ARM Compiler /
igor_v	0:8ad47e2b6f00	736
igor_v	0:8ad47e2b6f00	737	#elif defined ( __ICCARM__ )
igor_v	21:bc8c1cec3da6	738	#define __ASM __asm /!< asm keyword for IAR Compiler /
igor_v	21:bc8c1cec3da6	739	#define __INLINE inline /!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! /
igor_v	0:8ad47e2b6f00	740
igor_v	0:8ad47e2b6f00	741	#elif defined ( __GNUC__ )
igor_v	21:bc8c1cec3da6	742	#define __ASM __asm /!< asm keyword for GNU Compiler /
igor_v	21:bc8c1cec3da6	743	#define __INLINE inline /!< inline keyword for GNU Compiler /
igor_v	0:8ad47e2b6f00	744
igor_v	0:8ad47e2b6f00	745	#elif defined ( __TASKING__ )
igor_v	21:bc8c1cec3da6	746	#define __ASM __asm /!< asm keyword for TASKING Compiler /
igor_v	21:bc8c1cec3da6	747	#define __INLINE inline /!< inline keyword for TASKING Compiler /
igor_v	0:8ad47e2b6f00	748
igor_v	0:8ad47e2b6f00	749	#endif
igor_v	0:8ad47e2b6f00	750
igor_v	11:af609f6dee46	751
igor_v	21:bc8c1cec3da6	752	/* ################### Compiler specific Intrinsics ########################### */
igor_v	11:af609f6dee46	753
igor_v	11:af609f6dee46	754	#if defined ( __CC_ARM ) /------------------RealView Compiler -----------------/
igor_v	21:bc8c1cec3da6	755	/* ARM armcc specific functions */
igor_v	11:af609f6dee46	756
igor_v	11:af609f6dee46	757	#define __enable_fault_irq __enable_fiq
igor_v	11:af609f6dee46	758	#define __disable_fault_irq __disable_fiq
igor_v	11:af609f6dee46	759
igor_v	11:af609f6dee46	760	#define __NOP __nop
igor_v	11:af609f6dee46	761	#define __WFI __wfi
igor_v	11:af609f6dee46	762	#define __WFE __wfe
igor_v	11:af609f6dee46	763	#define __SEV __sev
igor_v	11:af609f6dee46	764	#define __ISB() __isb(0)
igor_v	11:af609f6dee46	765	#define __DSB() __dsb(0)
igor_v	11:af609f6dee46	766	#define __DMB() __dmb(0)
igor_v	11:af609f6dee46	767	#define __REV __rev
igor_v	11:af609f6dee46	768	#define __RBIT __rbit
igor_v	11:af609f6dee46	769	#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
igor_v	11:af609f6dee46	770	#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
igor_v	11:af609f6dee46	771	#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
igor_v	11:af609f6dee46	772	#define __STREXB(value, ptr) __strex(value, ptr)
igor_v	11:af609f6dee46	773	#define __STREXH(value, ptr) __strex(value, ptr)
igor_v	11:af609f6dee46	774	#define __STREXW(value, ptr) __strex(value, ptr)
igor_v	11:af609f6dee46	775
igor_v	11:af609f6dee46	776
igor_v	21:bc8c1cec3da6	777	/* intrinsic unsigned long long __ldrexd(volatile void ptr) /
igor_v	21:bc8c1cec3da6	778	/* intrinsic int __strexd(unsigned long long val, volatile void ptr) /
igor_v	21:bc8c1cec3da6	779	/* intrinsic void __enable_irq(); */
igor_v	21:bc8c1cec3da6	780	/* intrinsic void __disable_irq(); */
igor_v	11:af609f6dee46	781
igor_v	11:af609f6dee46	782
igor_v	21:bc8c1cec3da6	783	/**
igor_v	21:bc8c1cec3da6	784	* @brief Return the Process Stack Pointer
igor_v	21:bc8c1cec3da6	785	*
igor_v	21:bc8c1cec3da6	786	* @return ProcessStackPointer
igor_v	21:bc8c1cec3da6	787	*
igor_v	21:bc8c1cec3da6	788	* Return the actual process stack pointer
igor_v	21:bc8c1cec3da6	789	*/
igor_v	21:bc8c1cec3da6	790	extern uint32_t __get_PSP(void);
igor_v	0:8ad47e2b6f00	791
igor_v	21:bc8c1cec3da6	792	/**
igor_v	21:bc8c1cec3da6	793	* @brief Set the Process Stack Pointer
igor_v	21:bc8c1cec3da6	794	*
igor_v	21:bc8c1cec3da6	795	* @param topOfProcStack Process Stack Pointer
igor_v	21:bc8c1cec3da6	796	*
igor_v	21:bc8c1cec3da6	797	* Assign the value ProcessStackPointer to the MSP
igor_v	21:bc8c1cec3da6	798	* (process stack pointer) Cortex processor register
igor_v	21:bc8c1cec3da6	799	*/
igor_v	21:bc8c1cec3da6	800	extern void __set_PSP(uint32_t topOfProcStack);
igor_v	11:af609f6dee46	801
igor_v	21:bc8c1cec3da6	802	/**
igor_v	21:bc8c1cec3da6	803	* @brief Return the Main Stack Pointer
igor_v	21:bc8c1cec3da6	804	*
igor_v	21:bc8c1cec3da6	805	* @return Main Stack Pointer
igor_v	21:bc8c1cec3da6	806	*
igor_v	21:bc8c1cec3da6	807	* Return the current value of the MSP (main stack pointer)
igor_v	21:bc8c1cec3da6	808	* Cortex processor register
igor_v	21:bc8c1cec3da6	809	*/
igor_v	21:bc8c1cec3da6	810	extern uint32_t __get_MSP(void);
igor_v	11:af609f6dee46	811
igor_v	21:bc8c1cec3da6	812	/**
igor_v	21:bc8c1cec3da6	813	* @brief Set the Main Stack Pointer
igor_v	21:bc8c1cec3da6	814	*
igor_v	21:bc8c1cec3da6	815	* @param topOfMainStack Main Stack Pointer
igor_v	21:bc8c1cec3da6	816	*
igor_v	21:bc8c1cec3da6	817	* Assign the value mainStackPointer to the MSP
igor_v	21:bc8c1cec3da6	818	* (main stack pointer) Cortex processor register
igor_v	21:bc8c1cec3da6	819	*/
igor_v	21:bc8c1cec3da6	820	extern void __set_MSP(uint32_t topOfMainStack);
igor_v	11:af609f6dee46	821
igor_v	21:bc8c1cec3da6	822	/**
igor_v	21:bc8c1cec3da6	823	* @brief Reverse byte order in unsigned short value
igor_v	21:bc8c1cec3da6	824	*
igor_v	21:bc8c1cec3da6	825	* @param value value to reverse
igor_v	21:bc8c1cec3da6	826	* @return reversed value
igor_v	21:bc8c1cec3da6	827	*
igor_v	21:bc8c1cec3da6	828	* Reverse byte order in unsigned short value
igor_v	21:bc8c1cec3da6	829	*/
igor_v	21:bc8c1cec3da6	830	extern uint32_t __REV16(uint16_t value);
igor_v	11:af609f6dee46	831
igor_v	21:bc8c1cec3da6	832	/**
igor_v	21:bc8c1cec3da6	833	* @brief Reverse byte order in signed short value with sign extension to integer
igor_v	21:bc8c1cec3da6	834	*
igor_v	21:bc8c1cec3da6	835	* @param value value to reverse
igor_v	21:bc8c1cec3da6	836	* @return reversed value
igor_v	21:bc8c1cec3da6	837	*
igor_v	21:bc8c1cec3da6	838	* Reverse byte order in signed short value with sign extension to integer
igor_v	21:bc8c1cec3da6	839	*/
igor_v	21:bc8c1cec3da6	840	extern int32_t __REVSH(int16_t value);
igor_v	0:8ad47e2b6f00	841
igor_v	0:8ad47e2b6f00	842
igor_v	11:af609f6dee46	843	#if (__ARMCC_VERSION < 400000)
igor_v	11:af609f6dee46	844
igor_v	21:bc8c1cec3da6	845	/**
igor_v	21:bc8c1cec3da6	846	* @brief Remove the exclusive lock created by ldrex
igor_v	21:bc8c1cec3da6	847	*
igor_v	21:bc8c1cec3da6	848	* Removes the exclusive lock which is created by ldrex.
igor_v	21:bc8c1cec3da6	849	*/
igor_v	21:bc8c1cec3da6	850	extern void __CLREX(void);
igor_v	11:af609f6dee46	851
igor_v	21:bc8c1cec3da6	852	/**
igor_v	21:bc8c1cec3da6	853	* @brief Return the Base Priority value
igor_v	21:bc8c1cec3da6	854	*
igor_v	21:bc8c1cec3da6	855	* @return BasePriority
igor_v	21:bc8c1cec3da6	856	*
igor_v	21:bc8c1cec3da6	857	* Return the content of the base priority register
igor_v	21:bc8c1cec3da6	858	*/
igor_v	21:bc8c1cec3da6	859	extern uint32_t __get_BASEPRI(void);
igor_v	11:af609f6dee46	860
igor_v	21:bc8c1cec3da6	861	/**
igor_v	21:bc8c1cec3da6	862	* @brief Set the Base Priority value
igor_v	21:bc8c1cec3da6	863	*
igor_v	21:bc8c1cec3da6	864	* @param basePri BasePriority
igor_v	21:bc8c1cec3da6	865	*
igor_v	21:bc8c1cec3da6	866	* Set the base priority register
igor_v	21:bc8c1cec3da6	867	*/
igor_v	21:bc8c1cec3da6	868	extern void __set_BASEPRI(uint32_t basePri);
igor_v	11:af609f6dee46	869
igor_v	21:bc8c1cec3da6	870	/**
igor_v	21:bc8c1cec3da6	871	* @brief Return the Priority Mask value
igor_v	21:bc8c1cec3da6	872	*
igor_v	21:bc8c1cec3da6	873	* @return PriMask
igor_v	21:bc8c1cec3da6	874	*
igor_v	21:bc8c1cec3da6	875	* Return state of the priority mask bit from the priority mask register
igor_v	21:bc8c1cec3da6	876	*/
igor_v	21:bc8c1cec3da6	877	extern uint32_t __get_PRIMASK(void);
igor_v	11:af609f6dee46	878
igor_v	21:bc8c1cec3da6	879	/**
igor_v	21:bc8c1cec3da6	880	* @brief Set the Priority Mask value
igor_v	21:bc8c1cec3da6	881	*
igor_v	21:bc8c1cec3da6	882	* @param priMask PriMask
igor_v	21:bc8c1cec3da6	883	*
igor_v	21:bc8c1cec3da6	884	* Set the priority mask bit in the priority mask register
igor_v	21:bc8c1cec3da6	885	*/
igor_v	21:bc8c1cec3da6	886	extern void __set_PRIMASK(uint32_t priMask);
igor_v	0:8ad47e2b6f00	887
igor_v	21:bc8c1cec3da6	888	/**
igor_v	21:bc8c1cec3da6	889	* @brief Return the Fault Mask value
igor_v	21:bc8c1cec3da6	890	*
igor_v	21:bc8c1cec3da6	891	* @return FaultMask
igor_v	21:bc8c1cec3da6	892	*
igor_v	21:bc8c1cec3da6	893	* Return the content of the fault mask register
igor_v	21:bc8c1cec3da6	894	*/
igor_v	21:bc8c1cec3da6	895	extern uint32_t __get_FAULTMASK(void);
igor_v	11:af609f6dee46	896
igor_v	21:bc8c1cec3da6	897	/**
igor_v	21:bc8c1cec3da6	898	* @brief Set the Fault Mask value
igor_v	21:bc8c1cec3da6	899	*
igor_v	21:bc8c1cec3da6	900	* @param faultMask faultMask value
igor_v	21:bc8c1cec3da6	901	*
igor_v	21:bc8c1cec3da6	902	* Set the fault mask register
igor_v	21:bc8c1cec3da6	903	*/
igor_v	21:bc8c1cec3da6	904	extern void __set_FAULTMASK(uint32_t faultMask);
igor_v	11:af609f6dee46	905
igor_v	21:bc8c1cec3da6	906	/**
igor_v	21:bc8c1cec3da6	907	* @brief Return the Control Register value
igor_v	21:bc8c1cec3da6	908	*
igor_v	21:bc8c1cec3da6	909	* @return Control value
igor_v	21:bc8c1cec3da6	910	*
igor_v	21:bc8c1cec3da6	911	* Return the content of the control register
igor_v	21:bc8c1cec3da6	912	*/
igor_v	21:bc8c1cec3da6	913	extern uint32_t __get_CONTROL(void);
igor_v	11:af609f6dee46	914
igor_v	21:bc8c1cec3da6	915	/**
igor_v	21:bc8c1cec3da6	916	* @brief Set the Control Register value
igor_v	21:bc8c1cec3da6	917	*
igor_v	21:bc8c1cec3da6	918	* @param control Control value
igor_v	21:bc8c1cec3da6	919	*
igor_v	21:bc8c1cec3da6	920	* Set the control register
igor_v	21:bc8c1cec3da6	921	*/
igor_v	21:bc8c1cec3da6	922	extern void __set_CONTROL(uint32_t control);
igor_v	11:af609f6dee46	923
igor_v	11:af609f6dee46	924	#else /* (__ARMCC_VERSION >= 400000) */
igor_v	11:af609f6dee46	925
igor_v	21:bc8c1cec3da6	926	/**
igor_v	21:bc8c1cec3da6	927	* @brief Remove the exclusive lock created by ldrex
igor_v	21:bc8c1cec3da6	928	*
igor_v	21:bc8c1cec3da6	929	* Removes the exclusive lock which is created by ldrex.
igor_v	21:bc8c1cec3da6	930	*/
igor_v	11:af609f6dee46	931	#define __CLREX __clrex
igor_v	0:8ad47e2b6f00	932
igor_v	21:bc8c1cec3da6	933	/**
igor_v	21:bc8c1cec3da6	934	* @brief Return the Base Priority value
igor_v	21:bc8c1cec3da6	935	*
igor_v	21:bc8c1cec3da6	936	* @return BasePriority
igor_v	21:bc8c1cec3da6	937	*
igor_v	21:bc8c1cec3da6	938	* Return the content of the base priority register
igor_v	21:bc8c1cec3da6	939	*/
igor_v	21:bc8c1cec3da6	940	static __INLINE uint32_t __get_BASEPRI(void)
igor_v	21:bc8c1cec3da6	941	{
igor_v	21:bc8c1cec3da6	942	register uint32_t __regBasePri __ASM("basepri");
igor_v	21:bc8c1cec3da6	943	return(__regBasePri);
igor_v	21:bc8c1cec3da6	944	}
igor_v	11:af609f6dee46	945
igor_v	21:bc8c1cec3da6	946	/**
igor_v	21:bc8c1cec3da6	947	* @brief Set the Base Priority value
igor_v	21:bc8c1cec3da6	948	*
igor_v	21:bc8c1cec3da6	949	* @param basePri BasePriority
igor_v	21:bc8c1cec3da6	950	*
igor_v	21:bc8c1cec3da6	951	* Set the base priority register
igor_v	21:bc8c1cec3da6	952	*/
igor_v	21:bc8c1cec3da6	953	static __INLINE void __set_BASEPRI(uint32_t basePri)
igor_v	21:bc8c1cec3da6	954	{
igor_v	21:bc8c1cec3da6	955	register uint32_t __regBasePri __ASM("basepri");
igor_v	21:bc8c1cec3da6	956	__regBasePri = (basePri & 0xff);
igor_v	21:bc8c1cec3da6	957	}
igor_v	11:af609f6dee46	958
igor_v	21:bc8c1cec3da6	959	/**
igor_v	21:bc8c1cec3da6	960	* @brief Return the Priority Mask value
igor_v	21:bc8c1cec3da6	961	*
igor_v	21:bc8c1cec3da6	962	* @return PriMask
igor_v	21:bc8c1cec3da6	963	*
igor_v	21:bc8c1cec3da6	964	* Return state of the priority mask bit from the priority mask register
igor_v	21:bc8c1cec3da6	965	*/
igor_v	21:bc8c1cec3da6	966	static __INLINE uint32_t __get_PRIMASK(void)
igor_v	21:bc8c1cec3da6	967	{
igor_v	21:bc8c1cec3da6	968	register uint32_t __regPriMask __ASM("primask");
igor_v	21:bc8c1cec3da6	969	return(__regPriMask);
igor_v	21:bc8c1cec3da6	970	}
igor_v	11:af609f6dee46	971
igor_v	21:bc8c1cec3da6	972	/**
igor_v	21:bc8c1cec3da6	973	* @brief Set the Priority Mask value
igor_v	21:bc8c1cec3da6	974	*
igor_v	21:bc8c1cec3da6	975	* @param priMask PriMask
igor_v	21:bc8c1cec3da6	976	*
igor_v	21:bc8c1cec3da6	977	* Set the priority mask bit in the priority mask register
igor_v	21:bc8c1cec3da6	978	*/
igor_v	21:bc8c1cec3da6	979	static __INLINE void __set_PRIMASK(uint32_t priMask)
igor_v	21:bc8c1cec3da6	980	{
igor_v	21:bc8c1cec3da6	981	register uint32_t __regPriMask __ASM("primask");
igor_v	21:bc8c1cec3da6	982	__regPriMask = (priMask);
igor_v	21:bc8c1cec3da6	983	}
igor_v	0:8ad47e2b6f00	984
igor_v	21:bc8c1cec3da6	985	/**
igor_v	21:bc8c1cec3da6	986	* @brief Return the Fault Mask value
igor_v	21:bc8c1cec3da6	987	*
igor_v	21:bc8c1cec3da6	988	* @return FaultMask
igor_v	21:bc8c1cec3da6	989	*
igor_v	21:bc8c1cec3da6	990	* Return the content of the fault mask register
igor_v	21:bc8c1cec3da6	991	*/
igor_v	21:bc8c1cec3da6	992	static __INLINE uint32_t __get_FAULTMASK(void)
igor_v	21:bc8c1cec3da6	993	{
igor_v	21:bc8c1cec3da6	994	register uint32_t __regFaultMask __ASM("faultmask");
igor_v	21:bc8c1cec3da6	995	return(__regFaultMask);
igor_v	21:bc8c1cec3da6	996	}
igor_v	11:af609f6dee46	997
igor_v	21:bc8c1cec3da6	998	/**
igor_v	21:bc8c1cec3da6	999	* @brief Set the Fault Mask value
igor_v	21:bc8c1cec3da6	1000	*
igor_v	21:bc8c1cec3da6	1001	* @param faultMask faultMask value
igor_v	21:bc8c1cec3da6	1002	*
igor_v	21:bc8c1cec3da6	1003	* Set the fault mask register
igor_v	21:bc8c1cec3da6	1004	*/
igor_v	21:bc8c1cec3da6	1005	static __INLINE void __set_FAULTMASK(uint32_t faultMask)
igor_v	21:bc8c1cec3da6	1006	{
igor_v	21:bc8c1cec3da6	1007	register uint32_t __regFaultMask __ASM("faultmask");
igor_v	21:bc8c1cec3da6	1008	__regFaultMask = (faultMask & 1);
igor_v	21:bc8c1cec3da6	1009	}
igor_v	11:af609f6dee46	1010
igor_v	21:bc8c1cec3da6	1011	/**
igor_v	21:bc8c1cec3da6	1012	* @brief Return the Control Register value
igor_v	21:bc8c1cec3da6	1013	*
igor_v	21:bc8c1cec3da6	1014	* @return Control value
igor_v	21:bc8c1cec3da6	1015	*
igor_v	21:bc8c1cec3da6	1016	* Return the content of the control register
igor_v	21:bc8c1cec3da6	1017	*/
igor_v	21:bc8c1cec3da6	1018	static __INLINE uint32_t __get_CONTROL(void)
igor_v	21:bc8c1cec3da6	1019	{
igor_v	21:bc8c1cec3da6	1020	register uint32_t __regControl __ASM("control");
igor_v	21:bc8c1cec3da6	1021	return(__regControl);
igor_v	21:bc8c1cec3da6	1022	}
igor_v	11:af609f6dee46	1023
igor_v	21:bc8c1cec3da6	1024	/**
igor_v	21:bc8c1cec3da6	1025	* @brief Set the Control Register value
igor_v	21:bc8c1cec3da6	1026	*
igor_v	21:bc8c1cec3da6	1027	* @param control Control value
igor_v	21:bc8c1cec3da6	1028	*
igor_v	21:bc8c1cec3da6	1029	* Set the control register
igor_v	21:bc8c1cec3da6	1030	*/
igor_v	21:bc8c1cec3da6	1031	static __INLINE void __set_CONTROL(uint32_t control)
igor_v	21:bc8c1cec3da6	1032	{
igor_v	21:bc8c1cec3da6	1033	register uint32_t __regControl __ASM("control");
igor_v	21:bc8c1cec3da6	1034	__regControl = control;
igor_v	21:bc8c1cec3da6	1035	}
igor_v	11:af609f6dee46	1036
igor_v	21:bc8c1cec3da6	1037	#endif /* __ARMCC_VERSION */
igor_v	0:8ad47e2b6f00	1038
igor_v	0:8ad47e2b6f00	1039
igor_v	0:8ad47e2b6f00	1040
igor_v	11:af609f6dee46	1041	#elif (defined (__ICCARM__)) /------------------ ICC Compiler -------------------/
igor_v	21:bc8c1cec3da6	1042	/* IAR iccarm specific functions */
igor_v	0:8ad47e2b6f00	1043
igor_v	11:af609f6dee46	1044	#define __enable_irq __enable_interrupt /!< global Interrupt enable /
igor_v	11:af609f6dee46	1045	#define __disable_irq __disable_interrupt /!< global Interrupt disable /
igor_v	11:af609f6dee46	1046
igor_v	21:bc8c1cec3da6	1047	static __INLINE void __enable_fault_irq()
igor_v	21:bc8c1cec3da6	1048	{
igor_v	21:bc8c1cec3da6	1049	__ASM ("cpsie f");
igor_v	21:bc8c1cec3da6	1050	}
igor_v	21:bc8c1cec3da6	1051	static __INLINE void __disable_fault_irq()
igor_v	21:bc8c1cec3da6	1052	{
igor_v	21:bc8c1cec3da6	1053	__ASM ("cpsid f");
igor_v	21:bc8c1cec3da6	1054	}
igor_v	11:af609f6dee46	1055
igor_v	21:bc8c1cec3da6	1056	#define __NOP __no_operation /!< no operation intrinsic in IAR Compiler /
igor_v	21:bc8c1cec3da6	1057	static __INLINE void __WFI()
igor_v	21:bc8c1cec3da6	1058	{
igor_v	21:bc8c1cec3da6	1059	__ASM ("wfi");
igor_v	21:bc8c1cec3da6	1060	}
igor_v	21:bc8c1cec3da6	1061	static __INLINE void __WFE()
igor_v	21:bc8c1cec3da6	1062	{
igor_v	21:bc8c1cec3da6	1063	__ASM ("wfe");
igor_v	21:bc8c1cec3da6	1064	}
igor_v	21:bc8c1cec3da6	1065	static __INLINE void __SEV()
igor_v	21:bc8c1cec3da6	1066	{
igor_v	21:bc8c1cec3da6	1067	__ASM ("sev");
igor_v	21:bc8c1cec3da6	1068	}
igor_v	21:bc8c1cec3da6	1069	static __INLINE void __CLREX()
igor_v	21:bc8c1cec3da6	1070	{
igor_v	21:bc8c1cec3da6	1071	__ASM ("clrex");
igor_v	21:bc8c1cec3da6	1072	}
igor_v	21:bc8c1cec3da6	1073
igor_v	21:bc8c1cec3da6	1074	/* intrinsic void __ISB(void) */
igor_v	21:bc8c1cec3da6	1075	/* intrinsic void __DSB(void) */
igor_v	21:bc8c1cec3da6	1076	/* intrinsic void __DMB(void) */
igor_v	21:bc8c1cec3da6	1077	/* intrinsic void __set_PRIMASK(); */
igor_v	21:bc8c1cec3da6	1078	/* intrinsic void __get_PRIMASK(); */
igor_v	21:bc8c1cec3da6	1079	/* intrinsic void __set_FAULTMASK(); */
igor_v	21:bc8c1cec3da6	1080	/* intrinsic void __get_FAULTMASK(); */
igor_v	21:bc8c1cec3da6	1081	/* intrinsic uint32_t __REV(uint32_t value); */
igor_v	21:bc8c1cec3da6	1082	/* intrinsic uint32_t __REVSH(uint32_t value); */
igor_v	21:bc8c1cec3da6	1083	/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
igor_v	21:bc8c1cec3da6	1084	/* intrinsic unsigned long __LDREX(unsigned long ); /
igor_v	0:8ad47e2b6f00	1085
igor_v	0:8ad47e2b6f00	1086
igor_v	21:bc8c1cec3da6	1087	/**
igor_v	21:bc8c1cec3da6	1088	* @brief Return the Process Stack Pointer
igor_v	21:bc8c1cec3da6	1089	*
igor_v	21:bc8c1cec3da6	1090	* @return ProcessStackPointer
igor_v	21:bc8c1cec3da6	1091	*
igor_v	21:bc8c1cec3da6	1092	* Return the actual process stack pointer
igor_v	21:bc8c1cec3da6	1093	*/
igor_v	21:bc8c1cec3da6	1094	extern uint32_t __get_PSP(void);
igor_v	11:af609f6dee46	1095
igor_v	21:bc8c1cec3da6	1096	/**
igor_v	21:bc8c1cec3da6	1097	* @brief Set the Process Stack Pointer
igor_v	21:bc8c1cec3da6	1098	*
igor_v	21:bc8c1cec3da6	1099	* @param topOfProcStack Process Stack Pointer
igor_v	21:bc8c1cec3da6	1100	*
igor_v	21:bc8c1cec3da6	1101	* Assign the value ProcessStackPointer to the MSP
igor_v	21:bc8c1cec3da6	1102	* (process stack pointer) Cortex processor register
igor_v	21:bc8c1cec3da6	1103	*/
igor_v	21:bc8c1cec3da6	1104	extern void __set_PSP(uint32_t topOfProcStack);
igor_v	11:af609f6dee46	1105
igor_v	21:bc8c1cec3da6	1106	/**
igor_v	21:bc8c1cec3da6	1107	* @brief Return the Main Stack Pointer
igor_v	21:bc8c1cec3da6	1108	*
igor_v	21:bc8c1cec3da6	1109	* @return Main Stack Pointer
igor_v	21:bc8c1cec3da6	1110	*
igor_v	21:bc8c1cec3da6	1111	* Return the current value of the MSP (main stack pointer)
igor_v	21:bc8c1cec3da6	1112	* Cortex processor register
igor_v	21:bc8c1cec3da6	1113	*/
igor_v	21:bc8c1cec3da6	1114	extern uint32_t __get_MSP(void);
igor_v	11:af609f6dee46	1115
igor_v	21:bc8c1cec3da6	1116	/**
igor_v	21:bc8c1cec3da6	1117	* @brief Set the Main Stack Pointer
igor_v	21:bc8c1cec3da6	1118	*
igor_v	21:bc8c1cec3da6	1119	* @param topOfMainStack Main Stack Pointer
igor_v	21:bc8c1cec3da6	1120	*
igor_v	21:bc8c1cec3da6	1121	* Assign the value mainStackPointer to the MSP
igor_v	21:bc8c1cec3da6	1122	* (main stack pointer) Cortex processor register
igor_v	21:bc8c1cec3da6	1123	*/
igor_v	21:bc8c1cec3da6	1124	extern void __set_MSP(uint32_t topOfMainStack);
igor_v	11:af609f6dee46	1125
igor_v	21:bc8c1cec3da6	1126	/**
igor_v	21:bc8c1cec3da6	1127	* @brief Reverse byte order in unsigned short value
igor_v	21:bc8c1cec3da6	1128	*
igor_v	21:bc8c1cec3da6	1129	* @param value value to reverse
igor_v	21:bc8c1cec3da6	1130	* @return reversed value
igor_v	21:bc8c1cec3da6	1131	*
igor_v	21:bc8c1cec3da6	1132	* Reverse byte order in unsigned short value
igor_v	21:bc8c1cec3da6	1133	*/
igor_v	21:bc8c1cec3da6	1134	extern uint32_t __REV16(uint16_t value);
igor_v	11:af609f6dee46	1135
igor_v	21:bc8c1cec3da6	1136	/**
igor_v	21:bc8c1cec3da6	1137	* @brief Reverse bit order of value
igor_v	21:bc8c1cec3da6	1138	*
igor_v	21:bc8c1cec3da6	1139	* @param value value to reverse
igor_v	21:bc8c1cec3da6	1140	* @return reversed value
igor_v	21:bc8c1cec3da6	1141	*
igor_v	21:bc8c1cec3da6	1142	* Reverse bit order of value
igor_v	21:bc8c1cec3da6	1143	*/
igor_v	21:bc8c1cec3da6	1144	extern uint32_t __RBIT(uint32_t value);
igor_v	11:af609f6dee46	1145
igor_v	21:bc8c1cec3da6	1146	/**
igor_v	21:bc8c1cec3da6	1147	* @brief LDR Exclusive (8 bit)
igor_v	21:bc8c1cec3da6	1148	*
igor_v	21:bc8c1cec3da6	1149	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1150	* @return value of (*address)
igor_v	21:bc8c1cec3da6	1151	*
igor_v	21:bc8c1cec3da6	1152	* Exclusive LDR command for 8 bit values)
igor_v	21:bc8c1cec3da6	1153	*/
igor_v	21:bc8c1cec3da6	1154	extern uint8_t __LDREXB(uint8_t *addr);
igor_v	11:af609f6dee46	1155
igor_v	21:bc8c1cec3da6	1156	/**
igor_v	21:bc8c1cec3da6	1157	* @brief LDR Exclusive (16 bit)
igor_v	21:bc8c1cec3da6	1158	*
igor_v	21:bc8c1cec3da6	1159	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1160	* @return value of (*address)
igor_v	21:bc8c1cec3da6	1161	*
igor_v	21:bc8c1cec3da6	1162	* Exclusive LDR command for 16 bit values
igor_v	21:bc8c1cec3da6	1163	*/
igor_v	21:bc8c1cec3da6	1164	extern uint16_t __LDREXH(uint16_t *addr);
igor_v	11:af609f6dee46	1165
igor_v	21:bc8c1cec3da6	1166	/**
igor_v	21:bc8c1cec3da6	1167	* @brief LDR Exclusive (32 bit)
igor_v	21:bc8c1cec3da6	1168	*
igor_v	21:bc8c1cec3da6	1169	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1170	* @return value of (*address)
igor_v	21:bc8c1cec3da6	1171	*
igor_v	21:bc8c1cec3da6	1172	* Exclusive LDR command for 32 bit values
igor_v	21:bc8c1cec3da6	1173	*/
igor_v	21:bc8c1cec3da6	1174	extern uint32_t __LDREXW(uint32_t *addr);
igor_v	11:af609f6dee46	1175
igor_v	21:bc8c1cec3da6	1176	/**
igor_v	21:bc8c1cec3da6	1177	* @brief STR Exclusive (8 bit)
igor_v	21:bc8c1cec3da6	1178	*
igor_v	21:bc8c1cec3da6	1179	* @param value value to store
igor_v	21:bc8c1cec3da6	1180	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1181	* @return successful / failed
igor_v	21:bc8c1cec3da6	1182	*
igor_v	21:bc8c1cec3da6	1183	* Exclusive STR command for 8 bit values
igor_v	21:bc8c1cec3da6	1184	*/
igor_v	21:bc8c1cec3da6	1185	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
igor_v	11:af609f6dee46	1186
igor_v	21:bc8c1cec3da6	1187	/**
igor_v	21:bc8c1cec3da6	1188	* @brief STR Exclusive (16 bit)
igor_v	21:bc8c1cec3da6	1189	*
igor_v	21:bc8c1cec3da6	1190	* @param value value to store
igor_v	21:bc8c1cec3da6	1191	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1192	* @return successful / failed
igor_v	21:bc8c1cec3da6	1193	*
igor_v	21:bc8c1cec3da6	1194	* Exclusive STR command for 16 bit values
igor_v	21:bc8c1cec3da6	1195	*/
igor_v	21:bc8c1cec3da6	1196	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
igor_v	11:af609f6dee46	1197
igor_v	21:bc8c1cec3da6	1198	/**
igor_v	21:bc8c1cec3da6	1199	* @brief STR Exclusive (32 bit)
igor_v	21:bc8c1cec3da6	1200	*
igor_v	21:bc8c1cec3da6	1201	* @param value value to store
igor_v	21:bc8c1cec3da6	1202	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1203	* @return successful / failed
igor_v	21:bc8c1cec3da6	1204	*
igor_v	21:bc8c1cec3da6	1205	* Exclusive STR command for 32 bit values
igor_v	21:bc8c1cec3da6	1206	*/
igor_v	21:bc8c1cec3da6	1207	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
igor_v	11:af609f6dee46	1208
igor_v	11:af609f6dee46	1209
igor_v	11:af609f6dee46	1210
igor_v	11:af609f6dee46	1211	#elif (defined (__GNUC__)) /------------------ GNU Compiler ---------------------/
igor_v	21:bc8c1cec3da6	1212	/* GNU gcc specific functions */
igor_v	11:af609f6dee46	1213
igor_v	21:bc8c1cec3da6	1214	static __INLINE void __enable_irq()
igor_v	21:bc8c1cec3da6	1215	{
igor_v	21:bc8c1cec3da6	1216	__ASM volatile ("cpsie i");
igor_v	21:bc8c1cec3da6	1217	}
igor_v	21:bc8c1cec3da6	1218	static __INLINE void __disable_irq()
igor_v	21:bc8c1cec3da6	1219	{
igor_v	21:bc8c1cec3da6	1220	__ASM volatile ("cpsid i");
igor_v	21:bc8c1cec3da6	1221	}
igor_v	11:af609f6dee46	1222
igor_v	21:bc8c1cec3da6	1223	static __INLINE void __enable_fault_irq()
igor_v	21:bc8c1cec3da6	1224	{
igor_v	21:bc8c1cec3da6	1225	__ASM volatile ("cpsie f");
igor_v	21:bc8c1cec3da6	1226	}
igor_v	21:bc8c1cec3da6	1227	static __INLINE void __disable_fault_irq()
igor_v	21:bc8c1cec3da6	1228	{
igor_v	21:bc8c1cec3da6	1229	__ASM volatile ("cpsid f");
igor_v	21:bc8c1cec3da6	1230	}
igor_v	11:af609f6dee46	1231
igor_v	21:bc8c1cec3da6	1232	static __INLINE void __NOP()
igor_v	21:bc8c1cec3da6	1233	{
igor_v	21:bc8c1cec3da6	1234	__ASM volatile ("nop");
igor_v	21:bc8c1cec3da6	1235	}
igor_v	21:bc8c1cec3da6	1236	static __INLINE void __WFI()
igor_v	21:bc8c1cec3da6	1237	{
igor_v	21:bc8c1cec3da6	1238	__ASM volatile ("wfi");
igor_v	21:bc8c1cec3da6	1239	}
igor_v	21:bc8c1cec3da6	1240	static __INLINE void __WFE()
igor_v	21:bc8c1cec3da6	1241	{
igor_v	21:bc8c1cec3da6	1242	__ASM volatile ("wfe");
igor_v	21:bc8c1cec3da6	1243	}
igor_v	21:bc8c1cec3da6	1244	static __INLINE void __SEV()
igor_v	21:bc8c1cec3da6	1245	{
igor_v	21:bc8c1cec3da6	1246	__ASM volatile ("sev");
igor_v	21:bc8c1cec3da6	1247	}
igor_v	21:bc8c1cec3da6	1248	static __INLINE void __ISB()
igor_v	21:bc8c1cec3da6	1249	{
igor_v	21:bc8c1cec3da6	1250	__ASM volatile ("isb");
igor_v	21:bc8c1cec3da6	1251	}
igor_v	21:bc8c1cec3da6	1252	static __INLINE void __DSB()
igor_v	21:bc8c1cec3da6	1253	{
igor_v	21:bc8c1cec3da6	1254	__ASM volatile ("dsb");
igor_v	21:bc8c1cec3da6	1255	}
igor_v	21:bc8c1cec3da6	1256	static __INLINE void __DMB()
igor_v	21:bc8c1cec3da6	1257	{
igor_v	21:bc8c1cec3da6	1258	__ASM volatile ("dmb");
igor_v	21:bc8c1cec3da6	1259	}
igor_v	21:bc8c1cec3da6	1260	static __INLINE void __CLREX()
igor_v	21:bc8c1cec3da6	1261	{
igor_v	21:bc8c1cec3da6	1262	__ASM volatile ("clrex");
igor_v	21:bc8c1cec3da6	1263	}
igor_v	0:8ad47e2b6f00	1264
igor_v	0:8ad47e2b6f00	1265
igor_v	21:bc8c1cec3da6	1266	/**
igor_v	21:bc8c1cec3da6	1267	* @brief Return the Process Stack Pointer
igor_v	21:bc8c1cec3da6	1268	*
igor_v	21:bc8c1cec3da6	1269	* @return ProcessStackPointer
igor_v	21:bc8c1cec3da6	1270	*
igor_v	21:bc8c1cec3da6	1271	* Return the actual process stack pointer
igor_v	21:bc8c1cec3da6	1272	*/
igor_v	21:bc8c1cec3da6	1273	extern uint32_t __get_PSP(void);
igor_v	11:af609f6dee46	1274
igor_v	21:bc8c1cec3da6	1275	/**
igor_v	21:bc8c1cec3da6	1276	* @brief Set the Process Stack Pointer
igor_v	21:bc8c1cec3da6	1277	*
igor_v	21:bc8c1cec3da6	1278	* @param topOfProcStack Process Stack Pointer
igor_v	21:bc8c1cec3da6	1279	*
igor_v	21:bc8c1cec3da6	1280	* Assign the value ProcessStackPointer to the MSP
igor_v	21:bc8c1cec3da6	1281	* (process stack pointer) Cortex processor register
igor_v	21:bc8c1cec3da6	1282	*/
igor_v	21:bc8c1cec3da6	1283	extern void __set_PSP(uint32_t topOfProcStack);
igor_v	11:af609f6dee46	1284
igor_v	21:bc8c1cec3da6	1285	/**
igor_v	21:bc8c1cec3da6	1286	* @brief Return the Main Stack Pointer
igor_v	21:bc8c1cec3da6	1287	*
igor_v	21:bc8c1cec3da6	1288	* @return Main Stack Pointer
igor_v	21:bc8c1cec3da6	1289	*
igor_v	21:bc8c1cec3da6	1290	* Return the current value of the MSP (main stack pointer)
igor_v	21:bc8c1cec3da6	1291	* Cortex processor register
igor_v	21:bc8c1cec3da6	1292	*/
igor_v	21:bc8c1cec3da6	1293	extern uint32_t __get_MSP(void);
igor_v	11:af609f6dee46	1294
igor_v	21:bc8c1cec3da6	1295	/**
igor_v	21:bc8c1cec3da6	1296	* @brief Set the Main Stack Pointer
igor_v	21:bc8c1cec3da6	1297	*
igor_v	21:bc8c1cec3da6	1298	* @param topOfMainStack Main Stack Pointer
igor_v	21:bc8c1cec3da6	1299	*
igor_v	21:bc8c1cec3da6	1300	* Assign the value mainStackPointer to the MSP
igor_v	21:bc8c1cec3da6	1301	* (main stack pointer) Cortex processor register
igor_v	21:bc8c1cec3da6	1302	*/
igor_v	21:bc8c1cec3da6	1303	extern void __set_MSP(uint32_t topOfMainStack);
igor_v	11:af609f6dee46	1304
igor_v	21:bc8c1cec3da6	1305	/**
igor_v	21:bc8c1cec3da6	1306	* @brief Return the Base Priority value
igor_v	21:bc8c1cec3da6	1307	*
igor_v	21:bc8c1cec3da6	1308	* @return BasePriority
igor_v	21:bc8c1cec3da6	1309	*
igor_v	21:bc8c1cec3da6	1310	* Return the content of the base priority register
igor_v	21:bc8c1cec3da6	1311	*/
igor_v	21:bc8c1cec3da6	1312	extern uint32_t __get_BASEPRI(void);
igor_v	11:af609f6dee46	1313
igor_v	21:bc8c1cec3da6	1314	/**
igor_v	21:bc8c1cec3da6	1315	* @brief Set the Base Priority value
igor_v	21:bc8c1cec3da6	1316	*
igor_v	21:bc8c1cec3da6	1317	* @param basePri BasePriority
igor_v	21:bc8c1cec3da6	1318	*
igor_v	21:bc8c1cec3da6	1319	* Set the base priority register
igor_v	21:bc8c1cec3da6	1320	*/
igor_v	21:bc8c1cec3da6	1321	extern void __set_BASEPRI(uint32_t basePri);
igor_v	11:af609f6dee46	1322
igor_v	21:bc8c1cec3da6	1323	/**
igor_v	21:bc8c1cec3da6	1324	* @brief Return the Priority Mask value
igor_v	21:bc8c1cec3da6	1325	*
igor_v	21:bc8c1cec3da6	1326	* @return PriMask
igor_v	21:bc8c1cec3da6	1327	*
igor_v	21:bc8c1cec3da6	1328	* Return state of the priority mask bit from the priority mask register
igor_v	21:bc8c1cec3da6	1329	*/
igor_v	21:bc8c1cec3da6	1330	extern uint32_t __get_PRIMASK(void);
igor_v	11:af609f6dee46	1331
igor_v	21:bc8c1cec3da6	1332	/**
igor_v	21:bc8c1cec3da6	1333	* @brief Set the Priority Mask value
igor_v	21:bc8c1cec3da6	1334	*
igor_v	21:bc8c1cec3da6	1335	* @param priMask PriMask
igor_v	21:bc8c1cec3da6	1336	*
igor_v	21:bc8c1cec3da6	1337	* Set the priority mask bit in the priority mask register
igor_v	21:bc8c1cec3da6	1338	*/
igor_v	21:bc8c1cec3da6	1339	extern void __set_PRIMASK(uint32_t priMask);
igor_v	11:af609f6dee46	1340
igor_v	21:bc8c1cec3da6	1341	/**
igor_v	21:bc8c1cec3da6	1342	* @brief Return the Fault Mask value
igor_v	21:bc8c1cec3da6	1343	*
igor_v	21:bc8c1cec3da6	1344	* @return FaultMask
igor_v	21:bc8c1cec3da6	1345	*
igor_v	21:bc8c1cec3da6	1346	* Return the content of the fault mask register
igor_v	21:bc8c1cec3da6	1347	*/
igor_v	21:bc8c1cec3da6	1348	extern uint32_t __get_FAULTMASK(void);
igor_v	11:af609f6dee46	1349
igor_v	21:bc8c1cec3da6	1350	/**
igor_v	21:bc8c1cec3da6	1351	* @brief Set the Fault Mask value
igor_v	21:bc8c1cec3da6	1352	*
igor_v	21:bc8c1cec3da6	1353	* @param faultMask faultMask value
igor_v	21:bc8c1cec3da6	1354	*
igor_v	21:bc8c1cec3da6	1355	* Set the fault mask register
igor_v	21:bc8c1cec3da6	1356	*/
igor_v	21:bc8c1cec3da6	1357	extern void __set_FAULTMASK(uint32_t faultMask);
igor_v	11:af609f6dee46	1358
igor_v	21:bc8c1cec3da6	1359	/**
igor_v	21:bc8c1cec3da6	1360	* @brief Return the Control Register value
igor_v	21:bc8c1cec3da6	1361	*
igor_v	21:bc8c1cec3da6	1362	* @return Control value
igor_v	21:bc8c1cec3da6	1363	*
igor_v	21:bc8c1cec3da6	1364	* Return the content of the control register
igor_v	21:bc8c1cec3da6	1365	*/
igor_v	21:bc8c1cec3da6	1366	extern uint32_t __get_CONTROL(void);
igor_v	11:af609f6dee46	1367
igor_v	21:bc8c1cec3da6	1368	/**
igor_v	21:bc8c1cec3da6	1369	* @brief Set the Control Register value
igor_v	21:bc8c1cec3da6	1370	*
igor_v	21:bc8c1cec3da6	1371	* @param control Control value
igor_v	21:bc8c1cec3da6	1372	*
igor_v	21:bc8c1cec3da6	1373	* Set the control register
igor_v	21:bc8c1cec3da6	1374	*/
igor_v	21:bc8c1cec3da6	1375	extern void __set_CONTROL(uint32_t control);
igor_v	11:af609f6dee46	1376
igor_v	21:bc8c1cec3da6	1377	/**
igor_v	21:bc8c1cec3da6	1378	* @brief Reverse byte order in integer value
igor_v	21:bc8c1cec3da6	1379	*
igor_v	21:bc8c1cec3da6	1380	* @param value value to reverse
igor_v	21:bc8c1cec3da6	1381	* @return reversed value
igor_v	21:bc8c1cec3da6	1382	*
igor_v	21:bc8c1cec3da6	1383	* Reverse byte order in integer value
igor_v	21:bc8c1cec3da6	1384	*/
igor_v	21:bc8c1cec3da6	1385	extern uint32_t __REV(uint32_t value);
igor_v	11:af609f6dee46	1386
igor_v	21:bc8c1cec3da6	1387	/**
igor_v	21:bc8c1cec3da6	1388	* @brief Reverse byte order in unsigned short value
igor_v	21:bc8c1cec3da6	1389	*
igor_v	21:bc8c1cec3da6	1390	* @param value value to reverse
igor_v	21:bc8c1cec3da6	1391	* @return reversed value
igor_v	21:bc8c1cec3da6	1392	*
igor_v	21:bc8c1cec3da6	1393	* Reverse byte order in unsigned short value
igor_v	21:bc8c1cec3da6	1394	*/
igor_v	21:bc8c1cec3da6	1395	extern uint32_t __REV16(uint16_t value);
igor_v	11:af609f6dee46	1396
igor_v	21:bc8c1cec3da6	1397	/**
igor_v	21:bc8c1cec3da6	1398	* @brief Reverse byte order in signed short value with sign extension to integer
igor_v	21:bc8c1cec3da6	1399	*
igor_v	21:bc8c1cec3da6	1400	* @param value value to reverse
igor_v	21:bc8c1cec3da6	1401	* @return reversed value
igor_v	21:bc8c1cec3da6	1402	*
igor_v	21:bc8c1cec3da6	1403	* Reverse byte order in signed short value with sign extension to integer
igor_v	21:bc8c1cec3da6	1404	*/
igor_v	21:bc8c1cec3da6	1405	extern int32_t __REVSH(int16_t value);
igor_v	11:af609f6dee46	1406
igor_v	21:bc8c1cec3da6	1407	/**
igor_v	21:bc8c1cec3da6	1408	* @brief Reverse bit order of value
igor_v	21:bc8c1cec3da6	1409	*
igor_v	21:bc8c1cec3da6	1410	* @param value value to reverse
igor_v	21:bc8c1cec3da6	1411	* @return reversed value
igor_v	21:bc8c1cec3da6	1412	*
igor_v	21:bc8c1cec3da6	1413	* Reverse bit order of value
igor_v	21:bc8c1cec3da6	1414	*/
igor_v	21:bc8c1cec3da6	1415	extern uint32_t __RBIT(uint32_t value);
igor_v	11:af609f6dee46	1416
igor_v	21:bc8c1cec3da6	1417	/**
igor_v	21:bc8c1cec3da6	1418	* @brief LDR Exclusive (8 bit)
igor_v	21:bc8c1cec3da6	1419	*
igor_v	21:bc8c1cec3da6	1420	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1421	* @return value of (*address)
igor_v	21:bc8c1cec3da6	1422	*
igor_v	21:bc8c1cec3da6	1423	* Exclusive LDR command for 8 bit value
igor_v	21:bc8c1cec3da6	1424	*/
igor_v	21:bc8c1cec3da6	1425	extern uint8_t __LDREXB(uint8_t *addr);
igor_v	11:af609f6dee46	1426
igor_v	21:bc8c1cec3da6	1427	/**
igor_v	21:bc8c1cec3da6	1428	* @brief LDR Exclusive (16 bit)
igor_v	21:bc8c1cec3da6	1429	*
igor_v	21:bc8c1cec3da6	1430	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1431	* @return value of (*address)
igor_v	21:bc8c1cec3da6	1432	*
igor_v	21:bc8c1cec3da6	1433	* Exclusive LDR command for 16 bit values
igor_v	21:bc8c1cec3da6	1434	*/
igor_v	21:bc8c1cec3da6	1435	extern uint16_t __LDREXH(uint16_t *addr);
igor_v	11:af609f6dee46	1436
igor_v	21:bc8c1cec3da6	1437	/**
igor_v	21:bc8c1cec3da6	1438	* @brief LDR Exclusive (32 bit)
igor_v	21:bc8c1cec3da6	1439	*
igor_v	21:bc8c1cec3da6	1440	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1441	* @return value of (*address)
igor_v	21:bc8c1cec3da6	1442	*
igor_v	21:bc8c1cec3da6	1443	* Exclusive LDR command for 32 bit values
igor_v	21:bc8c1cec3da6	1444	*/
igor_v	21:bc8c1cec3da6	1445	extern uint32_t __LDREXW(uint32_t *addr);
igor_v	11:af609f6dee46	1446
igor_v	21:bc8c1cec3da6	1447	/**
igor_v	21:bc8c1cec3da6	1448	* @brief STR Exclusive (8 bit)
igor_v	21:bc8c1cec3da6	1449	*
igor_v	21:bc8c1cec3da6	1450	* @param value value to store
igor_v	21:bc8c1cec3da6	1451	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1452	* @return successful / failed
igor_v	21:bc8c1cec3da6	1453	*
igor_v	21:bc8c1cec3da6	1454	* Exclusive STR command for 8 bit values
igor_v	21:bc8c1cec3da6	1455	*/
igor_v	21:bc8c1cec3da6	1456	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
igor_v	11:af609f6dee46	1457
igor_v	21:bc8c1cec3da6	1458	/**
igor_v	21:bc8c1cec3da6	1459	* @brief STR Exclusive (16 bit)
igor_v	21:bc8c1cec3da6	1460	*
igor_v	21:bc8c1cec3da6	1461	* @param value value to store
igor_v	21:bc8c1cec3da6	1462	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1463	* @return successful / failed
igor_v	21:bc8c1cec3da6	1464	*
igor_v	21:bc8c1cec3da6	1465	* Exclusive STR command for 16 bit values
igor_v	21:bc8c1cec3da6	1466	*/
igor_v	21:bc8c1cec3da6	1467	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
igor_v	11:af609f6dee46	1468
igor_v	21:bc8c1cec3da6	1469	/**
igor_v	21:bc8c1cec3da6	1470	* @brief STR Exclusive (32 bit)
igor_v	21:bc8c1cec3da6	1471	*
igor_v	21:bc8c1cec3da6	1472	* @param value value to store
igor_v	21:bc8c1cec3da6	1473	* @param *addr address pointer
igor_v	21:bc8c1cec3da6	1474	* @return successful / failed
igor_v	21:bc8c1cec3da6	1475	*
igor_v	21:bc8c1cec3da6	1476	* Exclusive STR command for 32 bit values
igor_v	21:bc8c1cec3da6	1477	*/
igor_v	21:bc8c1cec3da6	1478	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
igor_v	0:8ad47e2b6f00	1479
igor_v	0:8ad47e2b6f00	1480
igor_v	11:af609f6dee46	1481	#elif (defined (__TASKING__)) /------------------ TASKING Compiler ---------------------/
igor_v	21:bc8c1cec3da6	1482	/* TASKING carm specific functions */
igor_v	0:8ad47e2b6f00	1483
igor_v	21:bc8c1cec3da6	1484	/*
igor_v	21:bc8c1cec3da6	1485	* The CMSIS functions have been implemented as intrinsics in the compiler.
igor_v	21:bc8c1cec3da6	1486	* Please use "carm -?i" to get an up to date list of all instrinsics,
igor_v	21:bc8c1cec3da6	1487	* Including the CMSIS ones.
igor_v	21:bc8c1cec3da6	1488	*/
igor_v	0:8ad47e2b6f00	1489
igor_v	0:8ad47e2b6f00	1490	#endif
igor_v	0:8ad47e2b6f00	1491
igor_v	0:8ad47e2b6f00	1492
igor_v	21:bc8c1cec3da6	1493	/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
igor_v	21:bc8c1cec3da6	1494	Core Function Interface containing:
igor_v	21:bc8c1cec3da6	1495	- Core NVIC Functions
igor_v	21:bc8c1cec3da6	1496	- Core SysTick Functions
igor_v	21:bc8c1cec3da6	1497	- Core Reset Functions
igor_v	21:bc8c1cec3da6	1498	*/
igor_v	21:bc8c1cec3da6	1499	/@{/
igor_v	0:8ad47e2b6f00	1500
igor_v	21:bc8c1cec3da6	1501	/* ########################## NVIC functions #################################### */
igor_v	0:8ad47e2b6f00	1502
igor_v	21:bc8c1cec3da6	1503	/**
igor_v	21:bc8c1cec3da6	1504	* @brief Set the Priority Grouping in NVIC Interrupt Controller
igor_v	21:bc8c1cec3da6	1505	*
igor_v	21:bc8c1cec3da6	1506	* @param PriorityGroup is priority grouping field
igor_v	21:bc8c1cec3da6	1507	*
igor_v	21:bc8c1cec3da6	1508	* Set the priority grouping field using the required unlock sequence.
igor_v	21:bc8c1cec3da6	1509	* The parameter priority_grouping is assigned to the field
igor_v	21:bc8c1cec3da6	1510	* SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
igor_v	21:bc8c1cec3da6	1511	* In case of a conflict between priority grouping and available
igor_v	21:bc8c1cec3da6	1512	* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
igor_v	21:bc8c1cec3da6	1513	*/
igor_v	21:bc8c1cec3da6	1514	static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
igor_v	21:bc8c1cec3da6	1515	{
igor_v	21:bc8c1cec3da6	1516	uint32_t reg_value;
igor_v	21:bc8c1cec3da6	1517	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	21:bc8c1cec3da6	1518
igor_v	21:bc8c1cec3da6	1519	reg_value = SCB->AIRCR; /* read old register configuration */
igor_v	21:bc8c1cec3da6	1520	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
igor_v	21:bc8c1cec3da6	1521	reg_value = (reg_value \|
igor_v	21:bc8c1cec3da6	1522	(0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
igor_v	21:bc8c1cec3da6	1523	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
igor_v	21:bc8c1cec3da6	1524	SCB->AIRCR = reg_value;
igor_v	21:bc8c1cec3da6	1525	}
igor_v	0:8ad47e2b6f00	1526
igor_v	21:bc8c1cec3da6	1527	/**
igor_v	21:bc8c1cec3da6	1528	* @brief Get the Priority Grouping from NVIC Interrupt Controller
igor_v	21:bc8c1cec3da6	1529	*
igor_v	21:bc8c1cec3da6	1530	* @return priority grouping field
igor_v	21:bc8c1cec3da6	1531	*
igor_v	21:bc8c1cec3da6	1532	* Get the priority grouping from NVIC Interrupt Controller.
igor_v	21:bc8c1cec3da6	1533	* priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
igor_v	21:bc8c1cec3da6	1534	*/
igor_v	21:bc8c1cec3da6	1535	static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
igor_v	21:bc8c1cec3da6	1536	{
igor_v	21:bc8c1cec3da6	1537	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
igor_v	21:bc8c1cec3da6	1538	}
igor_v	21:bc8c1cec3da6	1539
igor_v	21:bc8c1cec3da6	1540	/**
igor_v	21:bc8c1cec3da6	1541	* @brief Enable Interrupt in NVIC Interrupt Controller
igor_v	21:bc8c1cec3da6	1542	*
igor_v	21:bc8c1cec3da6	1543	* @param IRQn The positive number of the external interrupt to enable
igor_v	21:bc8c1cec3da6	1544	*
igor_v	21:bc8c1cec3da6	1545	* Enable a device specific interupt in the NVIC interrupt controller.
igor_v	21:bc8c1cec3da6	1546	* The interrupt number cannot be a negative value.
igor_v	21:bc8c1cec3da6	1547	*/
igor_v	21:bc8c1cec3da6	1548	static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
igor_v	21:bc8c1cec3da6	1549	{
igor_v	21:bc8c1cec3da6	1550	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
igor_v	21:bc8c1cec3da6	1551	}
igor_v	0:8ad47e2b6f00	1552
igor_v	21:bc8c1cec3da6	1553	/**
igor_v	21:bc8c1cec3da6	1554	* @brief Disable the interrupt line for external interrupt specified
igor_v	21:bc8c1cec3da6	1555	*
igor_v	21:bc8c1cec3da6	1556	* @param IRQn The positive number of the external interrupt to disable
igor_v	21:bc8c1cec3da6	1557	*
igor_v	21:bc8c1cec3da6	1558	* Disable a device specific interupt in the NVIC interrupt controller.
igor_v	21:bc8c1cec3da6	1559	* The interrupt number cannot be a negative value.
igor_v	21:bc8c1cec3da6	1560	*/
igor_v	21:bc8c1cec3da6	1561	static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
igor_v	21:bc8c1cec3da6	1562	{
igor_v	21:bc8c1cec3da6	1563	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
igor_v	21:bc8c1cec3da6	1564	}
igor_v	0:8ad47e2b6f00	1565
igor_v	21:bc8c1cec3da6	1566	/**
igor_v	21:bc8c1cec3da6	1567	* @brief Read the interrupt pending bit for a device specific interrupt source
igor_v	21:bc8c1cec3da6	1568	*
igor_v	21:bc8c1cec3da6	1569	* @param IRQn The number of the device specifc interrupt
igor_v	21:bc8c1cec3da6	1570	* @return 1 = interrupt pending, 0 = interrupt not pending
igor_v	21:bc8c1cec3da6	1571	*
igor_v	21:bc8c1cec3da6	1572	* Read the pending register in NVIC and return 1 if its status is pending,
igor_v	21:bc8c1cec3da6	1573	* otherwise it returns 0
igor_v	21:bc8c1cec3da6	1574	*/
igor_v	21:bc8c1cec3da6	1575	static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
igor_v	21:bc8c1cec3da6	1576	{
igor_v	21:bc8c1cec3da6	1577	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
igor_v	21:bc8c1cec3da6	1578	}
igor_v	0:8ad47e2b6f00	1579
igor_v	21:bc8c1cec3da6	1580	/**
igor_v	21:bc8c1cec3da6	1581	* @brief Set the pending bit for an external interrupt
igor_v	21:bc8c1cec3da6	1582	*
igor_v	21:bc8c1cec3da6	1583	* @param IRQn The number of the interrupt for set pending
igor_v	21:bc8c1cec3da6	1584	*
igor_v	21:bc8c1cec3da6	1585	* Set the pending bit for the specified interrupt.
igor_v	21:bc8c1cec3da6	1586	* The interrupt number cannot be a negative value.
igor_v	21:bc8c1cec3da6	1587	*/
igor_v	21:bc8c1cec3da6	1588	static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
igor_v	21:bc8c1cec3da6	1589	{
igor_v	21:bc8c1cec3da6	1590	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
igor_v	21:bc8c1cec3da6	1591	}
igor_v	0:8ad47e2b6f00	1592
igor_v	21:bc8c1cec3da6	1593	/**
igor_v	21:bc8c1cec3da6	1594	* @brief Clear the pending bit for an external interrupt
igor_v	21:bc8c1cec3da6	1595	*
igor_v	21:bc8c1cec3da6	1596	* @param IRQn The number of the interrupt for clear pending
igor_v	21:bc8c1cec3da6	1597	*
igor_v	21:bc8c1cec3da6	1598	* Clear the pending bit for the specified interrupt.
igor_v	21:bc8c1cec3da6	1599	* The interrupt number cannot be a negative value.
igor_v	21:bc8c1cec3da6	1600	*/
igor_v	21:bc8c1cec3da6	1601	static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
igor_v	21:bc8c1cec3da6	1602	{
igor_v	21:bc8c1cec3da6	1603	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
igor_v	21:bc8c1cec3da6	1604	}
igor_v	0:8ad47e2b6f00	1605
igor_v	21:bc8c1cec3da6	1606	/**
igor_v	21:bc8c1cec3da6	1607	* @brief Read the active bit for an external interrupt
igor_v	21:bc8c1cec3da6	1608	*
igor_v	21:bc8c1cec3da6	1609	* @param IRQn The number of the interrupt for read active bit
igor_v	21:bc8c1cec3da6	1610	* @return 1 = interrupt active, 0 = interrupt not active
igor_v	21:bc8c1cec3da6	1611	*
igor_v	21:bc8c1cec3da6	1612	* Read the active register in NVIC and returns 1 if its status is active,
igor_v	21:bc8c1cec3da6	1613	* otherwise it returns 0.
igor_v	21:bc8c1cec3da6	1614	*/
igor_v	21:bc8c1cec3da6	1615	static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
igor_v	21:bc8c1cec3da6	1616	{
igor_v	21:bc8c1cec3da6	1617	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
igor_v	21:bc8c1cec3da6	1618	}
igor_v	0:8ad47e2b6f00	1619
igor_v	21:bc8c1cec3da6	1620	/**
igor_v	21:bc8c1cec3da6	1621	* @brief Set the priority for an interrupt
igor_v	21:bc8c1cec3da6	1622	*
igor_v	21:bc8c1cec3da6	1623	* @param IRQn The number of the interrupt for set priority
igor_v	21:bc8c1cec3da6	1624	* @param priority The priority to set
igor_v	21:bc8c1cec3da6	1625	*
igor_v	21:bc8c1cec3da6	1626	* Set the priority for the specified interrupt. The interrupt
igor_v	21:bc8c1cec3da6	1627	* number can be positive to specify an external (device specific)
igor_v	21:bc8c1cec3da6	1628	* interrupt, or negative to specify an internal (core) interrupt.
igor_v	21:bc8c1cec3da6	1629	*
igor_v	21:bc8c1cec3da6	1630	* Note: The priority cannot be set for every core interrupt.
igor_v	21:bc8c1cec3da6	1631	*/
igor_v	21:bc8c1cec3da6	1632	static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
igor_v	21:bc8c1cec3da6	1633	{
igor_v	21:bc8c1cec3da6	1634	if(IRQn < 0) {
igor_v	21:bc8c1cec3da6	1635	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
igor_v	21:bc8c1cec3da6	1636	} /* set Priority for Cortex-M3 System Interrupts */
igor_v	21:bc8c1cec3da6	1637	else {
igor_v	21:bc8c1cec3da6	1638	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
igor_v	21:bc8c1cec3da6	1639	} /* set Priority for device specific Interrupts */
igor_v	21:bc8c1cec3da6	1640	}
igor_v	0:8ad47e2b6f00	1641
igor_v	21:bc8c1cec3da6	1642	/**
igor_v	21:bc8c1cec3da6	1643	* @brief Read the priority for an interrupt
igor_v	21:bc8c1cec3da6	1644	*
igor_v	21:bc8c1cec3da6	1645	* @param IRQn The number of the interrupt for get priority
igor_v	21:bc8c1cec3da6	1646	* @return The priority for the interrupt
igor_v	21:bc8c1cec3da6	1647	*
igor_v	21:bc8c1cec3da6	1648	* Read the priority for the specified interrupt. The interrupt
igor_v	21:bc8c1cec3da6	1649	* number can be positive to specify an external (device specific)
igor_v	21:bc8c1cec3da6	1650	* interrupt, or negative to specify an internal (core) interrupt.
igor_v	21:bc8c1cec3da6	1651	*
igor_v	21:bc8c1cec3da6	1652	* The returned priority value is automatically aligned to the implemented
igor_v	21:bc8c1cec3da6	1653	* priority bits of the microcontroller.
igor_v	21:bc8c1cec3da6	1654	*
igor_v	21:bc8c1cec3da6	1655	* Note: The priority cannot be set for every core interrupt.
igor_v	21:bc8c1cec3da6	1656	*/
igor_v	21:bc8c1cec3da6	1657	static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
igor_v	21:bc8c1cec3da6	1658	{
igor_v	0:8ad47e2b6f00	1659
igor_v	21:bc8c1cec3da6	1660	if(IRQn < 0) {
igor_v	21:bc8c1cec3da6	1661	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));
igor_v	21:bc8c1cec3da6	1662	} /* get priority for Cortex-M3 system interrupts */
igor_v	21:bc8c1cec3da6	1663	else {
igor_v	21:bc8c1cec3da6	1664	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS)));
igor_v	21:bc8c1cec3da6	1665	} /* get priority for device specific interrupts */
igor_v	21:bc8c1cec3da6	1666	}
igor_v	0:8ad47e2b6f00	1667
igor_v	0:8ad47e2b6f00	1668
igor_v	21:bc8c1cec3da6	1669	/**
igor_v	21:bc8c1cec3da6	1670	* @brief Encode the priority for an interrupt
igor_v	21:bc8c1cec3da6	1671	*
igor_v	21:bc8c1cec3da6	1672	* @param PriorityGroup The used priority group
igor_v	21:bc8c1cec3da6	1673	* @param PreemptPriority The preemptive priority value (starting from 0)
igor_v	21:bc8c1cec3da6	1674	* @param SubPriority The sub priority value (starting from 0)
igor_v	21:bc8c1cec3da6	1675	* @return The encoded priority for the interrupt
igor_v	21:bc8c1cec3da6	1676	*
igor_v	21:bc8c1cec3da6	1677	* Encode the priority for an interrupt with the given priority group,
igor_v	21:bc8c1cec3da6	1678	* preemptive priority value and sub priority value.
igor_v	21:bc8c1cec3da6	1679	* In case of a conflict between priority grouping and available
igor_v	21:bc8c1cec3da6	1680	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
igor_v	21:bc8c1cec3da6	1681	*
igor_v	21:bc8c1cec3da6	1682	* The returned priority value can be used for NVIC_SetPriority(...) function
igor_v	21:bc8c1cec3da6	1683	*/
igor_v	21:bc8c1cec3da6	1684	static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
igor_v	21:bc8c1cec3da6	1685	{
igor_v	21:bc8c1cec3da6	1686	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	21:bc8c1cec3da6	1687	uint32_t PreemptPriorityBits;
igor_v	21:bc8c1cec3da6	1688	uint32_t SubPriorityBits;
igor_v	0:8ad47e2b6f00	1689
igor_v	21:bc8c1cec3da6	1690	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
igor_v	21:bc8c1cec3da6	1691	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
igor_v	21:bc8c1cec3da6	1692
igor_v	21:bc8c1cec3da6	1693	return (
igor_v	21:bc8c1cec3da6	1694	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
igor_v	21:bc8c1cec3da6	1695	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
igor_v	21:bc8c1cec3da6	1696	);
igor_v	21:bc8c1cec3da6	1697	}
igor_v	0:8ad47e2b6f00	1698
igor_v	0:8ad47e2b6f00	1699
igor_v	21:bc8c1cec3da6	1700	/**
igor_v	21:bc8c1cec3da6	1701	* @brief Decode the priority of an interrupt
igor_v	21:bc8c1cec3da6	1702	*
igor_v	21:bc8c1cec3da6	1703	* @param Priority The priority for the interrupt
igor_v	21:bc8c1cec3da6	1704	* @param PriorityGroup The used priority group
igor_v	21:bc8c1cec3da6	1705	* @param pPreemptPriority The preemptive priority value (starting from 0)
igor_v	21:bc8c1cec3da6	1706	* @param pSubPriority The sub priority value (starting from 0)
igor_v	21:bc8c1cec3da6	1707	*
igor_v	21:bc8c1cec3da6	1708	* Decode an interrupt priority value with the given priority group to
igor_v	21:bc8c1cec3da6	1709	* preemptive priority value and sub priority value.
igor_v	21:bc8c1cec3da6	1710	* In case of a conflict between priority grouping and available
igor_v	21:bc8c1cec3da6	1711	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
igor_v	21:bc8c1cec3da6	1712	*
igor_v	21:bc8c1cec3da6	1713	* The priority value can be retrieved with NVIC_GetPriority(...) function
igor_v	21:bc8c1cec3da6	1714	*/
igor_v	21:bc8c1cec3da6	1715	static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
igor_v	21:bc8c1cec3da6	1716	{
igor_v	21:bc8c1cec3da6	1717	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	21:bc8c1cec3da6	1718	uint32_t PreemptPriorityBits;
igor_v	21:bc8c1cec3da6	1719	uint32_t SubPriorityBits;
igor_v	0:8ad47e2b6f00	1720
igor_v	21:bc8c1cec3da6	1721	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
igor_v	21:bc8c1cec3da6	1722	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
igor_v	21:bc8c1cec3da6	1723
igor_v	21:bc8c1cec3da6	1724	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
igor_v	21:bc8c1cec3da6	1725	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
igor_v	21:bc8c1cec3da6	1726	}
igor_v	0:8ad47e2b6f00	1727
igor_v	0:8ad47e2b6f00	1728
igor_v	0:8ad47e2b6f00	1729
igor_v	21:bc8c1cec3da6	1730	/* ################################## SysTick function ############################################ */
igor_v	0:8ad47e2b6f00	1731
igor_v	11:af609f6dee46	1732	#if (!defined (__Vendor_SysTickConfig)) \|\| (__Vendor_SysTickConfig == 0)
igor_v	0:8ad47e2b6f00	1733
igor_v	21:bc8c1cec3da6	1734	/**
igor_v	21:bc8c1cec3da6	1735	* @brief Initialize and start the SysTick counter and its interrupt.
igor_v	21:bc8c1cec3da6	1736	*
igor_v	21:bc8c1cec3da6	1737	* @param ticks number of ticks between two interrupts
igor_v	21:bc8c1cec3da6	1738	* @return 1 = failed, 0 = successful
igor_v	21:bc8c1cec3da6	1739	*
igor_v	21:bc8c1cec3da6	1740	* Initialise the system tick timer and its interrupt and start the
igor_v	21:bc8c1cec3da6	1741	* system tick timer / counter in free running mode to generate
igor_v	21:bc8c1cec3da6	1742	* periodical interrupts.
igor_v	21:bc8c1cec3da6	1743	*/
igor_v	21:bc8c1cec3da6	1744	static __INLINE uint32_t SysTick_Config(uint32_t ticks)
igor_v	21:bc8c1cec3da6	1745	{
igor_v	21:bc8c1cec3da6	1746	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
igor_v	21:bc8c1cec3da6	1747
igor_v	21:bc8c1cec3da6	1748	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
igor_v	21:bc8c1cec3da6	1749	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
igor_v	21:bc8c1cec3da6	1750	SysTick->VAL = 0; /* Load the SysTick Counter Value */
igor_v	21:bc8c1cec3da6	1751	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
igor_v	21:bc8c1cec3da6	1752	SysTick_CTRL_TICKINT_Msk \|
igor_v	21:bc8c1cec3da6	1753	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
igor_v	21:bc8c1cec3da6	1754	return (0); /* Function successful */
igor_v	21:bc8c1cec3da6	1755	}
igor_v	0:8ad47e2b6f00	1756
igor_v	0:8ad47e2b6f00	1757	#endif
igor_v	0:8ad47e2b6f00	1758
igor_v	11:af609f6dee46	1759
igor_v	11:af609f6dee46	1760
igor_v	11:af609f6dee46	1761
igor_v	21:bc8c1cec3da6	1762	/* ################################## Reset function ############################################ */
igor_v	11:af609f6dee46	1763
igor_v	21:bc8c1cec3da6	1764	/**
igor_v	21:bc8c1cec3da6	1765	* @brief Initiate a system reset request.
igor_v	21:bc8c1cec3da6	1766	*
igor_v	21:bc8c1cec3da6	1767	* Initiate a system reset request to reset the MCU
igor_v	21:bc8c1cec3da6	1768	*/
igor_v	21:bc8c1cec3da6	1769	static __INLINE void NVIC_SystemReset(void)
igor_v	21:bc8c1cec3da6	1770	{
igor_v	21:bc8c1cec3da6	1771	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
igor_v	21:bc8c1cec3da6	1772	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
igor_v	21:bc8c1cec3da6	1773	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
igor_v	21:bc8c1cec3da6	1774	__DSB(); /* Ensure completion of memory access */
igor_v	21:bc8c1cec3da6	1775	while(1); /* wait until reset */
igor_v	21:bc8c1cec3da6	1776	}
igor_v	11:af609f6dee46	1777
igor_v	21:bc8c1cec3da6	1778	/@}/ /* end of group CMSIS_CM3_Core_FunctionInterface */
igor_v	0:8ad47e2b6f00	1779
igor_v	0:8ad47e2b6f00	1780
igor_v	0:8ad47e2b6f00	1781
igor_v	21:bc8c1cec3da6	1782	/* ##################################### Debug In/Output function ########################################### */
igor_v	0:8ad47e2b6f00	1783
igor_v	21:bc8c1cec3da6	1784	/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
igor_v	21:bc8c1cec3da6	1785	Core Debug Interface containing:
igor_v	21:bc8c1cec3da6	1786	- Core Debug Receive / Transmit Functions
igor_v	21:bc8c1cec3da6	1787	- Core Debug Defines
igor_v	21:bc8c1cec3da6	1788	- Core Debug Variables
igor_v	21:bc8c1cec3da6	1789	*/
igor_v	21:bc8c1cec3da6	1790	/@{/
igor_v	11:af609f6dee46	1791
igor_v	21:bc8c1cec3da6	1792	extern volatile int ITM_RxBuffer; /!< variable to receive characters /
igor_v	11:af609f6dee46	1793	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< value identifying ITM_RxBuffer is ready for next character /
igor_v	0:8ad47e2b6f00	1794
igor_v	0:8ad47e2b6f00	1795
igor_v	21:bc8c1cec3da6	1796	/**
igor_v	21:bc8c1cec3da6	1797	* @brief Outputs a character via the ITM channel 0
igor_v	21:bc8c1cec3da6	1798	*
igor_v	21:bc8c1cec3da6	1799	* @param ch character to output
igor_v	21:bc8c1cec3da6	1800	* @return character to output
igor_v	21:bc8c1cec3da6	1801	*
igor_v	21:bc8c1cec3da6	1802	* The function outputs a character via the ITM channel 0.
igor_v	21:bc8c1cec3da6	1803	* The function returns when no debugger is connected that has booked the output.
igor_v	21:bc8c1cec3da6	1804	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
igor_v	21:bc8c1cec3da6	1805	*/
igor_v	21:bc8c1cec3da6	1806	static __INLINE uint32_t ITM_SendChar (uint32_t ch)
igor_v	21:bc8c1cec3da6	1807	{
igor_v	21:bc8c1cec3da6	1808	if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
igor_v	21:bc8c1cec3da6	1809	(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
igor_v	21:bc8c1cec3da6	1810	(ITM->TER & (1ul << 0) ) ) { /* ITM Port #0 enabled */
igor_v	21:bc8c1cec3da6	1811	while (ITM->PORT[0].u32 == 0);
igor_v	21:bc8c1cec3da6	1812	ITM->PORT[0].u8 = (uint8_t) ch;
igor_v	21:bc8c1cec3da6	1813	}
igor_v	21:bc8c1cec3da6	1814	return (ch);
igor_v	21:bc8c1cec3da6	1815	}
igor_v	0:8ad47e2b6f00	1816
igor_v	0:8ad47e2b6f00	1817
igor_v	21:bc8c1cec3da6	1818	/**
igor_v	21:bc8c1cec3da6	1819	* @brief Inputs a character via variable ITM_RxBuffer
igor_v	21:bc8c1cec3da6	1820	*
igor_v	21:bc8c1cec3da6	1821	* @return received character, -1 = no character received
igor_v	21:bc8c1cec3da6	1822	*
igor_v	21:bc8c1cec3da6	1823	* The function inputs a character via variable ITM_RxBuffer.
igor_v	21:bc8c1cec3da6	1824	* The function returns when no debugger is connected that has booked the output.
igor_v	21:bc8c1cec3da6	1825	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
igor_v	21:bc8c1cec3da6	1826	*/
igor_v	21:bc8c1cec3da6	1827	static __INLINE int ITM_ReceiveChar (void)
igor_v	21:bc8c1cec3da6	1828	{
igor_v	21:bc8c1cec3da6	1829	int ch = -1; /* no character available */
igor_v	0:8ad47e2b6f00	1830
igor_v	21:bc8c1cec3da6	1831	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
igor_v	21:bc8c1cec3da6	1832	ch = ITM_RxBuffer;
igor_v	21:bc8c1cec3da6	1833	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
igor_v	21:bc8c1cec3da6	1834	}
igor_v	21:bc8c1cec3da6	1835
igor_v	21:bc8c1cec3da6	1836	return (ch);
igor_v	21:bc8c1cec3da6	1837	}
igor_v	0:8ad47e2b6f00	1838
igor_v	0:8ad47e2b6f00	1839
igor_v	21:bc8c1cec3da6	1840	/**
igor_v	21:bc8c1cec3da6	1841	* @brief Check if a character via variable ITM_RxBuffer is available
igor_v	21:bc8c1cec3da6	1842	*
igor_v	21:bc8c1cec3da6	1843	* @return 1 = character available, 0 = no character available
igor_v	21:bc8c1cec3da6	1844	*
igor_v	21:bc8c1cec3da6	1845	* The function checks variable ITM_RxBuffer whether a character is available or not.
igor_v	21:bc8c1cec3da6	1846	* The function returns '1' if a character is available and '0' if no character is available.
igor_v	21:bc8c1cec3da6	1847	*/
igor_v	21:bc8c1cec3da6	1848	static __INLINE int ITM_CheckChar (void)
igor_v	21:bc8c1cec3da6	1849	{
igor_v	0:8ad47e2b6f00	1850
igor_v	21:bc8c1cec3da6	1851	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
igor_v	21:bc8c1cec3da6	1852	return (0); /* no character available */
igor_v	21:bc8c1cec3da6	1853	} else {
igor_v	21:bc8c1cec3da6	1854	return (1); /* character available */
igor_v	21:bc8c1cec3da6	1855	}
igor_v	21:bc8c1cec3da6	1856	}
igor_v	0:8ad47e2b6f00	1857
igor_v	21:bc8c1cec3da6	1858	/@}/ /* end of group CMSIS_CM3_core_DebugInterface */
igor_v	0:8ad47e2b6f00	1859
igor_v	0:8ad47e2b6f00	1860
igor_v	0:8ad47e2b6f00	1861	#ifdef __cplusplus
igor_v	0:8ad47e2b6f00	1862	}
igor_v	0:8ad47e2b6f00	1863	#endif
igor_v	0:8ad47e2b6f00	1864
igor_v	11:af609f6dee46	1865	/@}/ /* end of group CMSIS_CM3_core_definitions */
igor_v	11:af609f6dee46	1866
igor_v	11:af609f6dee46	1867	#endif /* __CM3_CORE_H__ */
igor_v	11:af609f6dee46	1868
igor_v	0:8ad47e2b6f00	1869	/lint -restore /
igor_v	0:8ad47e2b6f00	1870

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	20 Oct 2016
Imports:	4
Forks:	1
Commits:	220
Dependents:	0
Dependencies:	1
Followers:	1

core_cm3.h@217:15cd8752bb6c, 2017-09-04 (annotated)

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