Martin Kojtal / USBHost

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Dependencies:   FATFileSystem mbed-rtos

Fork of USBHost by mbed official

targets/TARGET_NUVOTON/TARGET_NUC472/USBHALHost_NUC472.cpp@39:d96aa62afc5b, 2017-07-27 (annotated)

Committer:
Kojto
Date:
Thu Jul 27 12:24:30 2017 +0100
Revision:
39:d96aa62afc5b
Update USBHost - add targets directory



This corresponds to mbed-os/master commit 9207365

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 39:d96aa62afc5b 1 /* mbed Microcontroller Library
Kojto 39:d96aa62afc5b 2 * Copyright (c) 2015-2016 Nuvoton
Kojto 39:d96aa62afc5b 3 *
Kojto 39:d96aa62afc5b 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 39:d96aa62afc5b 5 * you may not use this file except in compliance with the License.
Kojto 39:d96aa62afc5b 6 * You may obtain a copy of the License at
Kojto 39:d96aa62afc5b 7 *
Kojto 39:d96aa62afc5b 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 39:d96aa62afc5b 9 *
Kojto 39:d96aa62afc5b 10 * Unless required by applicable law or agreed to in writing, software
Kojto 39:d96aa62afc5b 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 39:d96aa62afc5b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 39:d96aa62afc5b 13 * See the License for the specific language governing permissions and
Kojto 39:d96aa62afc5b 14 * limitations under the License.
Kojto 39:d96aa62afc5b 15 */
Kojto 39:d96aa62afc5b 16
Kojto 39:d96aa62afc5b 17 #if defined(TARGET_NUC472)
Kojto 39:d96aa62afc5b 18
Kojto 39:d96aa62afc5b 19 #include "mbed.h"
Kojto 39:d96aa62afc5b 20 #include "USBHALHost.h"
Kojto 39:d96aa62afc5b 21 #include "dbg.h"
Kojto 39:d96aa62afc5b 22 #include "pinmap.h"
Kojto 39:d96aa62afc5b 23
Kojto 39:d96aa62afc5b 24 #define HCCA_SIZE sizeof(HCCA)
Kojto 39:d96aa62afc5b 25 #define ED_SIZE sizeof(HCED)
Kojto 39:d96aa62afc5b 26 #define TD_SIZE sizeof(HCTD)
Kojto 39:d96aa62afc5b 27
Kojto 39:d96aa62afc5b 28 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
Kojto 39:d96aa62afc5b 29
Kojto 39:d96aa62afc5b 30 static volatile MBED_ALIGN(256) uint8_t usb_buf[TOTAL_SIZE]; // 256 bytes aligned!
Kojto 39:d96aa62afc5b 31
Kojto 39:d96aa62afc5b 32 USBHALHost * USBHALHost::instHost;
Kojto 39:d96aa62afc5b 33
Kojto 39:d96aa62afc5b 34 USBHALHost::USBHALHost()
Kojto 39:d96aa62afc5b 35 {
Kojto 39:d96aa62afc5b 36 instHost = this;
Kojto 39:d96aa62afc5b 37 memInit();
Kojto 39:d96aa62afc5b 38 memset((void*)usb_hcca, 0, HCCA_SIZE);
Kojto 39:d96aa62afc5b 39 for (int i = 0; i < MAX_ENDPOINT; i++) {
Kojto 39:d96aa62afc5b 40 edBufAlloc[i] = false;
Kojto 39:d96aa62afc5b 41 }
Kojto 39:d96aa62afc5b 42 for (int i = 0; i < MAX_TD; i++) {
Kojto 39:d96aa62afc5b 43 tdBufAlloc[i] = false;
Kojto 39:d96aa62afc5b 44 }
Kojto 39:d96aa62afc5b 45 }
Kojto 39:d96aa62afc5b 46
Kojto 39:d96aa62afc5b 47 void USBHALHost::init()
Kojto 39:d96aa62afc5b 48 {
Kojto 39:d96aa62afc5b 49 // Unlock protected registers
Kojto 39:d96aa62afc5b 50 SYS_UnlockReg();
Kojto 39:d96aa62afc5b 51
Kojto 39:d96aa62afc5b 52 // NOTE: Configure as OTG device first; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
Kojto 39:d96aa62afc5b 53 SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk | SYS_USBPHY_USBROLE_ON_THE_GO;
Kojto 39:d96aa62afc5b 54
Kojto 39:d96aa62afc5b 55 // NOTE: Enable OTG here; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
Kojto 39:d96aa62afc5b 56 CLK_EnableModuleClock(OTG_MODULE);
Kojto 39:d96aa62afc5b 57 OTG->PHYCTL = (OTG->PHYCTL | OTG_PHYCTL_OTGPHYEN_Msk) & ~OTG_PHYCTL_IDDETEN_Msk;
Kojto 39:d96aa62afc5b 58 //OTG->CTL |= OTG_CTL_OTGEN_Msk | OTG_CTL_BUSREQ_Msk;
Kojto 39:d96aa62afc5b 59
Kojto 39:d96aa62afc5b 60 // PB.0: USB0 external VBUS regulator status
Kojto 39:d96aa62afc5b 61 // USB_OC
Kojto 39:d96aa62afc5b 62 // PB.1: USB0 external VBUS regulator enable
Kojto 39:d96aa62afc5b 63 // NCT3520U low active (USB_PWR_EN)
Kojto 39:d96aa62afc5b 64 pin_function(PB_0, SYS_GPB_MFPL_PB0MFP_USB0_OTG5V_ST);
Kojto 39:d96aa62afc5b 65 pin_function(PB_1, SYS_GPB_MFPL_PB1MFP_USB0_OTG5V_EN);
Kojto 39:d96aa62afc5b 66
Kojto 39:d96aa62afc5b 67 // PB.2: USB1 differential signal D-
Kojto 39:d96aa62afc5b 68 // PB.3: USB1 differential signal D+
Kojto 39:d96aa62afc5b 69 //pin_function(PB_2, SYS_GPB_MFPL_PB2MFP_USB1_D_N);
Kojto 39:d96aa62afc5b 70 //pin_function(PB_3, SYS_GPB_MFPL_PB3MFP_USB1_D_P);
Kojto 39:d96aa62afc5b 71
Kojto 39:d96aa62afc5b 72 // Set PB.4 output high to enable USB power
Kojto 39:d96aa62afc5b 73 //gpio_t gpio;
Kojto 39:d96aa62afc5b 74 //gpio_init_out_ex(&gpio, PB_4, 1);
Kojto 39:d96aa62afc5b 75
Kojto 39:d96aa62afc5b 76 // NOTE:
Kojto 39:d96aa62afc5b 77 // 1. Set USBH clock source to PLL2; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
Kojto 39:d96aa62afc5b 78 // 2. Don't set CLK_PLL2CTL_PLL2CKEN_Msk. USBH will work abnormally with it enabled.
Kojto 39:d96aa62afc5b 79 CLK->CLKSEL0 &= ~CLK_CLKSEL0_USBHSEL_Msk;
Kojto 39:d96aa62afc5b 80 // Enable PLL2, 480 MHz / 2 / (1+4) => 48 MHz output
Kojto 39:d96aa62afc5b 81 CLK->PLL2CTL = /*CLK_PLL2CTL_PLL2CKEN_Msk | */ (4 << CLK_PLL2CTL_PLL2DIV_Pos);
Kojto 39:d96aa62afc5b 82 // Wait PLL2 stable ...
Kojto 39:d96aa62afc5b 83 while (!(CLK->STATUS & CLK_STATUS_PLL2STB_Msk));
Kojto 39:d96aa62afc5b 84
Kojto 39:d96aa62afc5b 85 // Select USB Host clock source from PLL2, clock divied by 1
Kojto 39:d96aa62afc5b 86 CLK_SetModuleClock(USBH_MODULE, CLK_CLKSEL0_USBHSEL_PLL2, CLK_CLKDIV0_USB(1));
Kojto 39:d96aa62afc5b 87
Kojto 39:d96aa62afc5b 88 // Enable USB Host clock
Kojto 39:d96aa62afc5b 89 CLK_EnableModuleClock(USBH_MODULE);
Kojto 39:d96aa62afc5b 90
Kojto 39:d96aa62afc5b 91 // Lock protected registers
Kojto 39:d96aa62afc5b 92 SYS_LockReg();
Kojto 39:d96aa62afc5b 93
Kojto 39:d96aa62afc5b 94 // Overcurrent flag is high active
Kojto 39:d96aa62afc5b 95 USBH->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk;
Kojto 39:d96aa62afc5b 96
Kojto 39:d96aa62afc5b 97 // Disable HC interrupts
Kojto 39:d96aa62afc5b 98 USBH->HcInterruptDisable = OR_INTR_ENABLE_MIE;
Kojto 39:d96aa62afc5b 99
Kojto 39:d96aa62afc5b 100 // Needed by some controllers
Kojto 39:d96aa62afc5b 101 USBH->HcControl = 0;
Kojto 39:d96aa62afc5b 102
Kojto 39:d96aa62afc5b 103 // Software reset
Kojto 39:d96aa62afc5b 104 USBH->HcCommandStatus = OR_CMD_STATUS_HCR;
Kojto 39:d96aa62afc5b 105 while (USBH->HcCommandStatus & OR_CMD_STATUS_HCR);
Kojto 39:d96aa62afc5b 106
Kojto 39:d96aa62afc5b 107 // Put HC in reset state
Kojto 39:d96aa62afc5b 108 USBH->HcControl = (USBH->HcControl & ~OR_CONTROL_HCFS) | OR_CONTROL_HC_RSET;
Kojto 39:d96aa62afc5b 109 // HCD must wait 10ms for HC reset complete
Kojto 39:d96aa62afc5b 110 wait_ms(100);
Kojto 39:d96aa62afc5b 111
Kojto 39:d96aa62afc5b 112 USBH->HcControlHeadED = 0; // Initialize Control ED list head to 0
Kojto 39:d96aa62afc5b 113 USBH->HcBulkHeadED = 0; // Initialize Bulk ED list head to 0
Kojto 39:d96aa62afc5b 114 USBH->HcHCCA = (uint32_t) usb_hcca;
Kojto 39:d96aa62afc5b 115
Kojto 39:d96aa62afc5b 116 USBH->HcFmInterval = DEFAULT_FMINTERVAL; // Frame interval = 12000 - 1
Kojto 39:d96aa62afc5b 117 // MPS = 10,104
Kojto 39:d96aa62afc5b 118 USBH->HcPeriodicStart = FI * 90 / 100; // 90% of frame interval
Kojto 39:d96aa62afc5b 119 USBH->HcLSThreshold = 0x628; // Low speed threshold
Kojto 39:d96aa62afc5b 120
Kojto 39:d96aa62afc5b 121 // Put HC in operational state
Kojto 39:d96aa62afc5b 122 USBH->HcControl = (USBH->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
Kojto 39:d96aa62afc5b 123
Kojto 39:d96aa62afc5b 124 // FIXME: Ports are power switched. All ports are powered at the same time. Doesn't match BSP sample.
Kojto 39:d96aa62afc5b 125 USBH->HcRhDescriptorA = USBH->HcRhDescriptorA & ~USBH_HcRhDescriptorA_NPS_Msk & ~USBH_HcRhDescriptorA_PSM_Msk;
Kojto 39:d96aa62afc5b 126 // Issue SetGlobalPower command
Kojto 39:d96aa62afc5b 127 USBH->HcRhStatus = USBH_HcRhStatus_LPSC_Msk;
Kojto 39:d96aa62afc5b 128 // Power On To Power Good Time, in 2 ms units
Kojto 39:d96aa62afc5b 129 wait_ms(((USBH->HcRhDescriptorA & USBH_HcRhDescriptorA_POTPGT_Msk) >> USBH_HcRhDescriptorA_POTPGT_Pos) * 2);
Kojto 39:d96aa62afc5b 130
Kojto 39:d96aa62afc5b 131 // Clear Interrrupt Status
Kojto 39:d96aa62afc5b 132 USBH->HcInterruptStatus |= USBH->HcInterruptStatus;
Kojto 39:d96aa62afc5b 133 // Enable interrupts we care about
Kojto 39:d96aa62afc5b 134 USBH->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
Kojto 39:d96aa62afc5b 135
Kojto 39:d96aa62afc5b 136
Kojto 39:d96aa62afc5b 137 // Unlock protected registers
Kojto 39:d96aa62afc5b 138 SYS_UnlockReg();
Kojto 39:d96aa62afc5b 139
Kojto 39:d96aa62afc5b 140 // NOTE: Configure as USB host after USBH init above; otherwise system will crash.
Kojto 39:d96aa62afc5b 141 SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_USBROLE_STD_USBH;
Kojto 39:d96aa62afc5b 142
Kojto 39:d96aa62afc5b 143 // Lock protected registers
Kojto 39:d96aa62afc5b 144 SYS_LockReg();
Kojto 39:d96aa62afc5b 145
Kojto 39:d96aa62afc5b 146 NVIC_SetVector(USBH_IRQn, (uint32_t)(_usbisr));
Kojto 39:d96aa62afc5b 147 NVIC_EnableIRQ(USBH_IRQn);
Kojto 39:d96aa62afc5b 148
Kojto 39:d96aa62afc5b 149 // Check for any connected devices
Kojto 39:d96aa62afc5b 150 if (USBH->HcRhPortStatus[0] & OR_RH_PORT_CCS) {
Kojto 39:d96aa62afc5b 151 // Device connected
Kojto 39:d96aa62afc5b 152 wait_ms(150);
Kojto 39:d96aa62afc5b 153 deviceConnected(0, 1, USBH->HcRhPortStatus[0] & OR_RH_PORT_LSDA);
Kojto 39:d96aa62afc5b 154 }
Kojto 39:d96aa62afc5b 155 }
Kojto 39:d96aa62afc5b 156
Kojto 39:d96aa62afc5b 157 uint32_t USBHALHost::controlHeadED()
Kojto 39:d96aa62afc5b 158 {
Kojto 39:d96aa62afc5b 159 return USBH->HcControlHeadED;
Kojto 39:d96aa62afc5b 160 }
Kojto 39:d96aa62afc5b 161
Kojto 39:d96aa62afc5b 162 uint32_t USBHALHost::bulkHeadED()
Kojto 39:d96aa62afc5b 163 {
Kojto 39:d96aa62afc5b 164 return USBH->HcBulkHeadED;
Kojto 39:d96aa62afc5b 165 }
Kojto 39:d96aa62afc5b 166
Kojto 39:d96aa62afc5b 167 uint32_t USBHALHost::interruptHeadED()
Kojto 39:d96aa62afc5b 168 {
Kojto 39:d96aa62afc5b 169 // FIXME: Only support one INT ED?
Kojto 39:d96aa62afc5b 170 return usb_hcca->IntTable[0];
Kojto 39:d96aa62afc5b 171 }
Kojto 39:d96aa62afc5b 172
Kojto 39:d96aa62afc5b 173 void USBHALHost::updateBulkHeadED(uint32_t addr)
Kojto 39:d96aa62afc5b 174 {
Kojto 39:d96aa62afc5b 175 USBH->HcBulkHeadED = addr;
Kojto 39:d96aa62afc5b 176 }
Kojto 39:d96aa62afc5b 177
Kojto 39:d96aa62afc5b 178
Kojto 39:d96aa62afc5b 179 void USBHALHost::updateControlHeadED(uint32_t addr)
Kojto 39:d96aa62afc5b 180 {
Kojto 39:d96aa62afc5b 181 USBH->HcControlHeadED = addr;
Kojto 39:d96aa62afc5b 182 }
Kojto 39:d96aa62afc5b 183
Kojto 39:d96aa62afc5b 184 void USBHALHost::updateInterruptHeadED(uint32_t addr)
Kojto 39:d96aa62afc5b 185 {
Kojto 39:d96aa62afc5b 186 // FIXME: Only support one INT ED?
Kojto 39:d96aa62afc5b 187 usb_hcca->IntTable[0] = addr;
Kojto 39:d96aa62afc5b 188 }
Kojto 39:d96aa62afc5b 189
Kojto 39:d96aa62afc5b 190
Kojto 39:d96aa62afc5b 191 void USBHALHost::enableList(ENDPOINT_TYPE type)
Kojto 39:d96aa62afc5b 192 {
Kojto 39:d96aa62afc5b 193 switch(type) {
Kojto 39:d96aa62afc5b 194 case CONTROL_ENDPOINT:
Kojto 39:d96aa62afc5b 195 USBH->HcCommandStatus = OR_CMD_STATUS_CLF;
Kojto 39:d96aa62afc5b 196 USBH->HcControl |= OR_CONTROL_CLE;
Kojto 39:d96aa62afc5b 197 break;
Kojto 39:d96aa62afc5b 198 case ISOCHRONOUS_ENDPOINT:
Kojto 39:d96aa62afc5b 199 // FIXME
Kojto 39:d96aa62afc5b 200 break;
Kojto 39:d96aa62afc5b 201 case BULK_ENDPOINT:
Kojto 39:d96aa62afc5b 202 USBH->HcCommandStatus = OR_CMD_STATUS_BLF;
Kojto 39:d96aa62afc5b 203 USBH->HcControl |= OR_CONTROL_BLE;
Kojto 39:d96aa62afc5b 204 break;
Kojto 39:d96aa62afc5b 205 case INTERRUPT_ENDPOINT:
Kojto 39:d96aa62afc5b 206 USBH->HcControl |= OR_CONTROL_PLE;
Kojto 39:d96aa62afc5b 207 break;
Kojto 39:d96aa62afc5b 208 }
Kojto 39:d96aa62afc5b 209 }
Kojto 39:d96aa62afc5b 210
Kojto 39:d96aa62afc5b 211
Kojto 39:d96aa62afc5b 212 bool USBHALHost::disableList(ENDPOINT_TYPE type)
Kojto 39:d96aa62afc5b 213 {
Kojto 39:d96aa62afc5b 214 switch(type) {
Kojto 39:d96aa62afc5b 215 case CONTROL_ENDPOINT:
Kojto 39:d96aa62afc5b 216 if(USBH->HcControl & OR_CONTROL_CLE) {
Kojto 39:d96aa62afc5b 217 USBH->HcControl &= ~OR_CONTROL_CLE;
Kojto 39:d96aa62afc5b 218 return true;
Kojto 39:d96aa62afc5b 219 }
Kojto 39:d96aa62afc5b 220 return false;
Kojto 39:d96aa62afc5b 221 case ISOCHRONOUS_ENDPOINT:
Kojto 39:d96aa62afc5b 222 // FIXME
Kojto 39:d96aa62afc5b 223 return false;
Kojto 39:d96aa62afc5b 224 case BULK_ENDPOINT:
Kojto 39:d96aa62afc5b 225 if(USBH->HcControl & OR_CONTROL_BLE){
Kojto 39:d96aa62afc5b 226 USBH->HcControl &= ~OR_CONTROL_BLE;
Kojto 39:d96aa62afc5b 227 return true;
Kojto 39:d96aa62afc5b 228 }
Kojto 39:d96aa62afc5b 229 return false;
Kojto 39:d96aa62afc5b 230 case INTERRUPT_ENDPOINT:
Kojto 39:d96aa62afc5b 231 if(USBH->HcControl & OR_CONTROL_PLE) {
Kojto 39:d96aa62afc5b 232 USBH->HcControl &= ~OR_CONTROL_PLE;
Kojto 39:d96aa62afc5b 233 return true;
Kojto 39:d96aa62afc5b 234 }
Kojto 39:d96aa62afc5b 235 return false;
Kojto 39:d96aa62afc5b 236 }
Kojto 39:d96aa62afc5b 237 return false;
Kojto 39:d96aa62afc5b 238 }
Kojto 39:d96aa62afc5b 239
Kojto 39:d96aa62afc5b 240
Kojto 39:d96aa62afc5b 241 void USBHALHost::memInit()
Kojto 39:d96aa62afc5b 242 {
Kojto 39:d96aa62afc5b 243 usb_hcca = (volatile HCCA *)usb_buf;
Kojto 39:d96aa62afc5b 244 usb_edBuf = usb_buf + HCCA_SIZE;
Kojto 39:d96aa62afc5b 245 usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
Kojto 39:d96aa62afc5b 246 }
Kojto 39:d96aa62afc5b 247
Kojto 39:d96aa62afc5b 248 volatile uint8_t * USBHALHost::getED()
Kojto 39:d96aa62afc5b 249 {
Kojto 39:d96aa62afc5b 250 for (int i = 0; i < MAX_ENDPOINT; i++) {
Kojto 39:d96aa62afc5b 251 if ( !edBufAlloc[i] ) {
Kojto 39:d96aa62afc5b 252 edBufAlloc[i] = true;
Kojto 39:d96aa62afc5b 253 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
Kojto 39:d96aa62afc5b 254 }
Kojto 39:d96aa62afc5b 255 }
Kojto 39:d96aa62afc5b 256 perror("Could not allocate ED\r\n");
Kojto 39:d96aa62afc5b 257 return NULL; //Could not alloc ED
Kojto 39:d96aa62afc5b 258 }
Kojto 39:d96aa62afc5b 259
Kojto 39:d96aa62afc5b 260 volatile uint8_t * USBHALHost::getTD()
Kojto 39:d96aa62afc5b 261 {
Kojto 39:d96aa62afc5b 262 int i;
Kojto 39:d96aa62afc5b 263 for (i = 0; i < MAX_TD; i++) {
Kojto 39:d96aa62afc5b 264 if ( !tdBufAlloc[i] ) {
Kojto 39:d96aa62afc5b 265 tdBufAlloc[i] = true;
Kojto 39:d96aa62afc5b 266 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
Kojto 39:d96aa62afc5b 267 }
Kojto 39:d96aa62afc5b 268 }
Kojto 39:d96aa62afc5b 269 perror("Could not allocate TD\r\n");
Kojto 39:d96aa62afc5b 270 return NULL; //Could not alloc TD
Kojto 39:d96aa62afc5b 271 }
Kojto 39:d96aa62afc5b 272
Kojto 39:d96aa62afc5b 273
Kojto 39:d96aa62afc5b 274 void USBHALHost::freeED(volatile uint8_t * ed)
Kojto 39:d96aa62afc5b 275 {
Kojto 39:d96aa62afc5b 276 int i;
Kojto 39:d96aa62afc5b 277 i = (ed - usb_edBuf) / ED_SIZE;
Kojto 39:d96aa62afc5b 278 edBufAlloc[i] = false;
Kojto 39:d96aa62afc5b 279 }
Kojto 39:d96aa62afc5b 280
Kojto 39:d96aa62afc5b 281 void USBHALHost::freeTD(volatile uint8_t * td)
Kojto 39:d96aa62afc5b 282 {
Kojto 39:d96aa62afc5b 283 int i;
Kojto 39:d96aa62afc5b 284 i = (td - usb_tdBuf) / TD_SIZE;
Kojto 39:d96aa62afc5b 285 tdBufAlloc[i] = false;
Kojto 39:d96aa62afc5b 286 }
Kojto 39:d96aa62afc5b 287
Kojto 39:d96aa62afc5b 288
Kojto 39:d96aa62afc5b 289 void USBHALHost::resetRootHub()
Kojto 39:d96aa62afc5b 290 {
Kojto 39:d96aa62afc5b 291 // Reset port1
Kojto 39:d96aa62afc5b 292 USBH->HcRhPortStatus[0] = OR_RH_PORT_PRS;
Kojto 39:d96aa62afc5b 293 while (USBH->HcRhPortStatus[0] & OR_RH_PORT_PRS);
Kojto 39:d96aa62afc5b 294 USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
Kojto 39:d96aa62afc5b 295 }
Kojto 39:d96aa62afc5b 296
Kojto 39:d96aa62afc5b 297
Kojto 39:d96aa62afc5b 298 void USBHALHost::_usbisr(void)
Kojto 39:d96aa62afc5b 299 {
Kojto 39:d96aa62afc5b 300 if (instHost) {
Kojto 39:d96aa62afc5b 301 instHost->UsbIrqhandler();
Kojto 39:d96aa62afc5b 302 }
Kojto 39:d96aa62afc5b 303 }
Kojto 39:d96aa62afc5b 304
Kojto 39:d96aa62afc5b 305 void USBHALHost::UsbIrqhandler()
Kojto 39:d96aa62afc5b 306 {
Kojto 39:d96aa62afc5b 307 uint32_t ints = USBH->HcInterruptStatus;
Kojto 39:d96aa62afc5b 308
Kojto 39:d96aa62afc5b 309 // Root hub status change interrupt
Kojto 39:d96aa62afc5b 310 if (ints & OR_INTR_STATUS_RHSC) {
Kojto 39:d96aa62afc5b 311 uint32_t ints_roothub = USBH->HcRhStatus;
Kojto 39:d96aa62afc5b 312 uint32_t ints_port1 = USBH->HcRhPortStatus[0];
Kojto 39:d96aa62afc5b 313
Kojto 39:d96aa62afc5b 314 // Port1: ConnectStatusChange
Kojto 39:d96aa62afc5b 315 if (ints_port1 & OR_RH_PORT_CSC) {
Kojto 39:d96aa62afc5b 316 if (ints_roothub & OR_RH_STATUS_DRWE) {
Kojto 39:d96aa62afc5b 317 // When DRWE is on, Connect Status Change means a remote wakeup event.
Kojto 39:d96aa62afc5b 318 } else {
Kojto 39:d96aa62afc5b 319 if (ints_port1 & OR_RH_PORT_CCS) {
Kojto 39:d96aa62afc5b 320 // Root device connected
Kojto 39:d96aa62afc5b 321
Kojto 39:d96aa62afc5b 322 // wait 150ms to avoid bounce
Kojto 39:d96aa62afc5b 323 wait_ms(150);
Kojto 39:d96aa62afc5b 324
Kojto 39:d96aa62afc5b 325 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
Kojto 39:d96aa62afc5b 326 deviceConnected(0, 1, ints_port1 & OR_RH_PORT_LSDA);
Kojto 39:d96aa62afc5b 327 } else {
Kojto 39:d96aa62afc5b 328 // Root device disconnected
Kojto 39:d96aa62afc5b 329
Kojto 39:d96aa62afc5b 330 if (!(ints & OR_INTR_STATUS_WDH)) {
Kojto 39:d96aa62afc5b 331 usb_hcca->DoneHead = 0;
Kojto 39:d96aa62afc5b 332 }
Kojto 39:d96aa62afc5b 333
Kojto 39:d96aa62afc5b 334 // wait 200ms to avoid bounce
Kojto 39:d96aa62afc5b 335 wait_ms(200);
Kojto 39:d96aa62afc5b 336
Kojto 39:d96aa62afc5b 337 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
Kojto 39:d96aa62afc5b 338
Kojto 39:d96aa62afc5b 339 if (ints & OR_INTR_STATUS_WDH) {
Kojto 39:d96aa62afc5b 340 usb_hcca->DoneHead = 0;
Kojto 39:d96aa62afc5b 341 USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
Kojto 39:d96aa62afc5b 342 }
Kojto 39:d96aa62afc5b 343 }
Kojto 39:d96aa62afc5b 344 }
Kojto 39:d96aa62afc5b 345 USBH->HcRhPortStatus[0] = OR_RH_PORT_CSC;
Kojto 39:d96aa62afc5b 346 }
Kojto 39:d96aa62afc5b 347 // Port1: Reset completed
Kojto 39:d96aa62afc5b 348 if (ints_port1 & OR_RH_PORT_PRSC) {
Kojto 39:d96aa62afc5b 349 USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
Kojto 39:d96aa62afc5b 350 }
Kojto 39:d96aa62afc5b 351 // Port1: PortEnableStatusChange
Kojto 39:d96aa62afc5b 352 if (ints_port1 & OR_RH_PORT_PESC) {
Kojto 39:d96aa62afc5b 353 USBH->HcRhPortStatus[0] = OR_RH_PORT_PESC;
Kojto 39:d96aa62afc5b 354 }
Kojto 39:d96aa62afc5b 355
Kojto 39:d96aa62afc5b 356 USBH->HcInterruptStatus = OR_INTR_STATUS_RHSC;
Kojto 39:d96aa62afc5b 357 }
Kojto 39:d96aa62afc5b 358
Kojto 39:d96aa62afc5b 359 // Writeback Done Head interrupt
Kojto 39:d96aa62afc5b 360 if (ints & OR_INTR_STATUS_WDH) {
Kojto 39:d96aa62afc5b 361 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
Kojto 39:d96aa62afc5b 362 USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
Kojto 39:d96aa62afc5b 363 }
Kojto 39:d96aa62afc5b 364 }
Kojto 39:d96aa62afc5b 365 #endif