Jack Berkhout / BurstSPI

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Dependents:   20180621_FT813

Fork of BurstSPI by Erik -

BurstSPI_STM32F4.cpp@14:35df38577abd, 2018-07-23 (annotated)

Committer:
JackB
Date:
Mon Jul 23 12:23:44 2018 +0000
Revision:
14:35df38577abd
Parent:
13:bc069279eb37 
BSPI

Who changed what in which revision?

UserRevisionLine numberNew contents of line
JackB 14:35df38577abd 1 //#if (defined(TARGET_STM32F4) || defined(TARGET_STM32F7))
Sissors 13:bc069279eb37 2 #if defined(TARGET_STM32F4)
Sissors 13:bc069279eb37 3 #include "BurstSPI.h"
Sissors 13:bc069279eb37 4
Sissors 13:bc069279eb37 5 void BurstSPI::fastWrite(int data) {
Sissors 13:bc069279eb37 6
Sissors 13:bc069279eb37 7 SPI_TypeDef *spi = (SPI_TypeDef *)(_spi.spi);
Sissors 13:bc069279eb37 8 // Check if data is transmitted
Sissors 13:bc069279eb37 9 while ((spi->SR & SPI_SR_TXE) == 0);
Sissors 13:bc069279eb37 10 spi->DR = data;
Sissors 13:bc069279eb37 11 }
Sissors 13:bc069279eb37 12
Sissors 13:bc069279eb37 13 void BurstSPI::clearRX( void ) {
Sissors 13:bc069279eb37 14 //Check if the RX buffer is busy
Sissors 13:bc069279eb37 15 SPI_TypeDef *spi = (SPI_TypeDef *)(_spi.spi);
Sissors 13:bc069279eb37 16 //While busy, keep checking
Sissors 13:bc069279eb37 17 while (spi->SR & SPI_SR_BSY){
Sissors 13:bc069279eb37 18 // Check RX buffer readable
Sissors 13:bc069279eb37 19 while ((spi->SR & SPI_SR_RXNE) == 0);
Sissors 13:bc069279eb37 20 int dummy = spi->DR;
Sissors 13:bc069279eb37 21 }
Sissors 13:bc069279eb37 22 }
Sissors 13:bc069279eb37 23 #endif
Sissors 13:bc069279eb37 24