JST 2011 / PowerControl

*power consumption control(phy , semihost) library written by Michael Wei (some compile errors with mbed lib (20131011) were fixed) *for Mbed LPC1768 *for clock control , see "ClockControl"

Dependents:   GPSReceiver-EthernetDisabled GPS_1590R-A GPSXbee SerialConsol ... more

PowerControl.h@1:d0fa2aeb02a4, 2013-10-11 (annotated)

Committer:
JST2011
Date:
Fri Oct 11 02:53:21 2013 +0000
Revision:
1:d0fa2aeb02a4
Parent:
0:8599d485662f 
*change "LPC1768/ARM/LPC17xx.h" to "TARGET_LPC1768/LPC17xx.h" for mbed lib(13/10/11) ; *see also :http://mbed.org/users/mbed_official/code/mbed/file/a9913a65894f/TARGET_LPC1768

Who changed what in which revision?

UserRevisionLine numberNew contents of line
JST2011 0:8599d485662f 1 /* mbed PowerControl Library
JST2011 0:8599d485662f 2 * Copyright (c) 2010 Michael Wei
JST2011 0:8599d485662f 3 */
JST2011 0:8599d485662f 4
JST2011 0:8599d485662f 5 #ifndef MBED_POWERCONTROL_H
JST2011 0:8599d485662f 6 #define MBED_POWERCONTROL_H
JST2011 0:8599d485662f 7
JST2011 0:8599d485662f 8 //shouldn't have to include, but fixes weird problems with defines
JST2011 1:d0fa2aeb02a4 9 #include "TARGET_LPC1768/LPC17xx.h"
JST2011 0:8599d485662f 10
JST2011 0:8599d485662f 11 //System Control Register
JST2011 0:8599d485662f 12 // bit 0: Reserved
JST2011 0:8599d485662f 13 // bit 1: Sleep on Exit
JST2011 0:8599d485662f 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
JST2011 0:8599d485662f 15 // bit 2: Deep Sleep
JST2011 0:8599d485662f 16 #define LPC1768_SCR_SLEEPDEEP 0x4
JST2011 0:8599d485662f 17 // bit 3: Resereved
JST2011 0:8599d485662f 18 // bit 4: Send on Pending
JST2011 0:8599d485662f 19 #define LPC1768_SCR_SEVONPEND 0x10
JST2011 0:8599d485662f 20 // bit 5-31: Reserved
JST2011 0:8599d485662f 21
JST2011 0:8599d485662f 22 //Power Control Register
JST2011 0:8599d485662f 23 // bit 0: Power mode control bit 0 (power-down mode)
JST2011 0:8599d485662f 24 #define LPC1768_PCON_PM0 0x1
JST2011 0:8599d485662f 25 // bit 1: Power mode control bit 1 (deep power-down mode)
JST2011 0:8599d485662f 26 #define LPC1768_PCON_PM1 0x2
JST2011 0:8599d485662f 27 // bit 2: Brown-out reduced power mode
JST2011 0:8599d485662f 28 #define LPC1768_PCON_BODRPM 0x4
JST2011 0:8599d485662f 29 // bit 3: Brown-out global disable
JST2011 0:8599d485662f 30 #define LPC1768_PCON_BOGD 0x8
JST2011 0:8599d485662f 31 // bit 4: Brown-out reset disable
JST2011 0:8599d485662f 32 #define LPC1768_PCON_BORD 0x10
JST2011 0:8599d485662f 33 // bit 5-7 : Reserved
JST2011 0:8599d485662f 34 // bit 8: Sleep Mode Entry Flag
JST2011 0:8599d485662f 35 #define LPC1768_PCON_SMFLAG 0x100
JST2011 0:8599d485662f 36 // bit 9: Deep Sleep Entry Flag
JST2011 0:8599d485662f 37 #define LPC1768_PCON_DSFLAG 0x200
JST2011 0:8599d485662f 38 // bit 10: Power Down Entry Flag
JST2011 0:8599d485662f 39 #define LPC1768_PCON_PDFLAG 0x400
JST2011 0:8599d485662f 40 // bit 11: Deep Power Down Entry Flag
JST2011 0:8599d485662f 41 #define LPC1768_PCON_DPDFLAG 0x800
JST2011 0:8599d485662f 42 // bit 12-31: Reserved
JST2011 0:8599d485662f 43
JST2011 0:8599d485662f 44 //"Sleep Mode" (WFI).
JST2011 0:8599d485662f 45 inline void Sleep(void)
JST2011 0:8599d485662f 46 {
JST2011 0:8599d485662f 47 __WFI();
JST2011 0:8599d485662f 48 }
JST2011 0:8599d485662f 49
JST2011 0:8599d485662f 50 //"Deep Sleep" Mode
JST2011 0:8599d485662f 51 inline void DeepSleep(void)
JST2011 0:8599d485662f 52 {
JST2011 0:8599d485662f 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
JST2011 0:8599d485662f 54 __WFI();
JST2011 0:8599d485662f 55 }
JST2011 0:8599d485662f 56
JST2011 0:8599d485662f 57 //"Power-Down" Mode
JST2011 0:8599d485662f 58 inline void PowerDown(void)
JST2011 0:8599d485662f 59 {
JST2011 0:8599d485662f 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
JST2011 0:8599d485662f 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
JST2011 0:8599d485662f 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
JST2011 0:8599d485662f 63 __WFI();
JST2011 0:8599d485662f 64 //reset back to normal
JST2011 0:8599d485662f 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
JST2011 0:8599d485662f 66 }
JST2011 0:8599d485662f 67
JST2011 0:8599d485662f 68 //"Deep Power-Down" Mode
JST2011 0:8599d485662f 69 inline void DeepPowerDown(void)
JST2011 0:8599d485662f 70 {
JST2011 0:8599d485662f 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
JST2011 0:8599d485662f 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
JST2011 0:8599d485662f 73 __WFI();
JST2011 0:8599d485662f 74 //reset back to normal
JST2011 0:8599d485662f 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
JST2011 0:8599d485662f 76 }
JST2011 0:8599d485662f 77
JST2011 0:8599d485662f 78 //shut down BOD during power-down/deep sleep
JST2011 0:8599d485662f 79 inline void BrownOut_ReducedPowerMode_Enable(void)
JST2011 0:8599d485662f 80 {
JST2011 0:8599d485662f 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
JST2011 0:8599d485662f 82 }
JST2011 0:8599d485662f 83
JST2011 0:8599d485662f 84 //turn on BOD during power-down/deep sleep
JST2011 0:8599d485662f 85 inline void BrownOut_ReducedPowerMode_Disable(void)
JST2011 0:8599d485662f 86 {
JST2011 0:8599d485662f 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
JST2011 0:8599d485662f 88 }
JST2011 0:8599d485662f 89
JST2011 0:8599d485662f 90 //turn off brown out circutry
JST2011 0:8599d485662f 91 inline void BrownOut_Global_Disable(void)
JST2011 0:8599d485662f 92 {
JST2011 0:8599d485662f 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
JST2011 0:8599d485662f 94 }
JST2011 0:8599d485662f 95
JST2011 0:8599d485662f 96 //turn on brown out circutry
JST2011 0:8599d485662f 97 inline void BrownOut_Global_Enable(void)
JST2011 0:8599d485662f 98 {
JST2011 0:8599d485662f 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
JST2011 0:8599d485662f 100 }
JST2011 0:8599d485662f 101
JST2011 0:8599d485662f 102 //turn off brown out reset circutry
JST2011 0:8599d485662f 103 inline void BrownOut_Reset_Disable(void)
JST2011 0:8599d485662f 104 {
JST2011 0:8599d485662f 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
JST2011 0:8599d485662f 106 }
JST2011 0:8599d485662f 107
JST2011 0:8599d485662f 108 //turn on brown outreset circutry
JST2011 0:8599d485662f 109 inline void BrownOut_Reset_Enable(void)
JST2011 0:8599d485662f 110 {
JST2011 0:8599d485662f 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
JST2011 0:8599d485662f 112 }
JST2011 0:8599d485662f 113 //Peripheral Control Register
JST2011 0:8599d485662f 114 // bit 0: Reserved
JST2011 0:8599d485662f 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
JST2011 0:8599d485662f 116 #define LPC1768_PCONP_PCTIM0 0x2
JST2011 0:8599d485662f 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
JST2011 0:8599d485662f 118 #define LPC1768_PCONP_PCTIM1 0x4
JST2011 0:8599d485662f 119 // bit 3: PCUART0: UART 0 power/clock enable
JST2011 0:8599d485662f 120 #define LPC1768_PCONP_PCUART0 0x8
JST2011 0:8599d485662f 121 // bit 4: PCUART1: UART 1 power/clock enable
JST2011 0:8599d485662f 122 #define LPC1768_PCONP_PCUART1 0x10
JST2011 0:8599d485662f 123 // bit 5: Reserved
JST2011 0:8599d485662f 124 // bit 6: PCPWM1: PWM 1 power/clock enable
JST2011 0:8599d485662f 125 #define LPC1768_PCONP_PCPWM1 0x40
JST2011 0:8599d485662f 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
JST2011 0:8599d485662f 127 #define LPC1768_PCONP_PCI2C0 0x80
JST2011 0:8599d485662f 128 // bit 8: PCSPI: SPI interface power/clock enable
JST2011 0:8599d485662f 129 #define LPC1768_PCONP_PCSPI 0x100
JST2011 0:8599d485662f 130 // bit 9: PCRTC: RTC power/clock enable
JST2011 0:8599d485662f 131 #define LPC1768_PCONP_PCRTC 0x200
JST2011 0:8599d485662f 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
JST2011 0:8599d485662f 133 #define LPC1768_PCONP_PCSSP1 0x400
JST2011 0:8599d485662f 134 // bit 11: Reserved
JST2011 0:8599d485662f 135 // bit 12: PCADC: A/D converter power/clock enable
JST2011 0:8599d485662f 136 #define LPC1768_PCONP_PCADC 0x1000
JST2011 0:8599d485662f 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
JST2011 0:8599d485662f 138 #define LPC1768_PCONP_PCCAN1 0x2000
JST2011 0:8599d485662f 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
JST2011 0:8599d485662f 140 #define LPC1768_PCONP_PCCAN2 0x4000
JST2011 0:8599d485662f 141 // bit 15: PCGPIO: GPIOs power/clock enable
JST2011 0:8599d485662f 142 #define LPC1768_PCONP_PCGPIO 0x8000
JST2011 0:8599d485662f 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
JST2011 0:8599d485662f 144 #define LPC1768_PCONP_PCRIT 0x10000
JST2011 0:8599d485662f 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
JST2011 0:8599d485662f 146 #define LPC1768_PCONP_PCMCPWM 0x20000
JST2011 0:8599d485662f 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
JST2011 0:8599d485662f 148 #define LPC1768_PCONP_PCQEI 0x40000
JST2011 0:8599d485662f 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
JST2011 0:8599d485662f 150 #define LPC1768_PCONP_PCI2C1 0x80000
JST2011 0:8599d485662f 151 // bit 20: Reserved
JST2011 0:8599d485662f 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
JST2011 0:8599d485662f 153 #define LPC1768_PCONP_PCSSP0 0x200000
JST2011 0:8599d485662f 154 // bit 22: PCTIM2: Timer 2 power/clock enable
JST2011 0:8599d485662f 155 #define LPC1768_PCONP_PCTIM2 0x400000
JST2011 0:8599d485662f 156 // bit 23: PCTIM3: Timer 3 power/clock enable
JST2011 0:8599d485662f 157 #define LPC1768_PCONP_PCQTIM3 0x800000
JST2011 0:8599d485662f 158 // bit 24: PCUART2: UART 2 power/clock enable
JST2011 0:8599d485662f 159 #define LPC1768_PCONP_PCUART2 0x1000000
JST2011 0:8599d485662f 160 // bit 25: PCUART3: UART 3 power/clock enable
JST2011 0:8599d485662f 161 #define LPC1768_PCONP_PCUART3 0x2000000
JST2011 0:8599d485662f 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
JST2011 0:8599d485662f 163 #define LPC1768_PCONP_PCI2C2 0x4000000
JST2011 0:8599d485662f 164 // bit 27: PCI2S: I2S interface power/clock enable
JST2011 0:8599d485662f 165 #define LPC1768_PCONP_PCI2S 0x8000000
JST2011 0:8599d485662f 166 // bit 28: Reserved
JST2011 0:8599d485662f 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
JST2011 0:8599d485662f 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
JST2011 0:8599d485662f 169 // bit 30: PCENET: Ethernet block power/clock enable
JST2011 0:8599d485662f 170 #define LPC1768_PCONP_PCENET 0x40000000
JST2011 0:8599d485662f 171 // bit 31: PCUSB: USB interface power/clock enable
JST2011 0:8599d485662f 172 #define LPC1768_PCONP_PCUSB 0x80000000
JST2011 0:8599d485662f 173
JST2011 0:8599d485662f 174 //Powers Up specified Peripheral(s)
JST2011 0:8599d485662f 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
JST2011 0:8599d485662f 176 {
JST2011 0:8599d485662f 177 return LPC_SC->PCONP |= bitMask;
JST2011 0:8599d485662f 178 }
JST2011 0:8599d485662f 179
JST2011 0:8599d485662f 180 //Powers Down specified Peripheral(s)
JST2011 0:8599d485662f 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
JST2011 0:8599d485662f 182 {
JST2011 0:8599d485662f 183 return LPC_SC->PCONP &= ~bitMask;
JST2011 0:8599d485662f 184 }
JST2011 0:8599d485662f 185
JST2011 0:8599d485662f 186 //returns if the peripheral is on or off
JST2011 0:8599d485662f 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
JST2011 0:8599d485662f 188 {
JST2011 0:8599d485662f 189 return (LPC_SC->PCONP & peripheral) ? true : false;
JST2011 0:8599d485662f 190 }
JST2011 0:8599d485662f 191
JST2011 0:8599d485662f 192 #endif