wifi_Example - wifi test

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wifi test

Dependencies: X_NUCLEO_IKS01A2 mbed-http

easy-connect/stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Regs.h@0:24d3eb812fd4, 2018-09-05 (annotated)

Committer:: JMF
Date:: Wed Sep 05 14:28:24 2018 +0000
Revision:: 0:24d3eb812fd4

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
JMF	0:24d3eb812fd4	1	/**
JMF	0:24d3eb812fd4	2	******************************************************************************
JMF	0:24d3eb812fd4	3	* @file SPIRIT_Regs.h
JMF	0:24d3eb812fd4	4	* @author VMA division - AMS
JMF	0:24d3eb812fd4	5	* @version 3.2.2
JMF	0:24d3eb812fd4	6	* @date 08-July-2015
JMF	0:24d3eb812fd4	7	* @brief This file contains all the SPIRIT registers address and masks.
JMF	0:24d3eb812fd4	8	* @details
JMF	0:24d3eb812fd4	9	*
JMF	0:24d3eb812fd4	10	* @attention
JMF	0:24d3eb812fd4	11	*
JMF	0:24d3eb812fd4	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
JMF	0:24d3eb812fd4	13	*
JMF	0:24d3eb812fd4	14	* Redistribution and use in source and binary forms, with or without modification,
JMF	0:24d3eb812fd4	15	* are permitted provided that the following conditions are met:
JMF	0:24d3eb812fd4	16	* 1. Redistributions of source code must retain the above copyright notice,
JMF	0:24d3eb812fd4	17	* this list of conditions and the following disclaimer.
JMF	0:24d3eb812fd4	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
JMF	0:24d3eb812fd4	19	* this list of conditions and the following disclaimer in the documentation
JMF	0:24d3eb812fd4	20	* and/or other materials provided with the distribution.
JMF	0:24d3eb812fd4	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
JMF	0:24d3eb812fd4	22	* may be used to endorse or promote products derived from this software
JMF	0:24d3eb812fd4	23	* without specific prior written permission.
JMF	0:24d3eb812fd4	24	*
JMF	0:24d3eb812fd4	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
JMF	0:24d3eb812fd4	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
JMF	0:24d3eb812fd4	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
JMF	0:24d3eb812fd4	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
JMF	0:24d3eb812fd4	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
JMF	0:24d3eb812fd4	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
JMF	0:24d3eb812fd4	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
JMF	0:24d3eb812fd4	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
JMF	0:24d3eb812fd4	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
JMF	0:24d3eb812fd4	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
JMF	0:24d3eb812fd4	35	*
JMF	0:24d3eb812fd4	36	******************************************************************************
JMF	0:24d3eb812fd4	37	*/
JMF	0:24d3eb812fd4	38
JMF	0:24d3eb812fd4	39	/* Define to prevent recursive inclusion -------------------------------------*/
JMF	0:24d3eb812fd4	40	#ifndef __SPIRIT1_REGS_H
JMF	0:24d3eb812fd4	41	#define __SPIRIT1_REGS_H
JMF	0:24d3eb812fd4	42
JMF	0:24d3eb812fd4	43	#ifdef __cplusplus
JMF	0:24d3eb812fd4	44	extern "C" {
JMF	0:24d3eb812fd4	45	#endif
JMF	0:24d3eb812fd4	46
JMF	0:24d3eb812fd4	47	/**
JMF	0:24d3eb812fd4	48	* @addtogroup SPIRIT_Registers SPIRIT Registers
JMF	0:24d3eb812fd4	49	* @brief Header file containing all the SPIRIT registers address and masks.
JMF	0:24d3eb812fd4	50	* @details See the file <i>@ref SPIRIT_Regs.h</i> for more details.
JMF	0:24d3eb812fd4	51	* @{
JMF	0:24d3eb812fd4	52	*/
JMF	0:24d3eb812fd4	53
JMF	0:24d3eb812fd4	54	/** @defgroup General_Configuration_Registers
JMF	0:24d3eb812fd4	55	* @{
JMF	0:24d3eb812fd4	56	*/
JMF	0:24d3eb812fd4	57
JMF	0:24d3eb812fd4	58	/** @defgroup ANA_FUNC_CONF_1_Register
JMF	0:24d3eb812fd4	59	* @{
JMF	0:24d3eb812fd4	60	*/
JMF	0:24d3eb812fd4	61
JMF	0:24d3eb812fd4	62	/**
JMF	0:24d3eb812fd4	63	* \brief ANA_FUNC_CONF register 1
JMF	0:24d3eb812fd4	64	* \code
JMF	0:24d3eb812fd4	65	* Read Write
JMF	0:24d3eb812fd4	66	* Default value: 0x0C
JMF	0:24d3eb812fd4	67	* 7:5 NUM_EN_PIPES: Number of enabled pipes (starting from Data Pipe 0).
JMF	0:24d3eb812fd4	68	* 4:2 GM_CONF[2:0]: Sets the driver gm of the XO at start-up:
JMF	0:24d3eb812fd4	69	* GM_CONF2 \| GM_CONF1 \| GM_CONF0 \| GM [mS]
JMF	0:24d3eb812fd4	70	* ------------------------------------------
JMF	0:24d3eb812fd4	71	* 0 \| 0 \| 0 \| 13.2
JMF	0:24d3eb812fd4	72	* 0 \| 0 \| 1 \| 18.2
JMF	0:24d3eb812fd4	73	* 0 \| 1 \| 0 \| 21.5
JMF	0:24d3eb812fd4	74	* 0 \| 1 \| 1 \| 25.6
JMF	0:24d3eb812fd4	75	* 1 \| 0 \| 0 \| 28.8
JMF	0:24d3eb812fd4	76	* 1 \| 0 \| 1 \| 33.9
JMF	0:24d3eb812fd4	77	* 1 \| 1 \| 0 \| 38.5
JMF	0:24d3eb812fd4	78	* 1 \| 1 \| 1 \| 43.0
JMF	0:24d3eb812fd4	79	* 1:0 SET_BLD_LVL[1:0]: Sets the Battery Level Detector threshold:
JMF	0:24d3eb812fd4	80	* SET_BLD_LVL1 \| SET_BLD_LVL0 \| Threshold [V]
JMF	0:24d3eb812fd4	81	* ------------------------------------------
JMF	0:24d3eb812fd4	82	* 0 \| 0 \| 2.7
JMF	0:24d3eb812fd4	83	* 0 \| 1 \| 2.5
JMF	0:24d3eb812fd4	84	* 1 \| 0 \| 2.3
JMF	0:24d3eb812fd4	85	* 1 \| 1 \| 2.1
JMF	0:24d3eb812fd4	86	* \endcode
JMF	0:24d3eb812fd4	87	*/
JMF	0:24d3eb812fd4	88
JMF	0:24d3eb812fd4	89	#define ANA_FUNC_CONF1_BASE ((uint8_t)0x00) /!< ANA_FUNC_CONF1 Address (R/W) /
JMF	0:24d3eb812fd4	90
JMF	0:24d3eb812fd4	91	#define ANA_FUNC_CONF1_NUM_PIPES_MASK ((uint8_t)0xE0) /!< Mask for number of enabled pipes/
JMF	0:24d3eb812fd4	92
JMF	0:24d3eb812fd4	93	#define ANA_FUNC_CONF1_GMCONF_MASK ((uint8_t)0x1C) /!< Mask of the GmConf field of ANA_FUNC_CONF1 register (R/W) /
JMF	0:24d3eb812fd4	94
JMF	0:24d3eb812fd4	95	#define GM_13_2 ((uint8_t)0x00) /!< Transconducatance Gm at start-up 13.2 mS /
JMF	0:24d3eb812fd4	96	#define GM_18_2 ((uint8_t)0x04) /!< Transconducatance Gm at start-up 18.2 mS /
JMF	0:24d3eb812fd4	97	#define GM_21_5 ((uint8_t)0x08) /!< Transconducatance Gm at start-up 21.5 mS /
JMF	0:24d3eb812fd4	98	#define GM_25_6 ((uint8_t)0x0C) /!< Transconducatance Gm at start-up 25.6 mS /
JMF	0:24d3eb812fd4	99	#define GM_28_8 ((uint8_t)0x10) /!< Transconducatance Gm at start-up 28.8 mS /
JMF	0:24d3eb812fd4	100	#define GM_33_9 ((uint8_t)0x14) /!< Transconducatance Gm at start-up 33.9 mS /
JMF	0:24d3eb812fd4	101	#define GM_38_5 ((uint8_t)0x18) /!< Transconducatance Gm at start-up 38.5 mS /
JMF	0:24d3eb812fd4	102	#define GM_43_0 ((uint8_t)0x1C) /!< Transconducatance Gm at start-up 43.0 mS /
JMF	0:24d3eb812fd4	103
JMF	0:24d3eb812fd4	104	#define ANA_FUNC_CONF1_SET_BLD_LVL_MASK ((uint8_t)0x03) /!< Mask of the SET_BLD_LV field of ANA_FUNC_CONF1 register (R/W) /
JMF	0:24d3eb812fd4	105
JMF	0:24d3eb812fd4	106	#define BLD_LVL_2_7 ((uint8_t)0x00) /!< Sets the Battery Level Detector threshold to 2.7V /
JMF	0:24d3eb812fd4	107	#define BLD_LVL_2_5 ((uint8_t)0x01) /!< Sets the Battery Level Detector threshold to 2.5V /
JMF	0:24d3eb812fd4	108	#define BLD_LVL_2_3 ((uint8_t)0x02) /!< Sets the Battery Level Detector threshold to 2.3V /
JMF	0:24d3eb812fd4	109	#define BLD_LVL_2_1 ((uint8_t)0x03) /!< Sets the Battery Level Detector threshold to 2.1V /
JMF	0:24d3eb812fd4	110
JMF	0:24d3eb812fd4	111	/**
JMF	0:24d3eb812fd4	112	* @}
JMF	0:24d3eb812fd4	113	*/
JMF	0:24d3eb812fd4	114
JMF	0:24d3eb812fd4	115
JMF	0:24d3eb812fd4	116	/** @defgroup ANA_FUNC_CONF_0_Register
JMF	0:24d3eb812fd4	117	* @{
JMF	0:24d3eb812fd4	118	*/
JMF	0:24d3eb812fd4	119
JMF	0:24d3eb812fd4	120	/**
JMF	0:24d3eb812fd4	121	* \brief ANA_FUNC_CONF register 0
JMF	0:24d3eb812fd4	122	* \code
JMF	0:24d3eb812fd4	123	* Read Write
JMF	0:24d3eb812fd4	124	* Default value: 0xC0
JMF	0:24d3eb812fd4	125	* 7 Reserved.
JMF	0:24d3eb812fd4	126	* 6 24_26_MHz_SELECT: 1 - 26 MHz configuration
JMF	0:24d3eb812fd4	127	* 0 - 24 MHz configuration
JMF	0:24d3eb812fd4	128	* 5 AES_ON: 1 - AES engine enabled
JMF	0:24d3eb812fd4	129	* 0 - AES engine disabled
JMF	0:24d3eb812fd4	130	* 4 EXT_REF: 1 - Reference signal from XIN pin
JMF	0:24d3eb812fd4	131	* 0 - Reference signal from XO circuit
JMF	0:24d3eb812fd4	132	* 3 HIGH_POWER_MODE: 1 - SET_SMPS_LEVEL word will be set to the value to
JMF	0:24d3eb812fd4	133	* PM_TEST register in RX state, while in TX state it
JMF	0:24d3eb812fd4	134	* will be fixed to 111 (which programs the SMPS output
JMF	0:24d3eb812fd4	135	* at max value 1.8V)
JMF	0:24d3eb812fd4	136	* 0 - SET_SMPS_LEVEL word will hold the value written in the
JMF	0:24d3eb812fd4	137	* PM_TEST register both in RX and TX state
JMF	0:24d3eb812fd4	138	* 2 BROWN_OUT: 1 - Brown_Out Detection enabled
JMF	0:24d3eb812fd4	139	* 0 - Brown_Out Detection disabled
JMF	0:24d3eb812fd4	140	* 1 BATTERY_LEVEL: 1 - Battery level detector enabled
JMF	0:24d3eb812fd4	141	* 0 - Battery level detector disabled
JMF	0:24d3eb812fd4	142	* 0 TS: 1 - Enable the "Temperature Sensor" function
JMF	0:24d3eb812fd4	143	* 0 - Disable the "Temperature Sensor" function
JMF	0:24d3eb812fd4	144	* \endcode
JMF	0:24d3eb812fd4	145	*/
JMF	0:24d3eb812fd4	146
JMF	0:24d3eb812fd4	147
JMF	0:24d3eb812fd4	148	#define ANA_FUNC_CONF0_BASE ((uint8_t)0x01) /!< ANA_FUNC_CONF0 Address (R/W) /
JMF	0:24d3eb812fd4	149
JMF	0:24d3eb812fd4	150	#define SELECT_24_26_MHZ_MASK ((uint8_t)0x40) /!< Configure the RCO if using 26 MHz or 24 MHz master clock/reference signal /
JMF	0:24d3eb812fd4	151	#define AES_MASK ((uint8_t)0x20) /!< AES engine on/off /
JMF	0:24d3eb812fd4	152	#define EXT_REF_MASK ((uint8_t)0x10) /!< Reference signal from XIN pin (oscillator external) or from XO circuit (oscillator internal)/
JMF	0:24d3eb812fd4	153	#define HIGH_POWER_MODE_MASK ((uint8_t)0x08) /*!< SET_SMPS_LEVEL word will be set to the value to PM_TEST register
JMF	0:24d3eb812fd4	154	in RX state, while in TX state it will be fixed to 111
JMF	0:24d3eb812fd4	155	(which programs the SMPS output at max value, 1.8V) */
JMF	0:24d3eb812fd4	156	#define BROWN_OUT_MASK ((uint8_t)0x04) /!< Accurate Brown-Out detection on/off /
JMF	0:24d3eb812fd4	157	#define BATTERY_LEVEL_MASK ((uint8_t)0x02) /!< Battery level detector circuit on/off /
JMF	0:24d3eb812fd4	158	#define TEMPERATURE_SENSOR_MASK ((uint8_t)0x01) /!< The Temperature Sensor (available on GPIO0) on/off /
JMF	0:24d3eb812fd4	159
JMF	0:24d3eb812fd4	160	/**
JMF	0:24d3eb812fd4	161	* @}
JMF	0:24d3eb812fd4	162	*/
JMF	0:24d3eb812fd4	163
JMF	0:24d3eb812fd4	164	/** @defgroup ANT_SELECT_CONF_Register
JMF	0:24d3eb812fd4	165	* @{
JMF	0:24d3eb812fd4	166	*/
JMF	0:24d3eb812fd4	167
JMF	0:24d3eb812fd4	168	/**
JMF	0:24d3eb812fd4	169	* \brief ANT_SELECT_CONF register
JMF	0:24d3eb812fd4	170	* \code
JMF	0:24d3eb812fd4	171	* Read Write
JMF	0:24d3eb812fd4	172	* Default value: 0x05
JMF	0:24d3eb812fd4	173	*
JMF	0:24d3eb812fd4	174	* 7:5 Reserved.
JMF	0:24d3eb812fd4	175	*
JMF	0:24d3eb812fd4	176	* 4 CS_BLANKING: Blank received data if signal is below the CS threshold
JMF	0:24d3eb812fd4	177	*
JMF	0:24d3eb812fd4	178	* 3 AS_ENABLE: Enable antenna switching
JMF	0:24d3eb812fd4	179	* 1 - Enable
JMF	0:24d3eb812fd4	180	* 0 - Disable
JMF	0:24d3eb812fd4	181	*
JMF	0:24d3eb812fd4	182	* 2:0 AS_MEAS_TIME[2:0]: Measurement time according to the formula Tmeas = 242^(EchFlt)2^AS_MEAS_TIME/fxo
JMF	0:24d3eb812fd4	183	* \endcode
JMF	0:24d3eb812fd4	184	*/
JMF	0:24d3eb812fd4	185	#define ANT_SELECT_CONF_BASE ((uint8_t)0x27) /!< Antenna diversity (works only in static carrier sense mode) /
JMF	0:24d3eb812fd4	186	#define ANT_SELECT_CS_BLANKING_MASK ((uint8_t)0x10) /!< CS data blanking on/off /
JMF	0:24d3eb812fd4	187	#define ANT_SELECT_CONF_AS_MASK ((uint8_t)0x08) /!< Antenna diversity on/off /
JMF	0:24d3eb812fd4	188
JMF	0:24d3eb812fd4	189	/**
JMF	0:24d3eb812fd4	190	* @}
JMF	0:24d3eb812fd4	191	*/
JMF	0:24d3eb812fd4	192
JMF	0:24d3eb812fd4	193	/** @defgroup DEVICE_INFO1_Register
JMF	0:24d3eb812fd4	194	* @{
JMF	0:24d3eb812fd4	195	*/
JMF	0:24d3eb812fd4	196
JMF	0:24d3eb812fd4	197	/**
JMF	0:24d3eb812fd4	198	* \brief DEVICE_INFO1[7:0] registers
JMF	0:24d3eb812fd4	199	* \code
JMF	0:24d3eb812fd4	200	* Default value: 0x01
JMF	0:24d3eb812fd4	201	* Read
JMF	0:24d3eb812fd4	202	*
JMF	0:24d3eb812fd4	203	* 7:0 PARTNUM[7:0]: Device part number
JMF	0:24d3eb812fd4	204	* \endcode
JMF	0:24d3eb812fd4	205	*/
JMF	0:24d3eb812fd4	206	#define DEVICE_INFO1_PARTNUM ((uint8_t)(0xF0)) /!< Device part number [7:0] /
JMF	0:24d3eb812fd4	207
JMF	0:24d3eb812fd4	208	/**
JMF	0:24d3eb812fd4	209	* @}
JMF	0:24d3eb812fd4	210	*/
JMF	0:24d3eb812fd4	211
JMF	0:24d3eb812fd4	212	/** @defgroup DEVICE_INFO0_Register
JMF	0:24d3eb812fd4	213	* @{
JMF	0:24d3eb812fd4	214	*/
JMF	0:24d3eb812fd4	215
JMF	0:24d3eb812fd4	216	/**
JMF	0:24d3eb812fd4	217	* \brief DEVICE_INFO0[7:0] registers
JMF	0:24d3eb812fd4	218	* \code
JMF	0:24d3eb812fd4	219	* Read
JMF	0:24d3eb812fd4	220	*
JMF	0:24d3eb812fd4	221	* 7:0 VERSION[7:0]: Device version number
JMF	0:24d3eb812fd4	222	* \endcode
JMF	0:24d3eb812fd4	223	*/
JMF	0:24d3eb812fd4	224	#define DEVICE_INFO0_VERSION ((uint8_t)(0xF1)) /!< Device version [7:0]; (0x55 in CUT1.0) /
JMF	0:24d3eb812fd4	225
JMF	0:24d3eb812fd4	226	/**
JMF	0:24d3eb812fd4	227	* @}
JMF	0:24d3eb812fd4	228	*/
JMF	0:24d3eb812fd4	229
JMF	0:24d3eb812fd4	230
JMF	0:24d3eb812fd4	231	/**
JMF	0:24d3eb812fd4	232	* @}
JMF	0:24d3eb812fd4	233	*/
JMF	0:24d3eb812fd4	234
JMF	0:24d3eb812fd4	235
JMF	0:24d3eb812fd4	236	/** @defgroup GPIO_Registers
JMF	0:24d3eb812fd4	237	* @{
JMF	0:24d3eb812fd4	238	*/
JMF	0:24d3eb812fd4	239
JMF	0:24d3eb812fd4	240	/** @defgroup GPIOx_CONF_Registers
JMF	0:24d3eb812fd4	241	* @{
JMF	0:24d3eb812fd4	242	*/
JMF	0:24d3eb812fd4	243
JMF	0:24d3eb812fd4	244	/**
JMF	0:24d3eb812fd4	245	* \brief GPIOx registers
JMF	0:24d3eb812fd4	246	* \code
JMF	0:24d3eb812fd4	247	* Read Write
JMF	0:24d3eb812fd4	248	* Default value: 0x03
JMF	0:24d3eb812fd4	249	* 7:3 GPIO_SELECT[4:0]: Specify the I/O signal.
JMF	0:24d3eb812fd4	250	* GPIO_SELECT[4:0] \| I/O \| Signal
JMF	0:24d3eb812fd4	251	* ------------------------------------------------
JMF	0:24d3eb812fd4	252	* 0 \| Output \| nIRQ
JMF	0:24d3eb812fd4	253	* 0 \| Input \| TX command
JMF	0:24d3eb812fd4	254	* 1 \| Output \| POR inverted
JMF	0:24d3eb812fd4	255	* 1 \| Input \| RX command
JMF	0:24d3eb812fd4	256	* 2 \| Output \| Wake-Up timer expiration
JMF	0:24d3eb812fd4	257	* 2 \| Input \| TX data for direct modulation
JMF	0:24d3eb812fd4	258	* 3 \| Output \| Low Battery Detection
JMF	0:24d3eb812fd4	259	* 3 \| Input \| Wake-up from external input
JMF	0:24d3eb812fd4	260	* 4 \| Output \| TX clock output
JMF	0:24d3eb812fd4	261	* 5 \| Output \| TX state
JMF	0:24d3eb812fd4	262	* 6 \| Output \| TX FIFO Almost Empty Flag
JMF	0:24d3eb812fd4	263	* 7 \| Output \| TX FIFO ALmost Full Flag
JMF	0:24d3eb812fd4	264	* 8 \| Output \| RX data output
JMF	0:24d3eb812fd4	265	* 9 \| Output \| RX clock output
JMF	0:24d3eb812fd4	266	* 10 \| Output \| RX state
JMF	0:24d3eb812fd4	267	* 11 \| Output \| RX FIFO Almost Full Flag
JMF	0:24d3eb812fd4	268	* 12 \| Output \| RX FIFO Almost Empty Flag
JMF	0:24d3eb812fd4	269	* 13 \| Output \| Antenna switch
JMF	0:24d3eb812fd4	270	* 14 \| Output \| Valid preamble detected
JMF	0:24d3eb812fd4	271	* 15 \| Output \| Sync word detected
JMF	0:24d3eb812fd4	272	* 16 \| Output \| RSSI above threshold
JMF	0:24d3eb812fd4	273	* 17 \| Output \| MCU clock
JMF	0:24d3eb812fd4	274	* 18 \| Output \| TX or RX mode indicator
JMF	0:24d3eb812fd4	275	* 19 \| Output \| VDD
JMF	0:24d3eb812fd4	276	* 20 \| Output \| GND
JMF	0:24d3eb812fd4	277	* 21 \| Output \| External SMPS enable signal
JMF	0:24d3eb812fd4	278	* 22-31 \| Not Used \| Not Used
JMF	0:24d3eb812fd4	279	* 2 Reserved
JMF	0:24d3eb812fd4	280	* 1:0 GpioMode[1:0]: Specify the mode:
JMF	0:24d3eb812fd4	281	* GPIO_MODE1 \| GPIO_MODE0 \| MODE
JMF	0:24d3eb812fd4	282	* ------------------------------------------------------------
JMF	0:24d3eb812fd4	283	* 0 \| 0 \| Analog (valid only for GPIO_0)
JMF	0:24d3eb812fd4	284	* 0 \| 1 \| Digital Input
JMF	0:24d3eb812fd4	285	* 1 \| 0 \| Digital Output Low Power
JMF	0:24d3eb812fd4	286	* 1 \| 1 \| Digital Output High Power
JMF	0:24d3eb812fd4	287	*
JMF	0:24d3eb812fd4	288	* Note: The Analog mode is used only for temperature sensor indication. This is available only
JMF	0:24d3eb812fd4	289	* on GPIO_0 by setting the TS bit in the ANA_FUNC_CONF_0_Register.
JMF	0:24d3eb812fd4	290	* \endcode
JMF	0:24d3eb812fd4	291	*/
JMF	0:24d3eb812fd4	292
JMF	0:24d3eb812fd4	293
JMF	0:24d3eb812fd4	294	#define GPIO3_CONF_BASE ((uint8_t)0x02) /!< GPIO_3 register address /
JMF	0:24d3eb812fd4	295	#define GPIO2_CONF_BASE ((uint8_t)0x03) /!< GPIO_3 register address /
JMF	0:24d3eb812fd4	296	#define GPIO1_CONF_BASE ((uint8_t)0x04) /!< GPIO_3 register address /
JMF	0:24d3eb812fd4	297	#define GPIO0_CONF_BASE ((uint8_t)0x05) /!< GPIO_3 register address /
JMF	0:24d3eb812fd4	298
JMF	0:24d3eb812fd4	299	#define CONF_GPIO_IN_TX_Command ((uint8_t)0x00) /!< TX command direct from PIN (rising edge, width min=50ns) /
JMF	0:24d3eb812fd4	300	#define CONF_GPIO_IN_RX_Command ((uint8_t)0x08) /!< RX command direct from PIN (rising edge, width min=50ns)/
JMF	0:24d3eb812fd4	301	#define CONF_GPIO_IN_TX_Data ((uint8_t)0x10) /!< TX data input for direct modulation /
JMF	0:24d3eb812fd4	302	#define CONF_GPIO_IN_WKUP_Ext ((uint8_t)0x18) /!< Wake up from external input /
JMF	0:24d3eb812fd4	303
JMF	0:24d3eb812fd4	304	#define CONF_GPIO_OUT_nIRQ ((uint8_t)0x00) /!< nIRQ (Interrupt Request, active low) , default configuration after POR /
JMF	0:24d3eb812fd4	305	#define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /!< POR inverted (active low) /
JMF	0:24d3eb812fd4	306	#define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /!< Wake-Up Timer expiration: 1 when WUT has expired /
JMF	0:24d3eb812fd4	307	#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /!< Low battery detection: 1 when battery is below threshold setting /
JMF	0:24d3eb812fd4	308	#define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /!< TX data internal clock output (TX data are sampled on the rising edge of it) /
JMF	0:24d3eb812fd4	309	#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /!< TX state indication: 1 when Spirit1 is transiting in the TX state /
JMF	0:24d3eb812fd4	310	#define CONF_GPIO_OUT_TX_FIFO_Almost_Empty ((uint8_t)0x30) /!< TX FIFO Almost Empty Flag /
JMF	0:24d3eb812fd4	311	#define CONF_GPIO_OUT_TX_FIFO_Amost_Full ((uint8_t)0x38) /!< TX FIFO Almost Full Flag /
JMF	0:24d3eb812fd4	312	#define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /!< RX data output /
JMF	0:24d3eb812fd4	313	#define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /!< RX clock output (recovered from received data) /
JMF	0:24d3eb812fd4	314	#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /!< RX state indication: 1 when Spirit1 is transiting in the RX state /
JMF	0:24d3eb812fd4	315	#define CONF_GPIO_OUT_RX_FIFO_Almost_Full ((uint8_t)0x58) /!< RX FIFO Almost Full Flag /
JMF	0:24d3eb812fd4	316	#define CONF_GPIO_OUT_RX_FIFO_Almost_Empty ((uint8_t)0x60) /!< RX FIFO Almost Empty Flag /
JMF	0:24d3eb812fd4	317	#define CONF_GPIO_OUT_Antenna_Switch ((uint8_t)0x68) /!< Antenna switch used for antenna diversity /
JMF	0:24d3eb812fd4	318	#define CONF_GPIO_OUT_Valid_Preamble ((uint8_t)0x70) /!< Valid Preamble Detected Flag /
JMF	0:24d3eb812fd4	319	#define CONF_GPIO_OUT_Sync_Detected ((uint8_t)0x78) /!< Sync WordSync Word Detected Flag /
JMF	0:24d3eb812fd4	320	#define CONF_GPIO_OUT_RSSI_Threshold ((uint8_t)0x80) /!< CCA Assessment Flag /
JMF	0:24d3eb812fd4	321	#define CONF_GPIO_OUT_MCU_Clock ((uint8_t)0x88) /!< MCU Clock /
JMF	0:24d3eb812fd4	322	#define CONF_GPIO_OUT_TX_RX_Mode ((uint8_t)0x90) /!< TX or RX mode indicator (to enable an external range extender) /
JMF	0:24d3eb812fd4	323	#define CONF_GPIO_OUT_VDD ((uint8_t)0x98) /!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) /
JMF	0:24d3eb812fd4	324	#define CONF_GPIO_OUT_GND ((uint8_t)0xA0) /!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) /
JMF	0:24d3eb812fd4	325	#define CONF_GPIO_OUT_SMPS_Ext ((uint8_t)0xA8) /!< External SMPS enable signal (active high) /
JMF	0:24d3eb812fd4	326
JMF	0:24d3eb812fd4	327	#define CONF_GPIO_MODE_ANALOG ((uint8_t)0x00) /!< Analog test BUS on GPIO; used only in test mode (except for temperature sensor) /
JMF	0:24d3eb812fd4	328	#define CONF_GPIO_MODE_DIG_IN ((uint8_t)0x01) /!< Digital Input on GPIO /
JMF	0:24d3eb812fd4	329	#define CONF_GPIO_MODE_DIG_OUTL ((uint8_t)0x02) /!< Digital Output on GPIO (low current) /
JMF	0:24d3eb812fd4	330	#define CONF_GPIO_MODE_DIG_OUTH ((uint8_t)0x03) /!< Digital Output on GPIO (high current) /
JMF	0:24d3eb812fd4	331
JMF	0:24d3eb812fd4	332	/**
JMF	0:24d3eb812fd4	333	* @}
JMF	0:24d3eb812fd4	334	*/
JMF	0:24d3eb812fd4	335
JMF	0:24d3eb812fd4	336
JMF	0:24d3eb812fd4	337	/** @defgroup MCU_CK_CONF_Register
JMF	0:24d3eb812fd4	338	* @{
JMF	0:24d3eb812fd4	339	*/
JMF	0:24d3eb812fd4	340
JMF	0:24d3eb812fd4	341	/**
JMF	0:24d3eb812fd4	342	* \brief MCU_CK_CONF register
JMF	0:24d3eb812fd4	343	* \code
JMF	0:24d3eb812fd4	344	* Read Write
JMF	0:24d3eb812fd4	345	* Default value: 0x00
JMF	0:24d3eb812fd4	346	* 7 Reserved.
JMF	0:24d3eb812fd4	347	* 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided before entering in STANDBY state.
JMF	0:24d3eb812fd4	348	* CLOCK_TAIL1 \| CLOCK_TAIL0 \| Number of Extra Cycles
JMF	0:24d3eb812fd4	349	* ------------------------------------------------------------
JMF	0:24d3eb812fd4	350	* 0 \| 0 \| 0
JMF	0:24d3eb812fd4	351	* 0 \| 1 \| 64
JMF	0:24d3eb812fd4	352	* 1 \| 0 \| 256
JMF	0:24d3eb812fd4	353	* 1 \| 1 \| 512
JMF	0:24d3eb812fd4	354	* 4:1 XO_RATIO[3:0]: Specifies the division ratio when XO oscillator is the clock source
JMF	0:24d3eb812fd4	355	* XO_RATIO[3:0] \| Division Ratio
JMF	0:24d3eb812fd4	356	* -----------------------------------
JMF	0:24d3eb812fd4	357	* 0 \| 1
JMF	0:24d3eb812fd4	358	* 1 \| 2/3
JMF	0:24d3eb812fd4	359	* 2 \| 1/2
JMF	0:24d3eb812fd4	360	* 3 \| 1/3
JMF	0:24d3eb812fd4	361	* 4 \| 1/4
JMF	0:24d3eb812fd4	362	* 5 \| 1/6
JMF	0:24d3eb812fd4	363	* 6 \| 1/8
JMF	0:24d3eb812fd4	364	* 7 \| 1/12
JMF	0:24d3eb812fd4	365	* 8 \| 1/16
JMF	0:24d3eb812fd4	366	* 9 \| 1/24
JMF	0:24d3eb812fd4	367	* 10 \| 1/36
JMF	0:24d3eb812fd4	368	* 11 \| 1/48
JMF	0:24d3eb812fd4	369	* 12 \| 1/64
JMF	0:24d3eb812fd4	370	* 13 \| 1/96
JMF	0:24d3eb812fd4	371	* 14 \| 1/128
JMF	0:24d3eb812fd4	372	* 15 \| 1/256
JMF	0:24d3eb812fd4	373	* 0 RCO_RATIO: Specifies the divsion ratio when RC oscillator is the clock source
JMF	0:24d3eb812fd4	374	* 0 - Division Ratio equal to 0
JMF	0:24d3eb812fd4	375	* 1 - Division Ratio equal to 1/128
JMF	0:24d3eb812fd4	376	* \endcode
JMF	0:24d3eb812fd4	377	*/
JMF	0:24d3eb812fd4	378
JMF	0:24d3eb812fd4	379
JMF	0:24d3eb812fd4	380	#define MCU_CK_CONF_BASE ((uint8_t)0x06) /!< MCU Clock Config register address /
JMF	0:24d3eb812fd4	381
JMF	0:24d3eb812fd4	382	#define MCU_CK_ENABLE ((uint8_t)0x80) /!< MCU clock enable bit /
JMF	0:24d3eb812fd4	383
JMF	0:24d3eb812fd4	384	#define MCU_CK_CONF_CLOCK_TAIL_0 ((uint8_t)0x00) /!< 0 extra clock cycles provided to the MCU before switching to STANDBY state /
JMF	0:24d3eb812fd4	385	#define MCU_CK_CONF_CLOCK_TAIL_64 ((uint8_t)0x20) /!< 64 extra clock cycles provided to the MCU before switching to STANDBY state /
JMF	0:24d3eb812fd4	386	#define MCU_CK_CONF_CLOCK_TAIL_256 ((uint8_t)0x40) /!< 256 extra clock cycles provided to the MCU before switching to STANDBY state /
JMF	0:24d3eb812fd4	387	#define MCU_CK_CONF_CLOCK_TAIL_512 ((uint8_t)0x60) /!< 512 extra clock cycles provided to the MCU before switching to STANDBY state /
JMF	0:24d3eb812fd4	388	#define MCU_CK_CONF_XO_RATIO_1 ((uint8_t)0x00) /!< XO Clock signal available on the GPIO divided by 1 /
JMF	0:24d3eb812fd4	389	#define MCU_CK_CONF_XO_RATIO_2_3 ((uint8_t)0x02) /!< XO Clock signal available on the GPIO divided by 2/3 /
JMF	0:24d3eb812fd4	390	#define MCU_CK_CONF_XO_RATIO_1_2 ((uint8_t)0x04) /!< XO Clock signal available on the GPIO divided by 1/2 /
JMF	0:24d3eb812fd4	391	#define MCU_CK_CONF_XO_RATIO_1_3 ((uint8_t)0x06) /!< XO Clock signal available on the GPIO divided by 1/3 /
JMF	0:24d3eb812fd4	392	#define MCU_CK_CONF_XO_RATIO_1_4 ((uint8_t)0x08) /!< XO Clock signal available on the GPIO divided by 1/4 /
JMF	0:24d3eb812fd4	393	#define MCU_CK_CONF_XO_RATIO_1_6 ((uint8_t)0x0A) /!< XO Clock signal available on the GPIO divided by 1/6 /
JMF	0:24d3eb812fd4	394	#define MCU_CK_CONF_XO_RATIO_1_8 ((uint8_t)0x0C) /!< XO Clock signal available on the GPIO divided by 1/8 /
JMF	0:24d3eb812fd4	395	#define MCU_CK_CONF_XO_RATIO_1_12 ((uint8_t)0x0E) /!< XO Clock signal available on the GPIO divided by 1/12 /
JMF	0:24d3eb812fd4	396	#define MCU_CK_CONF_XO_RATIO_1_16 ((uint8_t)0x10) /!< XO Clock signal available on the GPIO divided by 1/16 /
JMF	0:24d3eb812fd4	397	#define MCU_CK_CONF_XO_RATIO_1_24 ((uint8_t)0x12) /!< XO Clock signal available on the GPIO divided by 1/24 /
JMF	0:24d3eb812fd4	398	#define MCU_CK_CONF_XO_RATIO_1_36 ((uint8_t)0x14) /!< XO Clock signal available on the GPIO divided by 1/36 /
JMF	0:24d3eb812fd4	399	#define MCU_CK_CONF_XO_RATIO_1_48 ((uint8_t)0x16) /!< XO Clock signal available on the GPIO divided by 1/48 /
JMF	0:24d3eb812fd4	400	#define MCU_CK_CONF_XO_RATIO_1_64 ((uint8_t)0x18) /!< XO Clock signal available on the GPIO divided by 1/64 /
JMF	0:24d3eb812fd4	401	#define MCU_CK_CONF_XO_RATIO_1_96 ((uint8_t)0x1A) /!< XO Clock signal available on the GPIO divided by 1/96 /
JMF	0:24d3eb812fd4	402	#define MCU_CK_CONF_XO_RATIO_1_128 ((uint8_t)0x1C) /!< XO Clock signal available on the GPIO divided by 1/128 /
JMF	0:24d3eb812fd4	403	#define MCU_CK_CONF_XO_RATIO_1_192 ((uint8_t)0x1E) /!< XO Clock signal available on the GPIO divided by 1/196 /
JMF	0:24d3eb812fd4	404	#define MCU_CK_CONF_RCO_RATIO_1 ((uint8_t)0x00) /!< RCO Clock signal available on the GPIO divided by 1 /
JMF	0:24d3eb812fd4	405	#define MCU_CK_CONF_RCO_RATIO_1_128 ((uint8_t)0x01) /!< RCO Clock signal available on the GPIO divided by 1/128/
JMF	0:24d3eb812fd4	406
JMF	0:24d3eb812fd4	407	/**
JMF	0:24d3eb812fd4	408	* @}
JMF	0:24d3eb812fd4	409	*/
JMF	0:24d3eb812fd4	410
JMF	0:24d3eb812fd4	411	/**
JMF	0:24d3eb812fd4	412	* @}
JMF	0:24d3eb812fd4	413	*/
JMF	0:24d3eb812fd4	414
JMF	0:24d3eb812fd4	415
JMF	0:24d3eb812fd4	416	/** @defgroup Radio_Configuration_Registers
JMF	0:24d3eb812fd4	417	* @{
JMF	0:24d3eb812fd4	418	*/
JMF	0:24d3eb812fd4	419
JMF	0:24d3eb812fd4	420
JMF	0:24d3eb812fd4	421
JMF	0:24d3eb812fd4	422	/** @defgroup SYNT3_Register
JMF	0:24d3eb812fd4	423	* @{
JMF	0:24d3eb812fd4	424	*/
JMF	0:24d3eb812fd4	425
JMF	0:24d3eb812fd4	426	/**
JMF	0:24d3eb812fd4	427	* \brief SYNT3 register
JMF	0:24d3eb812fd4	428	* \code
JMF	0:24d3eb812fd4	429	* Read Write
JMF	0:24d3eb812fd4	430	* Default value: 0x0C
JMF	0:24d3eb812fd4	431	*
JMF	0:24d3eb812fd4	432	* 7:5 WCP[2:0]: Set the charge pump current according to the VCO frequency in RX mode.
JMF	0:24d3eb812fd4	433	*
JMF	0:24d3eb812fd4	434	* VCO Frequency \| WCP2 \| WCP1 \| WCP0 \| Charge Pump Current (uA)
JMF	0:24d3eb812fd4	435	* ------------------------------------------------------------------------------------------------------------
JMF	0:24d3eb812fd4	436	* 4644-4678 \| 0 \| 0 \| 0 \| 378.4
JMF	0:24d3eb812fd4	437	* 4708-4772 \| 0 \| 0 \| 1 \| 368.9
JMF	0:24d3eb812fd4	438	* 4772-4836 \| 0 \| 1 \| 0 \| 359.5
JMF	0:24d3eb812fd4	439	* 4836-4902 \| 0 \| 1 \| 1 \| 350
JMF	0:24d3eb812fd4	440	* 4902-4966 \| 1 \| 0 \| 0 \| 340.5
JMF	0:24d3eb812fd4	441	* 4966-5030 \| 1 \| 0 \| 1 \| 331.1
JMF	0:24d3eb812fd4	442	* 5030-5095 \| 1 \| 1 \| 0 \| 321.6
JMF	0:24d3eb812fd4	443	* 5095-5161 \| 1 \| 1 \| 1 \| 312.2
JMF	0:24d3eb812fd4	444	* 5161-5232 \| 0 \| 0 \| 0 \| 378.4
JMF	0:24d3eb812fd4	445	* 5232-5303 \| 0 \| 0 \| 1 \| 368.9
JMF	0:24d3eb812fd4	446	* 5303-5375 \| 0 \| 1 \| 0 \| 359.5
JMF	0:24d3eb812fd4	447	* 5375-5448 \| 0 \| 1 \| 1 \| 350
JMF	0:24d3eb812fd4	448	* 5448-5519 \| 1 \| 0 \| 0 \| 340.5
JMF	0:24d3eb812fd4	449	* 5519-5592 \| 1 \| 0 \| 1 \| 331.1
JMF	0:24d3eb812fd4	450	* 5592-5663 \| 1 \| 1 \| 0 \| 321.6
JMF	0:24d3eb812fd4	451	* 5663-5736 \| 1 \| 1 \| 1 \| 312.2
JMF	0:24d3eb812fd4	452	*
JMF	0:24d3eb812fd4	453	*
JMF	0:24d3eb812fd4	454	* 4:0 SYNT[25:21]: highest 5 bits of the PLL programmable divider
JMF	0:24d3eb812fd4	455	* The valid range depends on fXO and REFDIV settings; for
JMF	0:24d3eb812fd4	456	* fXO=26MHz
JMF	0:24d3eb812fd4	457	* REFDIV = 0 - SYNT[25:21] = 11...13
JMF	0:24d3eb812fd4	458	* REFDIV = 1 - SYNT[25:21] = 2227
JMF	0:24d3eb812fd4	459	*
JMF	0:24d3eb812fd4	460	*
JMF	0:24d3eb812fd4	461	* \endcode
JMF	0:24d3eb812fd4	462	*/
JMF	0:24d3eb812fd4	463	#define SYNT3_BASE ((uint8_t)0x08) /!< [4:0] -> SYNT[25:21], highest 5 bits of the PLL programmable divider /
JMF	0:24d3eb812fd4	464
JMF	0:24d3eb812fd4	465	#define WCP_CONF_WCP_378UA ((uint8_t)0x00) /!< Charge pump current nominal value = 378uA [VCO 4644-4708]&[VCO 5161-5232] /
JMF	0:24d3eb812fd4	466	#define WCP_CONF_WCP_369UA ((uint8_t)0x01) /!< Charge pump current nominal value = 369uA [VCO 4708-4772]&[VCO 5232-5303] /
JMF	0:24d3eb812fd4	467	#define WCP_CONF_WCP_359UA ((uint8_t)0x02) /!< Charge pump current nominal value = 359uA [VCO 4772-4836]&[VCO 5303-5375] /
JMF	0:24d3eb812fd4	468	#define WCP_CONF_WCP_350UA ((uint8_t)0x03) /!< Charge pump current nominal value = 350uA [VCO 4836-4902]&[VCO 5375-5448] /
JMF	0:24d3eb812fd4	469	#define WCP_CONF_WCP_340UA ((uint8_t)0x04) /!< Charge pump current nominal value = 340uA [VCO 4902-4966]&[VCO 5448-5519] /
JMF	0:24d3eb812fd4	470	#define WCP_CONF_WCP_331UA ((uint8_t)0x05) /!< Charge pump current nominal value = 331uA [VCO 4966-5030]&[VCO 5519-5592] /
JMF	0:24d3eb812fd4	471	#define WCP_CONF_WCP_321UA ((uint8_t)0x06) /!< Charge pump current nominal value = 321uA [VCO 5030-5095]&[VCO 5592-5563] /
JMF	0:24d3eb812fd4	472	#define WCP_CONF_WCP_312UA ((uint8_t)0x07) /!< Charge pump current nominal value = 312uA [VCO 5095-5160]&[VCO 5563-5736] /
JMF	0:24d3eb812fd4	473
JMF	0:24d3eb812fd4	474
JMF	0:24d3eb812fd4	475	/**
JMF	0:24d3eb812fd4	476	* @}
JMF	0:24d3eb812fd4	477	*/
JMF	0:24d3eb812fd4	478
JMF	0:24d3eb812fd4	479
JMF	0:24d3eb812fd4	480	/** @defgroup SYNT2_Register
JMF	0:24d3eb812fd4	481	* @{
JMF	0:24d3eb812fd4	482	*/
JMF	0:24d3eb812fd4	483
JMF	0:24d3eb812fd4	484	/**
JMF	0:24d3eb812fd4	485	* \brief SYNT2 register
JMF	0:24d3eb812fd4	486	* \code
JMF	0:24d3eb812fd4	487	* Read Write
JMF	0:24d3eb812fd4	488	* Default value: 0x84
JMF	0:24d3eb812fd4	489	* 7:0 SYNT[20:13]: intermediate bits of the PLL programmable divider.
JMF	0:24d3eb812fd4	490	*
JMF	0:24d3eb812fd4	491	* \endcode
JMF	0:24d3eb812fd4	492	*/
JMF	0:24d3eb812fd4	493
JMF	0:24d3eb812fd4	494	#define SYNT2_BASE ((uint8_t)0x09) /!< SYNT[20:13], intermediate bits of the PLL programmable divider /
JMF	0:24d3eb812fd4	495
JMF	0:24d3eb812fd4	496	/**
JMF	0:24d3eb812fd4	497	* @}
JMF	0:24d3eb812fd4	498	*/
JMF	0:24d3eb812fd4	499
JMF	0:24d3eb812fd4	500	/** @defgroup SYNT1_Register
JMF	0:24d3eb812fd4	501	* @{
JMF	0:24d3eb812fd4	502	*/
JMF	0:24d3eb812fd4	503
JMF	0:24d3eb812fd4	504	/**
JMF	0:24d3eb812fd4	505	* \brief SYNT1 register
JMF	0:24d3eb812fd4	506	* \code
JMF	0:24d3eb812fd4	507	* Read Write
JMF	0:24d3eb812fd4	508	* Default value: 0xEC
JMF	0:24d3eb812fd4	509	* 7:0 SYNT[12:5]: intermediate bits of the PLL programmable divider.
JMF	0:24d3eb812fd4	510	*
JMF	0:24d3eb812fd4	511	* \endcode
JMF	0:24d3eb812fd4	512	*/
JMF	0:24d3eb812fd4	513
JMF	0:24d3eb812fd4	514	#define SYNT1_BASE ((uint8_t)0x0A) /!< SYNT[12:5], intermediate bits of the PLL programmable divider /
JMF	0:24d3eb812fd4	515
JMF	0:24d3eb812fd4	516	/**
JMF	0:24d3eb812fd4	517	* @}
JMF	0:24d3eb812fd4	518	*/
JMF	0:24d3eb812fd4	519
JMF	0:24d3eb812fd4	520	/** @defgroup SYNT0_Register
JMF	0:24d3eb812fd4	521	* @{
JMF	0:24d3eb812fd4	522	*/
JMF	0:24d3eb812fd4	523
JMF	0:24d3eb812fd4	524	/**
JMF	0:24d3eb812fd4	525	* \brief SYNT0 register
JMF	0:24d3eb812fd4	526	* \code
JMF	0:24d3eb812fd4	527	* Read Write
JMF	0:24d3eb812fd4	528	* Default value: 0x51
JMF	0:24d3eb812fd4	529	* 7:3 SYNT[4:0]: lowest bits of the PLL programmable divider.
JMF	0:24d3eb812fd4	530	* 2:0 BS[2:0]: Synthesizer band select. This parameter selects the out-of-loop divide factor of the synthesizer
JMF	0:24d3eb812fd4	531	* according to the formula fxo/(B/2)/D*SYNT/2^18
JMF	0:24d3eb812fd4	532	*
JMF	0:24d3eb812fd4	533	* BS2 \| BS1 \| BS0 \| value of B
JMF	0:24d3eb812fd4	534	* ---------------------------------------------------------------------------
JMF	0:24d3eb812fd4	535	* 0 \| 0 \| 1 \| 6
JMF	0:24d3eb812fd4	536	* 0 \| 1 \| 0 \| 8
JMF	0:24d3eb812fd4	537	* 0 \| 1 \| 1 \| 12
JMF	0:24d3eb812fd4	538	* 1 \| 0 \| 0 \| 16
JMF	0:24d3eb812fd4	539	* 1 \| 0 \| 1 \| 32
JMF	0:24d3eb812fd4	540	*
JMF	0:24d3eb812fd4	541	* \endcode
JMF	0:24d3eb812fd4	542	*/
JMF	0:24d3eb812fd4	543	#define SYNT0_BASE ((uint8_t)0x0B) /!< [7:3] -> SYNT[4:0], lowest bits of the PLL programmable divider /
JMF	0:24d3eb812fd4	544
JMF	0:24d3eb812fd4	545	#define SYNT0_BS_6 ((uint8_t)0x01) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=6 (779-956MHz) /
JMF	0:24d3eb812fd4	546	#define SYNT0_BS_8 ((uint8_t)0x02) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=8 (387-470MHz)/
JMF	0:24d3eb812fd4	547	#define SYNT0_BS_12 ((uint8_t)0x03) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=12 (387-470MHz)/
JMF	0:24d3eb812fd4	548	#define SYNT0_BS_16 ((uint8_t)0x04) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=16 (300-348MHz)/
JMF	0:24d3eb812fd4	549	#define SYNT0_BS_32 ((uint8_t)0x05) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=32 (150-174MHz)/
JMF	0:24d3eb812fd4	550
JMF	0:24d3eb812fd4	551	/**
JMF	0:24d3eb812fd4	552	* @}
JMF	0:24d3eb812fd4	553	*/
JMF	0:24d3eb812fd4	554
JMF	0:24d3eb812fd4	555	/** @defgroup CHSPACE_Register
JMF	0:24d3eb812fd4	556	* @{
JMF	0:24d3eb812fd4	557	*/
JMF	0:24d3eb812fd4	558
JMF	0:24d3eb812fd4	559	/**
JMF	0:24d3eb812fd4	560	* \brief CHSPACE register
JMF	0:24d3eb812fd4	561	* \code
JMF	0:24d3eb812fd4	562	* Read Write
JMF	0:24d3eb812fd4	563	* Default value: 0xFC
JMF	0:24d3eb812fd4	564	* 7:0 CH_SPACING[7:0]: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps
JMF	0:24d3eb812fd4	565	* (in general, frequency step is fXO/215=26MHz/215~793Hz).
JMF	0:24d3eb812fd4	566	*
JMF	0:24d3eb812fd4	567	* \endcode
JMF	0:24d3eb812fd4	568	*/
JMF	0:24d3eb812fd4	569
JMF	0:24d3eb812fd4	570	#define CHSPACE_BASE ((uint8_t)0x0C) /!< Channel spacing. From ~0.8KHz to ~200KHz in (fXO/2^15)Hz (793Hz for 26MHz XO) steps /
JMF	0:24d3eb812fd4	571
JMF	0:24d3eb812fd4	572	/**
JMF	0:24d3eb812fd4	573	* @}
JMF	0:24d3eb812fd4	574	*/
JMF	0:24d3eb812fd4	575
JMF	0:24d3eb812fd4	576
JMF	0:24d3eb812fd4	577
JMF	0:24d3eb812fd4	578	/** @defgroup IF_OFFSET_DIG_Register
JMF	0:24d3eb812fd4	579	* @{
JMF	0:24d3eb812fd4	580	*/
JMF	0:24d3eb812fd4	581
JMF	0:24d3eb812fd4	582	/**
JMF	0:24d3eb812fd4	583	* \brief IF_OFFSET_DIG register
JMF	0:24d3eb812fd4	584	* \code
JMF	0:24d3eb812fd4	585	* Read Write
JMF	0:24d3eb812fd4	586	* Default value: 0xA3
JMF	0:24d3eb812fd4	587	* 7:0 IF_OFFSET_DIG[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
JMF	0:24d3eb812fd4	588	*
JMF	0:24d3eb812fd4	589	* \endcode
JMF	0:24d3eb812fd4	590	*/
JMF	0:24d3eb812fd4	591	#define IF_OFFSET_DIG_BASE ((uint8_t)0x0D) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
JMF	0:24d3eb812fd4	592
JMF	0:24d3eb812fd4	593	/**
JMF	0:24d3eb812fd4	594	* @}
JMF	0:24d3eb812fd4	595	*/
JMF	0:24d3eb812fd4	596
JMF	0:24d3eb812fd4	597	/** @defgroup IF_OFFSET_ANA_Register
JMF	0:24d3eb812fd4	598	* @{
JMF	0:24d3eb812fd4	599	*/
JMF	0:24d3eb812fd4	600
JMF	0:24d3eb812fd4	601	/**
JMF	0:24d3eb812fd4	602	* \brief IF_OFFSET_ANA register
JMF	0:24d3eb812fd4	603	* \code
JMF	0:24d3eb812fd4	604	* Read Write
JMF	0:24d3eb812fd4	605	* Default value: 0xA3
JMF	0:24d3eb812fd4	606	* 7:0 IF_OFFSET_ANA[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
JMF	0:24d3eb812fd4	607	*
JMF	0:24d3eb812fd4	608	* \endcode
JMF	0:24d3eb812fd4	609	*/
JMF	0:24d3eb812fd4	610	#define IF_OFFSET_ANA_BASE ((uint8_t)0x07) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
JMF	0:24d3eb812fd4	611
JMF	0:24d3eb812fd4	612
JMF	0:24d3eb812fd4	613	/**
JMF	0:24d3eb812fd4	614	* @}
JMF	0:24d3eb812fd4	615	*/
JMF	0:24d3eb812fd4	616
JMF	0:24d3eb812fd4	617	/** @defgroup FC_OFFSET1_Register
JMF	0:24d3eb812fd4	618	* @{
JMF	0:24d3eb812fd4	619	*/
JMF	0:24d3eb812fd4	620
JMF	0:24d3eb812fd4	621	/**
JMF	0:24d3eb812fd4	622	* \brief FC_OFFSET1 registers
JMF	0:24d3eb812fd4	623	* \code
JMF	0:24d3eb812fd4	624	* Read Write
JMF	0:24d3eb812fd4	625	* Default value: 0xA3
JMF	0:24d3eb812fd4	626	* 7:4 Reserved.
JMF	0:24d3eb812fd4	627	* 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a 12-bit 2s complement integer
JMF	0:24d3eb812fd4	628	* representing an offset in 99Hz(2) units added/subtracted to the
JMF	0:24d3eb812fd4	629	* carrier frequency set by registers SYNT3SYNT0.
JMF	0:24d3eb812fd4	630	* This register can be used to set a fixed correction value
JMF	0:24d3eb812fd4	631	* obtained e.g. from crystal measurements.
JMF	0:24d3eb812fd4	632	*
JMF	0:24d3eb812fd4	633	* \endcode
JMF	0:24d3eb812fd4	634	*/
JMF	0:24d3eb812fd4	635	#define FC_OFFSET1_BASE ((uint8_t)0x0E) /!< [3:0] -> [11:8] Carrier offset (upper part) /
JMF	0:24d3eb812fd4	636
JMF	0:24d3eb812fd4	637	/**
JMF	0:24d3eb812fd4	638	* @}
JMF	0:24d3eb812fd4	639	*/
JMF	0:24d3eb812fd4	640
JMF	0:24d3eb812fd4	641
JMF	0:24d3eb812fd4	642	/** @defgroup FC_OFFSET0_Register
JMF	0:24d3eb812fd4	643	* @{
JMF	0:24d3eb812fd4	644	*/
JMF	0:24d3eb812fd4	645
JMF	0:24d3eb812fd4	646	/**
JMF	0:24d3eb812fd4	647	* \brief FC_OFFSET0 registers
JMF	0:24d3eb812fd4	648	* \code
JMF	0:24d3eb812fd4	649	* Default value: 0x00
JMF	0:24d3eb812fd4	650	* Read Write
JMF	0:24d3eb812fd4	651	* 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a 12-bit 2s complement integer
JMF	0:24d3eb812fd4	652	* representing an offset in 99Hz(2) units added/subtracted to the
JMF	0:24d3eb812fd4	653	* carrier frequency set by registers SYNT3SYNT0.
JMF	0:24d3eb812fd4	654	* This register can be used to set a fixed correction value
JMF	0:24d3eb812fd4	655	* obtained e.g. from crystal measurements.
JMF	0:24d3eb812fd4	656	*
JMF	0:24d3eb812fd4	657	* \endcode
JMF	0:24d3eb812fd4	658	*/
JMF	0:24d3eb812fd4	659	#define FC_OFFSET0_BASE ((uint8_t)0x0F) /*!< [7:0] -> [7:0] Carrier offset (lower part). This value is a 12-bit 2s complement integer
JMF	0:24d3eb812fd4	660	representing an offset in fXO/2^18 (99Hz for 26 MHz XO) units added/subtracted to the carrier frequency
JMF	0:24d3eb812fd4	661	set by registers SYNT3SYNT0. Range is +/-200kHz with 26 MHz XO */
JMF	0:24d3eb812fd4	662	/**
JMF	0:24d3eb812fd4	663	* @}
JMF	0:24d3eb812fd4	664	*/
JMF	0:24d3eb812fd4	665
JMF	0:24d3eb812fd4	666
JMF	0:24d3eb812fd4	667	/** @defgroup PA_LEVEL_x_Registers
JMF	0:24d3eb812fd4	668	* @{
JMF	0:24d3eb812fd4	669	*/
JMF	0:24d3eb812fd4	670
JMF	0:24d3eb812fd4	671	/**
JMF	0:24d3eb812fd4	672	* \brief PA_POWER_x[8:1] registers
JMF	0:24d3eb812fd4	673	* \code
JMF	0:24d3eb812fd4	674	* Default values from 8 to 1: [0x03, 0x0E, 0x1A, 0x25, 0x35, 0x40, 0x4E, 0x00]
JMF	0:24d3eb812fd4	675	* Read Write
JMF	0:24d3eb812fd4	676	*
JMF	0:24d3eb812fd4	677	* 7 Reserved.
JMF	0:24d3eb812fd4	678	* 6:0 PA_LEVEL_(x-1)[6:0]: Output power level for x-th slot.
JMF	0:24d3eb812fd4	679	* \endcode
JMF	0:24d3eb812fd4	680	*/
JMF	0:24d3eb812fd4	681
JMF	0:24d3eb812fd4	682	#define PA_POWER8_BASE ((uint8_t)0x10) /!< PA Power level for 8th slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	683	#define PA_POWER7_BASE ((uint8_t)0x11) /!< PA Power level for 7th slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	684	#define PA_POWER6_BASE ((uint8_t)0x12) /!< PA Power level for 6th slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	685	#define PA_POWER5_BASE ((uint8_t)0x13) /!< PA Power level for 5th slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	686	#define PA_POWER4_BASE ((uint8_t)0x14) /!< PA Power level for 4th slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	687	#define PA_POWER3_BASE ((uint8_t)0x15) /!< PA Power level for 3rd slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	688	#define PA_POWER2_BASE ((uint8_t)0x16) /!< PA Power level for 2nd slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	689	#define PA_POWER1_BASE ((uint8_t)0x17) /!< PA Power level for 1st slot of PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	690
JMF	0:24d3eb812fd4	691	/**
JMF	0:24d3eb812fd4	692	* @}
JMF	0:24d3eb812fd4	693	*/
JMF	0:24d3eb812fd4	694
JMF	0:24d3eb812fd4	695	/** @defgroup PA_POWER_CONF_Registers
JMF	0:24d3eb812fd4	696	* @{
JMF	0:24d3eb812fd4	697	*/
JMF	0:24d3eb812fd4	698
JMF	0:24d3eb812fd4	699	/**
JMF	0:24d3eb812fd4	700	* \brief PA_POWER_CONF_Registers
JMF	0:24d3eb812fd4	701	* \code
JMF	0:24d3eb812fd4	702	* Default value:0x07
JMF	0:24d3eb812fd4	703	* Read Write
JMF	0:24d3eb812fd4	704	*
JMF	0:24d3eb812fd4	705	* 7:6 CWC[1:0]: Output stage additional load capacitors bank (to be used to
JMF	0:24d3eb812fd4	706	* optimize the PA for different sub-bands).
JMF	0:24d3eb812fd4	707	*
JMF	0:24d3eb812fd4	708	* CWC1 \| CWC0 \| Total capacity in pF
JMF	0:24d3eb812fd4	709	* ---------------------------------------------------------
JMF	0:24d3eb812fd4	710	* 0 \| 0 \| 0
JMF	0:24d3eb812fd4	711	* 0 \| 1 \| 1.2
JMF	0:24d3eb812fd4	712	* 1 \| 0 \| 2.4
JMF	0:24d3eb812fd4	713	* 1 \| 1 \| 3.6
JMF	0:24d3eb812fd4	714	*
JMF	0:24d3eb812fd4	715	* 5 PA_RAMP_ENABLE:
JMF	0:24d3eb812fd4	716	* 1 - Enable the power ramping
JMF	0:24d3eb812fd4	717	* 0 - Disable the power ramping
JMF	0:24d3eb812fd4	718	* 4:3 PA_RAMP_STEP_WIDTH[1:0]: Step width in bit period
JMF	0:24d3eb812fd4	719	*
JMF	0:24d3eb812fd4	720	* PA_RAMP_STEP_WIDTH1 \| PA_RAMP_STEP_WIDTH0 \| PA ramping time step
JMF	0:24d3eb812fd4	721	* -------------------------------------------------------------------------------------------
JMF	0:24d3eb812fd4	722	* 0 \| 0 \| 1/8 Bit period
JMF	0:24d3eb812fd4	723	* 0 \| 1 \| 2/8 Bit period
JMF	0:24d3eb812fd4	724	* 1 \| 0 \| 3/8 Bit period
JMF	0:24d3eb812fd4	725	* 1 \| 1 \| 4/8 Bit period
JMF	0:24d3eb812fd4	726	*
JMF	0:24d3eb812fd4	727	* 2:0 PA_LEVEL_MAX_INDEX[2:0]: Fixes the MAX PA LEVEL in PA ramping or ASK modulation
JMF	0:24d3eb812fd4	728	*
JMF	0:24d3eb812fd4	729	* \endcode
JMF	0:24d3eb812fd4	730	*/
JMF	0:24d3eb812fd4	731	#define PA_POWER0_BASE ((uint8_t)0x18) /*!< PA ramping settings and additional load capacitor banks used
JMF	0:24d3eb812fd4	732	for PA optimization in different sub bands*/
JMF	0:24d3eb812fd4	733	#define PA_POWER0_CWC_MASK ((uint8_t)0x20) /!< Output stage additional load capacitors bank /
JMF	0:24d3eb812fd4	734	#define PA_POWER0_CWC_0 ((uint8_t)0x00) /!< No additional PA load capacitor /
JMF	0:24d3eb812fd4	735	#define PA_POWER0_CWC_1_2P ((uint8_t)0x40) /!< 1.2pF additional PA load capacitor /
JMF	0:24d3eb812fd4	736	#define PA_POWER0_CWC_2_4P ((uint8_t)0x80) /!< 2.4pF additional PA load capacitor /
JMF	0:24d3eb812fd4	737	#define PA_POWER0_CWC_3_6P ((uint8_t)0xC0) /!< 3.6pF additional PA load capacitor /
JMF	0:24d3eb812fd4	738	#define PA_POWER0_PA_RAMP_MASK ((uint8_t)0x20) /!< The PA power ramping /
JMF	0:24d3eb812fd4	739	#define PA_POWER0_PA_RAMP_STEP_WIDTH_MASK ((uint8_t)0x20) /!< The step width /
JMF	0:24d3eb812fd4	740	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_8 ((uint8_t)0x00) /!< PA ramping time step = 1/8 Bit period/
JMF	0:24d3eb812fd4	741	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_4 ((uint8_t)0x08) /!< PA ramping time step = 2/8 Bit period/
JMF	0:24d3eb812fd4	742	#define PA_POWER0_PA_RAMP_STEP_WIDTH_3TB_8 ((uint8_t)0x10) /!< PA ramping time step = 3/8 Bit period/
JMF	0:24d3eb812fd4	743	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_2 ((uint8_t)0x18) /!< PA ramping time step = 4/8 Bit period/
JMF	0:24d3eb812fd4	744	#define PA_POWER0_PA_LEVEL_MAX_INDEX ((uint8_t)0x20) /!< Final level for power ramping /
JMF	0:24d3eb812fd4	745	#define PA_POWER0_PA_LEVEL_MAX_INDEX_0 ((uint8_t)0x00) /!< /
JMF	0:24d3eb812fd4	746	#define PA_POWER0_PA_LEVEL_MAX_INDEX_1 ((uint8_t)0x01) /!< Fixes the MAX PA LEVEL in PA ramping or ASK modulation /
JMF	0:24d3eb812fd4	747	#define PA_POWER0_PA_LEVEL_MAX_INDEX_2 ((uint8_t)0x02) /!< /
JMF	0:24d3eb812fd4	748	#define PA_POWER0_PA_LEVEL_MAX_INDEX_3 ((uint8_t)0x03) /!< _________ /
JMF	0:24d3eb812fd4	749	#define PA_POWER0_PA_LEVEL_MAX_INDEX_4 ((uint8_t)0x04) /!< PA_LVL2 _\| <--\| /
JMF	0:24d3eb812fd4	750	#define PA_POWER0_PA_LEVEL_MAX_INDEX_5 ((uint8_t)0x05) /!< _\| \| /
JMF	0:24d3eb812fd4	751	#define PA_POWER0_PA_LEVEL_MAX_INDEX_6 ((uint8_t)0x06) /!< PA_LVL1 _\| \| /
JMF	0:24d3eb812fd4	752	#define PA_POWER0_PA_LEVEL_MAX_INDEX_7 ((uint8_t)0x07) /!< PA_LVL0 _\| MAX_INDEX- /
JMF	0:24d3eb812fd4	753
JMF	0:24d3eb812fd4	754
JMF	0:24d3eb812fd4	755
JMF	0:24d3eb812fd4	756	/**
JMF	0:24d3eb812fd4	757	* @}
JMF	0:24d3eb812fd4	758	*/
JMF	0:24d3eb812fd4	759
JMF	0:24d3eb812fd4	760
JMF	0:24d3eb812fd4	761	/** @defgroup MOD1_Register
JMF	0:24d3eb812fd4	762	* @{
JMF	0:24d3eb812fd4	763	*/
JMF	0:24d3eb812fd4	764
JMF	0:24d3eb812fd4	765	/**
JMF	0:24d3eb812fd4	766	* \brief MOD1 register
JMF	0:24d3eb812fd4	767	* \code
JMF	0:24d3eb812fd4	768	* Read Write
JMF	0:24d3eb812fd4	769	* Default value: 0x83
JMF	0:24d3eb812fd4	770	* 7:0 DATARATE_M[7:0]: The Mantissa of the specified data rate
JMF	0:24d3eb812fd4	771	*
JMF	0:24d3eb812fd4	772	* \endcode
JMF	0:24d3eb812fd4	773	*/
JMF	0:24d3eb812fd4	774	#define MOD1_BASE ((uint8_t)0x1A) /!< The Mantissa of the specified data rate /
JMF	0:24d3eb812fd4	775
JMF	0:24d3eb812fd4	776	/**
JMF	0:24d3eb812fd4	777	* @}
JMF	0:24d3eb812fd4	778	*/
JMF	0:24d3eb812fd4	779
JMF	0:24d3eb812fd4	780	/** @defgroup MOD0_Register
JMF	0:24d3eb812fd4	781	* @{
JMF	0:24d3eb812fd4	782	*/
JMF	0:24d3eb812fd4	783
JMF	0:24d3eb812fd4	784	/**
JMF	0:24d3eb812fd4	785	* \brief MOD0 register
JMF	0:24d3eb812fd4	786	* \code
JMF	0:24d3eb812fd4	787	* Read Write
JMF	0:24d3eb812fd4	788	* Default value: 0x1A
JMF	0:24d3eb812fd4	789	* 7 CW: 1 - CW Mode enabled - enables the generation of a continous wave carrier without any modulation
JMF	0:24d3eb812fd4	790	* 0 - CW Mode disabled
JMF	0:24d3eb812fd4	791	*
JMF	0:24d3eb812fd4	792	* 6 BT_SEL: Select BT value for GFSK
JMF	0:24d3eb812fd4	793	* 1 - BT=0.5
JMF	0:24d3eb812fd4	794	* 0 - BT=1
JMF	0:24d3eb812fd4	795	*
JMF	0:24d3eb812fd4	796	* 5:4 MOD_TYPE[1:0]: Modulation type
JMF	0:24d3eb812fd4	797	*
JMF	0:24d3eb812fd4	798	*
JMF	0:24d3eb812fd4	799	* MOD_TYPE1 \| MOD_TYPE0 \| Modulation
JMF	0:24d3eb812fd4	800	* ---------------------------------------------------------
JMF	0:24d3eb812fd4	801	* 0 \| 0 \| 2-FSK,MSK
JMF	0:24d3eb812fd4	802	* 0 \| 1 \| GFSK,GMSK
JMF	0:24d3eb812fd4	803	* 1 \| 0 \| ASK/OOK
JMF	0:24d3eb812fd4	804	*
JMF	0:24d3eb812fd4	805	* 3:0 DATARATE_E[3:0]: The Exponent of the specified data rate
JMF	0:24d3eb812fd4	806	*
JMF	0:24d3eb812fd4	807	* \endcode
JMF	0:24d3eb812fd4	808	*/
JMF	0:24d3eb812fd4	809	#define MOD0_BASE ((uint8_t)0x1B) /!< Modulation Settings, Exponent of the specified data rate, CW mode/
JMF	0:24d3eb812fd4	810
JMF	0:24d3eb812fd4	811	#define MOD0_MOD_TYPE_2_FSK ((uint8_t)0x00) /!< Modulation type 2-FSK (MSK if the frequency deviation is identical to a quarter of the data rate) /
JMF	0:24d3eb812fd4	812	#define MOD0_MOD_TYPE_GFSK ((uint8_t)0x10) /!< Modulation type GFSK (GMSK if the frequency deviation is identical to a quarter of the data rate) /
JMF	0:24d3eb812fd4	813	#define MOD0_MOD_TYPE_ASK ((uint8_t)0x20) /!< Modulation type ASK (OOK the PA is switched off for symbol "0") /
JMF	0:24d3eb812fd4	814	#define MOD0_MOD_TYPE_MSK ((uint8_t)0x00) /!< Modulation type MSK (the frequency deviation must be identical to a quarter of the data rate) /
JMF	0:24d3eb812fd4	815	#define MOD0_MOD_TYPE_GMSK ((uint8_t)0x10) /!< Modulation type GMSK (the frequency deviation must be identical to a quarter of the data rate) /
JMF	0:24d3eb812fd4	816	#define MOD0_BT_SEL_BT_MASK ((uint8_t)0x00) /!< Select the BT = 1 or BT = 0.5 valid only for GFSK or GMSK modulation/
JMF	0:24d3eb812fd4	817	#define MOD0_CW ((uint8_t)0x80) /!< Set the Continous Wave (no modulation) transmit mode /
JMF	0:24d3eb812fd4	818
JMF	0:24d3eb812fd4	819	/**
JMF	0:24d3eb812fd4	820	* @}
JMF	0:24d3eb812fd4	821	*/
JMF	0:24d3eb812fd4	822
JMF	0:24d3eb812fd4	823
JMF	0:24d3eb812fd4	824	/** @defgroup FDEV0_Register
JMF	0:24d3eb812fd4	825	* @{
JMF	0:24d3eb812fd4	826	*/
JMF	0:24d3eb812fd4	827
JMF	0:24d3eb812fd4	828	/**
JMF	0:24d3eb812fd4	829	* \brief FDEV0 register
JMF	0:24d3eb812fd4	830	* \code
JMF	0:24d3eb812fd4	831	* Read Write
JMF	0:24d3eb812fd4	832	* Default value: 0x45
JMF	0:24d3eb812fd4	833	* 7:4 FDEV_E[3:0]: Exponent of the frequency deviation (allowed values from 0 to 9)
JMF	0:24d3eb812fd4	834	*
JMF	0:24d3eb812fd4	835	* 3 CLOCK_REC_ALGO_SEL: Select PLL or DLL mode for clock recovery
JMF	0:24d3eb812fd4	836	* 1 - DLL mode
JMF	0:24d3eb812fd4	837	* 0 - PLL mode
JMF	0:24d3eb812fd4	838	*
JMF	0:24d3eb812fd4	839	* 2:0 FDEV_M[1:0]: Mantissa of the frequency deviation (allowed values from 0 to 7)
JMF	0:24d3eb812fd4	840	*
JMF	0:24d3eb812fd4	841	*
JMF	0:24d3eb812fd4	842	* \endcode
JMF	0:24d3eb812fd4	843	*/
JMF	0:24d3eb812fd4	844	#define FDEV0_BASE ((uint8_t)0x1C) /*!< Sets the Mantissa and exponent of frequency deviation (frequency separation/2)
JMF	0:24d3eb812fd4	845	and PLL or DLL alogrithm from clock recovery in RX digital demod*/
JMF	0:24d3eb812fd4	846	#define FDEV0_CLOCK_REG_ALGO_SEL_MASK ((uint8_t)0x08) /!< Can be DLL or PLL algorithm for clock recovery in RX digital demod (see CLOCKREC reg) /
JMF	0:24d3eb812fd4	847	#define FDEV0_CLOCK_REG_ALGO_SEL_PLL ((uint8_t)0x00) /!< Sets PLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
JMF	0:24d3eb812fd4	848	#define FDEV0_CLOCK_REG_ALGO_SEL_DLL ((uint8_t)0x08) /!< Sets DLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
JMF	0:24d3eb812fd4	849
JMF	0:24d3eb812fd4	850	/**
JMF	0:24d3eb812fd4	851	* @}
JMF	0:24d3eb812fd4	852	*/
JMF	0:24d3eb812fd4	853
JMF	0:24d3eb812fd4	854	/** @defgroup CHFLT_Register
JMF	0:24d3eb812fd4	855	* @{
JMF	0:24d3eb812fd4	856	*/
JMF	0:24d3eb812fd4	857
JMF	0:24d3eb812fd4	858	/**
JMF	0:24d3eb812fd4	859	* \brief CHFLT register
JMF	0:24d3eb812fd4	860	* \code
JMF	0:24d3eb812fd4	861	* Read Write
JMF	0:24d3eb812fd4	862	* Default value: 0x23
JMF	0:24d3eb812fd4	863	* 7:4 CHFLT_M[3:0]: Mantissa of the channel filter BW (allowed values from 0 to 8)
JMF	0:24d3eb812fd4	864	*
JMF	0:24d3eb812fd4	865	* 3:0 CHFLT_E[3:0]: Exponent of the channel filter BW (allowed values from 0 to 9)
JMF	0:24d3eb812fd4	866	*
JMF	0:24d3eb812fd4	867	* M\E \| 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \| 8 \| 9 \|
JMF	0:24d3eb812fd4	868	* -----+-------+-------+-------+-------+------+------+------+-----+-----+-----+
JMF	0:24d3eb812fd4	869	* 0 \| 800.1 \| 450.9 \| 224.7 \| 112.3 \| 56.1 \| 28.0 \| 14.0 \| 7.0 \| 3.5 \| 1.8 \|
JMF	0:24d3eb812fd4	870	* 1 \| 795.1 \| 425.9 \| 212.4 \| 106.2 \| 53.0 \| 26.5 \| 13.3 \| 6.6 \| 3.3 \| 1.7 \|
JMF	0:24d3eb812fd4	871	* 2 \| 768.4 \| 403.2 \| 201.1 \| 100.5 \| 50.2 \| 25.1 \| 12.6 \| 6.3 \| 3.1 \| 1.6 \|
JMF	0:24d3eb812fd4	872	* 3 \| 736.8 \| 380.8 \| 190.0 \| 95.0 \| 47.4 \| 23.7 \| 11.9 \| 5.9 \| 3.0 \| 1.5 \|
JMF	0:24d3eb812fd4	873	* 4 \| 705.1 \| 362.1 \| 180.7 \| 90.3 \| 45.1 \| 22.6 \| 11.3 \| 5.6 \| 2.8 \| 1.4 \|
JMF	0:24d3eb812fd4	874	* 5 \| 670.9 \| 341.7 \| 170.6 \| 85.3 \| 42.6 \| 21.3 \| 10.6 \| 5.3 \| 2.7 \| 1.3 \|
JMF	0:24d3eb812fd4	875	* 6 \| 642.3 \| 325.4 \| 162.4 \| 81.2 \| 40.6 \| 20.3 \| 10.1 \| 5.1 \| 2.5 \| 1.3 \|
JMF	0:24d3eb812fd4	876	* 7 \| 586.7 \| 294.5 \| 147.1 \| 73.5 \| 36.7 \| 18.4 \| 9.2 \| 4.6 \| 2.3 \| 1.2 \|
JMF	0:24d3eb812fd4	877	* 8 \| 541.4 \| 270.3 \| 135.0 \| 67.5 \| 33.7 \| 16.9 \| 8.4 \| 4.2 \| 2.1 \| 1.1 \|
JMF	0:24d3eb812fd4	878	*
JMF	0:24d3eb812fd4	879	* \endcode
JMF	0:24d3eb812fd4	880	*/
JMF	0:24d3eb812fd4	881	#define CHFLT_BASE ((uint8_t)0x1D) /!< RX Channel Filter Bandwidth /
JMF	0:24d3eb812fd4	882
JMF	0:24d3eb812fd4	883	#define CHFLT_800_1 ((uint8_t)0x00) /!< RX Channel Filter Bandwidth = 800.1 kHz /
JMF	0:24d3eb812fd4	884	#define CHFLT_795_1 ((uint8_t)0x10) /!< RX Channel Filter Bandwidth = 795.1 kHz /
JMF	0:24d3eb812fd4	885	#define CHFLT_768_4 ((uint8_t)0x20) /!< RX Channel Filter Bandwidth = 768.4 kHz /
JMF	0:24d3eb812fd4	886	#define CHFLT_736_8 ((uint8_t)0x30) /!< RX Channel Filter Bandwidth = 736.8 kHz /
JMF	0:24d3eb812fd4	887	#define CHFLT_705_1 ((uint8_t)0x40) /!< RX Channel Filter Bandwidth = 705.1 kHz /
JMF	0:24d3eb812fd4	888	#define CHFLT_670_9 ((uint8_t)0x50) /!< RX Channel Filter Bandwidth = 670.9 kHz /
JMF	0:24d3eb812fd4	889	#define CHFLT_642_3 ((uint8_t)0x60) /!< RX Channel Filter Bandwidth = 642.3 kHz /
JMF	0:24d3eb812fd4	890	#define CHFLT_586_7 ((uint8_t)0x70) /!< RX Channel Filter Bandwidth = 586.7 kHz /
JMF	0:24d3eb812fd4	891	#define CHFLT_541_4 ((uint8_t)0x80) /!< RX Channel Filter Bandwidth = 541.4 kHz /
JMF	0:24d3eb812fd4	892	#define CHFLT_450_9 ((uint8_t)0x01) /!< RX Channel Filter Bandwidth = 450.9 kHz /
JMF	0:24d3eb812fd4	893	#define CHFLT_425_9 ((uint8_t)0x11) /!< RX Channel Filter Bandwidth = 425.9 kHz /
JMF	0:24d3eb812fd4	894	#define CHFLT_403_2 ((uint8_t)0x21) /!< RX Channel Filter Bandwidth = 403.2 kHz /
JMF	0:24d3eb812fd4	895	#define CHFLT_380_8 ((uint8_t)0x31) /!< RX Channel Filter Bandwidth = 380.8 kHz /
JMF	0:24d3eb812fd4	896	#define CHFLT_362_1 ((uint8_t)0x41) /!< RX Channel Filter Bandwidth = 362.1 kHz /
JMF	0:24d3eb812fd4	897	#define CHFLT_341_7 ((uint8_t)0x51) /!< RX Channel Filter Bandwidth = 341.7 kHz /
JMF	0:24d3eb812fd4	898	#define CHFLT_325_4 ((uint8_t)0x61) /!< RX Channel Filter Bandwidth = 325.4 kHz /
JMF	0:24d3eb812fd4	899	#define CHFLT_294_5 ((uint8_t)0x71) /!< RX Channel Filter Bandwidth = 294.5 kHz /
JMF	0:24d3eb812fd4	900	#define CHFLT_270_3 ((uint8_t)0x81) /!< RX Channel Filter Bandwidth = 270.3 kHz /
JMF	0:24d3eb812fd4	901	#define CHFLT_224_7 ((uint8_t)0x02) /!< RX Channel Filter Bandwidth = 224.7 kHz /
JMF	0:24d3eb812fd4	902	#define CHFLT_212_4 ((uint8_t)0x12) /!< RX Channel Filter Bandwidth = 212.4 kHz /
JMF	0:24d3eb812fd4	903	#define CHFLT_201_1 ((uint8_t)0x22) /!< RX Channel Filter Bandwidth = 201.1 kHz /
JMF	0:24d3eb812fd4	904	#define CHFLT_190 ((uint8_t)0x32) /!< RX Channel Filter Bandwidth = 190.0 kHz /
JMF	0:24d3eb812fd4	905	#define CHFLT_180_7 ((uint8_t)0x42) /!< RX Channel Filter Bandwidth = 180.7 kHz /
JMF	0:24d3eb812fd4	906	#define CHFLT_170_6 ((uint8_t)0x52) /!< RX Channel Filter Bandwidth = 170.6 kHz /
JMF	0:24d3eb812fd4	907	#define CHFLT_162_4 ((uint8_t)0x62) /!< RX Channel Filter Bandwidth = 162.4 kHz /
JMF	0:24d3eb812fd4	908	#define CHFLT_147_1 ((uint8_t)0x72) /!< RX Channel Filter Bandwidth = 147.1 kHz /
JMF	0:24d3eb812fd4	909	#define CHFLT_135 ((uint8_t)0x82) /!< RX Channel Filter Bandwidth = 135.0 kHz /
JMF	0:24d3eb812fd4	910	#define CHFLT_112_3 ((uint8_t)0x03) /!< RX Channel Filter Bandwidth = 112.3 kHz /
JMF	0:24d3eb812fd4	911	#define CHFLT_106_2 ((uint8_t)0x13) /!< RX Channel Filter Bandwidth = 106.2 kHz /
JMF	0:24d3eb812fd4	912	#define CHFLT_100_5 ((uint8_t)0x23) /!< RX Channel Filter Bandwidth = 100.5 kHz /
JMF	0:24d3eb812fd4	913	#define CHFLT_95 ((uint8_t)0x33) /!< RX Channel Filter Bandwidth = 95.0 kHz /
JMF	0:24d3eb812fd4	914	#define CHFLT_90_3 ((uint8_t)0x43) /!< RX Channel Filter Bandwidth = 90.3 kHz /
JMF	0:24d3eb812fd4	915	#define CHFLT_85_3 ((uint8_t)0x53) /!< RX Channel Filter Bandwidth = 85.3 kHz /
JMF	0:24d3eb812fd4	916	#define CHFLT_81_2 ((uint8_t)0x63) /!< RX Channel Filter Bandwidth = 81.2 kHz /
JMF	0:24d3eb812fd4	917	#define CHFLT_73_5 ((uint8_t)0x73) /!< RX Channel Filter Bandwidth = 73.5 kHz /
JMF	0:24d3eb812fd4	918	#define CHFLT_67_5 ((uint8_t)0x83) /!< RX Channel Filter Bandwidth = 67.5 kHz /
JMF	0:24d3eb812fd4	919	#define CHFLT_56_1 ((uint8_t)0x04) /!< RX Channel Filter Bandwidth = 56.1 kHz /
JMF	0:24d3eb812fd4	920	#define CHFLT_53 ((uint8_t)0x14) /!< RX Channel Filter Bandwidth = 53.0 kHz /
JMF	0:24d3eb812fd4	921	#define CHFLT_50_2 ((uint8_t)0x24) /!< RX Channel Filter Bandwidth = 50.2 kHz /
JMF	0:24d3eb812fd4	922	#define CHFLT_47_4 ((uint8_t)0x34) /!< RX Channel Filter Bandwidth = 47.4 kHz /
JMF	0:24d3eb812fd4	923	#define CHFLT_45_1 ((uint8_t)0x44) /!< RX Channel Filter Bandwidth = 45.1 kHz /
JMF	0:24d3eb812fd4	924	#define CHFLT_42_6 ((uint8_t)0x54) /!< RX Channel Filter Bandwidth = 42.6 kHz /
JMF	0:24d3eb812fd4	925	#define CHFLT_40_6 ((uint8_t)0x64) /!< RX Channel Filter Bandwidth = 40.6 kHz /
JMF	0:24d3eb812fd4	926	#define CHFLT_36_7 ((uint8_t)0x74) /!< RX Channel Filter Bandwidth = 36.7 kHz /
JMF	0:24d3eb812fd4	927	#define CHFLT_33_7 ((uint8_t)0x84) /!< RX Channel Filter Bandwidth = 33.7 kHz /
JMF	0:24d3eb812fd4	928	#define CHFLT_28 ((uint8_t)0x05) /!< RX Channel Filter Bandwidth = 28.0 kHz /
JMF	0:24d3eb812fd4	929	#define CHFLT_26_5 ((uint8_t)0x15) /!< RX Channel Filter Bandwidth = 26.5 kHz /
JMF	0:24d3eb812fd4	930	#define CHFLT_25_1 ((uint8_t)0x25) /!< RX Channel Filter Bandwidth = 25.1 kHz /
JMF	0:24d3eb812fd4	931	#define CHFLT_23_7 ((uint8_t)0x35) /!< RX Channel Filter Bandwidth = 23.7 kHz /
JMF	0:24d3eb812fd4	932	#define CHFLT_22_6 ((uint8_t)0x45) /!< RX Channel Filter Bandwidth = 22.6 kHz /
JMF	0:24d3eb812fd4	933	#define CHFLT_21_3 ((uint8_t)0x55) /!< RX Channel Filter Bandwidth = 21.3 kHz /
JMF	0:24d3eb812fd4	934	#define CHFLT_20_3 ((uint8_t)0x65) /!< RX Channel Filter Bandwidth = 20.3 kHz /
JMF	0:24d3eb812fd4	935	#define CHFLT_18_4 ((uint8_t)0x75) /!< RX Channel Filter Bandwidth = 18.4 kHz /
JMF	0:24d3eb812fd4	936	#define CHFLT_16_9 ((uint8_t)0x85) /!< RX Channel Filter Bandwidth = 16.9 kHz /
JMF	0:24d3eb812fd4	937	#define CHFLT_14 ((uint8_t)0x06) /!< RX Channel Filter Bandwidth = 14.0 kHz /
JMF	0:24d3eb812fd4	938	#define CHFLT_13_3 ((uint8_t)0x16) /!< RX Channel Filter Bandwidth = 13.3 kHz /
JMF	0:24d3eb812fd4	939	#define CHFLT_12_6 ((uint8_t)0x26) /!< RX Channel Filter Bandwidth = 12.6 kHz /
JMF	0:24d3eb812fd4	940	#define CHFLT_11_9 ((uint8_t)0x36) /!< RX Channel Filter Bandwidth = 11.9 kHz /
JMF	0:24d3eb812fd4	941	#define CHFLT_11_3 ((uint8_t)0x46) /!< RX Channel Filter Bandwidth = 11.3 kHz /
JMF	0:24d3eb812fd4	942	#define CHFLT_10_6 ((uint8_t)0x56) /!< RX Channel Filter Bandwidth = 10.6 kHz /
JMF	0:24d3eb812fd4	943	#define CHFLT_10_1 ((uint8_t)0x66) /!< RX Channel Filter Bandwidth = 10.1 kHz /
JMF	0:24d3eb812fd4	944	#define CHFLT_9_2 ((uint8_t)0x76) /!< RX Channel Filter Bandwidth = 9.2 kHz /
JMF	0:24d3eb812fd4	945	#define CHFLT_8_4 ((uint8_t)0x86) /!< RX Channel Filter Bandwidth = 8.4 kHz /
JMF	0:24d3eb812fd4	946	#define CHFLT_7 ((uint8_t)0x07) /!< RX Channel Filter Bandwidth = 7.0 kHz /
JMF	0:24d3eb812fd4	947	#define CHFLT_6_6 ((uint8_t)0x17) /!< RX Channel Filter Bandwidth = 6.6 kHz /
JMF	0:24d3eb812fd4	948	#define CHFLT_6_3 ((uint8_t)0x27) /!< RX Channel Filter Bandwidth = 6.3 kHz /
JMF	0:24d3eb812fd4	949	#define CHFLT_5_9 ((uint8_t)0x37) /!< RX Channel Filter Bandwidth = 5.9 kHz /
JMF	0:24d3eb812fd4	950	#define CHFLT_5_6 ((uint8_t)0x47) /!< RX Channel Filter Bandwidth = 5.6 kHz /
JMF	0:24d3eb812fd4	951	#define CHFLT_5_3 ((uint8_t)0x57) /!< RX Channel Filter Bandwidth = 5.3 kHz /
JMF	0:24d3eb812fd4	952	#define CHFLT_5_1 ((uint8_t)0x67) /!< RX Channel Filter Bandwidth = 5.1 kHz /
JMF	0:24d3eb812fd4	953	#define CHFLT_4_6 ((uint8_t)0x77) /!< RX Channel Filter Bandwidth = 4.6 kHz /
JMF	0:24d3eb812fd4	954	#define CHFLT_4_2 ((uint8_t)0x87) /!< RX Channel Filter Bandwidth = 4.2 kHz /
JMF	0:24d3eb812fd4	955	#define CHFLT_3_5 ((uint8_t)0x08) /!< RX Channel Filter Bandwidth = 3.5 kHz /
JMF	0:24d3eb812fd4	956	#define CHFLT_3_3 ((uint8_t)0x18) /!< RX Channel Filter Bandwidth = 3.3 kHz /
JMF	0:24d3eb812fd4	957	#define CHFLT_3_1 ((uint8_t)0x28) /!< RX Channel Filter Bandwidth = 3.1 kHz /
JMF	0:24d3eb812fd4	958	#define CHFLT_3 ((uint8_t)0x38) /!< RX Channel Filter Bandwidth = 3.0 kHz /
JMF	0:24d3eb812fd4	959	#define CHFLT_2_8 ((uint8_t)0x48) /!< RX Channel Filter Bandwidth = 2.8 kHz /
JMF	0:24d3eb812fd4	960	#define CHFLT_2_7 ((uint8_t)0x58) /!< RX Channel Filter Bandwidth = 2.7 kHz /
JMF	0:24d3eb812fd4	961	#define CHFLT_2_5 ((uint8_t)0x68) /!< RX Channel Filter Bandwidth = 2.5 kHz /
JMF	0:24d3eb812fd4	962	#define CHFLT_2_3 ((uint8_t)0x78) /!< RX Channel Filter Bandwidth = 2.3 kHz /
JMF	0:24d3eb812fd4	963	#define CHFLT_2_1 ((uint8_t)0x88) /!< RX Channel Filter Bandwidth = 2.1 kHz /
JMF	0:24d3eb812fd4	964	#define CHFLT_1_8 ((uint8_t)0x09) /!< RX Channel Filter Bandwidth = 1.8 kHz /
JMF	0:24d3eb812fd4	965	#define CHFLT_1_7 ((uint8_t)0x19) /!< RX Channel Filter Bandwidth = 1.7 kHz /
JMF	0:24d3eb812fd4	966	#define CHFLT_1_6 ((uint8_t)0x29) /!< RX Channel Filter Bandwidth = 1.6 kHz /
JMF	0:24d3eb812fd4	967	#define CHFLT_1_5 ((uint8_t)0x39) /!< RX Channel Filter Bandwidth = 1.5 kHz /
JMF	0:24d3eb812fd4	968	#define CHFLT_1_4 ((uint8_t)0x49) /!< RX Channel Filter Bandwidth = 1.4 kHz /
JMF	0:24d3eb812fd4	969	#define CHFLT_1_3a ((uint8_t)0x59) /!< RX Channel Filter Bandwidth = 1.3 kHz /
JMF	0:24d3eb812fd4	970	#define CHFLT_1_3 ((uint8_t)0x69) /!< RX Channel Filter Bandwidth = 1.3 kHz /
JMF	0:24d3eb812fd4	971	#define CHFLT_1_2 ((uint8_t)0x79) /!< RX Channel Filter Bandwidth = 1.2 kHz /
JMF	0:24d3eb812fd4	972	#define CHFLT_1_1 ((uint8_t)0x89) /!< RX Channel Filter Bandwidth = 1.1 kHz /
JMF	0:24d3eb812fd4	973
JMF	0:24d3eb812fd4	974	/**
JMF	0:24d3eb812fd4	975	* @}
JMF	0:24d3eb812fd4	976	*/
JMF	0:24d3eb812fd4	977
JMF	0:24d3eb812fd4	978	/** @defgroup AFC2_Register
JMF	0:24d3eb812fd4	979	* @{
JMF	0:24d3eb812fd4	980	*/
JMF	0:24d3eb812fd4	981
JMF	0:24d3eb812fd4	982	/**
JMF	0:24d3eb812fd4	983	* \brief AFC2 register
JMF	0:24d3eb812fd4	984	* \code
JMF	0:24d3eb812fd4	985	* Read Write
JMF	0:24d3eb812fd4	986	* Default value: 0x48
JMF	0:24d3eb812fd4	987	* 7 AFC Freeze on Sync: Freeze AFC correction upon sync word detection.
JMF	0:24d3eb812fd4	988	* 1 - AFC Freeze enabled
JMF	0:24d3eb812fd4	989	* 0 - AFC Freeze disabled
JMF	0:24d3eb812fd4	990	*
JMF	0:24d3eb812fd4	991	* 6 AFC Enabled: Enable AFC
JMF	0:24d3eb812fd4	992	* 1 - AFC enabled
JMF	0:24d3eb812fd4	993	* 0 - AFC disabled
JMF	0:24d3eb812fd4	994	*
JMF	0:24d3eb812fd4	995	* 5 AFC Mode: Select AFC mode
JMF	0:24d3eb812fd4	996	* 1 - AFC Loop closed on 2nd conversion stage.
JMF	0:24d3eb812fd4	997	* 0 - AFC Loop closed on slicer
JMF	0:24d3eb812fd4	998	*
JMF	0:24d3eb812fd4	999	* 4:0 AFC PD leakage[4:0]: Peak detector leakage. This parameter sets the decay speed of the min/max frequency peak detector (AFC2 register),
JMF	0:24d3eb812fd4	1000	* the range allowed is 0..31 (0 - no leakage, 31 - high leakage). The recommended value for this parameter is 4.
JMF	0:24d3eb812fd4	1001	*
JMF	0:24d3eb812fd4	1002	* \endcode
JMF	0:24d3eb812fd4	1003	*/
JMF	0:24d3eb812fd4	1004	#define AFC2_BASE ((uint8_t)0x1E) /!< Automatic frequency compensation algorithm parameters (FSK/GFSK/MSK)/
JMF	0:24d3eb812fd4	1005
JMF	0:24d3eb812fd4	1006	#define AFC2_AFC_FREEZE_ON_SYNC_MASK ((uint8_t)0x80) /!< The frequency correction value is frozen when SYNC word is detected /
JMF	0:24d3eb812fd4	1007	#define AFC2_AFC_MASK ((uint8_t)0x40) /!< Mask of Automatic Frequency Correction /
JMF	0:24d3eb812fd4	1008	#define AFC2_AFC_MODE_MASK ((uint8_t)0x20) /!< Automatic Frequency Correction can be in Main MODE or Auxiliary MODE/
JMF	0:24d3eb812fd4	1009	#define AFC2_AFC_MODE_SLICER ((uint8_t)0x00) /!< Automatic Frequency Correction Main MODE /
JMF	0:24d3eb812fd4	1010	#define AFC2_AFC_MODE_MIXER ((uint8_t)0x20) /!< Automatic Frequency Correction Auxiliary MODE /
JMF	0:24d3eb812fd4	1011
JMF	0:24d3eb812fd4	1012	/**
JMF	0:24d3eb812fd4	1013	* @}
JMF	0:24d3eb812fd4	1014	*/
JMF	0:24d3eb812fd4	1015
JMF	0:24d3eb812fd4	1016	/** @defgroup AFC1_Register
JMF	0:24d3eb812fd4	1017	* @{
JMF	0:24d3eb812fd4	1018	*/
JMF	0:24d3eb812fd4	1019
JMF	0:24d3eb812fd4	1020	/**
JMF	0:24d3eb812fd4	1021	* \brief AFC1 register
JMF	0:24d3eb812fd4	1022	* \code
JMF	0:24d3eb812fd4	1023	* Read Write
JMF	0:24d3eb812fd4	1024	* Default value: 0x18
JMF	0:24d3eb812fd4	1025	* 7:0 AFC_FAST_PERIOD: Length of the AFC fast period. this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed
JMF	0:24d3eb812fd4	1026	* is 0..255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the
JMF	0:24d3eb812fd4	1027	* algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble
JMF	0:24d3eb812fd4	1028	* symbols.
JMF	0:24d3eb812fd4	1029	*
JMF	0:24d3eb812fd4	1030	* \endcode
JMF	0:24d3eb812fd4	1031	*/
JMF	0:24d3eb812fd4	1032	#define AFC1_BASE ((uint8_t)0x1F) /!< Length of the AFC fast period /
JMF	0:24d3eb812fd4	1033
JMF	0:24d3eb812fd4	1034	/**
JMF	0:24d3eb812fd4	1035	* @}
JMF	0:24d3eb812fd4	1036	*/
JMF	0:24d3eb812fd4	1037
JMF	0:24d3eb812fd4	1038	/** @defgroup AFC0_Register
JMF	0:24d3eb812fd4	1039	* @{
JMF	0:24d3eb812fd4	1040	*/
JMF	0:24d3eb812fd4	1041
JMF	0:24d3eb812fd4	1042	/**
JMF	0:24d3eb812fd4	1043	* \brief AFC0 register
JMF	0:24d3eb812fd4	1044	* \code
JMF	0:24d3eb812fd4	1045	* Read Write
JMF	0:24d3eb812fd4	1046	* Default value: 0x25
JMF	0:24d3eb812fd4	1047	* 7:4 AFC_FAST_GAIN_LOG2[3:0]: AFC loop gain in fast mode (2's log)
JMF	0:24d3eb812fd4	1048	*
JMF	0:24d3eb812fd4	1049	* 3:0 AFC_SLOW_GAIN_LOG2[3:0]: AFC loop gain in slow mode (2's log)
JMF	0:24d3eb812fd4	1050	*
JMF	0:24d3eb812fd4	1051	* \endcode
JMF	0:24d3eb812fd4	1052	*/
JMF	0:24d3eb812fd4	1053	#define AFC0_BASE ((uint8_t)0x20) /!< AFC loop gain in fast and slow modes (2's log) /
JMF	0:24d3eb812fd4	1054
JMF	0:24d3eb812fd4	1055	/**
JMF	0:24d3eb812fd4	1056	* @}
JMF	0:24d3eb812fd4	1057	*/
JMF	0:24d3eb812fd4	1058
JMF	0:24d3eb812fd4	1059	/** @defgroup CLOCKREC_Register
JMF	0:24d3eb812fd4	1060	* @{
JMF	0:24d3eb812fd4	1061	*/
JMF	0:24d3eb812fd4	1062
JMF	0:24d3eb812fd4	1063	/**
JMF	0:24d3eb812fd4	1064	* \brief CLOCKREC register
JMF	0:24d3eb812fd4	1065	* \code
JMF	0:24d3eb812fd4	1066	* Read Write
JMF	0:24d3eb812fd4	1067	* Default value: 0x58
JMF	0:24d3eb812fd4	1068	*
JMF	0:24d3eb812fd4	1069	* 7:5 CLK_REC_P_GAIN [2:0]: Clock recovery loop gain (log2)
JMF	0:24d3eb812fd4	1070	*
JMF	0:24d3eb812fd4	1071	* 4 PSTFLT_LEN: Set Postfilter length
JMF	0:24d3eb812fd4	1072	* 1 - 16 symbols
JMF	0:24d3eb812fd4	1073	* 0 - 8 symbols
JMF	0:24d3eb812fd4	1074	*
JMF	0:24d3eb812fd4	1075	* 3:0 CLK_REC_I_GAIN[3:0]: Integral gain for the clock recovery loop
JMF	0:24d3eb812fd4	1076	* \endcode
JMF	0:24d3eb812fd4	1077	*/
JMF	0:24d3eb812fd4	1078
JMF	0:24d3eb812fd4	1079	#define CLOCKREC_BASE ((uint8_t)0x23) /!< Gain of clock recovery loop - Postfilter length 0-8 symbols, 1-16 symbols /
JMF	0:24d3eb812fd4	1080
JMF	0:24d3eb812fd4	1081	/**
JMF	0:24d3eb812fd4	1082	* @}
JMF	0:24d3eb812fd4	1083	*/
JMF	0:24d3eb812fd4	1084
JMF	0:24d3eb812fd4	1085	/** @defgroup AGCCTRL2_Register
JMF	0:24d3eb812fd4	1086	* @{
JMF	0:24d3eb812fd4	1087	*/
JMF	0:24d3eb812fd4	1088
JMF	0:24d3eb812fd4	1089	/**
JMF	0:24d3eb812fd4	1090	* \brief AGCCTRL2 register
JMF	0:24d3eb812fd4	1091	* \code
JMF	0:24d3eb812fd4	1092	* Read Write
JMF	0:24d3eb812fd4	1093	* Default value: 0x22
JMF	0:24d3eb812fd4	1094	*
JMF	0:24d3eb812fd4	1095	* 7 Reserved
JMF	0:24d3eb812fd4	1096	*
JMF	0:24d3eb812fd4	1097	* 6 FREEZE_ON_STEADY: Enable freezing on steady state
JMF	0:24d3eb812fd4	1098	* 1 - Enable
JMF	0:24d3eb812fd4	1099	* 0 - Disable
JMF	0:24d3eb812fd4	1100	*
JMF	0:24d3eb812fd4	1101	* 5 FREEZE_ON_SYNC: Enable freezing on sync detection
JMF	0:24d3eb812fd4	1102	* 1 - Enable
JMF	0:24d3eb812fd4	1103	* 0 - Disable
JMF	0:24d3eb812fd4	1104	*
JMF	0:24d3eb812fd4	1105	* 4 START_MAX_ATTENUATION: Start with max attenuation
JMF	0:24d3eb812fd4	1106	* 1 - Enable
JMF	0:24d3eb812fd4	1107	* 0 - Disable
JMF	0:24d3eb812fd4	1108	*
JMF	0:24d3eb812fd4	1109	* 3:0 MEAS_TIME[3:0]: Measure time during which the signal peak is detected (according to the formula 12/fxo*2^MEAS_TIME)
JMF	0:24d3eb812fd4	1110	* \endcode
JMF	0:24d3eb812fd4	1111	*/
JMF	0:24d3eb812fd4	1112	#define AGCCTRL2_BASE ((uint8_t)0x24) /!< AGC freeze strategy, AGC attenuation strategy, AGC measure time /
JMF	0:24d3eb812fd4	1113
JMF	0:24d3eb812fd4	1114	#define AGCCTRL2_FREEZE_ON_STEADY_MASK ((uint8_t)0x40) /*!< The attenuation settings will be frozen as soon as signal level
JMF	0:24d3eb812fd4	1115	is betweeen min and max treshold (see AGCCTRL1) */
JMF	0:24d3eb812fd4	1116	#define AGCCTRL2_FREEZE_ON_SYNC_MASK ((uint8_t)0x20) /!< The attenuation settings will be frozen as soon sync word is detected /
JMF	0:24d3eb812fd4	1117	#define AGCCTRL2_START_MAX_ATTENUATION_MASK ((uint8_t)0x10) /!< The AGC algorithm can start with MAX attenuation or MIN attenuation /
JMF	0:24d3eb812fd4	1118
JMF	0:24d3eb812fd4	1119	/**
JMF	0:24d3eb812fd4	1120	* @}
JMF	0:24d3eb812fd4	1121	*/
JMF	0:24d3eb812fd4	1122
JMF	0:24d3eb812fd4	1123	/** @defgroup AGCCTRL1_Register
JMF	0:24d3eb812fd4	1124	* @{
JMF	0:24d3eb812fd4	1125	*/
JMF	0:24d3eb812fd4	1126
JMF	0:24d3eb812fd4	1127	/**
JMF	0:24d3eb812fd4	1128	* \brief AGCCTRL1 register
JMF	0:24d3eb812fd4	1129	* \code
JMF	0:24d3eb812fd4	1130	* Read Write
JMF	0:24d3eb812fd4	1131	* Default value: 0x65
JMF	0:24d3eb812fd4	1132	*
JMF	0:24d3eb812fd4	1133	* 7:4 THRESHOLD_HIGH[3:0]: High threshold for the AGC
JMF	0:24d3eb812fd4	1134	*
JMF	0:24d3eb812fd4	1135	* 3:0 THRESHOLD_LOW[3:0]: Low threshold for the AGC
JMF	0:24d3eb812fd4	1136	* \endcode
JMF	0:24d3eb812fd4	1137	*/
JMF	0:24d3eb812fd4	1138	#define AGCCTRL1_BASE ((uint8_t)0x25) /!< Sets low and high threshold for AGC /
JMF	0:24d3eb812fd4	1139
JMF	0:24d3eb812fd4	1140	/**
JMF	0:24d3eb812fd4	1141	* @}
JMF	0:24d3eb812fd4	1142	*/
JMF	0:24d3eb812fd4	1143
JMF	0:24d3eb812fd4	1144	/** @defgroup AGCCTRL0_Register
JMF	0:24d3eb812fd4	1145	* @{
JMF	0:24d3eb812fd4	1146	*/
JMF	0:24d3eb812fd4	1147
JMF	0:24d3eb812fd4	1148	/**
JMF	0:24d3eb812fd4	1149	* \brief AGCCTRL0 register
JMF	0:24d3eb812fd4	1150	* \code
JMF	0:24d3eb812fd4	1151	* Read Write
JMF	0:24d3eb812fd4	1152	* Default value: 0x8A
JMF	0:24d3eb812fd4	1153	*
JMF	0:24d3eb812fd4	1154	* 7 AGC S_ENABLE: Enable AGC
JMF	0:24d3eb812fd4	1155	* 1 - Enable
JMF	0:24d3eb812fd4	1156	* 0 - Disable
JMF	0:24d3eb812fd4	1157	*
JMF	0:24d3eb812fd4	1158	* 6 AGC_MODE: Set linear-Binary AGC mode
JMF	0:24d3eb812fd4	1159	* 1 - Enable
JMF	0:24d3eb812fd4	1160	* 0 - Disable
JMF	0:24d3eb812fd4	1161	*
JMF	0:24d3eb812fd4	1162	* 5:0 HOLD_TIME[5:0]: Hold time after gain adjustment according to formula 12/fxo*HOLD_TIME
JMF	0:24d3eb812fd4	1163	* \endcode
JMF	0:24d3eb812fd4	1164	*/
JMF	0:24d3eb812fd4	1165	#define AGCCTRL0_BASE ((uint8_t)0x26) /*!< Enables AGC, set AGC algo between linear/binary mode, set hold time
JMF	0:24d3eb812fd4	1166	to account signal propagation through RX chain */
JMF	0:24d3eb812fd4	1167	#define AGCCTRL0_AGC_MASK ((uint8_t)0x80) /!< AGC on/off /
JMF	0:24d3eb812fd4	1168	#define AGCCTRL0_AGC_MODE_MASK ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode or sequential mode /
JMF	0:24d3eb812fd4	1169	#define AGCCTRL0_AGC_MODE_LINEAR ((uint8_t)0x00) /!< AGC search correct attenuation in sequential mode (recommended) /
JMF	0:24d3eb812fd4	1170	#define AGCCTRL0_AGC_MODE_BINARY ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode /
JMF	0:24d3eb812fd4	1171
JMF	0:24d3eb812fd4	1172	/**
JMF	0:24d3eb812fd4	1173	* @}
JMF	0:24d3eb812fd4	1174	*/
JMF	0:24d3eb812fd4	1175
JMF	0:24d3eb812fd4	1176	/** @defgroup CHNUM_Register
JMF	0:24d3eb812fd4	1177	* @{
JMF	0:24d3eb812fd4	1178	*/
JMF	0:24d3eb812fd4	1179
JMF	0:24d3eb812fd4	1180	/**
JMF	0:24d3eb812fd4	1181	* \brief CHNUM registers
JMF	0:24d3eb812fd4	1182	* \code
JMF	0:24d3eb812fd4	1183	* Default value: 0x00
JMF	0:24d3eb812fd4	1184	* Read Write
JMF	0:24d3eb812fd4	1185	* 7:0 CH_NUM[7:0]: Channel number. This value is multiplied by the channel spacing and added to the
JMF	0:24d3eb812fd4	1186	* synthesizer base frequency to generate the actual RF carrier frequency.
JMF	0:24d3eb812fd4	1187	* \endcode
JMF	0:24d3eb812fd4	1188	*/
JMF	0:24d3eb812fd4	1189	#define CHNUM_BASE ((uint8_t)0x6C) /*!< Channel number. This value is multiplied by the channel
JMF	0:24d3eb812fd4	1190	spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency */
JMF	0:24d3eb812fd4	1191	/**
JMF	0:24d3eb812fd4	1192	* @}
JMF	0:24d3eb812fd4	1193	*/
JMF	0:24d3eb812fd4	1194
JMF	0:24d3eb812fd4	1195	/** @defgroup AFC_CORR_Register
JMF	0:24d3eb812fd4	1196	* @{
JMF	0:24d3eb812fd4	1197	*/
JMF	0:24d3eb812fd4	1198
JMF	0:24d3eb812fd4	1199	/**
JMF	0:24d3eb812fd4	1200	* \brief AFC_CORR registers
JMF	0:24d3eb812fd4	1201	* \code
JMF	0:24d3eb812fd4	1202	* Default value: 0x00
JMF	0:24d3eb812fd4	1203	* Read
JMF	0:24d3eb812fd4	1204	*
JMF	0:24d3eb812fd4	1205	* 7:0 AFC_CORR[7:0]: AFC word of the received packet
JMF	0:24d3eb812fd4	1206	* \endcode
JMF	0:24d3eb812fd4	1207	*/
JMF	0:24d3eb812fd4	1208	#define AFC_CORR_BASE ((uint8_t)(0xC4)) /!< AFC word of the received packet /
JMF	0:24d3eb812fd4	1209
JMF	0:24d3eb812fd4	1210	/**
JMF	0:24d3eb812fd4	1211	* @}
JMF	0:24d3eb812fd4	1212	*/
JMF	0:24d3eb812fd4	1213
JMF	0:24d3eb812fd4	1214	/**
JMF	0:24d3eb812fd4	1215	* @}
JMF	0:24d3eb812fd4	1216	*/
JMF	0:24d3eb812fd4	1217
JMF	0:24d3eb812fd4	1218
JMF	0:24d3eb812fd4	1219	/** @defgroup Packet_Configuration_Registers
JMF	0:24d3eb812fd4	1220	* @{
JMF	0:24d3eb812fd4	1221	*/
JMF	0:24d3eb812fd4	1222
JMF	0:24d3eb812fd4	1223	/** @defgroup PCKTCTRL4_Register
JMF	0:24d3eb812fd4	1224	* @{
JMF	0:24d3eb812fd4	1225	*/
JMF	0:24d3eb812fd4	1226
JMF	0:24d3eb812fd4	1227	/**
JMF	0:24d3eb812fd4	1228	* \brief PCKTCTRL4 register
JMF	0:24d3eb812fd4	1229	* \code
JMF	0:24d3eb812fd4	1230	* Read Write
JMF	0:24d3eb812fd4	1231	* Default value: 0x00
JMF	0:24d3eb812fd4	1232	*
JMF	0:24d3eb812fd4	1233	* 7:5 NOT_USED.
JMF	0:24d3eb812fd4	1234	*
JMF	0:24d3eb812fd4	1235	* 4:3 ADDRESS_LEN[1:0]: length of address field in bytes
JMF	0:24d3eb812fd4	1236	*
JMF	0:24d3eb812fd4	1237	* 2:0 control_len[2:0]: length of control field in bytes
JMF	0:24d3eb812fd4	1238	* \endcode
JMF	0:24d3eb812fd4	1239	*/
JMF	0:24d3eb812fd4	1240	#define PCKTCTRL4_BASE ((uint8_t)0x30) /!< lenghts of address and control field /
JMF	0:24d3eb812fd4	1241
JMF	0:24d3eb812fd4	1242	#define PCKTCTRL4_ADDRESS_LEN_MASK ((uint8_t)0x18)
JMF	0:24d3eb812fd4	1243	#define PCKTCTRL4_CONTROL_LEN_MASK ((uint8_t)0x07)
JMF	0:24d3eb812fd4	1244
JMF	0:24d3eb812fd4	1245	/**
JMF	0:24d3eb812fd4	1246	* @}
JMF	0:24d3eb812fd4	1247	*/
JMF	0:24d3eb812fd4	1248
JMF	0:24d3eb812fd4	1249	/** @defgroup PCKTCTRL3_Register
JMF	0:24d3eb812fd4	1250	* @{
JMF	0:24d3eb812fd4	1251	*/
JMF	0:24d3eb812fd4	1252
JMF	0:24d3eb812fd4	1253	/**
JMF	0:24d3eb812fd4	1254	* \brief PCKTCTRL3 register
JMF	0:24d3eb812fd4	1255	* \code
JMF	0:24d3eb812fd4	1256	* Read Write
JMF	0:24d3eb812fd4	1257	* Default value: 0x07
JMF	0:24d3eb812fd4	1258	*
JMF	0:24d3eb812fd4	1259	* 7:6 PCKT_FRMT[1:0]: format of packet
JMF	0:24d3eb812fd4	1260	*
JMF	0:24d3eb812fd4	1261	* PCKT_FRMT1 \| PCKT_FRMT0 \| Format
JMF	0:24d3eb812fd4	1262	* ----------------------------------------------------------------------
JMF	0:24d3eb812fd4	1263	* 0 \| 0 \| BASIC
JMF	0:24d3eb812fd4	1264	* 1 \| 0 \| MBUS
JMF	0:24d3eb812fd4	1265	* 1 \| 1 \| STACK
JMF	0:24d3eb812fd4	1266	*
JMF	0:24d3eb812fd4	1267	* 5:4 RX_MODE[1:0]: length of address 0x30 field in bytes
JMF	0:24d3eb812fd4	1268	*
JMF	0:24d3eb812fd4	1269	* RX_MODE1 \| RX_MODE0 \| Rx Mode
JMF	0:24d3eb812fd4	1270	* --------------------------------------------------------------------
JMF	0:24d3eb812fd4	1271	* 0 \| 0 \| normal
JMF	0:24d3eb812fd4	1272	* 0 \| 1 \| direct through FIFO
JMF	0:24d3eb812fd4	1273	* 1 \| 0 \| direct through GPIO
JMF	0:24d3eb812fd4	1274	*
JMF	0:24d3eb812fd4	1275	* 3:0 LEN_WID[3:0]: length of length field in bits
JMF	0:24d3eb812fd4	1276	* \endcode
JMF	0:24d3eb812fd4	1277	*/
JMF	0:24d3eb812fd4	1278	#define PCKTCTRL3_BASE ((uint8_t)0x31) /!< packet format, RX mode, lenght of length field /
JMF	0:24d3eb812fd4	1279
JMF	0:24d3eb812fd4	1280	#define PCKTCTRL3_PCKT_FRMT_BASIC ((uint8_t)0x00) /!< Basic Packet Format /
JMF	0:24d3eb812fd4	1281	#define PCKTCTRL3_PCKT_FRMT_MBUS ((uint8_t)0x80) /!< Wireless M-BUS Packet Format /
JMF	0:24d3eb812fd4	1282	#define PCKTCTRL3_PCKT_FRMT_STACK ((uint8_t)0xC0) /!< STack Packet Format /
JMF	0:24d3eb812fd4	1283
JMF	0:24d3eb812fd4	1284	#define PCKTCTRL3_RX_MODE_NORMAL ((uint8_t)0x00) /!< Normal RX Mode /
JMF	0:24d3eb812fd4	1285	#define PCKTCTRL3_RX_MODE_DIRECT_FIFO ((uint8_t)0x10) /!< RX Direct Mode; data available through FIFO /
JMF	0:24d3eb812fd4	1286	#define PCKTCTRL3_RX_MODE_DIRECT_GPIO ((uint8_t)0x20) /!< RX Direct Mode; data available through selected GPIO /
JMF	0:24d3eb812fd4	1287
JMF	0:24d3eb812fd4	1288	#define PCKTCTRL3_PKT_FRMT_MASK ((uint8_t)0xC0)
JMF	0:24d3eb812fd4	1289	#define PCKTCTRL3_RX_MODE_MASK ((uint8_t)0x30)
JMF	0:24d3eb812fd4	1290	#define PCKTCTRL3_LEN_WID_MASK ((uint8_t)0x0F)
JMF	0:24d3eb812fd4	1291
JMF	0:24d3eb812fd4	1292	/**
JMF	0:24d3eb812fd4	1293	* @}
JMF	0:24d3eb812fd4	1294	*/
JMF	0:24d3eb812fd4	1295
JMF	0:24d3eb812fd4	1296	/** @defgroup PCKTCTRL2_Register
JMF	0:24d3eb812fd4	1297	* @{
JMF	0:24d3eb812fd4	1298	*/
JMF	0:24d3eb812fd4	1299
JMF	0:24d3eb812fd4	1300	/**
JMF	0:24d3eb812fd4	1301	* \brief PCKTCTRL2 register
JMF	0:24d3eb812fd4	1302	* \code
JMF	0:24d3eb812fd4	1303	* Read Write
JMF	0:24d3eb812fd4	1304	* Default value: 0x1E
JMF	0:24d3eb812fd4	1305	*
JMF	0:24d3eb812fd4	1306	* 7:3 PREAMBLE_LENGTH[4:0]: length of preamble field in bytes (0..31)
JMF	0:24d3eb812fd4	1307	*
JMF	0:24d3eb812fd4	1308	*
JMF	0:24d3eb812fd4	1309	* 2:1 SYNC_LENGTH[1:0]: length of sync field in bytes
JMF	0:24d3eb812fd4	1310	*
JMF	0:24d3eb812fd4	1311	*
JMF	0:24d3eb812fd4	1312	* 0 FIX_VAR_LEN: fixed/variable packet length
JMF	0:24d3eb812fd4	1313	* 1 - Variable
JMF	0:24d3eb812fd4	1314	* 0 - Fixed
JMF	0:24d3eb812fd4	1315	* \endcode
JMF	0:24d3eb812fd4	1316	*/
JMF	0:24d3eb812fd4	1317	#define PCKTCTRL2_BASE ((uint8_t)0x32) /!< length of preamble and sync fields (in bytes), fix or variable packet length /
JMF	0:24d3eb812fd4	1318
JMF	0:24d3eb812fd4	1319	#define PCKTCTRL2_FIX_VAR_LEN_MASK ((uint8_t)0x01) /!< Enable/disable the length mode /
JMF	0:24d3eb812fd4	1320	#define PCKTCTRL2_PREAMBLE_LENGTH_MASK ((uint8_t)0xF8)
JMF	0:24d3eb812fd4	1321	#define PCKTCTRL2_SYNC_LENGTH_MASK ((uint8_t)0x06)
JMF	0:24d3eb812fd4	1322
JMF	0:24d3eb812fd4	1323	/**
JMF	0:24d3eb812fd4	1324	* @}
JMF	0:24d3eb812fd4	1325	*/
JMF	0:24d3eb812fd4	1326
JMF	0:24d3eb812fd4	1327	/** @defgroup PCKTCTRL1_Register
JMF	0:24d3eb812fd4	1328	* @{
JMF	0:24d3eb812fd4	1329	*/
JMF	0:24d3eb812fd4	1330
JMF	0:24d3eb812fd4	1331	/**
JMF	0:24d3eb812fd4	1332	* \brief PCKTCTRL1 register
JMF	0:24d3eb812fd4	1333	* \code
JMF	0:24d3eb812fd4	1334	* Read Write
JMF	0:24d3eb812fd4	1335	* Default value: 0x20
JMF	0:24d3eb812fd4	1336	*
JMF	0:24d3eb812fd4	1337	* 7:5 CRC_MODE[2:0]: CRC type (0, 8, 16, 24 bits)
JMF	0:24d3eb812fd4	1338	*
JMF	0:24d3eb812fd4	1339	* CRC_MODE2 \| CRC_MODE1 \| CRC_MODE0 \| CRC Mode (n. bits - poly)
JMF	0:24d3eb812fd4	1340	* -------------------------------------------------------------------------------------------------
JMF	0:24d3eb812fd4	1341	* 0 \| 0 \| 1 \| 8 - 0x07
JMF	0:24d3eb812fd4	1342	* 0 \| 1 \| 0 \| 16 - 0x8005
JMF	0:24d3eb812fd4	1343	* 0 \| 1 \| 1 \| 16 - 0x1021
JMF	0:24d3eb812fd4	1344	* 1 \| 0 \| 0 \| 24 - 0x864CBF
JMF	0:24d3eb812fd4	1345	*
JMF	0:24d3eb812fd4	1346	* 4 WHIT_EN[0]: Enable Whitening
JMF	0:24d3eb812fd4	1347	* 1 - Enable
JMF	0:24d3eb812fd4	1348	* 0 - Disable
JMF	0:24d3eb812fd4	1349	*
JMF	0:24d3eb812fd4	1350	* 3:2 TX_SOURCE[1:0]: length of sync field in bytes
JMF	0:24d3eb812fd4	1351	*
JMF	0:24d3eb812fd4	1352	* TX_SOURCE1 \| TX_SOURCE0 \| Tx Mode
JMF	0:24d3eb812fd4	1353	* --------------------------------------------------------------------
JMF	0:24d3eb812fd4	1354	* 0 \| 0 \| normal
JMF	0:24d3eb812fd4	1355	* 0 \| 1 \| direct through FIFO
JMF	0:24d3eb812fd4	1356	* 1 \| 0 \| direct through GPIO
JMF	0:24d3eb812fd4	1357	* 1 \| 1 \| pn9
JMF	0:24d3eb812fd4	1358	*
JMF	0:24d3eb812fd4	1359	* 1 NOT_USED
JMF	0:24d3eb812fd4	1360	*
JMF	0:24d3eb812fd4	1361	* 0 FEC_EN: enable FEC
JMF	0:24d3eb812fd4	1362	* 1 - FEC in TX , Viterbi decoding in RX
JMF	0:24d3eb812fd4	1363	* 0 - Disabled
JMF	0:24d3eb812fd4	1364	* \endcode
JMF	0:24d3eb812fd4	1365	*/
JMF	0:24d3eb812fd4	1366	#define PCKTCTRL1_BASE ((uint8_t)0x33) /!< CRC type, whitening enable, TX mode /
JMF	0:24d3eb812fd4	1367
JMF	0:24d3eb812fd4	1368	#define PCKTCTRL1_FEC_MASK ((uint8_t)0x01) /!< Enable/disable the Forward Error Correction /
JMF	0:24d3eb812fd4	1369	#define PCKTCTRL1_TX_SOURCE_MASK ((uint8_t)0x0C) /!< TX source mode /
JMF	0:24d3eb812fd4	1370	#define PCKTCTRL1_CRC_MODE_MASK ((uint8_t)0xE0) /!< CRC type /
JMF	0:24d3eb812fd4	1371	#define PCKTCTRL1_WHIT_MASK ((uint8_t)0x10) /!< Enable/disable the Whitening /
JMF	0:24d3eb812fd4	1372
JMF	0:24d3eb812fd4	1373	/**
JMF	0:24d3eb812fd4	1374	* @}
JMF	0:24d3eb812fd4	1375	*/
JMF	0:24d3eb812fd4	1376
JMF	0:24d3eb812fd4	1377
JMF	0:24d3eb812fd4	1378
JMF	0:24d3eb812fd4	1379	/** @defgroup PCKTLEN1_Register
JMF	0:24d3eb812fd4	1380	* @{
JMF	0:24d3eb812fd4	1381	*/
JMF	0:24d3eb812fd4	1382
JMF	0:24d3eb812fd4	1383	/**
JMF	0:24d3eb812fd4	1384	* \brief PCKTLEN1 register
JMF	0:24d3eb812fd4	1385	* \code
JMF	0:24d3eb812fd4	1386	* Read Write
JMF	0:24d3eb812fd4	1387	* Default value: 0x00
JMF	0:24d3eb812fd4	1388	*
JMF	0:24d3eb812fd4	1389	* 7:0 pktlen1[7:0]: lenght of packet in bytes (upper field) LENGHT/256
JMF	0:24d3eb812fd4	1390	* \endcode
JMF	0:24d3eb812fd4	1391	*/
JMF	0:24d3eb812fd4	1392	#define PCKTLEN1_BASE ((uint8_t)0x34) /!< lenght of packet in bytes (upper field) /
JMF	0:24d3eb812fd4	1393
JMF	0:24d3eb812fd4	1394	/**
JMF	0:24d3eb812fd4	1395	* @}
JMF	0:24d3eb812fd4	1396	*/
JMF	0:24d3eb812fd4	1397
JMF	0:24d3eb812fd4	1398	/** @defgroup PCKTLEN0_Register
JMF	0:24d3eb812fd4	1399	* @{
JMF	0:24d3eb812fd4	1400	*/
JMF	0:24d3eb812fd4	1401
JMF	0:24d3eb812fd4	1402	/**
JMF	0:24d3eb812fd4	1403	* \brief PCKTLEN0 register
JMF	0:24d3eb812fd4	1404	* \code
JMF	0:24d3eb812fd4	1405	* Read Write
JMF	0:24d3eb812fd4	1406	* Default value: 0x14
JMF	0:24d3eb812fd4	1407	*
JMF	0:24d3eb812fd4	1408	* 7:0 pktlen0[7:0]: lenght of packet in bytes (lower field) LENGHT%256
JMF	0:24d3eb812fd4	1409	* \endcode
JMF	0:24d3eb812fd4	1410	*/
JMF	0:24d3eb812fd4	1411	#define PCKTLEN0_BASE ((uint8_t)0x35) /!< lenght of packet in bytes (lower field) [PCKTLEN=PCKTLEN1x256+PCKTLEN0]/
JMF	0:24d3eb812fd4	1412
JMF	0:24d3eb812fd4	1413	/**
JMF	0:24d3eb812fd4	1414	* @}
JMF	0:24d3eb812fd4	1415	*/
JMF	0:24d3eb812fd4	1416
JMF	0:24d3eb812fd4	1417	/** @defgroup SYNCx_Registers
JMF	0:24d3eb812fd4	1418	* @{
JMF	0:24d3eb812fd4	1419	*/
JMF	0:24d3eb812fd4	1420	/**
JMF	0:24d3eb812fd4	1421	* \brief SYNCx[4:1] Registers
JMF	0:24d3eb812fd4	1422	* \code
JMF	0:24d3eb812fd4	1423	* Read Write
JMF	0:24d3eb812fd4	1424	* Default value: 0x88
JMF	0:24d3eb812fd4	1425	*
JMF	0:24d3eb812fd4	1426	* 7:0 SYNCx[7:0]: xth sync word
JMF	0:24d3eb812fd4	1427	* \endcode
JMF	0:24d3eb812fd4	1428	*/
JMF	0:24d3eb812fd4	1429	#define SYNC4_BASE ((uint8_t)0x36) /!< Sync word 4 /
JMF	0:24d3eb812fd4	1430	#define SYNC3_BASE ((uint8_t)0x37) /!< Sync word 3 /
JMF	0:24d3eb812fd4	1431	#define SYNC2_BASE ((uint8_t)0x38) /!< Sync word 2 /
JMF	0:24d3eb812fd4	1432	#define SYNC1_BASE ((uint8_t)0x39) /!< Sync word 1 /
JMF	0:24d3eb812fd4	1433
JMF	0:24d3eb812fd4	1434	/**
JMF	0:24d3eb812fd4	1435	* @}
JMF	0:24d3eb812fd4	1436	*/
JMF	0:24d3eb812fd4	1437
JMF	0:24d3eb812fd4	1438
JMF	0:24d3eb812fd4	1439	/** @defgroup MBUS_PRMBL_Register
JMF	0:24d3eb812fd4	1440	* @{
JMF	0:24d3eb812fd4	1441	*/
JMF	0:24d3eb812fd4	1442
JMF	0:24d3eb812fd4	1443	/**
JMF	0:24d3eb812fd4	1444	* \brief MBUS_PRMBL register
JMF	0:24d3eb812fd4	1445	* \code
JMF	0:24d3eb812fd4	1446	* Read Write
JMF	0:24d3eb812fd4	1447	* Default value: 0x20
JMF	0:24d3eb812fd4	1448	*
JMF	0:24d3eb812fd4	1449	* 7:0 MBUS_PRMBL[7:0]: MBUS preamble control
JMF	0:24d3eb812fd4	1450	* \endcode
JMF	0:24d3eb812fd4	1451	*/
JMF	0:24d3eb812fd4	1452	#define MBUS_PRMBL_BASE ((uint8_t)0x3B) /!< MBUS preamble lenght (in 01 bit pairs) /
JMF	0:24d3eb812fd4	1453
JMF	0:24d3eb812fd4	1454	/**
JMF	0:24d3eb812fd4	1455	* @}
JMF	0:24d3eb812fd4	1456	*/
JMF	0:24d3eb812fd4	1457
JMF	0:24d3eb812fd4	1458
JMF	0:24d3eb812fd4	1459	/** @defgroup MBUS_PSTMBL_Register
JMF	0:24d3eb812fd4	1460	* @{
JMF	0:24d3eb812fd4	1461	*/
JMF	0:24d3eb812fd4	1462
JMF	0:24d3eb812fd4	1463	/**
JMF	0:24d3eb812fd4	1464	* \brief MBUS_PSTMBL register
JMF	0:24d3eb812fd4	1465	* \code
JMF	0:24d3eb812fd4	1466	* Read Write
JMF	0:24d3eb812fd4	1467	* Default value: 0x20
JMF	0:24d3eb812fd4	1468	*
JMF	0:24d3eb812fd4	1469	* 7:0 MBUS_PSTMBL[7:0]: MBUS postamble control
JMF	0:24d3eb812fd4	1470	* \endcode
JMF	0:24d3eb812fd4	1471	*/
JMF	0:24d3eb812fd4	1472	#define MBUS_PSTMBL_BASE ((uint8_t)0x3C) /!< MBUS postamble length (in 01 bit pairs) /
JMF	0:24d3eb812fd4	1473
JMF	0:24d3eb812fd4	1474	/**
JMF	0:24d3eb812fd4	1475	* @}
JMF	0:24d3eb812fd4	1476	*/
JMF	0:24d3eb812fd4	1477
JMF	0:24d3eb812fd4	1478	/** @defgroup MBUS_CTRL_Register
JMF	0:24d3eb812fd4	1479	* @{
JMF	0:24d3eb812fd4	1480	*/
JMF	0:24d3eb812fd4	1481
JMF	0:24d3eb812fd4	1482	/**
JMF	0:24d3eb812fd4	1483	* \brief MBUS_CTRL register
JMF	0:24d3eb812fd4	1484	* \code
JMF	0:24d3eb812fd4	1485	* Read Write
JMF	0:24d3eb812fd4	1486	* Default value: 0x00
JMF	0:24d3eb812fd4	1487	*
JMF	0:24d3eb812fd4	1488	* 7:4 NOT_USED
JMF	0:24d3eb812fd4	1489	*
JMF	0:24d3eb812fd4	1490	* 3:1 MBUS_SUBMODE[2:0]: MBUS submode (allowed values are 0,1,3,5)
JMF	0:24d3eb812fd4	1491	*
JMF	0:24d3eb812fd4	1492	* 0 NOT_USED
JMF	0:24d3eb812fd4	1493	* \endcode
JMF	0:24d3eb812fd4	1494	*/
JMF	0:24d3eb812fd4	1495	#define MBUS_CTRL_BASE ((uint8_t)0x3D) /!< MBUS sub-modes (S1, S2 short/long header, T1, T2, R2) /
JMF	0:24d3eb812fd4	1496
JMF	0:24d3eb812fd4	1497	#define MBUS_CTRL_MBUS_SUBMODE_S1_S2L ((uint8_t)0x00) /!< MBUS sub-modes S1 & S2L, header lenght min 279, sync 0x7696, Manchester /
JMF	0:24d3eb812fd4	1498	#define MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER ((uint8_t)0x02) /!< MBUS sub-modes S2, S1-m, T2 (only other to meter) short header, header lenght min 15, sync 0x7696, Manchester /
JMF	0:24d3eb812fd4	1499	#define MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER ((uint8_t)0x06) /!< MBUS sub-modes T1, T2 (only meter to other), header lenght min 19, sync 0x3D, 3 out of 6 /
JMF	0:24d3eb812fd4	1500	#define MBUS_CTRL_MBUS_SUBMODE_R2 ((uint8_t)0x0A) /!< MBUS sub-mode R2, header lenght min 39, sync 0x7696, Manchester /
JMF	0:24d3eb812fd4	1501
JMF	0:24d3eb812fd4	1502	/**
JMF	0:24d3eb812fd4	1503	* @}
JMF	0:24d3eb812fd4	1504	*/
JMF	0:24d3eb812fd4	1505
JMF	0:24d3eb812fd4	1506
JMF	0:24d3eb812fd4	1507
JMF	0:24d3eb812fd4	1508	/** @defgroup PCKT_FLT_GOALS_CONTROLx_MASK_Registers
JMF	0:24d3eb812fd4	1509	* @{
JMF	0:24d3eb812fd4	1510	*/
JMF	0:24d3eb812fd4	1511
JMF	0:24d3eb812fd4	1512	/**
JMF	0:24d3eb812fd4	1513	* \brief PCKT_FLT_GOALS_CONTROLx_MASK registers
JMF	0:24d3eb812fd4	1514	* \code
JMF	0:24d3eb812fd4	1515	* Default value: 0x00
JMF	0:24d3eb812fd4	1516	* Read Write
JMF	0:24d3eb812fd4	1517	* 7:0 CONTROLx_MASK[7:0]: All 0s - no filtering
JMF	0:24d3eb812fd4	1518	*
JMF	0:24d3eb812fd4	1519	* \endcode
JMF	0:24d3eb812fd4	1520	*/
JMF	0:24d3eb812fd4	1521	#define PCKT_FLT_GOALS_CONTROL0_MASK_BASE ((uint8_t)0x42) /!< Packet control field #3 mask, all 0s -> no filtering /
JMF	0:24d3eb812fd4	1522
JMF	0:24d3eb812fd4	1523	#define PCKT_FLT_GOALS_CONTROL1_MASK_BASE ((uint8_t)0x43) /!< Packet control field #2 mask, all 0s -> no filtering /
JMF	0:24d3eb812fd4	1524
JMF	0:24d3eb812fd4	1525	#define PCKT_FLT_GOALS_CONTROL2_MASK_BASE ((uint8_t)0x44) /!< Packet control field #1 mask, all 0s -> no filtering /
JMF	0:24d3eb812fd4	1526
JMF	0:24d3eb812fd4	1527	#define PCKT_FLT_GOALS_CONTROL3_MASK_BASE ((uint8_t)0x45) /!< Packet control field #0 mask, all 0s -> no filtering /
JMF	0:24d3eb812fd4	1528
JMF	0:24d3eb812fd4	1529	/**
JMF	0:24d3eb812fd4	1530	* @}
JMF	0:24d3eb812fd4	1531	*/
JMF	0:24d3eb812fd4	1532
JMF	0:24d3eb812fd4	1533	/** @defgroup PCKT_FLT_GOALS_CONTROLx_FIELD_Registers
JMF	0:24d3eb812fd4	1534	* @{
JMF	0:24d3eb812fd4	1535	*/
JMF	0:24d3eb812fd4	1536
JMF	0:24d3eb812fd4	1537	/**
JMF	0:24d3eb812fd4	1538	* \brief PCKT_FLT_GOALS_CONTROLx_FIELD registers
JMF	0:24d3eb812fd4	1539	* \code
JMF	0:24d3eb812fd4	1540	* Default value: 0x00
JMF	0:24d3eb812fd4	1541	* Read Write
JMF	0:24d3eb812fd4	1542	* 7:0 CONTROLx_FIELD[7:0]: Control field (byte x) to be used as reference
JMF	0:24d3eb812fd4	1543	*
JMF	0:24d3eb812fd4	1544	* \endcode
JMF	0:24d3eb812fd4	1545	*/
JMF	0:24d3eb812fd4	1546	#define PCKT_FLT_GOALS_CONTROL0_FIELD_BASE ((uint8_t)0x46) /!< Control field (byte #3) /
JMF	0:24d3eb812fd4	1547
JMF	0:24d3eb812fd4	1548	#define PCKT_FLT_GOALS_CONTROL1_FIELD_BASE ((uint8_t)0x47) /!< Control field (byte #2) /
JMF	0:24d3eb812fd4	1549
JMF	0:24d3eb812fd4	1550	#define PCKT_FLT_GOALS_CONTROL2_FIELD_BASE ((uint8_t)0x48) /!< Control field (byte #1) /
JMF	0:24d3eb812fd4	1551
JMF	0:24d3eb812fd4	1552	#define PCKT_FLT_GOALS_CONTROL3_FIELD_BASE ((uint8_t)0x49) /!< Control field (byte #0) /
JMF	0:24d3eb812fd4	1553
JMF	0:24d3eb812fd4	1554	/**
JMF	0:24d3eb812fd4	1555	* @}
JMF	0:24d3eb812fd4	1556	*/
JMF	0:24d3eb812fd4	1557
JMF	0:24d3eb812fd4	1558	/** @defgroup PCKT_FLT_GOALS_SOURCE_MASK_Register
JMF	0:24d3eb812fd4	1559	* @{
JMF	0:24d3eb812fd4	1560	*/
JMF	0:24d3eb812fd4	1561
JMF	0:24d3eb812fd4	1562	/**
JMF	0:24d3eb812fd4	1563	* \brief PCKT_FLT_GOALS_SOURCE_MASK register
JMF	0:24d3eb812fd4	1564	* \code
JMF	0:24d3eb812fd4	1565	* Default value: 0x00
JMF	0:24d3eb812fd4	1566	* Read Write
JMF	0:24d3eb812fd4	1567	* 7:0 RX_SOURCE_MASK[7:0]: For received packet only: all 0s - no filtering
JMF	0:24d3eb812fd4	1568	*
JMF	0:24d3eb812fd4	1569	* \endcode
JMF	0:24d3eb812fd4	1570	*/
JMF	0:24d3eb812fd4	1571	#define PCKT_FLT_GOALS_SOURCE_MASK_BASE ((uint8_t)0x4A) /!< Source address mask, valid in RX mode /
JMF	0:24d3eb812fd4	1572
JMF	0:24d3eb812fd4	1573	/**
JMF	0:24d3eb812fd4	1574	* @}
JMF	0:24d3eb812fd4	1575	*/
JMF	0:24d3eb812fd4	1576
JMF	0:24d3eb812fd4	1577	/** @defgroup PCKT_FLT_GOALS_SOURCE_ADDR_Register
JMF	0:24d3eb812fd4	1578	* @{
JMF	0:24d3eb812fd4	1579	*/
JMF	0:24d3eb812fd4	1580	/**
JMF	0:24d3eb812fd4	1581	* \brief PCKT_FLT_GOALS_SOURCE_ADDR register
JMF	0:24d3eb812fd4	1582	* \code
JMF	0:24d3eb812fd4	1583	* Default value: 0x00
JMF	0:24d3eb812fd4	1584	* Read Write
JMF	0:24d3eb812fd4	1585	* 7:0 RX_SOURCE_ADDR[7:0]: RX packet source / TX packet destination fields
JMF	0:24d3eb812fd4	1586	*
JMF	0:24d3eb812fd4	1587	* \endcode
JMF	0:24d3eb812fd4	1588	*/
JMF	0:24d3eb812fd4	1589	#define PCKT_FLT_GOALS_SOURCE_ADDR_BASE ((uint8_t)0x4B) /!< Source address /
JMF	0:24d3eb812fd4	1590
JMF	0:24d3eb812fd4	1591	/**
JMF	0:24d3eb812fd4	1592	* @}
JMF	0:24d3eb812fd4	1593	*/
JMF	0:24d3eb812fd4	1594
JMF	0:24d3eb812fd4	1595	/** @defgroup PCKT_FLT_GOALS_BROADCAST_Register
JMF	0:24d3eb812fd4	1596	* @{
JMF	0:24d3eb812fd4	1597	*/
JMF	0:24d3eb812fd4	1598
JMF	0:24d3eb812fd4	1599	/**
JMF	0:24d3eb812fd4	1600	* \brief PCKT_FLT_GOALS_BROADCAST register
JMF	0:24d3eb812fd4	1601	* \code
JMF	0:24d3eb812fd4	1602	* Default value: 0x00
JMF	0:24d3eb812fd4	1603	* Read Write
JMF	0:24d3eb812fd4	1604	* 7:0 BROADCAST[7:0]: Address shared for broadcast communication link
JMF	0:24d3eb812fd4	1605	*
JMF	0:24d3eb812fd4	1606	* \endcode
JMF	0:24d3eb812fd4	1607	*/
JMF	0:24d3eb812fd4	1608	#define PCKT_FLT_GOALS_BROADCAST_BASE ((uint8_t)0x4C) /!< Address shared for broadcast communication links /
JMF	0:24d3eb812fd4	1609
JMF	0:24d3eb812fd4	1610	/**
JMF	0:24d3eb812fd4	1611	* @}
JMF	0:24d3eb812fd4	1612	*/
JMF	0:24d3eb812fd4	1613
JMF	0:24d3eb812fd4	1614	/** @defgroup PCKT_FLT_GOALS_MULTICAST_Register
JMF	0:24d3eb812fd4	1615	* @{
JMF	0:24d3eb812fd4	1616	*/
JMF	0:24d3eb812fd4	1617
JMF	0:24d3eb812fd4	1618	/**
JMF	0:24d3eb812fd4	1619	* \brief PCKT_FLT_GOALS_MULTICAST register
JMF	0:24d3eb812fd4	1620	* \code
JMF	0:24d3eb812fd4	1621	* Default value: 0x00
JMF	0:24d3eb812fd4	1622	* Read Write
JMF	0:24d3eb812fd4	1623	* 7:0 MULTICAST[7:0]: Address shared for multicast communication links
JMF	0:24d3eb812fd4	1624	*
JMF	0:24d3eb812fd4	1625	* \endcode
JMF	0:24d3eb812fd4	1626	*/
JMF	0:24d3eb812fd4	1627	#define PCKT_FLT_GOALS_MULTICAST_BASE ((uint8_t)0x4D) /!< Address shared for multicast communication links /
JMF	0:24d3eb812fd4	1628
JMF	0:24d3eb812fd4	1629	/**
JMF	0:24d3eb812fd4	1630	* @}
JMF	0:24d3eb812fd4	1631	*/
JMF	0:24d3eb812fd4	1632
JMF	0:24d3eb812fd4	1633	/** @defgroup PCKT_FLT_GOALS_TX_SOURCE_ADDR_Register
JMF	0:24d3eb812fd4	1634	* @{
JMF	0:24d3eb812fd4	1635	*/
JMF	0:24d3eb812fd4	1636
JMF	0:24d3eb812fd4	1637	/**
JMF	0:24d3eb812fd4	1638	* \brief PCKT_FLT_GOALS_TX_SOURCE_ADDR register
JMF	0:24d3eb812fd4	1639	* \code
JMF	0:24d3eb812fd4	1640	* Default value: 0x00
JMF	0:24d3eb812fd4	1641	* Read Write
JMF	0:24d3eb812fd4	1642	* 7:0 TX_SOURCE_ADDR[7:0]: TX packet source / RX packet destination fields
JMF	0:24d3eb812fd4	1643	*
JMF	0:24d3eb812fd4	1644	* \endcode
JMF	0:24d3eb812fd4	1645	*/
JMF	0:24d3eb812fd4	1646	#define PCKT_FLT_GOALS_TX_ADDR_BASE ((uint8_t)0x4E) /!< Address of the destination (also device own address) /
JMF	0:24d3eb812fd4	1647
JMF	0:24d3eb812fd4	1648	/**
JMF	0:24d3eb812fd4	1649	* @}
JMF	0:24d3eb812fd4	1650	*/
JMF	0:24d3eb812fd4	1651
JMF	0:24d3eb812fd4	1652	/** @defgroup PCKT_FLT_OPTIONS_Register
JMF	0:24d3eb812fd4	1653	* @{
JMF	0:24d3eb812fd4	1654	*/
JMF	0:24d3eb812fd4	1655
JMF	0:24d3eb812fd4	1656	/**
JMF	0:24d3eb812fd4	1657	* \brief PCKT_FLT_OPTIONS register
JMF	0:24d3eb812fd4	1658	* \code
JMF	0:24d3eb812fd4	1659	* Default value: 0x70
JMF	0:24d3eb812fd4	1660	* Read Write
JMF	0:24d3eb812fd4	1661	* 7 Reserved.
JMF	0:24d3eb812fd4	1662	*
JMF	0:24d3eb812fd4	1663	* 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - OR logical function applied to CS/SQI/PQI
JMF	0:24d3eb812fd4	1664	* values (masked by 7:5 bits in PROTOCOL register)
JMF	0:24d3eb812fd4	1665	* 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control fields matches
JMF	0:24d3eb812fd4	1666	* with masked CONTROLx_FIELD registers.
JMF	0:24d3eb812fd4	1667	* 4 SOURCE_FILTERING[0]: 1 - RX packet accepted if its source field
JMF	0:24d3eb812fd4	1668	* matches w/ masked RX_SOURCE_ADDR register.
JMF	0:24d3eb812fd4	1669	* 3 DEST_VS_ SOURCE _ADDR[0]: 1 - RX packet accepted if its destination
JMF	0:24d3eb812fd4	1670	* address matches with TX_SOURCE_ADDR reg.
JMF	0:24d3eb812fd4	1671	* 2 DEST_VS_MULTICAST_ADDR[0]: 1 - RX packet accepted if its destination
JMF	0:24d3eb812fd4	1672	* address matches with MULTICAST register
JMF	0:24d3eb812fd4	1673	* 1 DEST_VS_BROADCAST_ADDR[0]: 1 - RX packet accepted if its destination
JMF	0:24d3eb812fd4	1674	* address matches with BROADCAST register.
JMF	0:24d3eb812fd4	1675	* 0 CRC_CHECK[0]: 1 - packet discarded if CRC not valid.
JMF	0:24d3eb812fd4	1676	*
JMF	0:24d3eb812fd4	1677	* \endcode
JMF	0:24d3eb812fd4	1678	*/
JMF	0:24d3eb812fd4	1679	#define PCKT_FLT_OPTIONS_BASE ((uint8_t)0x4F) /!< Options relative to packet filtering /
JMF	0:24d3eb812fd4	1680
JMF	0:24d3eb812fd4	1681	#define PCKT_FLT_OPTIONS_CRC_CHECK_MASK ((uint8_t)0x01) /!< Enable/disable of CRC check: packet is discarded if CRC is not valid [RX] /
JMF	0:24d3eb812fd4	1682	#define PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK ((uint8_t)0x02) /!< Packet discarded if destination address differs from BROADCAST register [RX] /
JMF	0:24d3eb812fd4	1683	#define PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK ((uint8_t)0x04) /!< Packet discarded if destination address differs from MULTICAST register [RX] /
JMF	0:24d3eb812fd4	1684	#define PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK ((uint8_t)0x08) /!< Packet discarded if destination address differs from TX_ADDR register [RX] /
JMF	0:24d3eb812fd4	1685	#define PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK ((uint8_t)0x10) /*!< Packet discarded if source address (masked by the SOURCE_MASK register)
JMF	0:24d3eb812fd4	1686	differs from SOURCE_ADDR register [RX] */
JMF	0:24d3eb812fd4	1687	#define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20) /*!< Packet discarded if the x-byte (x=1¸4) control field (masked by the CONTROLx_MASK register)
JMF	0:24d3eb812fd4	1688	differs from CONTROLx_FIELD register [RX] */
JMF	0:24d3eb812fd4	1689	#define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40) /*!< Logical function applied to CS/SQI/PQI values (masked by [7:5] bits in PROTOCOL[2]
JMF	0:24d3eb812fd4	1690	register) */
JMF	0:24d3eb812fd4	1691
JMF	0:24d3eb812fd4	1692	/**
JMF	0:24d3eb812fd4	1693	* @}
JMF	0:24d3eb812fd4	1694	*/
JMF	0:24d3eb812fd4	1695
JMF	0:24d3eb812fd4	1696	/** @defgroup TX_CTRL_FIELD_Registers
JMF	0:24d3eb812fd4	1697	* @{
JMF	0:24d3eb812fd4	1698	*/
JMF	0:24d3eb812fd4	1699
JMF	0:24d3eb812fd4	1700	/**
JMF	0:24d3eb812fd4	1701	* \brief TX_CTRL_FIELDx registers
JMF	0:24d3eb812fd4	1702	* \code
JMF	0:24d3eb812fd4	1703	* Default value: 0x00
JMF	0:24d3eb812fd4	1704	* Read Write
JMF	0:24d3eb812fd4	1705	* 7:0 TX_CTRLx[7:0]: Control field value to be used in TX packet as byte n.x
JMF	0:24d3eb812fd4	1706	* \endcode
JMF	0:24d3eb812fd4	1707	*/
JMF	0:24d3eb812fd4	1708	#define TX_CTRL_FIELD3_BASE ((uint8_t)0x68) /!< Control field value to be used in TX packet as byte n.3 /
JMF	0:24d3eb812fd4	1709
JMF	0:24d3eb812fd4	1710	#define TX_CTRL_FIELD2_BASE ((uint8_t)0x69) /!< Control field value to be used in TX packet as byte n.2 /
JMF	0:24d3eb812fd4	1711
JMF	0:24d3eb812fd4	1712	#define TX_CTRL_FIELD1_BASE ((uint8_t)0x6A) /!< Control field value to be used in TX packet as byte n.1 /
JMF	0:24d3eb812fd4	1713
JMF	0:24d3eb812fd4	1714	#define TX_CTRL_FIELD0_BASE ((uint8_t)0x6B) /!< Control field value to be used in TX packet as byte n.0 /
JMF	0:24d3eb812fd4	1715
JMF	0:24d3eb812fd4	1716	/**
JMF	0:24d3eb812fd4	1717	* @}
JMF	0:24d3eb812fd4	1718	*/
JMF	0:24d3eb812fd4	1719
JMF	0:24d3eb812fd4	1720
JMF	0:24d3eb812fd4	1721	/** @defgroup TX_PCKT_INFO_Register
JMF	0:24d3eb812fd4	1722	* @{
JMF	0:24d3eb812fd4	1723	*/
JMF	0:24d3eb812fd4	1724
JMF	0:24d3eb812fd4	1725	/**
JMF	0:24d3eb812fd4	1726	* \brief TX_PCKT_INFO registers
JMF	0:24d3eb812fd4	1727	* \code
JMF	0:24d3eb812fd4	1728	* Default value: 0x00
JMF	0:24d3eb812fd4	1729	* Read
JMF	0:24d3eb812fd4	1730	*
JMF	0:24d3eb812fd4	1731	* 7:6 Not used.
JMF	0:24d3eb812fd4	1732	*
JMF	0:24d3eb812fd4	1733	* 5:4 TX_SEQ_NUM: Current TX packet sequence number
JMF	0:24d3eb812fd4	1734	*
JMF	0:24d3eb812fd4	1735	* 0 N_RETX[3:0]: Number of retransmissions done on the
JMF	0:24d3eb812fd4	1736	* last TX packet
JMF	0:24d3eb812fd4	1737	* \endcode
JMF	0:24d3eb812fd4	1738	*/
JMF	0:24d3eb812fd4	1739	#define TX_PCKT_INFO_BASE ((uint8_t)(0xC2)) /*!< Current TX packet sequence number [5:4];
JMF	0:24d3eb812fd4	1740	Number of retransmissions done on the last TX packet [3:0]*/
JMF	0:24d3eb812fd4	1741	/**
JMF	0:24d3eb812fd4	1742	* @}
JMF	0:24d3eb812fd4	1743	*/
JMF	0:24d3eb812fd4	1744
JMF	0:24d3eb812fd4	1745	/** @defgroup RX_PCKT_INFO_Register
JMF	0:24d3eb812fd4	1746	* @{
JMF	0:24d3eb812fd4	1747	*/
JMF	0:24d3eb812fd4	1748
JMF	0:24d3eb812fd4	1749	/**
JMF	0:24d3eb812fd4	1750	* \brief RX_PCKT_INFO registers
JMF	0:24d3eb812fd4	1751	* \code
JMF	0:24d3eb812fd4	1752	* Default value: 0x00
JMF	0:24d3eb812fd4	1753	* Read
JMF	0:24d3eb812fd4	1754	*
JMF	0:24d3eb812fd4	1755	* 7:3 Not used.
JMF	0:24d3eb812fd4	1756	*
JMF	0:24d3eb812fd4	1757	* 2 NACK_RX: NACK field of the received packet
JMF	0:24d3eb812fd4	1758	*
JMF	0:24d3eb812fd4	1759	* 1:0 RX_SEQ_NUM[1:0]: Sequence number of the received packet
JMF	0:24d3eb812fd4	1760	* \endcode
JMF	0:24d3eb812fd4	1761	*/
JMF	0:24d3eb812fd4	1762	#define RX_PCKT_INFO_BASE ((uint8_t)(0xC3)) /*!< NO_ACK field of the received packet [2];
JMF	0:24d3eb812fd4	1763	sequence number of the received packet [1:0]*/
JMF	0:24d3eb812fd4	1764
JMF	0:24d3eb812fd4	1765	#define TX_PCKT_INFO_NACK_RX ((uint8_t)(0x04)) /!< NACK field of the received packet /
JMF	0:24d3eb812fd4	1766
JMF	0:24d3eb812fd4	1767	/**
JMF	0:24d3eb812fd4	1768	* @}
JMF	0:24d3eb812fd4	1769	*/
JMF	0:24d3eb812fd4	1770
JMF	0:24d3eb812fd4	1771	/** @defgroup RX_PCKT_LEN1
JMF	0:24d3eb812fd4	1772	* @{
JMF	0:24d3eb812fd4	1773	*/
JMF	0:24d3eb812fd4	1774
JMF	0:24d3eb812fd4	1775	/**
JMF	0:24d3eb812fd4	1776	* \brief RX_PCKT_LEN1 registers
JMF	0:24d3eb812fd4	1777	* \code
JMF	0:24d3eb812fd4	1778	* Default value: 0x00
JMF	0:24d3eb812fd4	1779	* Read
JMF	0:24d3eb812fd4	1780	*
JMF	0:24d3eb812fd4	1781	* 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
JMF	0:24d3eb812fd4	1782	* This value is packet_length/256
JMF	0:24d3eb812fd4	1783	* \endcode
JMF	0:24d3eb812fd4	1784	*/
JMF	0:24d3eb812fd4	1785	#define RX_PCKT_LEN1_BASE ((uint8_t)(0xC9)) /!< Length (number of bytes) of the received packet: /
JMF	0:24d3eb812fd4	1786
JMF	0:24d3eb812fd4	1787	/**
JMF	0:24d3eb812fd4	1788	* @}
JMF	0:24d3eb812fd4	1789	*/
JMF	0:24d3eb812fd4	1790
JMF	0:24d3eb812fd4	1791	/** @defgroup RX_PCKT_LEN0
JMF	0:24d3eb812fd4	1792	* @{
JMF	0:24d3eb812fd4	1793	*/
JMF	0:24d3eb812fd4	1794
JMF	0:24d3eb812fd4	1795	/**
JMF	0:24d3eb812fd4	1796	* \brief RX_PCKT_LEN0 registers
JMF	0:24d3eb812fd4	1797	* \code
JMF	0:24d3eb812fd4	1798	* Default value: 0x00
JMF	0:24d3eb812fd4	1799	* Read
JMF	0:24d3eb812fd4	1800	*
JMF	0:24d3eb812fd4	1801	* 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
JMF	0:24d3eb812fd4	1802	* This value is packet_length%256
JMF	0:24d3eb812fd4	1803	* \endcode
JMF	0:24d3eb812fd4	1804	*/
JMF	0:24d3eb812fd4	1805	#define RX_PCKT_LEN0_BASE ((uint8_t)(0xCA)) /!< RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 /
JMF	0:24d3eb812fd4	1806
JMF	0:24d3eb812fd4	1807	/**
JMF	0:24d3eb812fd4	1808	* @}
JMF	0:24d3eb812fd4	1809	*/
JMF	0:24d3eb812fd4	1810
JMF	0:24d3eb812fd4	1811
JMF	0:24d3eb812fd4	1812	/** @defgroup CRC_FIELD_Register
JMF	0:24d3eb812fd4	1813	* @{
JMF	0:24d3eb812fd4	1814	*/
JMF	0:24d3eb812fd4	1815
JMF	0:24d3eb812fd4	1816	/**
JMF	0:24d3eb812fd4	1817	* \brief CRC_FIELD[2:0] registers
JMF	0:24d3eb812fd4	1818	* \code
JMF	0:24d3eb812fd4	1819	* Default value: 0x00
JMF	0:24d3eb812fd4	1820	* Read
JMF	0:24d3eb812fd4	1821	*
JMF	0:24d3eb812fd4	1822	* 7:0 CRC_FIELDx[7:0]: upper(x=2), middle(x=1) and lower(x=0) part of the crc field of the received packet
JMF	0:24d3eb812fd4	1823	* \endcode
JMF	0:24d3eb812fd4	1824	*/
JMF	0:24d3eb812fd4	1825	#define CRC_FIELD2_BASE ((uint8_t)(0xCB)) /!< CRC2 field of the received packet /
JMF	0:24d3eb812fd4	1826
JMF	0:24d3eb812fd4	1827	#define CRC_FIELD1_BASE ((uint8_t)(0xCC)) /!< CRC1 field of the received packet /
JMF	0:24d3eb812fd4	1828
JMF	0:24d3eb812fd4	1829	#define CRC_FIELD0_BASE ((uint8_t)(0xCD)) /!< CRC0 field of the received packet /
JMF	0:24d3eb812fd4	1830
JMF	0:24d3eb812fd4	1831	/**
JMF	0:24d3eb812fd4	1832	* @}
JMF	0:24d3eb812fd4	1833	*/
JMF	0:24d3eb812fd4	1834
JMF	0:24d3eb812fd4	1835	/** @defgroup RX_CTRL_FIELD_Register
JMF	0:24d3eb812fd4	1836	* @{
JMF	0:24d3eb812fd4	1837	*/
JMF	0:24d3eb812fd4	1838
JMF	0:24d3eb812fd4	1839	/**
JMF	0:24d3eb812fd4	1840	* \brief RX_CTRL_FIELD[3:0] registers
JMF	0:24d3eb812fd4	1841	* \code
JMF	0:24d3eb812fd4	1842	* Default value: 0x00
JMF	0:24d3eb812fd4	1843	* Read
JMF	0:24d3eb812fd4	1844	*
JMF	0:24d3eb812fd4	1845	* 7:0 RX_CTRL_FIELDx[7:0]: upper(x=3), middle(x=2), middle(x=1) and lower(x=0) part of the control field of the received packet
JMF	0:24d3eb812fd4	1846	* \endcode
JMF	0:24d3eb812fd4	1847	*/
JMF	0:24d3eb812fd4	1848	#define RX_CTRL_FIELD0_BASE ((uint8_t)(0xCE)) /!< CRTL3 Control field of the received packet /
JMF	0:24d3eb812fd4	1849
JMF	0:24d3eb812fd4	1850	#define RX_CTRL_FIELD1_BASE ((uint8_t)(0xCF)) /!< CRTL2 Control field of the received packet /
JMF	0:24d3eb812fd4	1851
JMF	0:24d3eb812fd4	1852	#define RX_CTRL_FIELD2_BASE ((uint8_t)(0xD0)) /!< CRTL1 Control field of the received packet /
JMF	0:24d3eb812fd4	1853
JMF	0:24d3eb812fd4	1854	#define RX_CTRL_FIELD3_BASE ((uint8_t)(0xD1)) /!< CRTL0 Control field of the received packet /
JMF	0:24d3eb812fd4	1855
JMF	0:24d3eb812fd4	1856	/**
JMF	0:24d3eb812fd4	1857	* @}
JMF	0:24d3eb812fd4	1858	*/
JMF	0:24d3eb812fd4	1859
JMF	0:24d3eb812fd4	1860	/** @defgroup RX_ADDR_FIELD_Register
JMF	0:24d3eb812fd4	1861	* @{
JMF	0:24d3eb812fd4	1862	*/
JMF	0:24d3eb812fd4	1863
JMF	0:24d3eb812fd4	1864	/**
JMF	0:24d3eb812fd4	1865	* \brief RX_ADDR_FIELD[1:0] registers
JMF	0:24d3eb812fd4	1866	* \code
JMF	0:24d3eb812fd4	1867	* Default value: 0x00
JMF	0:24d3eb812fd4	1868	* Read
JMF	0:24d3eb812fd4	1869	*
JMF	0:24d3eb812fd4	1870	* 7:0 RX_ADDR_FIELDx[7:0]: source(x=1) and destination(x=0) address field of the received packet
JMF	0:24d3eb812fd4	1871	* \endcode
JMF	0:24d3eb812fd4	1872	*/
JMF	0:24d3eb812fd4	1873	#define RX_ADDR_FIELD1_BASE ((uint8_t)(0xD2)) /!< ADDR1 Address field of the received packet /
JMF	0:24d3eb812fd4	1874
JMF	0:24d3eb812fd4	1875	#define RX_ADDR_FIELD0_BASE ((uint8_t)(0xD3)) /!< ADDR0 Address field of the received packet /
JMF	0:24d3eb812fd4	1876
JMF	0:24d3eb812fd4	1877	/**
JMF	0:24d3eb812fd4	1878	* @}
JMF	0:24d3eb812fd4	1879	*/
JMF	0:24d3eb812fd4	1880
JMF	0:24d3eb812fd4	1881	/**
JMF	0:24d3eb812fd4	1882	* @}
JMF	0:24d3eb812fd4	1883	*/
JMF	0:24d3eb812fd4	1884
JMF	0:24d3eb812fd4	1885
JMF	0:24d3eb812fd4	1886	/** @defgroup Protocol_Registers
JMF	0:24d3eb812fd4	1887	* @{
JMF	0:24d3eb812fd4	1888	*/
JMF	0:24d3eb812fd4	1889
JMF	0:24d3eb812fd4	1890	/** @defgroup PROTOCOL2_Register
JMF	0:24d3eb812fd4	1891	* @{
JMF	0:24d3eb812fd4	1892	*/
JMF	0:24d3eb812fd4	1893
JMF	0:24d3eb812fd4	1894	/**
JMF	0:24d3eb812fd4	1895	* \brief PROTOCOL2 register
JMF	0:24d3eb812fd4	1896	* \code
JMF	0:24d3eb812fd4	1897	* Default value: 0x06
JMF	0:24d3eb812fd4	1898	* Read Write
JMF	0:24d3eb812fd4	1899	* 7 CS_TIMEOUT_MASK: 1 - CS value contributes to timeout disabling
JMF	0:24d3eb812fd4	1900	*
JMF	0:24d3eb812fd4	1901	* 6 SQI_TIMEOUT_MASK: 1 - SQI value contributes to timeout disabling
JMF	0:24d3eb812fd4	1902	*
JMF	0:24d3eb812fd4	1903	* 5 PQI_TIMEOUT_MASK: 1 - PQI value contributes to timeout disabling
JMF	0:24d3eb812fd4	1904	*
JMF	0:24d3eb812fd4	1905	* 4:3 TX_SEQ_NUM_RELOAD[1:0]: TX sequence number to be used when counting reset is required using the related command.
JMF	0:24d3eb812fd4	1906	*
JMF	0:24d3eb812fd4	1907	* 2 RCO_CALIBRATION[0]: 1 - Enables the automatic RCO calibration
JMF	0:24d3eb812fd4	1908	*
JMF	0:24d3eb812fd4	1909	* 1 VCO_CALIBRATION[0]: 1 - Enables the automatic VCO calibration
JMF	0:24d3eb812fd4	1910	*
JMF	0:24d3eb812fd4	1911	* 0 LDCR_MODE[0]: 1 - LDCR mode enabled
JMF	0:24d3eb812fd4	1912	*
JMF	0:24d3eb812fd4	1913	* \endcode
JMF	0:24d3eb812fd4	1914	*/
JMF	0:24d3eb812fd4	1915	#define PROTOCOL2_BASE ((uint8_t)0x50) /!< Protocol2 regisetr address /
JMF	0:24d3eb812fd4	1916
JMF	0:24d3eb812fd4	1917	#define PROTOCOL2_LDC_MODE_MASK ((uint8_t)0x01) /!< Enable/disable Low duty Cycle mode /
JMF	0:24d3eb812fd4	1918	#define PROTOCOL2_VCO_CALIBRATION_MASK ((uint8_t)0x02) /!< Enable/disable VCO automatic calibration /
JMF	0:24d3eb812fd4	1919	#define PROTOCOL2_RCO_CALIBRATION_MASK ((uint8_t)0x04) /!< Enable/disable RCO automatic calibration /
JMF	0:24d3eb812fd4	1920	#define PROTOCOL2_PQI_TIMEOUT_MASK ((uint8_t)0x20) /!< PQI value contributes to timeout disabling /
JMF	0:24d3eb812fd4	1921	#define PROTOCOL2_SQI_TIMEOUT_MASK ((uint8_t)0x40) /!< SQI value contributes to timeout disabling /
JMF	0:24d3eb812fd4	1922	#define PROTOCOL2_CS_TIMEOUT_MASK ((uint8_t)0x80) /!< CS value contributes to timeout disabling /
JMF	0:24d3eb812fd4	1923
JMF	0:24d3eb812fd4	1924	/**
JMF	0:24d3eb812fd4	1925	* @}
JMF	0:24d3eb812fd4	1926	*/
JMF	0:24d3eb812fd4	1927
JMF	0:24d3eb812fd4	1928	/** @defgroup PROTOCOL1_Register
JMF	0:24d3eb812fd4	1929	* @{
JMF	0:24d3eb812fd4	1930	*/
JMF	0:24d3eb812fd4	1931
JMF	0:24d3eb812fd4	1932	/**
JMF	0:24d3eb812fd4	1933	* \brief PROTOCOL1 register
JMF	0:24d3eb812fd4	1934	* \code
JMF	0:24d3eb812fd4	1935	* Default value: 0x00
JMF	0:24d3eb812fd4	1936	* Read Write
JMF	0:24d3eb812fd4	1937	* 7 LDCR_RELOAD_ON_SYNC: 1 - LDCR timer will be reloaded with the value stored in the LDCR_RELOAD registers
JMF	0:24d3eb812fd4	1938	*
JMF	0:24d3eb812fd4	1939	* 6 PIGGYBACKING: 1 - PIGGYBACKING enabled
JMF	0:24d3eb812fd4	1940	*
JMF	0:24d3eb812fd4	1941	* 5:4 Reserved.
JMF	0:24d3eb812fd4	1942	*
JMF	0:24d3eb812fd4	1943	* 3 SEED_RELOAD[0]: 1 - Reload the back-off random generator
JMF	0:24d3eb812fd4	1944	* seed using the value written in the
JMF	0:24d3eb812fd4	1945	* BU_COUNTER_SEED_MSByte / LSByte registers
JMF	0:24d3eb812fd4	1946	*
JMF	0:24d3eb812fd4	1947	* 2 CSMA_ON [0]: 1 - CSMA channel access mode enabled
JMF	0:24d3eb812fd4	1948	*
JMF	0:24d3eb812fd4	1949	* 1 CSMA_PERS_ON[0]: 1 - CSMA persistent (no back-off) enabled
JMF	0:24d3eb812fd4	1950	*
JMF	0:24d3eb812fd4	1951	* 0 AUTO_PCKT_FLT[0]: 1 - automatic packet filtering mode enabled
JMF	0:24d3eb812fd4	1952	*
JMF	0:24d3eb812fd4	1953	* \endcode
JMF	0:24d3eb812fd4	1954	*/
JMF	0:24d3eb812fd4	1955	#define PROTOCOL1_BASE ((uint8_t)0x51) /!< Protocol1 regisetr address /
JMF	0:24d3eb812fd4	1956
JMF	0:24d3eb812fd4	1957	#define PROTOCOL1_AUTO_PCKT_FLT_MASK ((uint8_t)0x01) /!< Enable/disable automatic packet filtering mode /
JMF	0:24d3eb812fd4	1958	#define PROTOCOL1_CSMA_PERS_ON_MASK ((uint8_t)0x02) /!< Enable/disable CSMA persistent (no back-off) /
JMF	0:24d3eb812fd4	1959	#define PROTOCOL1_CSMA_ON_MASK ((uint8_t)0x04) /!< Enable/disable CSMA channel access mode /
JMF	0:24d3eb812fd4	1960	#define PROTOCOL1_SEED_RELOAD_MASK ((uint8_t)0x08) /!< Reloads the seed of the PN generator for CSMA procedure /
JMF	0:24d3eb812fd4	1961	#define PROTOCOL1_PIGGYBACKING_MASK ((uint8_t)0x40) /!< Enable/disable Piggybacking /
JMF	0:24d3eb812fd4	1962	#define PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK ((uint8_t)0x80) /!< LDC timer will be reloaded with the value stored in the LDC_RELOAD registers /
JMF	0:24d3eb812fd4	1963
JMF	0:24d3eb812fd4	1964	/**
JMF	0:24d3eb812fd4	1965	* @}
JMF	0:24d3eb812fd4	1966	*/
JMF	0:24d3eb812fd4	1967
JMF	0:24d3eb812fd4	1968	/** @defgroup PROTOCOL0_Register
JMF	0:24d3eb812fd4	1969	* @{
JMF	0:24d3eb812fd4	1970	*/
JMF	0:24d3eb812fd4	1971
JMF	0:24d3eb812fd4	1972	/**
JMF	0:24d3eb812fd4	1973	* \brief PROTOCOL0 register
JMF	0:24d3eb812fd4	1974	* \code
JMF	0:24d3eb812fd4	1975	* Default value: 0x08
JMF	0:24d3eb812fd4	1976	* Read Write
JMF	0:24d3eb812fd4	1977	* 7:4 NMAX_RETX[3:0]: Max number of re-TX. 0 - re-transmission is not performed
JMF	0:24d3eb812fd4	1978	*
JMF	0:24d3eb812fd4	1979	* 3 NACK_TX[0]: 1 - field NO_ACK=1 on transmitted packet
JMF	0:24d3eb812fd4	1980	*
JMF	0:24d3eb812fd4	1981	* 2 AUTO_ACK[0]: 1 - automatic ack after RX
JMF	0:24d3eb812fd4	1982	*
JMF	0:24d3eb812fd4	1983	* 1 PERS_RX[0]: 1 - persistent reception enabled
JMF	0:24d3eb812fd4	1984	*
JMF	0:24d3eb812fd4	1985	* 0 PERS_TX[0]: 1 - persistent transmission enabled
JMF	0:24d3eb812fd4	1986	*
JMF	0:24d3eb812fd4	1987	* \endcode
JMF	0:24d3eb812fd4	1988	*/
JMF	0:24d3eb812fd4	1989	#define PROTOCOL0_BASE ((uint8_t)0x52) /!< Persistent RX/TX, autoack, Max number of retransmissions /
JMF	0:24d3eb812fd4	1990
JMF	0:24d3eb812fd4	1991	#define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /!< Enables persistent transmission /
JMF	0:24d3eb812fd4	1992	#define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /!< Enables persistent reception /
JMF	0:24d3eb812fd4	1993	#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /!< Enables auto acknowlegment /
JMF	0:24d3eb812fd4	1994	#define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /!< Writes field NO_ACK=1 on transmitted packet /
JMF	0:24d3eb812fd4	1995	#define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xF0) /!< Retransmission mask /
JMF	0:24d3eb812fd4	1996
JMF	0:24d3eb812fd4	1997	/**
JMF	0:24d3eb812fd4	1998	* @}
JMF	0:24d3eb812fd4	1999	*/
JMF	0:24d3eb812fd4	2000
JMF	0:24d3eb812fd4	2001	/** @defgroup TIMERS5_Register
JMF	0:24d3eb812fd4	2002	* @{
JMF	0:24d3eb812fd4	2003	*/
JMF	0:24d3eb812fd4	2004
JMF	0:24d3eb812fd4	2005	/**
JMF	0:24d3eb812fd4	2006	* \brief TIMERS5 register
JMF	0:24d3eb812fd4	2007	* \code
JMF	0:24d3eb812fd4	2008	* Default value: 0x00
JMF	0:24d3eb812fd4	2009	* Read Write
JMF	0:24d3eb812fd4	2010	* 7:0 RX_TIMEOUT_PRESCALER[7:0] : RX operation timeout: prescaler value
JMF	0:24d3eb812fd4	2011	* \endcode
JMF	0:24d3eb812fd4	2012	*/
JMF	0:24d3eb812fd4	2013	#define TIMERS5_RX_TIMEOUT_PRESCALER_BASE ((uint8_t)0x53) /!< RX operation timeout: prescaler value /
JMF	0:24d3eb812fd4	2014
JMF	0:24d3eb812fd4	2015	/**
JMF	0:24d3eb812fd4	2016	* @}
JMF	0:24d3eb812fd4	2017	*/
JMF	0:24d3eb812fd4	2018
JMF	0:24d3eb812fd4	2019	/** @defgroup TIMERS4_Register
JMF	0:24d3eb812fd4	2020	* @{
JMF	0:24d3eb812fd4	2021	*/
JMF	0:24d3eb812fd4	2022
JMF	0:24d3eb812fd4	2023	/**
JMF	0:24d3eb812fd4	2024	* \brief TIMERS4 register
JMF	0:24d3eb812fd4	2025	* \code
JMF	0:24d3eb812fd4	2026	* Default value: 0x00
JMF	0:24d3eb812fd4	2027	* Read Write
JMF	0:24d3eb812fd4	2028	* 7:0 RX_TIMEOUT_COUNTER[7:0] : RX operation timeout: counter value
JMF	0:24d3eb812fd4	2029	* \endcode
JMF	0:24d3eb812fd4	2030	*/
JMF	0:24d3eb812fd4	2031	#define TIMERS4_RX_TIMEOUT_COUNTER_BASE ((uint8_t)0x54) /!< RX operation timeout: counter value /
JMF	0:24d3eb812fd4	2032
JMF	0:24d3eb812fd4	2033	/**
JMF	0:24d3eb812fd4	2034	* @}
JMF	0:24d3eb812fd4	2035	*/
JMF	0:24d3eb812fd4	2036
JMF	0:24d3eb812fd4	2037	/** @defgroup TIMERS3_Register
JMF	0:24d3eb812fd4	2038	* @{
JMF	0:24d3eb812fd4	2039	*/
JMF	0:24d3eb812fd4	2040
JMF	0:24d3eb812fd4	2041	/**
JMF	0:24d3eb812fd4	2042	* \brief TIMERS3 register
JMF	0:24d3eb812fd4	2043	* \code
JMF	0:24d3eb812fd4	2044	* Default value: 0x00
JMF	0:24d3eb812fd4	2045	* Read Write
JMF	0:24d3eb812fd4	2046	* 7:0 LDCR_PRESCALER[7:0] : LDC Mode: Prescaler part of the wake-up value
JMF	0:24d3eb812fd4	2047	* \endcode
JMF	0:24d3eb812fd4	2048	*/
JMF	0:24d3eb812fd4	2049	#define TIMERS3_LDC_PRESCALER_BASE ((uint8_t)0x55) /!< LDC Mode: Prescaler of the wake-up timer /
JMF	0:24d3eb812fd4	2050
JMF	0:24d3eb812fd4	2051	/**
JMF	0:24d3eb812fd4	2052	* @}
JMF	0:24d3eb812fd4	2053	*/
JMF	0:24d3eb812fd4	2054
JMF	0:24d3eb812fd4	2055	/** @defgroup TIMERS2_Register
JMF	0:24d3eb812fd4	2056	* @{
JMF	0:24d3eb812fd4	2057	*/
JMF	0:24d3eb812fd4	2058
JMF	0:24d3eb812fd4	2059	/**
JMF	0:24d3eb812fd4	2060	* \brief TIMERS2 register
JMF	0:24d3eb812fd4	2061	* \code
JMF	0:24d3eb812fd4	2062	* Default value: 0x00
JMF	0:24d3eb812fd4	2063	* Read Write
JMF	0:24d3eb812fd4	2064	* 7:0 LDCR_COUNTER[7:0] : LDC Mode: counter part of the wake-up value
JMF	0:24d3eb812fd4	2065	* \endcode
JMF	0:24d3eb812fd4	2066	*/
JMF	0:24d3eb812fd4	2067	#define TIMERS2_LDC_COUNTER_BASE ((uint8_t)0x56) /!< LDC Mode: counter of the wake-up timer /
JMF	0:24d3eb812fd4	2068
JMF	0:24d3eb812fd4	2069	/**
JMF	0:24d3eb812fd4	2070	* @}
JMF	0:24d3eb812fd4	2071	*/
JMF	0:24d3eb812fd4	2072
JMF	0:24d3eb812fd4	2073	/** @defgroup TIMERS1_Register
JMF	0:24d3eb812fd4	2074	* @{
JMF	0:24d3eb812fd4	2075	*/
JMF	0:24d3eb812fd4	2076
JMF	0:24d3eb812fd4	2077	/**
JMF	0:24d3eb812fd4	2078	* \brief TIMERS1 register
JMF	0:24d3eb812fd4	2079	* \code
JMF	0:24d3eb812fd4	2080	* Default value: 0x00
JMF	0:24d3eb812fd4	2081	* Read Write
JMF	0:24d3eb812fd4	2082	* 7:0 LDCR_RELOAD_PRESCALER[7:0] : LDC Mode: Prescaler part of the reload value
JMF	0:24d3eb812fd4	2083	* \endcode
JMF	0:24d3eb812fd4	2084	*/
JMF	0:24d3eb812fd4	2085	#define TIMERS1_LDC_RELOAD_PRESCALER_BASE ((uint8_t)0x57) /!< LDC Mode: Prescaler part of the reload value /
JMF	0:24d3eb812fd4	2086
JMF	0:24d3eb812fd4	2087	/**
JMF	0:24d3eb812fd4	2088	* @}
JMF	0:24d3eb812fd4	2089	*/
JMF	0:24d3eb812fd4	2090
JMF	0:24d3eb812fd4	2091	/** @defgroup TIMERS0_Register
JMF	0:24d3eb812fd4	2092	* @{
JMF	0:24d3eb812fd4	2093	*/
JMF	0:24d3eb812fd4	2094
JMF	0:24d3eb812fd4	2095	/**
JMF	0:24d3eb812fd4	2096	* \brief TIMERS0 register
JMF	0:24d3eb812fd4	2097	* \code
JMF	0:24d3eb812fd4	2098	* Default value: 0x00
JMF	0:24d3eb812fd4	2099	* Read Write
JMF	0:24d3eb812fd4	2100	* 7:0 LDCR_RELOAD_COUNTER[7:0] : LDC Mode: Counter part of the reload value
JMF	0:24d3eb812fd4	2101	* \endcode
JMF	0:24d3eb812fd4	2102	*/
JMF	0:24d3eb812fd4	2103	#define TIMERS0_LDC_RELOAD_COUNTER_BASE ((uint8_t)0x58) /!< LDC Mode: Counter part of the reload value /
JMF	0:24d3eb812fd4	2104
JMF	0:24d3eb812fd4	2105	/**
JMF	0:24d3eb812fd4	2106	* @}
JMF	0:24d3eb812fd4	2107	*/
JMF	0:24d3eb812fd4	2108
JMF	0:24d3eb812fd4	2109
JMF	0:24d3eb812fd4	2110	/** @defgroup CSMA_CONFIG3_Register
JMF	0:24d3eb812fd4	2111	* @{
JMF	0:24d3eb812fd4	2112	*/
JMF	0:24d3eb812fd4	2113
JMF	0:24d3eb812fd4	2114	/**
JMF	0:24d3eb812fd4	2115	* \brief CSMA_CONFIG3 registers
JMF	0:24d3eb812fd4	2116	* \code
JMF	0:24d3eb812fd4	2117	* Default value: 0xFF
JMF	0:24d3eb812fd4	2118	* Read Write
JMF	0:24d3eb812fd4	2119	* 7:0 BU_COUNTER_SEED_MSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB)
JMF	0:24d3eb812fd4	2120	* \endcode
JMF	0:24d3eb812fd4	2121	*/
JMF	0:24d3eb812fd4	2122	#define CSMA_CONFIG3_BASE ((uint8_t)0x64) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) /
JMF	0:24d3eb812fd4	2123
JMF	0:24d3eb812fd4	2124	/**
JMF	0:24d3eb812fd4	2125	* @}
JMF	0:24d3eb812fd4	2126	*/
JMF	0:24d3eb812fd4	2127
JMF	0:24d3eb812fd4	2128	/** @defgroup CSMA_CONFIG2_Register
JMF	0:24d3eb812fd4	2129	* @{
JMF	0:24d3eb812fd4	2130	*/
JMF	0:24d3eb812fd4	2131
JMF	0:24d3eb812fd4	2132	/**
JMF	0:24d3eb812fd4	2133	* \brief CSMA_CONFIG2 registers
JMF	0:24d3eb812fd4	2134	* \code
JMF	0:24d3eb812fd4	2135	* Default value: 0x00
JMF	0:24d3eb812fd4	2136	* Read Write
JMF	0:24d3eb812fd4	2137	* 7:0 BU_COUNTER_SEED_LSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB)
JMF	0:24d3eb812fd4	2138	* \endcode
JMF	0:24d3eb812fd4	2139	*/
JMF	0:24d3eb812fd4	2140	#define CSMA_CONFIG2_BASE ((uint8_t)0x65) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) /
JMF	0:24d3eb812fd4	2141
JMF	0:24d3eb812fd4	2142	/**
JMF	0:24d3eb812fd4	2143	* @}
JMF	0:24d3eb812fd4	2144	*/
JMF	0:24d3eb812fd4	2145
JMF	0:24d3eb812fd4	2146	/** @defgroup CSMA_CONFIG1_Register
JMF	0:24d3eb812fd4	2147	* @{
JMF	0:24d3eb812fd4	2148	*/
JMF	0:24d3eb812fd4	2149
JMF	0:24d3eb812fd4	2150	/**
JMF	0:24d3eb812fd4	2151	* \brief CSMA_CONFIG1 registers
JMF	0:24d3eb812fd4	2152	* \code
JMF	0:24d3eb812fd4	2153	* Default value: 0x04
JMF	0:24d3eb812fd4	2154	* Read Write
JMF	0:24d3eb812fd4	2155	* 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU
JMF	0:24d3eb812fd4	2156	*
JMF	0:24d3eb812fd4	2157	* 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time (64 / 128 /256 / 512 × Tbit.
JMF	0:24d3eb812fd4	2158	* \endcode
JMF	0:24d3eb812fd4	2159	*/
JMF	0:24d3eb812fd4	2160	#define CSMA_CONFIG1_BASE ((uint8_t)0x66) /!< CSMA/CA: Prescaler of the back-off time unit (BU); CCA period /
JMF	0:24d3eb812fd4	2161
JMF	0:24d3eb812fd4	2162	#define CSMA_CCA_PERIOD_64TBIT ((uint8_t)0x00) /!< CSMA/CA: Sets CCA period to 64TBIT */
JMF	0:24d3eb812fd4	2163	#define CSMA_CCA_PERIOD_128TBIT ((uint8_t)0x01) /!< CSMA/CA: Sets CCA period to 128TBIT */
JMF	0:24d3eb812fd4	2164	#define CSMA_CCA_PERIOD_256TBIT ((uint8_t)0x02) /!< CSMA/CA: Sets CCA period to 256TBIT */
JMF	0:24d3eb812fd4	2165	#define CSMA_CCA_PERIOD_512TBIT ((uint8_t)0x03) /!< CSMA/CA: Sets CCA period to 512TBIT */
JMF	0:24d3eb812fd4	2166
JMF	0:24d3eb812fd4	2167	/**
JMF	0:24d3eb812fd4	2168	* @}
JMF	0:24d3eb812fd4	2169	*/
JMF	0:24d3eb812fd4	2170
JMF	0:24d3eb812fd4	2171	/** @defgroup CSMA_CONFIG0_Register
JMF	0:24d3eb812fd4	2172	* @{
JMF	0:24d3eb812fd4	2173	*/
JMF	0:24d3eb812fd4	2174
JMF	0:24d3eb812fd4	2175	/**
JMF	0:24d3eb812fd4	2176	* \brief CSMA_CONFIG0 registers
JMF	0:24d3eb812fd4	2177	* \code
JMF	0:24d3eb812fd4	2178	* Default value: 0x00
JMF	0:24d3eb812fd4	2179	* Read Write
JMF	0:24d3eb812fd4	2180	* 7:4 CCA_LENGTH[3:0]: Used to program the Tlisten time
JMF	0:24d3eb812fd4	2181	*
JMF	0:24d3eb812fd4	2182	* 3 Reserved.
JMF	0:24d3eb812fd4	2183	*
JMF	0:24d3eb812fd4	2184	* 2:0 NBACKOFF_MAX[2:0]: Max number of back-off cycles.
JMF	0:24d3eb812fd4	2185	* \endcode
JMF	0:24d3eb812fd4	2186	*/
JMF	0:24d3eb812fd4	2187	#define CSMA_CONFIG0_BASE ((uint8_t)0x67) /!< CSMA/CA: CCA lenght; Max number of backoff cycles /
JMF	0:24d3eb812fd4	2188
JMF	0:24d3eb812fd4	2189	/**
JMF	0:24d3eb812fd4	2190	* @}
JMF	0:24d3eb812fd4	2191	*/
JMF	0:24d3eb812fd4	2192
JMF	0:24d3eb812fd4	2193	/**
JMF	0:24d3eb812fd4	2194	* @}
JMF	0:24d3eb812fd4	2195	*/
JMF	0:24d3eb812fd4	2196
JMF	0:24d3eb812fd4	2197
JMF	0:24d3eb812fd4	2198	/** @defgroup Link_Quality_Registers
JMF	0:24d3eb812fd4	2199	* @{
JMF	0:24d3eb812fd4	2200	*/
JMF	0:24d3eb812fd4	2201
JMF	0:24d3eb812fd4	2202	/** @defgroup QI_Register
JMF	0:24d3eb812fd4	2203	* @{
JMF	0:24d3eb812fd4	2204	*/
JMF	0:24d3eb812fd4	2205
JMF	0:24d3eb812fd4	2206	/**
JMF	0:24d3eb812fd4	2207	* \brief QI register
JMF	0:24d3eb812fd4	2208	* \code
JMF	0:24d3eb812fd4	2209	* Read Write
JMF	0:24d3eb812fd4	2210	* Default value: 0x02
JMF	0:24d3eb812fd4	2211	*
JMF	0:24d3eb812fd4	2212	* 7:6 SQI_TH[1:0]: SQI threshold according to the formula: 8SYNC_LEN - 2SQI_TH
JMF	0:24d3eb812fd4	2213	*
JMF	0:24d3eb812fd4	2214	* 5:2 PQI_TH[3:0]: PQI threshold according to the formula: 4*PQI_THR
JMF	0:24d3eb812fd4	2215	*
JMF	0:24d3eb812fd4	2216	*
JMF	0:24d3eb812fd4	2217	* 1 SQI_EN[0]: SQI enable
JMF	0:24d3eb812fd4	2218	* 1 - Enable
JMF	0:24d3eb812fd4	2219	* 0 - Disable
JMF	0:24d3eb812fd4	2220	*
JMF	0:24d3eb812fd4	2221	* 0 PQI_EN[0]: PQI enable
JMF	0:24d3eb812fd4	2222	* 1 - Enable
JMF	0:24d3eb812fd4	2223	* 0 - Disable
JMF	0:24d3eb812fd4	2224	* \endcode
JMF	0:24d3eb812fd4	2225	*/
JMF	0:24d3eb812fd4	2226	#define QI_BASE ((uint8_t)0x3A) /!< QI register /
JMF	0:24d3eb812fd4	2227
JMF	0:24d3eb812fd4	2228	#define QI_PQI_MASK ((uint8_t)0x01) /!< PQI enable/disable /
JMF	0:24d3eb812fd4	2229	#define QI_SQI_MASK ((uint8_t)0x02) /!< SQI enable/disable /
JMF	0:24d3eb812fd4	2230
JMF	0:24d3eb812fd4	2231	/**
JMF	0:24d3eb812fd4	2232	* @}
JMF	0:24d3eb812fd4	2233	*/
JMF	0:24d3eb812fd4	2234
JMF	0:24d3eb812fd4	2235	/** @defgroup LINK_QUALIF2
JMF	0:24d3eb812fd4	2236	* @{
JMF	0:24d3eb812fd4	2237	*/
JMF	0:24d3eb812fd4	2238
JMF	0:24d3eb812fd4	2239	/**
JMF	0:24d3eb812fd4	2240	* \brief LINK_QUALIF2 registers
JMF	0:24d3eb812fd4	2241	* \code
JMF	0:24d3eb812fd4	2242	* Default value: 0x00
JMF	0:24d3eb812fd4	2243	* Read
JMF	0:24d3eb812fd4	2244	*
JMF	0:24d3eb812fd4	2245	* 7:0 PQI[7:0]: PQI value of the received packet
JMF	0:24d3eb812fd4	2246	* \endcode
JMF	0:24d3eb812fd4	2247	*/
JMF	0:24d3eb812fd4	2248	#define LINK_QUALIF2_BASE ((uint8_t)(0xC5)) /!< PQI value of the received packet /
JMF	0:24d3eb812fd4	2249
JMF	0:24d3eb812fd4	2250	/**
JMF	0:24d3eb812fd4	2251	* @}
JMF	0:24d3eb812fd4	2252	*/
JMF	0:24d3eb812fd4	2253
JMF	0:24d3eb812fd4	2254	/** @defgroup LINK_QUALIF1
JMF	0:24d3eb812fd4	2255	* @{
JMF	0:24d3eb812fd4	2256	*/
JMF	0:24d3eb812fd4	2257
JMF	0:24d3eb812fd4	2258	/**
JMF	0:24d3eb812fd4	2259	* \brief LINK_QUALIF1 registers
JMF	0:24d3eb812fd4	2260	* \code
JMF	0:24d3eb812fd4	2261	* Default value: 0x00
JMF	0:24d3eb812fd4	2262	* Read
JMF	0:24d3eb812fd4	2263	*
JMF	0:24d3eb812fd4	2264	* 7 CS: Carrier Sense indication
JMF	0:24d3eb812fd4	2265	*
JMF	0:24d3eb812fd4	2266	* 6:0 SQI[6:0]: SQI value of the received packet
JMF	0:24d3eb812fd4	2267	* \endcode
JMF	0:24d3eb812fd4	2268	*/
JMF	0:24d3eb812fd4	2269	#define LINK_QUALIF1_BASE ((uint8_t)(0xC6)) /!< Carrier sense indication [7]; SQI value of the received packet /
JMF	0:24d3eb812fd4	2270
JMF	0:24d3eb812fd4	2271	#define LINK_QUALIF1_CS ((uint8_t)(0x80)) /!< Carrier sense indication [7] /
JMF	0:24d3eb812fd4	2272
JMF	0:24d3eb812fd4	2273	/**
JMF	0:24d3eb812fd4	2274	* @}
JMF	0:24d3eb812fd4	2275	*/
JMF	0:24d3eb812fd4	2276
JMF	0:24d3eb812fd4	2277	/** @defgroup LINK_QUALIF0
JMF	0:24d3eb812fd4	2278	* @{
JMF	0:24d3eb812fd4	2279	*/
JMF	0:24d3eb812fd4	2280
JMF	0:24d3eb812fd4	2281	/**
JMF	0:24d3eb812fd4	2282	* \brief LINK_QUALIF0 registers
JMF	0:24d3eb812fd4	2283	* \code
JMF	0:24d3eb812fd4	2284	* Default value: 0x00
JMF	0:24d3eb812fd4	2285	* Read
JMF	0:24d3eb812fd4	2286	*
JMF	0:24d3eb812fd4	2287	* 7:4 LQI [3:0]: LQI value of the received packet
JMF	0:24d3eb812fd4	2288	*
JMF	0:24d3eb812fd4	2289	* 3:0 AGC_WORD[3:0]: AGC word of the received packet
JMF	0:24d3eb812fd4	2290	* \endcode
JMF	0:24d3eb812fd4	2291	*/
JMF	0:24d3eb812fd4	2292	#define LINK_QUALIF0_BASE ((uint8_t)(0xC7)) /!< LQI value of the received packet [7:4]; AGC word of the received packet [3:0] /
JMF	0:24d3eb812fd4	2293
JMF	0:24d3eb812fd4	2294	/**
JMF	0:24d3eb812fd4	2295	* @}
JMF	0:24d3eb812fd4	2296	*/
JMF	0:24d3eb812fd4	2297
JMF	0:24d3eb812fd4	2298	/** @defgroup RSSI_LEVEL
JMF	0:24d3eb812fd4	2299	* @{
JMF	0:24d3eb812fd4	2300	*/
JMF	0:24d3eb812fd4	2301
JMF	0:24d3eb812fd4	2302	/**
JMF	0:24d3eb812fd4	2303	* \brief RSSI_LEVEL registers
JMF	0:24d3eb812fd4	2304	* \code
JMF	0:24d3eb812fd4	2305	* Default value: 0x00
JMF	0:24d3eb812fd4	2306	* Read
JMF	0:24d3eb812fd4	2307	*
JMF	0:24d3eb812fd4	2308	* 7:0 RSSI_LEVEL[7:0]: RSSI level of the received packet
JMF	0:24d3eb812fd4	2309	* \endcode
JMF	0:24d3eb812fd4	2310	*/
JMF	0:24d3eb812fd4	2311	#define RSSI_LEVEL_BASE ((uint8_t)(0xC8)) /!< RSSI level of the received packet /
JMF	0:24d3eb812fd4	2312
JMF	0:24d3eb812fd4	2313	/**
JMF	0:24d3eb812fd4	2314	* @}
JMF	0:24d3eb812fd4	2315	*/
JMF	0:24d3eb812fd4	2316
JMF	0:24d3eb812fd4	2317	/** @defgroup RSSI_FLT_Register
JMF	0:24d3eb812fd4	2318	* @{
JMF	0:24d3eb812fd4	2319	*/
JMF	0:24d3eb812fd4	2320
JMF	0:24d3eb812fd4	2321	/**
JMF	0:24d3eb812fd4	2322	* \brief RSSI register
JMF	0:24d3eb812fd4	2323	* \code
JMF	0:24d3eb812fd4	2324	* Read Write
JMF	0:24d3eb812fd4	2325	* Default value: 0xF3
JMF	0:24d3eb812fd4	2326	* 7:4 RSSI_FLT[3:0]: Gain of the RSSI filter
JMF	0:24d3eb812fd4	2327	*
JMF	0:24d3eb812fd4	2328	* 3:2 CS_MODE[1:0]: AFC loop gain in slow mode (2's log)
JMF	0:24d3eb812fd4	2329	*
JMF	0:24d3eb812fd4	2330	* CS_MODE1 \| CS_MODE0 \| CS Mode
JMF	0:24d3eb812fd4	2331	* -----------------------------------------------------------------------------------------
JMF	0:24d3eb812fd4	2332	* 0 \| 0 \| Static CS
JMF	0:24d3eb812fd4	2333	* 0 \| 1 \| Dynamic CS with 6dB dynamic threshold
JMF	0:24d3eb812fd4	2334	* 1 \| 0 \| Dynamic CS with 12dB dynamic threshold
JMF	0:24d3eb812fd4	2335	* 1 \| 1 \| Dynamic CS with 18dB dynamic threshold
JMF	0:24d3eb812fd4	2336	*
JMF	0:24d3eb812fd4	2337	* 1:0 OOK_PEAK_DECAY[1:0]: Peak decay control for OOK: 3 slow decay; 0 fast decay
JMF	0:24d3eb812fd4	2338	*
JMF	0:24d3eb812fd4	2339	* \endcode
JMF	0:24d3eb812fd4	2340	*/
JMF	0:24d3eb812fd4	2341	#define RSSI_FLT_BASE ((uint8_t)0x21) /*!< Gain of the RSSI filter; lower value is fast but inaccurate,
JMF	0:24d3eb812fd4	2342	higher value is slow and more accurate */
JMF	0:24d3eb812fd4	2343	#define RSSI_FLT_CS_MODE_MASK ((uint8_t)0x0C) /!< Carrier sense mode mask /
JMF	0:24d3eb812fd4	2344	#define RSSI_FLT_CS_MODE_STATIC ((uint8_t)0x00) /!< Carrier sense mode; static carrier sensing /
JMF	0:24d3eb812fd4	2345	#define RSSI_FLT_CS_MODE_DYNAMIC_6 ((uint8_t)0x04) /!< Carrier sense mode; dynamic carrier sensing with 6dB threshold /
JMF	0:24d3eb812fd4	2346	#define RSSI_FLT_CS_MODE_DYNAMIC_12 ((uint8_t)0x08) /!< Carrier sense mode; dynamic carrier sensing with 12dB threshold /
JMF	0:24d3eb812fd4	2347	#define RSSI_FLT_CS_MODE_DYNAMIC_18 ((uint8_t)0x0C) /!< Carrier sense mode; dynamic carrier sensing with 18dB threshold /
JMF	0:24d3eb812fd4	2348	#define RSSI_FLT_OOK_PEAK_DECAY_MASK ((uint8_t)0x03) /!< Peak decay control for OOK mask /
JMF	0:24d3eb812fd4	2349	#define RSSI_FLT_OOK_PEAK_DECAY_FAST ((uint8_t)0x00) /!< Peak decay control for OOK: fast decay /
JMF	0:24d3eb812fd4	2350	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_FAST ((uint8_t)0x01) /!< Peak decay control for OOK: medium_fast decay /
JMF	0:24d3eb812fd4	2351	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_SLOW ((uint8_t)0x02) /!< Peak decay control for OOK: medium_fast decay /
JMF	0:24d3eb812fd4	2352	#define RSSI_FLT_OOK_PEAK_DECAY_SLOW ((uint8_t)0x03) /!< Peak decay control for OOK: slow decay /
JMF	0:24d3eb812fd4	2353
JMF	0:24d3eb812fd4	2354	/**
JMF	0:24d3eb812fd4	2355	* @}
JMF	0:24d3eb812fd4	2356	*/
JMF	0:24d3eb812fd4	2357
JMF	0:24d3eb812fd4	2358	/** @defgroup RSSI_TH_Register
JMF	0:24d3eb812fd4	2359	* @{
JMF	0:24d3eb812fd4	2360	*/
JMF	0:24d3eb812fd4	2361
JMF	0:24d3eb812fd4	2362	/**
JMF	0:24d3eb812fd4	2363	* \brief RSSI_TH register
JMF	0:24d3eb812fd4	2364	* \code
JMF	0:24d3eb812fd4	2365	* Read Write
JMF	0:24d3eb812fd4	2366	* Default value: 0x24
JMF	0:24d3eb812fd4	2367	*
JMF	0:24d3eb812fd4	2368	* 7:0 RSSI_THRESHOLD [7:0]: Signal detect threshold in 0.5dB. -120dBm corresponds to 20
JMF	0:24d3eb812fd4	2369	* \endcode
JMF	0:24d3eb812fd4	2370	*/
JMF	0:24d3eb812fd4	2371	#define RSSI_TH_BASE ((uint8_t)0x22) /!< Signal detect threshold in 0.5dB stp. 20 correspond to -120 dBm /
JMF	0:24d3eb812fd4	2372
JMF	0:24d3eb812fd4	2373	/**
JMF	0:24d3eb812fd4	2374	* @}
JMF	0:24d3eb812fd4	2375	*/
JMF	0:24d3eb812fd4	2376
JMF	0:24d3eb812fd4	2377	/**
JMF	0:24d3eb812fd4	2378	* @}
JMF	0:24d3eb812fd4	2379	*/
JMF	0:24d3eb812fd4	2380
JMF	0:24d3eb812fd4	2381
JMF	0:24d3eb812fd4	2382	/** @defgroup FIFO_Registers
JMF	0:24d3eb812fd4	2383	* @{
JMF	0:24d3eb812fd4	2384	*/
JMF	0:24d3eb812fd4	2385
JMF	0:24d3eb812fd4	2386	/** @defgroup FIFO_CONFIG3_Register
JMF	0:24d3eb812fd4	2387	* @{
JMF	0:24d3eb812fd4	2388	*/
JMF	0:24d3eb812fd4	2389
JMF	0:24d3eb812fd4	2390	/**
JMF	0:24d3eb812fd4	2391	* \brief FIFO_CONFIG3 registers
JMF	0:24d3eb812fd4	2392	* \code
JMF	0:24d3eb812fd4	2393	* Default value: 0x30
JMF	0:24d3eb812fd4	2394	* Read Write
JMF	0:24d3eb812fd4	2395	* 7 Reserved.
JMF	0:24d3eb812fd4	2396	*
JMF	0:24d3eb812fd4	2397	* 6:0 rxafthr [6:0]: FIFO Almost Full threshold for rx fifo.
JMF	0:24d3eb812fd4	2398	*
JMF	0:24d3eb812fd4	2399	* \endcode
JMF	0:24d3eb812fd4	2400	*/
JMF	0:24d3eb812fd4	2401	#define FIFO_CONFIG3_RXAFTHR_BASE ((uint8_t)0x3E) /!< FIFO Almost Full threshold for rx fifo [6:0] /
JMF	0:24d3eb812fd4	2402
JMF	0:24d3eb812fd4	2403	/**
JMF	0:24d3eb812fd4	2404	* @}
JMF	0:24d3eb812fd4	2405	*/
JMF	0:24d3eb812fd4	2406
JMF	0:24d3eb812fd4	2407	/** @defgroup FIFO_CONFIG2_Register
JMF	0:24d3eb812fd4	2408	* @{
JMF	0:24d3eb812fd4	2409	*/
JMF	0:24d3eb812fd4	2410
JMF	0:24d3eb812fd4	2411	/**
JMF	0:24d3eb812fd4	2412	* \brief FIFO_CONFIG2 registers
JMF	0:24d3eb812fd4	2413	* \code
JMF	0:24d3eb812fd4	2414	* Default value: 0x30
JMF	0:24d3eb812fd4	2415	* Read Write
JMF	0:24d3eb812fd4	2416	* 7 Reserved.
JMF	0:24d3eb812fd4	2417	*
JMF	0:24d3eb812fd4	2418	* 6:0 rxaethr [6:0]: FIFO Almost Empty threshold for rx fifo.
JMF	0:24d3eb812fd4	2419	*
JMF	0:24d3eb812fd4	2420	* \endcode
JMF	0:24d3eb812fd4	2421	*/
JMF	0:24d3eb812fd4	2422	#define FIFO_CONFIG2_RXAETHR_BASE ((uint8_t)0x3F) /!< FIFO Almost Empty threshold for rx fifo [6:0] /
JMF	0:24d3eb812fd4	2423
JMF	0:24d3eb812fd4	2424	/**
JMF	0:24d3eb812fd4	2425	* @}
JMF	0:24d3eb812fd4	2426	*/
JMF	0:24d3eb812fd4	2427
JMF	0:24d3eb812fd4	2428	/** @defgroup FIFO_CONFIG1_Register
JMF	0:24d3eb812fd4	2429	* @{
JMF	0:24d3eb812fd4	2430	*/
JMF	0:24d3eb812fd4	2431
JMF	0:24d3eb812fd4	2432	/**
JMF	0:24d3eb812fd4	2433	* \brief FIFO_CONFIG1 registers
JMF	0:24d3eb812fd4	2434	* \code
JMF	0:24d3eb812fd4	2435	* Default value: 0x30
JMF	0:24d3eb812fd4	2436	* Read Write
JMF	0:24d3eb812fd4	2437	* 7 Reserved.
JMF	0:24d3eb812fd4	2438	*
JMF	0:24d3eb812fd4	2439	* 6:0 txafthr [6:0]: FIFO Almost Full threshold for tx fifo.
JMF	0:24d3eb812fd4	2440	*
JMF	0:24d3eb812fd4	2441	* \endcode
JMF	0:24d3eb812fd4	2442	*/
JMF	0:24d3eb812fd4	2443	#define FIFO_CONFIG1_TXAFTHR_BASE ((uint8_t)0x40) /!< FIFO Almost Full threshold for tx fifo [6:0] /
JMF	0:24d3eb812fd4	2444
JMF	0:24d3eb812fd4	2445	/**
JMF	0:24d3eb812fd4	2446	* @}
JMF	0:24d3eb812fd4	2447	*/
JMF	0:24d3eb812fd4	2448
JMF	0:24d3eb812fd4	2449	/** @defgroup FIFO_CONFIG0_Register
JMF	0:24d3eb812fd4	2450	* @{
JMF	0:24d3eb812fd4	2451	*/
JMF	0:24d3eb812fd4	2452
JMF	0:24d3eb812fd4	2453	/**
JMF	0:24d3eb812fd4	2454	* \brief FIFO_CONFIG0 registers
JMF	0:24d3eb812fd4	2455	* \code
JMF	0:24d3eb812fd4	2456	* Default value: 0x30
JMF	0:24d3eb812fd4	2457	* Read Write
JMF	0:24d3eb812fd4	2458	* 7 Reserved.
JMF	0:24d3eb812fd4	2459	*
JMF	0:24d3eb812fd4	2460	* 6:0 txaethr [6:0]: FIFO Almost Empty threshold for tx fifo.
JMF	0:24d3eb812fd4	2461	*
JMF	0:24d3eb812fd4	2462	* \endcode
JMF	0:24d3eb812fd4	2463	*/
JMF	0:24d3eb812fd4	2464	#define FIFO_CONFIG0_TXAETHR_BASE ((uint8_t)0x41) /!< FIFO Almost Empty threshold for tx fifo [6:0] /
JMF	0:24d3eb812fd4	2465
JMF	0:24d3eb812fd4	2466	/**
JMF	0:24d3eb812fd4	2467	* @}
JMF	0:24d3eb812fd4	2468	*/
JMF	0:24d3eb812fd4	2469
JMF	0:24d3eb812fd4	2470	/** @defgroup LINEAR_FIFO_STATUS1_Register
JMF	0:24d3eb812fd4	2471	* @{
JMF	0:24d3eb812fd4	2472	*/
JMF	0:24d3eb812fd4	2473
JMF	0:24d3eb812fd4	2474	/**
JMF	0:24d3eb812fd4	2475	* \brief LINEAR_FIFO_STATUS1 registers
JMF	0:24d3eb812fd4	2476	* \code
JMF	0:24d3eb812fd4	2477	* Default value: 0x00
JMF	0:24d3eb812fd4	2478	* Read
JMF	0:24d3eb812fd4	2479	*
JMF	0:24d3eb812fd4	2480	* 7 Reserved.
JMF	0:24d3eb812fd4	2481	*
JMF	0:24d3eb812fd4	2482	* 6:0 elem_txfifo[6:0]: Number of elements in the linear TXFIFO (<=96)
JMF	0:24d3eb812fd4	2483	* \endcode
JMF	0:24d3eb812fd4	2484	*/
JMF	0:24d3eb812fd4	2485	#define LINEAR_FIFO_STATUS1_BASE ((uint8_t)(0xE6)) /!< Number of elements in the linear TX FIFO [6:0] (<=96) /
JMF	0:24d3eb812fd4	2486
JMF	0:24d3eb812fd4	2487	/**
JMF	0:24d3eb812fd4	2488	* @}
JMF	0:24d3eb812fd4	2489	*/
JMF	0:24d3eb812fd4	2490
JMF	0:24d3eb812fd4	2491	/** @defgroup LINEAR_FIFO_STATUS0_Register
JMF	0:24d3eb812fd4	2492	* @{
JMF	0:24d3eb812fd4	2493	*/
JMF	0:24d3eb812fd4	2494
JMF	0:24d3eb812fd4	2495	/**
JMF	0:24d3eb812fd4	2496	* \brief LINEAR_FIFO_STATUS0 registers
JMF	0:24d3eb812fd4	2497	* \code
JMF	0:24d3eb812fd4	2498	* Default value: 0x00
JMF	0:24d3eb812fd4	2499	* Read
JMF	0:24d3eb812fd4	2500	*
JMF	0:24d3eb812fd4	2501	* 7 Reserved.
JMF	0:24d3eb812fd4	2502	*
JMF	0:24d3eb812fd4	2503	* 6:0 elem_rxfifo[6:0]: Number of elements in the linear RXFIFO (<=96)
JMF	0:24d3eb812fd4	2504	* \endcode
JMF	0:24d3eb812fd4	2505	*/
JMF	0:24d3eb812fd4	2506	#define LINEAR_FIFO_STATUS0_BASE ((uint8_t)(0xE7)) /!< Number of elements in the linear RX FIFO [6:0] (<=96) /
JMF	0:24d3eb812fd4	2507
JMF	0:24d3eb812fd4	2508	/**
JMF	0:24d3eb812fd4	2509	* @}
JMF	0:24d3eb812fd4	2510	*/
JMF	0:24d3eb812fd4	2511
JMF	0:24d3eb812fd4	2512
JMF	0:24d3eb812fd4	2513	/**
JMF	0:24d3eb812fd4	2514	* @}
JMF	0:24d3eb812fd4	2515	*/
JMF	0:24d3eb812fd4	2516
JMF	0:24d3eb812fd4	2517
JMF	0:24d3eb812fd4	2518	/** @defgroup Calibration_Registers
JMF	0:24d3eb812fd4	2519	* @{
JMF	0:24d3eb812fd4	2520	*/
JMF	0:24d3eb812fd4	2521
JMF	0:24d3eb812fd4	2522	/** @defgroup RCO_VCO_CALIBR_IN2_Register
JMF	0:24d3eb812fd4	2523	* @{
JMF	0:24d3eb812fd4	2524	*/
JMF	0:24d3eb812fd4	2525
JMF	0:24d3eb812fd4	2526	/**
JMF	0:24d3eb812fd4	2527	* \brief RCO_VCO_CALIBR_IN2 registers
JMF	0:24d3eb812fd4	2528	* \code
JMF	0:24d3eb812fd4	2529	* Default value: 0x70
JMF	0:24d3eb812fd4	2530	* Read Write
JMF	0:24d3eb812fd4	2531	* 7:4 RWT_IN[3:0]: RaWThermometric word value for the RCO [7:4]
JMF	0:24d3eb812fd4	2532	*
JMF	0:24d3eb812fd4	2533	* 3:0 RFB_IN[4:1]: ResistorFineBit word value for the RCO (first 4 bits)
JMF	0:24d3eb812fd4	2534	* \endcode
JMF	0:24d3eb812fd4	2535	*/
JMF	0:24d3eb812fd4	2536	#define RCO_VCO_CALIBR_IN2_BASE ((uint8_t)0x6D) /!< RaWThermometric word value for the RCO [7:4]; ResistorFineBit word value for the RCO [3:0] /
JMF	0:24d3eb812fd4	2537
JMF	0:24d3eb812fd4	2538	/**
JMF	0:24d3eb812fd4	2539	* @}
JMF	0:24d3eb812fd4	2540	*/
JMF	0:24d3eb812fd4	2541
JMF	0:24d3eb812fd4	2542	/** @defgroup RCO_VCO_CALIBR_IN1_Register
JMF	0:24d3eb812fd4	2543	* @{
JMF	0:24d3eb812fd4	2544	*/
JMF	0:24d3eb812fd4	2545
JMF	0:24d3eb812fd4	2546	/**
JMF	0:24d3eb812fd4	2547	* \brief RCO_VCO_CALIBR_IN1 registers
JMF	0:24d3eb812fd4	2548	* \code
JMF	0:24d3eb812fd4	2549	* Default value: 0x48
JMF	0:24d3eb812fd4	2550	* Read Write
JMF	0:24d3eb812fd4	2551	*
JMF	0:24d3eb812fd4	2552	* 7 RFB_IN[0]: ResistorFineBit word value for the RCO (LSb)
JMF	0:24d3eb812fd4	2553	*
JMF	0:24d3eb812fd4	2554	* 6:0 VCO_CALIBR_TX[6:0]: Word value for the VCO to be used in TX mode
JMF	0:24d3eb812fd4	2555	* \endcode
JMF	0:24d3eb812fd4	2556	*/
JMF	0:24d3eb812fd4	2557	#define RCO_VCO_CALIBR_IN1_BASE ((uint8_t)0x6E) /!< ResistorFineBit word value for the RCO [7]; Word value for the VCO to be used in TX mode [6:0]/
JMF	0:24d3eb812fd4	2558
JMF	0:24d3eb812fd4	2559	/**
JMF	0:24d3eb812fd4	2560	* @}
JMF	0:24d3eb812fd4	2561	*/
JMF	0:24d3eb812fd4	2562
JMF	0:24d3eb812fd4	2563	/** @defgroup RCO_VCO_CALIBR_IN0_Register
JMF	0:24d3eb812fd4	2564	* @{
JMF	0:24d3eb812fd4	2565	*/
JMF	0:24d3eb812fd4	2566
JMF	0:24d3eb812fd4	2567	/**
JMF	0:24d3eb812fd4	2568	* \brief RCO_VCO_CALIBR_IN0 registers
JMF	0:24d3eb812fd4	2569	* \code
JMF	0:24d3eb812fd4	2570	* Default value: 0x48
JMF	0:24d3eb812fd4	2571	* Read Write
JMF	0:24d3eb812fd4	2572	*
JMF	0:24d3eb812fd4	2573	* 7 Reserved.
JMF	0:24d3eb812fd4	2574	*
JMF	0:24d3eb812fd4	2575	* 6:0 VCO_CALIBR_RX[6:0]: Word value for the VCO to be used in RX mode
JMF	0:24d3eb812fd4	2576	* \endcode
JMF	0:24d3eb812fd4	2577	*/
JMF	0:24d3eb812fd4	2578	#define RCO_VCO_CALIBR_IN0_BASE ((uint8_t)0x6F) /!< Word value for the VCO to be used in RX mode [6:0] /
JMF	0:24d3eb812fd4	2579
JMF	0:24d3eb812fd4	2580	/**
JMF	0:24d3eb812fd4	2581	* @}
JMF	0:24d3eb812fd4	2582	*/
JMF	0:24d3eb812fd4	2583
JMF	0:24d3eb812fd4	2584	/** @defgroup RCO_VCO_CALIBR_OUT1_Register
JMF	0:24d3eb812fd4	2585	* @{
JMF	0:24d3eb812fd4	2586	*/
JMF	0:24d3eb812fd4	2587
JMF	0:24d3eb812fd4	2588	/**
JMF	0:24d3eb812fd4	2589	* \brief RCO_VCO_CALIBR_OUT1 registers
JMF	0:24d3eb812fd4	2590	* \code
JMF	0:24d3eb812fd4	2591	* Default value: 0x00
JMF	0:24d3eb812fd4	2592	* Read
JMF	0:24d3eb812fd4	2593	*
JMF	0:24d3eb812fd4	2594	* 7:4 RWT_OUT[3:0]: RWT word from internal RCO calibrator
JMF	0:24d3eb812fd4	2595	*
JMF	0:24d3eb812fd4	2596	* 3:0 RFB_OUT[4:1]: RFB word from internal RCO calibrator (upper part)
JMF	0:24d3eb812fd4	2597	* \endcode
JMF	0:24d3eb812fd4	2598	*/
JMF	0:24d3eb812fd4	2599	#define RCO_VCO_CALIBR_OUT1_BASE ((uint8_t)(0xE4)) /*!< RaWThermometric RWT word from internal RCO calibrator [7];
JMF	0:24d3eb812fd4	2600	ResistorFineBit RFB word from internal RCO oscillator [6:0] */
JMF	0:24d3eb812fd4	2601	/**
JMF	0:24d3eb812fd4	2602	* @}
JMF	0:24d3eb812fd4	2603	*/
JMF	0:24d3eb812fd4	2604
JMF	0:24d3eb812fd4	2605	/** @defgroup RCO_VCO_CALIBR_OUT0_Register
JMF	0:24d3eb812fd4	2606	* @{
JMF	0:24d3eb812fd4	2607	*/
JMF	0:24d3eb812fd4	2608
JMF	0:24d3eb812fd4	2609	/**
JMF	0:24d3eb812fd4	2610	* \brief RCO_VCO_CALIBR_OUT0 registers
JMF	0:24d3eb812fd4	2611	* \code
JMF	0:24d3eb812fd4	2612	* Default value: 0x00
JMF	0:24d3eb812fd4	2613	* Read
JMF	0:24d3eb812fd4	2614	*
JMF	0:24d3eb812fd4	2615	* 7 RFB_OUT[0]: RFB word from internal RCO calibrator (last bit LSB)
JMF	0:24d3eb812fd4	2616	*
JMF	0:24d3eb812fd4	2617	* 6:0 VCO_CALIBR_DATA[6:0]: Output word from internal VCO calibrator
JMF	0:24d3eb812fd4	2618	* \endcode
JMF	0:24d3eb812fd4	2619	*/
JMF	0:24d3eb812fd4	2620	#define RCO_VCO_CALIBR_OUT0_BASE ((uint8_t)(0xE5)) /*!< ResistorFineBit RFB word from internal RCO oscillator [0];
JMF	0:24d3eb812fd4	2621	Output word from internal calibrator [6:0]; */
JMF	0:24d3eb812fd4	2622	/**
JMF	0:24d3eb812fd4	2623	* @}
JMF	0:24d3eb812fd4	2624	*/
JMF	0:24d3eb812fd4	2625
JMF	0:24d3eb812fd4	2626	/**
JMF	0:24d3eb812fd4	2627	* @}
JMF	0:24d3eb812fd4	2628	*/
JMF	0:24d3eb812fd4	2629
JMF	0:24d3eb812fd4	2630
JMF	0:24d3eb812fd4	2631	/** @defgroup AES_Registers
JMF	0:24d3eb812fd4	2632	* @{
JMF	0:24d3eb812fd4	2633	*/
JMF	0:24d3eb812fd4	2634
JMF	0:24d3eb812fd4	2635	/** @defgroup AES_KEY_IN_Register
JMF	0:24d3eb812fd4	2636	* @{
JMF	0:24d3eb812fd4	2637	*/
JMF	0:24d3eb812fd4	2638
JMF	0:24d3eb812fd4	2639	/**
JMF	0:24d3eb812fd4	2640	* \brief AES_KEY_INx registers
JMF	0:24d3eb812fd4	2641	* \code
JMF	0:24d3eb812fd4	2642	* Default value: 0x00
JMF	0:24d3eb812fd4	2643	* Read Write
JMF	0:24d3eb812fd4	2644	*
JMF	0:24d3eb812fd4	2645	* 7:0 AES_KEY_INx[7:0]: AES engine key input (total - 128 bits)
JMF	0:24d3eb812fd4	2646	* \endcode
JMF	0:24d3eb812fd4	2647	*/
JMF	0:24d3eb812fd4	2648	#define AES_KEY_IN_15_BASE ((uint8_t)0x70) /!< AES engine key input 15 /
JMF	0:24d3eb812fd4	2649
JMF	0:24d3eb812fd4	2650	#define AES_KEY_IN_14_BASE ((uint8_t)0x71) /!< AES engine key input 14 /
JMF	0:24d3eb812fd4	2651
JMF	0:24d3eb812fd4	2652	#define AES_KEY_IN_13_BASE ((uint8_t)0x72) /!< AES engine key input 13 /
JMF	0:24d3eb812fd4	2653
JMF	0:24d3eb812fd4	2654	#define AES_KEY_IN_12_BASE ((uint8_t)0x73) /!< AES engine key input 12 /
JMF	0:24d3eb812fd4	2655
JMF	0:24d3eb812fd4	2656	#define AES_KEY_IN_11_BASE ((uint8_t)0x74) /!< AES engine key input 11 /
JMF	0:24d3eb812fd4	2657
JMF	0:24d3eb812fd4	2658	#define AES_KEY_IN_10_BASE ((uint8_t)0x75) /!< AES engine key input 10 /
JMF	0:24d3eb812fd4	2659
JMF	0:24d3eb812fd4	2660	#define AES_KEY_IN_9_BASE ((uint8_t)0x76) /!< AES engine key input 9 /
JMF	0:24d3eb812fd4	2661
JMF	0:24d3eb812fd4	2662	#define AES_KEY_IN_8_BASE ((uint8_t)0x77) /!< AES engine key input 8 /
JMF	0:24d3eb812fd4	2663
JMF	0:24d3eb812fd4	2664	#define AES_KEY_IN_7_BASE ((uint8_t)0x78) /!< AES engine key input 7 /
JMF	0:24d3eb812fd4	2665
JMF	0:24d3eb812fd4	2666	#define AES_KEY_IN_6_BASE ((uint8_t)0x79) /!< AES engine key input 6 /
JMF	0:24d3eb812fd4	2667
JMF	0:24d3eb812fd4	2668	#define AES_KEY_IN_5_BASE ((uint8_t)0x7A) /!< AES engine key input 5 /
JMF	0:24d3eb812fd4	2669
JMF	0:24d3eb812fd4	2670	#define AES_KEY_IN_4_BASE ((uint8_t)0x7B) /!< AES engine key input 4 /
JMF	0:24d3eb812fd4	2671
JMF	0:24d3eb812fd4	2672	#define AES_KEY_IN_3_BASE ((uint8_t)0x7C) /!< AES engine key input 3 /
JMF	0:24d3eb812fd4	2673
JMF	0:24d3eb812fd4	2674	#define AES_KEY_IN_2_BASE ((uint8_t)0x7D) /!< AES engine key input 2 /
JMF	0:24d3eb812fd4	2675
JMF	0:24d3eb812fd4	2676	#define AES_KEY_IN_1_BASE ((uint8_t)0x7E) /!< AES engine key input 1 /
JMF	0:24d3eb812fd4	2677
JMF	0:24d3eb812fd4	2678	#define AES_KEY_IN_0_BASE ((uint8_t)0x7F) /!< AES engine key input 0 /
JMF	0:24d3eb812fd4	2679
JMF	0:24d3eb812fd4	2680	/**
JMF	0:24d3eb812fd4	2681	* @}
JMF	0:24d3eb812fd4	2682	*/
JMF	0:24d3eb812fd4	2683
JMF	0:24d3eb812fd4	2684	/** @defgroup AES_DATA_IN_Register
JMF	0:24d3eb812fd4	2685	* @{
JMF	0:24d3eb812fd4	2686	*/
JMF	0:24d3eb812fd4	2687
JMF	0:24d3eb812fd4	2688	/**
JMF	0:24d3eb812fd4	2689	* \brief AES_DATA_INx registers
JMF	0:24d3eb812fd4	2690	* \code
JMF	0:24d3eb812fd4	2691	* Default value: 0x00
JMF	0:24d3eb812fd4	2692	* Read Write
JMF	0:24d3eb812fd4	2693	*
JMF	0:24d3eb812fd4	2694	* 7:0 AES_DATA_INx[7:0]: AES engine data input (total - 128 bits)
JMF	0:24d3eb812fd4	2695	* \endcode
JMF	0:24d3eb812fd4	2696	*/
JMF	0:24d3eb812fd4	2697	#define AES_DATA_IN_15_BASE ((uint8_t)0x80) /*!< AES engine data input 15
JMF	0:24d3eb812fd4	2698	Take care: Address is in reverse order respect data numbering; eg.: 0x81 -> AES_data14[7:0] */
JMF	0:24d3eb812fd4	2699	#define AES_DATA_IN_14_BASE ((uint8_t)0x81) /!< AES engine data input 14 /
JMF	0:24d3eb812fd4	2700
JMF	0:24d3eb812fd4	2701	#define AES_DATA_IN_13_BASE ((uint8_t)0x82) /!< AES engine data input 13 /
JMF	0:24d3eb812fd4	2702
JMF	0:24d3eb812fd4	2703	#define AES_DATA_IN_12_BASE ((uint8_t)0x83) /!< AES engine data input 12 /
JMF	0:24d3eb812fd4	2704
JMF	0:24d3eb812fd4	2705	#define AES_DATA_IN_11_BASE ((uint8_t)0x84) /!< AES engine data input 11 /
JMF	0:24d3eb812fd4	2706
JMF	0:24d3eb812fd4	2707	#define AES_DATA_IN_10_BASE ((uint8_t)0x85) /!< AES engine data input 10 /
JMF	0:24d3eb812fd4	2708
JMF	0:24d3eb812fd4	2709	#define AES_DATA_IN_9_BASE ((uint8_t)0x86) /!< AES engine data input 9 /
JMF	0:24d3eb812fd4	2710
JMF	0:24d3eb812fd4	2711	#define AES_DATA_IN_8_BASE ((uint8_t)0x87) /!< AES engine data input 8 /
JMF	0:24d3eb812fd4	2712
JMF	0:24d3eb812fd4	2713	#define AES_DATA_IN_7_BASE ((uint8_t)0x88) /!< AES engine data input 7 /
JMF	0:24d3eb812fd4	2714
JMF	0:24d3eb812fd4	2715	#define AES_DATA_IN_6_BASE ((uint8_t)0x89) /!< AES engine data input 6 /
JMF	0:24d3eb812fd4	2716
JMF	0:24d3eb812fd4	2717	#define AES_DATA_IN_5_BASE ((uint8_t)0x8A) /!< AES engine data input 5 /
JMF	0:24d3eb812fd4	2718
JMF	0:24d3eb812fd4	2719	#define AES_DATA_IN_4_BASE ((uint8_t)0x8B) /!< AES engine data input 4 /
JMF	0:24d3eb812fd4	2720
JMF	0:24d3eb812fd4	2721	#define AES_DATA_IN_3_BASE ((uint8_t)0x8C) /!< AES engine data input 3 /
JMF	0:24d3eb812fd4	2722
JMF	0:24d3eb812fd4	2723	#define AES_DATA_IN_2_BASE ((uint8_t)0x8D) /!< AES engine data input 2 /
JMF	0:24d3eb812fd4	2724
JMF	0:24d3eb812fd4	2725	#define AES_DATA_IN_1_BASE ((uint8_t)0x8E) /!< AES engine data input 1 /
JMF	0:24d3eb812fd4	2726
JMF	0:24d3eb812fd4	2727	#define AES_DATA_IN_0_BASE ((uint8_t)0x8F) /!< AES engine data input 0 /
JMF	0:24d3eb812fd4	2728
JMF	0:24d3eb812fd4	2729	/**
JMF	0:24d3eb812fd4	2730	* @}
JMF	0:24d3eb812fd4	2731	*/
JMF	0:24d3eb812fd4	2732
JMF	0:24d3eb812fd4	2733	/** @defgroup AES_DATA_OUT_Register
JMF	0:24d3eb812fd4	2734	* @{
JMF	0:24d3eb812fd4	2735	*/
JMF	0:24d3eb812fd4	2736
JMF	0:24d3eb812fd4	2737	/**
JMF	0:24d3eb812fd4	2738	* \brief AES_DATA_OUT[15:0] registers
JMF	0:24d3eb812fd4	2739	* \code
JMF	0:24d3eb812fd4	2740	* Default value: 0x00
JMF	0:24d3eb812fd4	2741	* Read
JMF	0:24d3eb812fd4	2742	*
JMF	0:24d3eb812fd4	2743	* 7:0 AES_DATA_OUTx[7:0]: AES engine data output (128 bits)
JMF	0:24d3eb812fd4	2744	* \endcode
JMF	0:24d3eb812fd4	2745	*/
JMF	0:24d3eb812fd4	2746	#define AES_DATA_OUT_15_BASE ((uint8_t)(0xD4)) /!< AES engine data output 15 /
JMF	0:24d3eb812fd4	2747
JMF	0:24d3eb812fd4	2748	#define AES_DATA_OUT_14_BASE ((uint8_t)(0xD5)) /!< AES engine data output 14 /
JMF	0:24d3eb812fd4	2749
JMF	0:24d3eb812fd4	2750	#define AES_DATA_OUT_13_BASE ((uint8_t)(0xD6)) /!< AES engine data output 13 /
JMF	0:24d3eb812fd4	2751
JMF	0:24d3eb812fd4	2752	#define AES_DATA_OUT_12_BASE ((uint8_t)(0xD7)) /!< AES engine data output 12 /
JMF	0:24d3eb812fd4	2753
JMF	0:24d3eb812fd4	2754	#define AES_DATA_OUT_11_BASE ((uint8_t)(0xD8)) /!< AES engine data output 11 /
JMF	0:24d3eb812fd4	2755
JMF	0:24d3eb812fd4	2756	#define AES_DATA_OUT_10_BASE ((uint8_t)(0xD9)) /!< AES engine data output 10 /
JMF	0:24d3eb812fd4	2757
JMF	0:24d3eb812fd4	2758	#define AES_DATA_OUT_9_BASE ((uint8_t)(0xDA)) /!< AES engine data output 9 /
JMF	0:24d3eb812fd4	2759
JMF	0:24d3eb812fd4	2760	#define AES_DATA_OUT_8_BASE ((uint8_t)(0xDB)) /!< AES engine data output 8 /
JMF	0:24d3eb812fd4	2761
JMF	0:24d3eb812fd4	2762	#define AES_DATA_OUT_7_BASE ((uint8_t)(0xDC)) /!< AES engine data output 7 /
JMF	0:24d3eb812fd4	2763
JMF	0:24d3eb812fd4	2764	#define AES_DATA_OUT_6_BASE ((uint8_t)(0xDD)) /!< AES engine data output 6 /
JMF	0:24d3eb812fd4	2765
JMF	0:24d3eb812fd4	2766	#define AES_DATA_OUT_5_BASE ((uint8_t)(0xDE)) /!< AES engine data output 5 /
JMF	0:24d3eb812fd4	2767
JMF	0:24d3eb812fd4	2768	#define AES_DATA_OUT_4_BASE ((uint8_t)(0xDF)) /!< AES engine data output 4 /
JMF	0:24d3eb812fd4	2769
JMF	0:24d3eb812fd4	2770	#define AES_DATA_OUT_3_BASE ((uint8_t)(0xE0)) /!< AES engine data output 3 /
JMF	0:24d3eb812fd4	2771
JMF	0:24d3eb812fd4	2772	#define AES_DATA_OUT_2_BASE ((uint8_t)(0xE1)) /!< AES engine data output 2 /
JMF	0:24d3eb812fd4	2773
JMF	0:24d3eb812fd4	2774	#define AES_DATA_OUT_1_BASE ((uint8_t)(0xE2)) /!< AES engine data output 1 /
JMF	0:24d3eb812fd4	2775
JMF	0:24d3eb812fd4	2776	#define AES_DATA_OUT_0_BASE ((uint8_t)(0xE3)) /!< AES engine data output 0 /
JMF	0:24d3eb812fd4	2777
JMF	0:24d3eb812fd4	2778	/**
JMF	0:24d3eb812fd4	2779	* @}
JMF	0:24d3eb812fd4	2780	*/
JMF	0:24d3eb812fd4	2781
JMF	0:24d3eb812fd4	2782	/**
JMF	0:24d3eb812fd4	2783	* @}
JMF	0:24d3eb812fd4	2784	*/
JMF	0:24d3eb812fd4	2785
JMF	0:24d3eb812fd4	2786	/** @defgroup IRQ_Registers
JMF	0:24d3eb812fd4	2787	* @{
JMF	0:24d3eb812fd4	2788	*/
JMF	0:24d3eb812fd4	2789
JMF	0:24d3eb812fd4	2790	/** @defgroup IRQ_MASK0_Register
JMF	0:24d3eb812fd4	2791	* @{
JMF	0:24d3eb812fd4	2792	*/
JMF	0:24d3eb812fd4	2793
JMF	0:24d3eb812fd4	2794	/**
JMF	0:24d3eb812fd4	2795	* \brief IRQ_MASK0 registers
JMF	0:24d3eb812fd4	2796	* \code
JMF	0:24d3eb812fd4	2797	* Default value: 0x00
JMF	0:24d3eb812fd4	2798	* Read Write
JMF	0:24d3eb812fd4	2799	*
JMF	0:24d3eb812fd4	2800	* 7:0 INT_MASK0: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
JMF	0:24d3eb812fd4	2801	*
JMF	0:24d3eb812fd4	2802	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	2803	* -------------------------------------------------------
JMF	0:24d3eb812fd4	2804	* 0 \| RX data ready
JMF	0:24d3eb812fd4	2805	* 1 \| RX data discarded (upon filtering)
JMF	0:24d3eb812fd4	2806	* 2 \| TX data sent
JMF	0:24d3eb812fd4	2807	* 3 \| Max re-TX reached
JMF	0:24d3eb812fd4	2808	* 4 \| CRC error
JMF	0:24d3eb812fd4	2809	* 5 \| TX FIFO underflow/overflow error
JMF	0:24d3eb812fd4	2810	* 6 \| RX FIFO underflow/overflow error
JMF	0:24d3eb812fd4	2811	* 7 \| TX FIFO almost full
JMF	0:24d3eb812fd4	2812	* \endcode
JMF	0:24d3eb812fd4	2813	*/
JMF	0:24d3eb812fd4	2814
JMF	0:24d3eb812fd4	2815
JMF	0:24d3eb812fd4	2816	#define IRQ_MASK0_BASE ((uint8_t)0x93) /!< IRQ_MASK is split into 4 registers/
JMF	0:24d3eb812fd4	2817
JMF	0:24d3eb812fd4	2818	#define IRQ_MASK0_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
JMF	0:24d3eb812fd4	2819	#define IRQ_MASK0_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
JMF	0:24d3eb812fd4	2820	#define IRQ_MASK0_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
JMF	0:24d3eb812fd4	2821	#define IRQ_MASK0_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
JMF	0:24d3eb812fd4	2822	#define IRQ_MASK0_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
JMF	0:24d3eb812fd4	2823	#define IRQ_MASK0_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
JMF	0:24d3eb812fd4	2824	#define IRQ_MASK0_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
JMF	0:24d3eb812fd4	2825	#define IRQ_MASK0_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
JMF	0:24d3eb812fd4	2826
JMF	0:24d3eb812fd4	2827	/**
JMF	0:24d3eb812fd4	2828	* @}
JMF	0:24d3eb812fd4	2829	*/
JMF	0:24d3eb812fd4	2830
JMF	0:24d3eb812fd4	2831	/** @defgroup IRQ_MASK1_Register
JMF	0:24d3eb812fd4	2832	* @{
JMF	0:24d3eb812fd4	2833	*/
JMF	0:24d3eb812fd4	2834
JMF	0:24d3eb812fd4	2835	/**
JMF	0:24d3eb812fd4	2836	* \brief IRQ_MASK1 registers
JMF	0:24d3eb812fd4	2837	* \code
JMF	0:24d3eb812fd4	2838	* Default value: 0x00
JMF	0:24d3eb812fd4	2839	* Read Write
JMF	0:24d3eb812fd4	2840	*
JMF	0:24d3eb812fd4	2841	* 7:0 INT_MASK1: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
JMF	0:24d3eb812fd4	2842	*
JMF	0:24d3eb812fd4	2843	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	2844	* -------------------------------------------------------
JMF	0:24d3eb812fd4	2845	* 8 \| TX FIFO almost empty
JMF	0:24d3eb812fd4	2846	* 9 \| RX FIFO almost full
JMF	0:24d3eb812fd4	2847	* 10 \| RX FIFO almost empty
JMF	0:24d3eb812fd4	2848	* 11 \| Max number of back-off during CCA
JMF	0:24d3eb812fd4	2849	* 12 \| Valid preamble detected
JMF	0:24d3eb812fd4	2850	* 13 \| Sync word detected
JMF	0:24d3eb812fd4	2851	* 14 \| RSSI above threshold (Carrier Sense)
JMF	0:24d3eb812fd4	2852	* 15 \| Wake-up timeout in LDCR mode13
JMF	0:24d3eb812fd4	2853	* \endcode
JMF	0:24d3eb812fd4	2854	*/
JMF	0:24d3eb812fd4	2855
JMF	0:24d3eb812fd4	2856	#define IRQ_MASK1_BASE ((uint8_t)0x92) /!< IRQ_MASK is split into 4 registers/
JMF	0:24d3eb812fd4	2857
JMF	0:24d3eb812fd4	2858	#define IRQ_MASK1_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
JMF	0:24d3eb812fd4	2859	#define IRQ_MASK1_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
JMF	0:24d3eb812fd4	2860	#define IRQ_MASK1_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
JMF	0:24d3eb812fd4	2861	#define IRQ_MASK1_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
JMF	0:24d3eb812fd4	2862	#define IRQ_MASK1_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
JMF	0:24d3eb812fd4	2863	#define IRQ_MASK1_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
JMF	0:24d3eb812fd4	2864	#define IRQ_MASK1_RSSI_ABOVE_TH ((uint8_t)0x40) /!< IRQ: RSSI above threshold /
JMF	0:24d3eb812fd4	2865	#define IRQ_MASK1_WKUP_TOUT_LDC ((uint8_t)0x80) /!< IRQ: Wake-up timeout in LDC mode /
JMF	0:24d3eb812fd4	2866
JMF	0:24d3eb812fd4	2867	/**
JMF	0:24d3eb812fd4	2868	* @}
JMF	0:24d3eb812fd4	2869	*/
JMF	0:24d3eb812fd4	2870
JMF	0:24d3eb812fd4	2871	/** @defgroup IRQ_MASK2_Register
JMF	0:24d3eb812fd4	2872	* @{
JMF	0:24d3eb812fd4	2873	*/
JMF	0:24d3eb812fd4	2874
JMF	0:24d3eb812fd4	2875	/**
JMF	0:24d3eb812fd4	2876	* \brief IRQ_MASK2 registers
JMF	0:24d3eb812fd4	2877	* \code
JMF	0:24d3eb812fd4	2878	* Default value: 0x00
JMF	0:24d3eb812fd4	2879	* Read Write
JMF	0:24d3eb812fd4	2880	*
JMF	0:24d3eb812fd4	2881	* 7:0 INT_MASK2: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
JMF	0:24d3eb812fd4	2882	*
JMF	0:24d3eb812fd4	2883	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	2884	* -------------------------------------------------------
JMF	0:24d3eb812fd4	2885	* 16 \| READY state in steady condition14
JMF	0:24d3eb812fd4	2886	* 17 \| STANDBY state switching in progress
JMF	0:24d3eb812fd4	2887	* 18 \| Low battery level
JMF	0:24d3eb812fd4	2888	* 19 \| Power-On reset
JMF	0:24d3eb812fd4	2889	* 20 \| Brown-Out event
JMF	0:24d3eb812fd4	2890	* 21 \| LOCK state in steady condition
JMF	0:24d3eb812fd4	2891	* 22 \| PM start-up timer expiration
JMF	0:24d3eb812fd4	2892	* 23 \| XO settling timeout
JMF	0:24d3eb812fd4	2893	* \endcode
JMF	0:24d3eb812fd4	2894	*/
JMF	0:24d3eb812fd4	2895	#define IRQ_MASK2_BASE ((uint8_t)0x91) /!< IRQ_MASK is split into 4 registers/
JMF	0:24d3eb812fd4	2896
JMF	0:24d3eb812fd4	2897	#define IRQ_MASK2_READY ((uint8_t)0x01) /!< IRQ: READY state /
JMF	0:24d3eb812fd4	2898	#define IRQ_MASK2_STANDBY_DELAYED ((uint8_t)0x02) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
JMF	0:24d3eb812fd4	2899	#define IRQ_MASK2_LOW_BATT_LVL ((uint8_t)0x04) /!< IRQ: Battery level below threshold/
JMF	0:24d3eb812fd4	2900	#define IRQ_MASK2_POR ((uint8_t)0x08) /!< IRQ: Power On Reset /
JMF	0:24d3eb812fd4	2901	#define IRQ_MASK2_BOR ((uint8_t)0x10) /!< IRQ: Brown out event (both accurate and inaccurate)/
JMF	0:24d3eb812fd4	2902	#define IRQ_MASK2_LOCK ((uint8_t)0x20) /!< IRQ: LOCK state /
JMF	0:24d3eb812fd4	2903	#define IRQ_MASK2_PM_COUNT_EXPIRED ((uint8_t)0x40) /!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
JMF	0:24d3eb812fd4	2904	#define IRQ_MASK2_XO_COUNT_EXPIRED ((uint8_t)0x80) /!< IRQ: only for debug; Crystal oscillator settling time counter expired /
JMF	0:24d3eb812fd4	2905
JMF	0:24d3eb812fd4	2906	/**
JMF	0:24d3eb812fd4	2907	* @}
JMF	0:24d3eb812fd4	2908	*/
JMF	0:24d3eb812fd4	2909
JMF	0:24d3eb812fd4	2910	/** @defgroup IRQ_MASK3_Register
JMF	0:24d3eb812fd4	2911	* @{
JMF	0:24d3eb812fd4	2912	*/
JMF	0:24d3eb812fd4	2913
JMF	0:24d3eb812fd4	2914	/**
JMF	0:24d3eb812fd4	2915	* \brief IRQ_MASK3 registers
JMF	0:24d3eb812fd4	2916	* \code
JMF	0:24d3eb812fd4	2917	* Default value: 0x00
JMF	0:24d3eb812fd4	2918	* Read Write
JMF	0:24d3eb812fd4	2919	*
JMF	0:24d3eb812fd4	2920	* 7:0 INT_MASK3: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
JMF	0:24d3eb812fd4	2921	*
JMF	0:24d3eb812fd4	2922	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	2923	* -------------------------------------------------------
JMF	0:24d3eb812fd4	2924	* 24 \| SYNTH locking timeout
JMF	0:24d3eb812fd4	2925	* 25 \| SYNTH calibration start-up time
JMF	0:24d3eb812fd4	2926	* 26 \| SYNTH calibration timeout
JMF	0:24d3eb812fd4	2927	* 27 \| TX circuitry start-up time
JMF	0:24d3eb812fd4	2928	* 28 \| RX circuitry start-up time
JMF	0:24d3eb812fd4	2929	* 29 \| RX operation timeout
JMF	0:24d3eb812fd4	2930	* 30 \| Others AES Endof Operation
JMF	0:24d3eb812fd4	2931	* 31 \| Reserved
JMF	0:24d3eb812fd4	2932	* \endcode
JMF	0:24d3eb812fd4	2933	*/
JMF	0:24d3eb812fd4	2934	#define IRQ_MASK3_BASE ((uint8_t)0x90) /!< IRQ_MASK is split into 4 registers/
JMF	0:24d3eb812fd4	2935
JMF	0:24d3eb812fd4	2936	#define IRQ_MASK3_SYNTH_LOCK_TIMEOUT ((uint8_t)0x01) /!< IRQ: only for debug; LOCK state timeout /
JMF	0:24d3eb812fd4	2937	#define IRQ_MASK3_SYNTH_LOCK_STARTUP ((uint8_t)0x02) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
JMF	0:24d3eb812fd4	2938	#define IRQ_MASK3_SYNTH_CAL_TIMEOUT ((uint8_t)0x04) /!< IRQ: only for debug; SYNTH calibration timeout /
JMF	0:24d3eb812fd4	2939	#define IRQ_MASK3_TX_START_TIME ((uint8_t)0x08) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
JMF	0:24d3eb812fd4	2940	#define IRQ_MASK3_RX_START_TIME ((uint8_t)0x10) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
JMF	0:24d3eb812fd4	2941	#define IRQ_MASK3_RX_TIMEOUT ((uint8_t)0x20) /!< IRQ: RX operation timeout /
JMF	0:24d3eb812fd4	2942	#define IRQ_MASK3_AES_END ((uint8_t)0x40) /!< IRQ: AES End of operation /
JMF	0:24d3eb812fd4	2943
JMF	0:24d3eb812fd4	2944	/**
JMF	0:24d3eb812fd4	2945	* @}
JMF	0:24d3eb812fd4	2946	*/
JMF	0:24d3eb812fd4	2947
JMF	0:24d3eb812fd4	2948
JMF	0:24d3eb812fd4	2949	/** @defgroup IRQ_STATUS0_Register
JMF	0:24d3eb812fd4	2950	* @{
JMF	0:24d3eb812fd4	2951	*/
JMF	0:24d3eb812fd4	2952
JMF	0:24d3eb812fd4	2953	/**
JMF	0:24d3eb812fd4	2954	* \brief IRQ_STATUS0 registers
JMF	0:24d3eb812fd4	2955	* \code
JMF	0:24d3eb812fd4	2956	* Default value: 0x00
JMF	0:24d3eb812fd4	2957	* Read Write
JMF	0:24d3eb812fd4	2958	*
JMF	0:24d3eb812fd4	2959	* 7:0 INT_STATUS0: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
JMF	0:24d3eb812fd4	2960	*
JMF	0:24d3eb812fd4	2961	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	2962	* -------------------------------------------------------
JMF	0:24d3eb812fd4	2963	* 0 \| RX data ready
JMF	0:24d3eb812fd4	2964	* 1 \| RX data discarded (upon filtering)
JMF	0:24d3eb812fd4	2965	* 2 \| TX data sent
JMF	0:24d3eb812fd4	2966	* 3 \| Max re-TX reached
JMF	0:24d3eb812fd4	2967	* 4 \| CRC error
JMF	0:24d3eb812fd4	2968	* 5 \| TX FIFO underflow/overflow error
JMF	0:24d3eb812fd4	2969	* 6 \| RX FIFO underflow/overflow error
JMF	0:24d3eb812fd4	2970	* 7 \| TX FIFO almost full
JMF	0:24d3eb812fd4	2971	* \endcode
JMF	0:24d3eb812fd4	2972	*/
JMF	0:24d3eb812fd4	2973
JMF	0:24d3eb812fd4	2974	#define IRQ_STATUS0_BASE ((uint8_t)(0xFD)) /!< IRQ Events(RR, split into 4 registers) /
JMF	0:24d3eb812fd4	2975
JMF	0:24d3eb812fd4	2976	#define IRQ_STATUS0_SYNTH_LOCK_TIMEOUT ((uint8_t)(0x01)) /!< IRQ: LOCK state timeout /
JMF	0:24d3eb812fd4	2977	#define IRQ_STATUS0_SYNTH_LOCK_STARTUP ((uint8_t)(0x02)) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
JMF	0:24d3eb812fd4	2978	#define IRQ_STATUS0_SYNTH_CAL_TIMEOUT ((uint8_t)(0x04)) /!< IRQ: SYNTH locking timeout /
JMF	0:24d3eb812fd4	2979	#define IRQ_STATUS0_TX_START_TIME ((uint8_t)(0x08)) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
JMF	0:24d3eb812fd4	2980	#define IRQ_STATUS0_RX_START_TIME ((uint8_t)(0x10)) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
JMF	0:24d3eb812fd4	2981	#define IRQ_STATUS0_RX_TIMEOUT ((uint8_t)(0x20)) /!< IRQ: RX operation timeout expiration /
JMF	0:24d3eb812fd4	2982	#define IRQ_STATUS0_AES_END ((uint8_t)(0x40)) /!< IRQ: AES End of operation /
JMF	0:24d3eb812fd4	2983
JMF	0:24d3eb812fd4	2984	/**
JMF	0:24d3eb812fd4	2985	* @}
JMF	0:24d3eb812fd4	2986	*/
JMF	0:24d3eb812fd4	2987
JMF	0:24d3eb812fd4	2988	/** @defgroup IRQ_STATUS1_Register
JMF	0:24d3eb812fd4	2989	* @{
JMF	0:24d3eb812fd4	2990	*/
JMF	0:24d3eb812fd4	2991
JMF	0:24d3eb812fd4	2992	/**
JMF	0:24d3eb812fd4	2993	* \brief IRQ_STATUS1 registers
JMF	0:24d3eb812fd4	2994	* \code
JMF	0:24d3eb812fd4	2995	* Default value: 0x00
JMF	0:24d3eb812fd4	2996	* Read Write
JMF	0:24d3eb812fd4	2997	*
JMF	0:24d3eb812fd4	2998	* 7:0 INT_STATUS1: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
JMF	0:24d3eb812fd4	2999	*
JMF	0:24d3eb812fd4	3000	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	3001	* -------------------------------------------------------
JMF	0:24d3eb812fd4	3002	* 8 \| TX FIFO almost empty
JMF	0:24d3eb812fd4	3003	* 9 \| RX FIFO almost full
JMF	0:24d3eb812fd4	3004	* 10 \| RX FIFO almost empty
JMF	0:24d3eb812fd4	3005	* 11 \| Max number of back-off during CCA
JMF	0:24d3eb812fd4	3006	* 12 \| Valid preamble detected
JMF	0:24d3eb812fd4	3007	* 13 \| Sync word detected
JMF	0:24d3eb812fd4	3008	* 14 \| RSSI above threshold (Carrier Sense)
JMF	0:24d3eb812fd4	3009	* 15 \| Wake-up timeout in LDCR mode13
JMF	0:24d3eb812fd4	3010	* \endcode
JMF	0:24d3eb812fd4	3011	*/
JMF	0:24d3eb812fd4	3012
JMF	0:24d3eb812fd4	3013	#define IRQ_STATUS1_BASE ((uint8_t)(0xFC)) /!< IRQ Events(RR, split into 4 registers) /
JMF	0:24d3eb812fd4	3014
JMF	0:24d3eb812fd4	3015	#define IRQ_STATUS1_READY ((uint8_t)(0x01)) /!< IRQ: READY state in steady condition/
JMF	0:24d3eb812fd4	3016	#define IRQ_STATUS1_STANDBY_DELAYED ((uint8_t)(0x02)) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
JMF	0:24d3eb812fd4	3017	#define IRQ_STATUS1_LOW_BATT_LVL ((uint8_t)(0x04)) /!< IRQ: Battery level below threshold/
JMF	0:24d3eb812fd4	3018	#define IRQ_STATUS1_POR ((uint8_t)(0x08)) /!< IRQ: Power On Reset /
JMF	0:24d3eb812fd4	3019	#define IRQ_STATUS1_BOR ((uint8_t)(0x10)) /!< IRQ: Brown out event (both accurate and inaccurate)/
JMF	0:24d3eb812fd4	3020	#define IRQ_STATUS1_LOCK ((uint8_t)(0x20)) /!< IRQ: LOCK state in steady condition /
JMF	0:24d3eb812fd4	3021	#define IRQ_STATUS1_PM_COUNT_EXPIRED ((uint8_t)(0x40)) /!< IRQ: Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
JMF	0:24d3eb812fd4	3022	#define IRQ_STATUS1_XO_COUNT_EXPIRED ((uint8_t)(0x80)) /!< IRQ: Crystal oscillator settling time counter expired /
JMF	0:24d3eb812fd4	3023
JMF	0:24d3eb812fd4	3024	/**
JMF	0:24d3eb812fd4	3025	* @}
JMF	0:24d3eb812fd4	3026	*/
JMF	0:24d3eb812fd4	3027
JMF	0:24d3eb812fd4	3028	/** @defgroup IRQ_STATUS2_Register
JMF	0:24d3eb812fd4	3029	* @{
JMF	0:24d3eb812fd4	3030	*/
JMF	0:24d3eb812fd4	3031
JMF	0:24d3eb812fd4	3032	/**
JMF	0:24d3eb812fd4	3033	* \brief IRQ_STATUS2 registers
JMF	0:24d3eb812fd4	3034	* \code
JMF	0:24d3eb812fd4	3035	* Default value: 0x00
JMF	0:24d3eb812fd4	3036	* Read Write
JMF	0:24d3eb812fd4	3037	*
JMF	0:24d3eb812fd4	3038	* 7:0 INT_STATUS2: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
JMF	0:24d3eb812fd4	3039	*
JMF	0:24d3eb812fd4	3040	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	3041	* -------------------------------------------------------
JMF	0:24d3eb812fd4	3042	* 16 \| READY state in steady condition14
JMF	0:24d3eb812fd4	3043	* 17 \| STANDBY state switching in progress
JMF	0:24d3eb812fd4	3044	* 18 \| Low battery level
JMF	0:24d3eb812fd4	3045	* 19 \| Power-On reset
JMF	0:24d3eb812fd4	3046	* 20 \| Brown-Out event
JMF	0:24d3eb812fd4	3047	* 21 \| LOCK state in steady condition
JMF	0:24d3eb812fd4	3048	* 22 \| PM start-up timer expiration
JMF	0:24d3eb812fd4	3049	* 23 \| XO settling timeout
JMF	0:24d3eb812fd4	3050	* \endcode
JMF	0:24d3eb812fd4	3051	*/
JMF	0:24d3eb812fd4	3052
JMF	0:24d3eb812fd4	3053	#define IRQ_STATUS2_BASE ((uint8_t)0xFB) /!< IRQ Events(RR, split into 4 registers) /
JMF	0:24d3eb812fd4	3054
JMF	0:24d3eb812fd4	3055	#define IRQ_STATUS2_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
JMF	0:24d3eb812fd4	3056	#define IRQ_STATUS2_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
JMF	0:24d3eb812fd4	3057	#define IRQ_STATUS2_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
JMF	0:24d3eb812fd4	3058	#define IRQ_STATUS2_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
JMF	0:24d3eb812fd4	3059	#define IRQ_STATUS2_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
JMF	0:24d3eb812fd4	3060	#define IRQ_STATUS2_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
JMF	0:24d3eb812fd4	3061	#define IRQ_STATUS2_RSSI_ABOVE_TH ((uint8_t)(0x40)) /!< IRQ: RSSI above threshold /
JMF	0:24d3eb812fd4	3062	#define IRQ_STATUS2_WKUP_TOUT_LDC ((uint8_t)(0x80)) /!< IRQ: Wake-up timeout in LDC mode /
JMF	0:24d3eb812fd4	3063
JMF	0:24d3eb812fd4	3064	/**
JMF	0:24d3eb812fd4	3065	* @}
JMF	0:24d3eb812fd4	3066	*/
JMF	0:24d3eb812fd4	3067
JMF	0:24d3eb812fd4	3068	/** @defgroup IRQ_STATUS3_Register
JMF	0:24d3eb812fd4	3069	* @{
JMF	0:24d3eb812fd4	3070	*/
JMF	0:24d3eb812fd4	3071
JMF	0:24d3eb812fd4	3072	/**
JMF	0:24d3eb812fd4	3073	* \brief IRQ_STATUS3 registers
JMF	0:24d3eb812fd4	3074	* \code
JMF	0:24d3eb812fd4	3075	* Default value: 0x00
JMF	0:24d3eb812fd4	3076	* Read Write
JMF	0:24d3eb812fd4	3077	*
JMF	0:24d3eb812fd4	3078	* 7:0 INT_STATUS3: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
JMF	0:24d3eb812fd4	3079	*
JMF	0:24d3eb812fd4	3080	* Bit \| Events Group Interrupt Event
JMF	0:24d3eb812fd4	3081	* -------------------------------------------------------
JMF	0:24d3eb812fd4	3082	* 24 \| SYNTH locking timeout
JMF	0:24d3eb812fd4	3083	* 25 \| SYNTH calibration start-up time
JMF	0:24d3eb812fd4	3084	* 26 \| SYNTH calibration timeout
JMF	0:24d3eb812fd4	3085	* 27 \| TX circuitry start-up time
JMF	0:24d3eb812fd4	3086	* 28 \| RX circuitry start-up time
JMF	0:24d3eb812fd4	3087	* 29 \| RX operation timeout
JMF	0:24d3eb812fd4	3088	* 30 \| Others AES Endof Operation
JMF	0:24d3eb812fd4	3089	* 31 \| Reserved
JMF	0:24d3eb812fd4	3090	* \endcode
JMF	0:24d3eb812fd4	3091	*/
JMF	0:24d3eb812fd4	3092	#define IRQ_STATUS3_BASE ((uint8_t)0xFA) /!< IRQ Events(RR, split into 4 registers) /
JMF	0:24d3eb812fd4	3093
JMF	0:24d3eb812fd4	3094	#define IRQ_STATUS3_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
JMF	0:24d3eb812fd4	3095	#define IRQ_STATUS3_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
JMF	0:24d3eb812fd4	3096	#define IRQ_STATUS3_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
JMF	0:24d3eb812fd4	3097	#define IRQ_STATUS3_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
JMF	0:24d3eb812fd4	3098	#define IRQ_STATUS3_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
JMF	0:24d3eb812fd4	3099	#define IRQ_STATUS3_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
JMF	0:24d3eb812fd4	3100	#define IRQ_STATUS3_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
JMF	0:24d3eb812fd4	3101	#define IRQ_STATUS3_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
JMF	0:24d3eb812fd4	3102
JMF	0:24d3eb812fd4	3103	/**
JMF	0:24d3eb812fd4	3104	* @}
JMF	0:24d3eb812fd4	3105	*/
JMF	0:24d3eb812fd4	3106
JMF	0:24d3eb812fd4	3107	/**
JMF	0:24d3eb812fd4	3108	* @}
JMF	0:24d3eb812fd4	3109	*/
JMF	0:24d3eb812fd4	3110
JMF	0:24d3eb812fd4	3111
JMF	0:24d3eb812fd4	3112	/** @defgroup MC_STATE_Registers
JMF	0:24d3eb812fd4	3113	* @{
JMF	0:24d3eb812fd4	3114	*/
JMF	0:24d3eb812fd4	3115
JMF	0:24d3eb812fd4	3116	/** @defgroup MC_STATE1_Register
JMF	0:24d3eb812fd4	3117	* @{
JMF	0:24d3eb812fd4	3118	*/
JMF	0:24d3eb812fd4	3119
JMF	0:24d3eb812fd4	3120	/**
JMF	0:24d3eb812fd4	3121	* \brief MC_STATE1 registers
JMF	0:24d3eb812fd4	3122	* \code
JMF	0:24d3eb812fd4	3123	* Default value: 0x50
JMF	0:24d3eb812fd4	3124	* Read
JMF	0:24d3eb812fd4	3125	*
JMF	0:24d3eb812fd4	3126	* 7:4 Reserved.
JMF	0:24d3eb812fd4	3127	*
JMF	0:24d3eb812fd4	3128	* 3 ANT_SELECT: Currently selected antenna
JMF	0:24d3eb812fd4	3129	*
JMF	0:24d3eb812fd4	3130	* 2 TX_FIFO_Full: 1 - TX FIFO is full
JMF	0:24d3eb812fd4	3131	*
JMF	0:24d3eb812fd4	3132	* 1 RX_FIFO_Empty: 1 - RX FIFO is empty
JMF	0:24d3eb812fd4	3133	*
JMF	0:24d3eb812fd4	3134	* 0 ERROR_LOCK: 1 - RCO calibrator error
JMF	0:24d3eb812fd4	3135	* \endcode
JMF	0:24d3eb812fd4	3136	*/
JMF	0:24d3eb812fd4	3137	#define MC_STATE1_BASE ((uint8_t)(0xC0)) /!< MC_STATE1 register address (see the SpiritStatus struct /
JMF	0:24d3eb812fd4	3138
JMF	0:24d3eb812fd4	3139
JMF	0:24d3eb812fd4	3140	/**
JMF	0:24d3eb812fd4	3141	* @}
JMF	0:24d3eb812fd4	3142	*/
JMF	0:24d3eb812fd4	3143
JMF	0:24d3eb812fd4	3144
JMF	0:24d3eb812fd4	3145	/** @defgroup MC_STATE0_Register
JMF	0:24d3eb812fd4	3146	* @{
JMF	0:24d3eb812fd4	3147	*/
JMF	0:24d3eb812fd4	3148
JMF	0:24d3eb812fd4	3149	/**
JMF	0:24d3eb812fd4	3150	* \brief MC_STATE0 registers
JMF	0:24d3eb812fd4	3151	* \code
JMF	0:24d3eb812fd4	3152	* Default value: 0x00
JMF	0:24d3eb812fd4	3153	* Read
JMF	0:24d3eb812fd4	3154	*
JMF	0:24d3eb812fd4	3155	* 7:1 STATE[6:0]: Current MC state.
JMF	0:24d3eb812fd4	3156	*
JMF	0:24d3eb812fd4	3157	* REGISTER VALUE \| STATE
JMF	0:24d3eb812fd4	3158	* --------------------------------------------
JMF	0:24d3eb812fd4	3159	* 0x40 \| STANDBY
JMF	0:24d3eb812fd4	3160	* 0x36 \| SLEEP
JMF	0:24d3eb812fd4	3161	* 0x03 \| READY
JMF	0:24d3eb812fd4	3162	* 0x3B \| PM setup
JMF	0:24d3eb812fd4	3163	* 0x23 \| XO settling
JMF	0:24d3eb812fd4	3164	* 0x53 \| SYNTH setup
JMF	0:24d3eb812fd4	3165	* 0x1F \| PROTOCOL
JMF	0:24d3eb812fd4	3166	* 0x4F \| SYNTH calibration
JMF	0:24d3eb812fd4	3167	* 0x0F \| LOCK
JMF	0:24d3eb812fd4	3168	* 0x33 \| RX
JMF	0:24d3eb812fd4	3169	* 0x5F \| TX
JMF	0:24d3eb812fd4	3170	*
JMF	0:24d3eb812fd4	3171	* 0 XO_ON: 1 - XO is operating
JMF	0:24d3eb812fd4	3172	* \endcode
JMF	0:24d3eb812fd4	3173	*/
JMF	0:24d3eb812fd4	3174	#define MC_STATE0_BASE ((uint8_t)(0xC1)) /*!< MC_STATE0 register address. In this version ALL existing states have been inserted
JMF	0:24d3eb812fd4	3175	and are still to be verified */
JMF	0:24d3eb812fd4	3176	/**
JMF	0:24d3eb812fd4	3177	* @}
JMF	0:24d3eb812fd4	3178	*/
JMF	0:24d3eb812fd4	3179
JMF	0:24d3eb812fd4	3180	/**
JMF	0:24d3eb812fd4	3181	* @}
JMF	0:24d3eb812fd4	3182	*/
JMF	0:24d3eb812fd4	3183
JMF	0:24d3eb812fd4	3184	/** @defgroup Engineering-Test_Registers
JMF	0:24d3eb812fd4	3185	* @{
JMF	0:24d3eb812fd4	3186	*/
JMF	0:24d3eb812fd4	3187
JMF	0:24d3eb812fd4	3188	#define SYNTH_CONFIG1_BASE ((uint8_t)(0x9E)) /*!< Synthesizier registers: M, A, K data sync on positive/negative clock edges [4],
JMF	0:24d3eb812fd4	3189	Enable Linearization of the charge pump [3], split time 1.75/3.45ns [2], VCO calibration window 16,32,64,128 clock cycles [1:0]*/
JMF	0:24d3eb812fd4	3190	#define SYNTH_CONFIG0_BASE ((uint8_t)(0x9F)) /!< Enable DSM randomizer [7], Window width 1.2-7.5ns (Down-up) of lock detector/
JMF	0:24d3eb812fd4	3191	#define VCOTH_BASE ((uint8_t)(0xA0)) /*!< Controls the threshold frequency between VCO low and VCO high [7:0]
JMF	0:24d3eb812fd4	3192	VCOth frequency=2fXO(96+VCO_TH/16), fmin=4992 MHz, fmax=5820 MHz*/
JMF	0:24d3eb812fd4	3193	#define PM_CONFIG2_BASE ((uint8_t)(0xA4)) /!< Enables high current buffer on Temperature sensor, sets SMPS options /
JMF	0:24d3eb812fd4	3194	#define PM_CONFIG1_BASE ((uint8_t)(0xA5)) /!< Set SMPS options /
JMF	0:24d3eb812fd4	3195	#define PM_CONFIG0_BASE ((uint8_t)(0xA6)) /!< Set SMPS options /
JMF	0:24d3eb812fd4	3196	#define VCO_CONFIG_BASE ((uint8_t)(0xA1)) /!< Set VCO current [5:2]part and [1:0] part /
JMF	0:24d3eb812fd4	3197	#define XO_CONFIG_BASE ((uint8_t)(0xA7)) /!< Clock management options from XO to digital part /
JMF	0:24d3eb812fd4	3198
JMF	0:24d3eb812fd4	3199	#define XO_RCO_TEST_BASE ((uint8_t)(0xB4)) /!< Test of XO and RCO /
JMF	0:24d3eb812fd4	3200
JMF	0:24d3eb812fd4	3201	/**
JMF	0:24d3eb812fd4	3202	* @}
JMF	0:24d3eb812fd4	3203	*/
JMF	0:24d3eb812fd4	3204
JMF	0:24d3eb812fd4	3205
JMF	0:24d3eb812fd4	3206	/** @addtogroup Commands
JMF	0:24d3eb812fd4	3207	* @{
JMF	0:24d3eb812fd4	3208	*/
JMF	0:24d3eb812fd4	3209
JMF	0:24d3eb812fd4	3210	#define COMMAND_TX ((uint8_t)(0x60)) /!< Start to transmit; valid only from READY /
JMF	0:24d3eb812fd4	3211	#define COMMAND_RX ((uint8_t)(0x61)) /!< Start to receive; valid only from READY /
JMF	0:24d3eb812fd4	3212	#define COMMAND_READY ((uint8_t)(0x62)) /!< Go to READY; valid only from STANDBY or SLEEP or LOCK /
JMF	0:24d3eb812fd4	3213	#define COMMAND_STANDBY ((uint8_t)(0x63)) /!< Go to STANDBY; valid only from READY /
JMF	0:24d3eb812fd4	3214	#define COMMAND_SLEEP ((uint8_t)(0x64)) /!< Go to SLEEP; valid only from READY /
JMF	0:24d3eb812fd4	3215	#define COMMAND_LOCKRX ((uint8_t)(0x65)) /!< Go to LOCK state by using the RX configuration of the synth; valid only from READY /
JMF	0:24d3eb812fd4	3216	#define COMMAND_LOCKTX ((uint8_t)(0x66)) /!< Go to LOCK state by using the TX configuration of the synth; valid only from READY /
JMF	0:24d3eb812fd4	3217	#define COMMAND_SABORT ((uint8_t)(0x67)) /!< Force exit form TX or RX states and go to READY state; valid only from TX or RX /
JMF	0:24d3eb812fd4	3218	#define COMMAND_LDC_RELOAD ((uint8_t)(0x68)) /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER
JMF	0:24d3eb812fd4	3219	registers; valid from all states */
JMF	0:24d3eb812fd4	3220	#define COMMAND_SEQUENCE_UPDATE ((uint8_t)(0x69)) /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register
JMF	0:24d3eb812fd4	3221	valid from all states */
JMF	0:24d3eb812fd4	3222	#define COMMAND_AES_ENC ((uint8_t)(0x6A)) /!< AES: Start the encryption routine; valid from all states; valid from all states /
JMF	0:24d3eb812fd4	3223	#define COMMAND_AES_KEY ((uint8_t)(0x6B)) /!< AES: Start the procedure to compute the key for the decryption; valid from all states /
JMF	0:24d3eb812fd4	3224	#define COMMAND_AES_DEC ((uint8_t)(0x6C)) /!< AES: Start the decryption routine using the current key; valid from all states /
JMF	0:24d3eb812fd4	3225	#define COMMAND_AES_KEY_DEC ((uint8_t)(0x6D)) /!< AES: Compute the key and start the decryption; valid from all states /
JMF	0:24d3eb812fd4	3226	#define COMMAND_SRES ((uint8_t)(0x70)) /!< Reset of all digital part, except SPI registers /
JMF	0:24d3eb812fd4	3227	#define COMMAND_FLUSHRXFIFO ((uint8_t)(0x71)) /!< Clean the RX FIFO; valid from all states /
JMF	0:24d3eb812fd4	3228	#define COMMAND_FLUSHTXFIFO ((uint8_t)(0x72)) /!< Clean the TX FIFO; valid from all states /
JMF	0:24d3eb812fd4	3229
JMF	0:24d3eb812fd4	3230	/**
JMF	0:24d3eb812fd4	3231	* @}
JMF	0:24d3eb812fd4	3232	*/
JMF	0:24d3eb812fd4	3233
JMF	0:24d3eb812fd4	3234	/**
JMF	0:24d3eb812fd4	3235	* @}
JMF	0:24d3eb812fd4	3236	*/
JMF	0:24d3eb812fd4	3237
JMF	0:24d3eb812fd4	3238	#ifdef __cplusplus
JMF	0:24d3eb812fd4	3239	}
JMF	0:24d3eb812fd4	3240	#endif
JMF	0:24d3eb812fd4	3241
JMF	0:24d3eb812fd4	3242	#endif
JMF	0:24d3eb812fd4	3243
JMF	0:24d3eb812fd4	3244	/***************** (C) COPYRIGHT 2015 STMicroelectronics *END OF FILE**/

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Type:	Program
Mbed OS support:	Mbed OS
Created:	05 Sep 2018
Imports:	5
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	2
Followers:	1

easy-connect/stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Regs.h@0:24d3eb812fd4, 2018-09-05 (annotated)

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