Ivo van Poorten / fastlib

Library to access LPC17xx peripherals. It uses static inline functions, constant propagation and dead code elimination to be as fast as possible.

Dependents:   Chua-VGA Wolfram-1D-VGA WolframRnd-1D-VGA Basin-VGA ... more

dma.h@0:7a91348b4a02, 2011-07-03 (annotated)

Committer:
Ivop
Date:
Sun Jul 03 17:11:55 2011 +0000
Revision:
0:7a91348b4a02

        

        
Who changed what in which revision?

        

            
                
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/* Copyright (C) 2010, 2011 by Ivo van Poorten <ivop@euronet.nl>





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 * This file is licensed under the terms of the GNU Lesser





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 * General Public License, version 3.





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 */





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#ifndef FASTLIB_DMA_H





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#define FASTLIB_DMA_H





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#include "fastlib/common.h"





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#define FL_DMACIntStat          ((volatile uint32_t *) 0x50004000)





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#define FL_DMACIntTCStat        ((volatile uint32_t *) 0x50004004)





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#define FL_DMACIntTCClear       ((volatile uint32_t *) 0x50004008)





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#define FL_DMACIntErrStat       ((volatile uint32_t *) 0x5000400C)





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#define FL_DMACIntErrClr        ((volatile uint32_t *) 0x50004010)





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#define FL_DMACRawIntTCStat     ((volatile uint32_t *) 0x50004014)





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#define FL_DMACRawIntErrStat    ((volatile uint32_t *) 0x50004018)





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#define FL_DMACEnbldChns        ((volatile uint32_t *) 0x5000401C)





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#define FL_DMACSoftBReq         ((volatile uint32_t *) 0x50004020)





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#define FL_DMACSoftSReq         ((volatile uint32_t *) 0x50004024)





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#define FL_DMACSoftLBReq        ((volatile uint32_t *) 0x50004028)





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#define FL_DMACSoftLSReq        ((volatile uint32_t *) 0x5000402C)





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#define FL_DMACConfig           ((volatile uint32_t *) 0x50004030)





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#define FL_DMACSync             ((volatile uint32_t *) 0x50004034)





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#define FL_DMAReqSel            ((volatile uint32_t *) 0x400FC1C4)





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#define FL_DMACC0   0x50004100





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#define FL_DMACC1   0x50004120





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#define FL_DMACC2   0x50004140





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#define FL_DMACC3   0x50004160





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#define FL_DMACC4   0x50004180





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#define FL_DMACC5   0x500041A0





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#define FL_DMACC6   0x500041C0





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#define FL_DMACC7   0x500041E0





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#define FL_DMA_SrcAddr  0x00





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#define FL_DMA_DestAddr 0x04





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#define FL_DMA_LLI      0x08





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#define FL_DMA_Control  0x0C





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#define FL_DMA_Config   0x10





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#define FL_DMA(channel, field) \





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    ((volatile uint32_t *)(fl_dma_channel_to_base(channel) + FL_DMA_##field))





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static inline unsigned fl_dma_channel_to_base(const unsigned channel) {





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    switch(channel) {





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    case 0:  return FL_DMACC0;





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    case 1:  return FL_DMACC1;





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    case 2:  return FL_DMACC2;





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    case 3:  return FL_DMACC3;





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    case 4:  return FL_DMACC4;





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    case 5:  return FL_DMACC5;





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    case 6:  return FL_DMACC6;





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    default: return FL_DMACC7;





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    }





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}





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// channel: 0-7





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static inline unsigned fl_dma_channel_has_active_interrupt_request(const unsigned channel) {





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    return *FL_DMACIntStat & (1U<<channel);





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}





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static inline unsigned fl_dma_channel_has_active_terminal_count_interrupt_request(const unsigned channel) {





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    return *FL_DMACIntTCStat & (1U<<channel);





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}





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static inline void fl_dma_clear_terminal_count_interrupt_request(const unsigned channel) {





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    *FL_DMACIntTCClear |= 1U<<channel;





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}





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static inline unsigned fl_dma_channel_has_active_terminal_count_interrupt_request_raw(const unsigned channel) {





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    return *FL_DMACRawIntTCStat & (1U<<channel);     // raw is prior to masking





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}





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static inline unsigned fl_dma_channel_has_active_error_interrupt_request(const unsigned channel) {





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    return *FL_DMACIntErrStat & (1U<<channel);





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}





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static inline void fl_dma_clear_error_interrupt_request(const unsigned channel) {





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    *FL_DMACIntErrClr |= 1U<<channel;





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}





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static inline unsigned fl_dma_channel_has_active_error_interrupt_request_raw(const unsigned channel) {





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    return *FL_DMACRawIntErrStat & (1U<<channel);





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}





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static inline unsigned fl_dma_channel_is_enabled(const unsigned channel) {





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    return *FL_DMACEnbldChns & (1U<<channel);





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}





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static inline void fl_dma_generate_software_burst_request(const unsigned request) {





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    *FL_DMACSoftBReq |= 1U << request;





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}





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static inline unsigned fl_dma_software_burst_request_sources(void) {





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    return *FL_DMACSoftBReq;





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}





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static inline void fl_dma_generate_software_single_request(const unsigned request) {





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    *FL_DMACSoftSReq |= 1U << request;





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}





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static inline unsigned fl_dma_software_single_request_sources(void) {





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    return *FL_DMACSoftSReq;





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}





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static inline void fl_dma_generate_software_last_burst_request(const unsigned request) {





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    *FL_DMACSoftLBReq |= 1U << request;





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}





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static inline unsigned fl_dma_software_last_burst_request_sources(void) {





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    return *FL_DMACSoftLBReq;





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}





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static inline void fl_dma_generate_software_last_single_request(const unsigned request) {





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    *FL_DMACSoftLSReq |= 1U << request;





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}





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static inline unsigned fl_dma_software_last_single_request_sources(void) {





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    return *FL_DMACSoftLSReq;





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}





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static inline void fl_dma_enable(const unsigned state) {





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    if (state) *FL_DMACConfig |=   1U<<0 ;





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    else       *FL_DMACConfig &= ~(1U<<0);





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}





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static inline unsigned fl_dma_is_enabled(void) {





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    return *FL_DMACConfig & 1;





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}





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static inline void fl_dma_set_endianness(const unsigned endianness) {





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    if (endianness) *FL_DMACConfig |=   1U<<1 ;





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    else            *FL_DMACConfig &= ~(1U<<1);





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}





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static inline void fl_dma_request_synchronization_enable(const unsigned request, const unsigned state) {





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    if (!state) *FL_DMACSync |=   1U<<request ;     // note that 0 is enabled





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    else        *FL_DMACSync &= ~(1U<<request);





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}





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#define FL_DMA_UART     0





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#define FL_DMA_TIMER    1





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// select between uart or timer dma requests for inputs 8 through 15





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// input: 8-16  which: 0-1





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static inline void fl_dma_request_select(const unsigned input, const unsigned which) {





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    if (which) *FL_DMAReqSel |=   1U<<(which-8) ;





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    else       *FL_DMAReqSel &= ~(1U<<(which-8));





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}





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// channel: 0-7





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static inline void fl_dma_set_srcaddr(const unsigned channel, const void *srcaddr) {





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    *FL_DMA(channel, SrcAddr) = (unsigned) srcaddr;





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}





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static inline void fl_dma_set_destaddr(const unsigned channel, const void *destaddr) {





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    *FL_DMA(channel, DestAddr) = (unsigned) destaddr;





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}





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// lli must be word-aligned





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static inline void fl_dma_set_next_lli(const unsigned channel, const void *lli) {





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    *FL_DMA(channel, LLI) = (unsigned) lli & (~3U);





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}





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#define FL_NO_SRC_INCREMENT     0





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#define FL_SRC_INCREMENT        1





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#define FL_NO_DEST_INCREMENT    0





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#define FL_DEST_INCREMENT       1





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static inline unsigned fl_dma_size_to_mask(const unsigned size) {





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    switch(size) {





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    case 4:     return 1;





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    case 8:     return 2;





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    case 16:    return 3;





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    case 32:    return 4;





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    case 64:    return 5;





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    case 128:   return 6;





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    case 256:   return 7;





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    default:    return 0;





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    }





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}





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static inline unsigned fl_dma_width_to_mask(const unsigned width) {





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    switch(width) {





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    case 16:    return 1;





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    case 32:    return 2;





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    default:    return 0;





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    }





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}





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// transfer_size: 12 bits





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// size: 1, 4, 8, 16, 32, 64, 128 or 256





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// width: 8, 16 or 32





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// irq: 0-1





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static inline void fl_dma_channel_control(const unsigned channel, const unsigned transfer_size,





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                                          const unsigned src_burst_size, const unsigned dest_burst_size,





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                                          const unsigned src_width, const unsigned dest_width,





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                                          const unsigned src_increment, const unsigned dest_increment,





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                                          const unsigned terminal_count_irq) {





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    *FL_DMA(channel, Control) = transfer_size & 0xfff





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                              | (fl_dma_size_to_mask(src_burst_size)  << 12)





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                              | (fl_dma_size_to_mask(dest_burst_size) << 15)





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                              | (fl_dma_width_to_mask(src_width)  << 18)





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                              | (fl_dma_width_to_mask(dest_width) << 21)





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                              | (src_increment  << 26)





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                              | (dest_increment << 27)





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                              | (terminal_count_irq << 31);





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}





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static inline void fl_dma_channel_control_by_mask(const unsigned channel, const unsigned mask) {





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    *FL_DMA(channel, Control) = mask;





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}





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static inline unsigned fl_dma_channel_get_control_mask(const unsigned channel) {





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    return *FL_DMA(channel, Control);





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}





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static inline void fl_dma_channel_terminal_count_irq_enable(const unsigned channel, const unsigned state) {





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    if (state) *FL_DMA(channel, Control) |=   1U<<31 ;





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    else       *FL_DMA(channel, Control) &= ~(1U<<31);





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}





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// channel configuration constants, src and dest peripherals





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#define FL_DMA_SINGLE_REQUEST_SSP0_Tx   0





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#define FL_DMA_SINGLE_REQUEST_SSP0_Rx   1





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#define FL_DMA_SINGLE_REQUEST_SSP1_Tx   2





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#define FL_DMA_SINGLE_REQUEST_SSP1_Rx   3





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#define FL_DMA_SINGLE_REQUEST_ADC       4





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#define FL_DMA_BURST_REQUEST_SSP0_Tx    0





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#define FL_DMA_BURST_REQUEST_SSP0_Rx    1





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#define FL_DMA_BURST_REQUEST_SSP1_Tx    2





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#define FL_DMA_BURST_REQUEST_SSP1_Rx    3





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#define FL_DMA_BURST_REQUEST_ADC        4





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#define FL_DMA_BURST_REQUEST_I2S_CH0    5





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#define FL_DMA_BURST_REQUEST_I2S_CH1    6





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#define FL_DMA_BURST_REQUEST_DAC        7





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#define FL_DMA_BURST_REQUEST_UART0_Tx   8





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#define FL_DMA_BURST_REQUEST_UART0_Rx   9





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#define FL_DMA_BURST_REQUEST_UART1_Tx   10





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#define FL_DMA_BURST_REQUEST_uART1_Rx   11





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#define FL_DMA_BURST_REQUEST_UART2_Tx   12





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#define FL_DMA_BURST_REQUEST_UART2_Rx   13





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#define FL_DMA_BURST_REQUEST_UART3_Tx   14





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#define FL_DMA_BURST_REQUEST_UART3_Rx   15





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#define FL_DMA_PERIPHERAL_IS_MEMORY     0





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// transfer types





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#define FL_DMA_MEMORY_TO_MEMORY         0





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#define FL_DMA_MEMORY_TO_PERIPHERAL     1





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#define FL_DMA_PERIPHERAL_TO_MEMORY     2





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#define FL_DMA_PERIPHERAL_TO_PERIPHERAL 3





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static inline void fl_dma_channel_config(const unsigned channel,





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    const unsigned enable, const unsigned src_peripheral, const unsigned dest_peripheral,





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    const unsigned transfer_type, const unsigned mask_error, const unsigned mask_tc) {





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    *FL_DMA(channel, Config) = enable | (src_peripheral<<1) | (dest_peripheral<<6) |





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                               (transfer_type<<11) | (mask_error<<14) | (mask_tc<<15);





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}





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// return 0 or !0 (channel fifo has data)





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static inline unsigned fl_dma_channel_is_active(const unsigned channel) {





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    return *FL_DMA(channel, Config) & (1U<<17);





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}





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static inline void fl_dma_channel_halt(const unsigned channel, const unsigned state) {





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    if (state) *FL_DMA(channel, Config) |=   1U<<18 ;





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    else       *FL_DMA(channel, Config) &= ~(1U<<18);





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}





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#endif