mille feuille
Home Page : http://www.mcugear.com/en/ MCU Gear manual mode (circuit quick changer!) You can save 8 schematic(bank 0-7) manually and change it quickly.
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commonM.h
00001 /* MCU Gear Library, only for testing MCUGear without any circuit you connected. 00002 * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/ 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a copy 00005 * of this software and associated documentation files (the "Software"), to deal 00006 * in the Software without restriction, including without limitation the rights 00007 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 00008 * copies of the Software, and to permit persons to whom the Software is 00009 * furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included in 00012 * all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 00015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 00016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 00017 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 00018 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 00019 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 00020 * THE SOFTWARE. 00021 */ 00022 00023 #define numBaseboardIO 48 00024 #define numMaxModuleIO 12 00025 00026 //#define DEBUG //If you need to debug, define this. 00027 #if defined TARGET_LPC1768 00028 00029 #define BaudRate 9600 00030 #define FPGA_I2C_CLOCK 1000000 00031 #define MODULE_I2C_CLOCK 1000000 00032 00033 #endif 00034 00035 #if defined TARGET_KL25Z 00036 00037 #define BaudRate 19200 00038 #define FPGA_I2C_CLOCK 2000000 //about 769kHz 00039 #define MODULE_I2C_CLOCK 2000000 00040 00041 #endif 00042 00043 00044 #define FPGA_I2C_ADR 0x78 00045 00046 #ifdef DEBUG 00047 #define BankMaxNum 3 //you can set 1 to 7 BANKs for Debug Mode. 00048 00049 #else 00050 #define BankMaxNum 7 //BANK layers 00051 00052 #endif 00053 00054 //PCA9674 00055 //VSS = GND VDD = +3.3V 00056 //AD2 AD1 AD0 00057 #define N_VSS_SCL_VSS 0x20 00058 #define N_VSS_SCL_VDD 0x22 00059 #define N_VSS_SDA_VSS 0x24 00060 #define N_VSS_SDA_VDD 0x26 00061 #define N_VDD_SCL_VSS 0x28 00062 #define N_VDD_SCL_VDD 0x2A 00063 #define N_VDD_SDA_VSS 0x2C 00064 #define N_VDD_SDA_VDD 0x2E 00065 #define N_VSS_SCL_SCL 0x30 00066 #define N_VSS_SCL_SDA 0x32 00067 #define N_VSS_SDA_SCL 0x34 00068 #define N_VSS_SDA_SDA 0x36 00069 #define N_VDD_SCL_SCL 0x38 00070 #define N_VDD_SCL_SDA 0x3A 00071 #define N_VDD_SDA_SCL 0x3C 00072 #define N_VDD_SDA_SDA 0x3E 00073 #define N_VSS_VSS_VSS 0x40 00074 #define N_VSS_VSS_VDD 0x42 00075 #define N_VSS_VDD_VSS 0x44 00076 #define N_VSS_VDD_VDD 0x46 00077 #define N_VDD_VSS_VSS 0x48 00078 #define N_VDD_VSS_VDD 0x4A 00079 #define N_VDD_VDD_VSS 0x4C 00080 #define N_VDD_VDD_VDD 0x4E 00081 #define N_VSS_VSS_SCL 0x50 00082 #define N_VSS_VSS_SDA 0x52 00083 #define N_VSS_VDD_SCL 0x54 00084 #define N_VSS_VDD_SDA 0x56 00085 #define N_VDD_VSS_SCL 0x58 00086 #define N_VDD_VSS_SDA 0x5A 00087 #define N_VDD_VDD_SCL 0x5C 00088 #define N_VDD_VDD_SDA 0x5E 00089 #define N_SCL_SCL_VSS 0xA0 00090 #define N_SCL_SCL_VDD 0xA2 00091 #define N_SCL_SDA_VSS 0xA4 00092 #define N_SCL_SDA_VDD 0xA6 00093 #define N_SDA_SCL_VSS 0xA8 00094 #define N_SDA_SCL_VDD 0xAA 00095 #define N_SDA_SDA_VSS 0xAC 00096 #define N_SDA_SDA_VDD 0xAE 00097 #define N_SCL_SCL_SCL 0xB0 00098 #define N_SCL_SCL_SDA 0xB2 00099 #define N_SCL_SDA_SCL 0xB4 00100 #define N_SCL_SDA_SDA 0xB6 00101 #define N_SDA_SCL_SCL 0xB8 00102 #define N_SDA_SCL_SDA 0xBA 00103 #define N_SDA_SDA_SCL 0xBC 00104 #define N_SDA_SDA_SDA 0xBE 00105 #define N_SCL_VSS_VSS 0xC0 00106 #define N_SCL_VSS_VDD 0xC2 00107 #define N_SCL_VDD_VSS 0xC4 00108 #define N_SCL_VDD_VDD 0xC6 00109 #define N_SDA_VSS_VSS 0xC8 00110 #define N_SDA_VSS_VDD 0xCA 00111 #define N_SDA_VDD_VSS 0xCC 00112 #define N_SDA_VDD_VDD 0xCE 00113 #define N_SCL_VSS_SCL 0xE0 00114 #define N_SCL_VSS_SDA 0xE2 00115 #define N_SCL_VDD_SCL 0xE4 00116 #define N_SCL_VDD_SDA 0xE6 00117 #define N_SDA_VSS_SCL 0xE8 00118 #define N_SDA_VSS_SDA 0xEA 00119 #define N_SDA_VDD_SCL 0xEC 00120 #define N_SDA_VDD_SDA 0xEE 00121 00122 00123 //PCA9674A 00124 //VSS = GND VDD = +3.3V 00125 //AD2 AD1 AD0 00126 #define A_VSS_SCL_VSS 0x10 00127 #define A_VSS_SCL_VDD 0x12 00128 #define A_VSS_SDA_VSS 0x14 00129 #define A_VSS_SDA_VDD 0x16 00130 #define A_VDD_SCL_VSS 0x18 00131 #define A_VDD_SCL_VDD 0x1A 00132 #define A_VDD_SDA_VSS 0x1C 00133 #define A_VDD_SDA_VDD 0x1E 00134 #define A_VSS_SCL_SCL 0x60 00135 #define A_VSS_SCL_SDA 0x62 00136 #define A_VSS_SDA_SCL 0x64 00137 #define A_VSS_SDA_SDA 0x66 00138 #define A_VDD_SCL_SCL 0x68 00139 #define A_VDD_SCL_SDA 0x6A 00140 #define A_VDD_SDA_SCL 0x6C 00141 #define A_VDD_SDA_SDA 0x6E 00142 #define A_VSS_VSS_VSS 0x70 00143 #define A_VSS_VSS_VDD 0x72 00144 #define A_VSS_VDD_VSS 0x74 00145 #define A_VSS_VDD_VDD 0x76 00146 //#define A_VDD_VSS_VSS 0x78 //This is baseboard address. It is reserved. 00147 #define A_VDD_VSS_VDD 0x7A 00148 #define A_VDD_VDD_VSS 0x7C 00149 #define A_VDD_VDD_VDD 0x7E 00150 #define A_VSS_VSS_SCL 0x80 00151 #define A_VSS_VSS_SDA 0x82 00152 #define A_VSS_VDD_SCL 0x84 00153 #define A_VSS_VDD_SDA 0x86 00154 #define A_VDD_VSS_SCL 0x88 00155 #define A_VDD_VSS_SDA 0x8A 00156 #define A_VDD_VDD_SCL 0x8C 00157 #define A_VDD_VDD_SDA 0x8E 00158 #define A_SCL_SCL_VSS 0x90 00159 #define A_SCL_SCL_VDD 0x92 00160 #define A_SCL_SDA_VSS 0x94 00161 #define A_SCL_SDA_VDD 0x96 00162 #define A_SDA_SCL_VSS 0x98 00163 #define A_SDA_SCL_VDD 0x9A 00164 #define A_SDA_SDA_VSS 0x9C 00165 #define A_SDA_SDA_VDD 0x9E 00166 #define A_SCL_SCL_SCL 0xD0 00167 #define A_SCL_SCL_SDA 0xD2 00168 #define A_SCL_SDA_SCL 0xD4 00169 #define A_SCL_SDA_SDA 0xD6 00170 #define A_SDA_SCL_SCL 0xD8 00171 #define A_SDA_SCL_SDA 0xDA 00172 #define A_SDA_SDA_SCL 0xDC 00173 #define A_SDA_SDA_SDA 0xDE 00174 #define A_SCL_VSS_VSS 0xF0 00175 #define A_SCL_VSS_VDD 0xF2 00176 #define A_SCL_VDD_VSS 0xF4 00177 #define A_SCL_VDD_VDD 0xF6 00178 #define A_SDA_VSS_VSS 0xF8 00179 #define A_SDA_VSS_VDD 0xFA 00180 #define A_SDA_VDD_VSS 0xFC 00181 #define A_SDA_VDD_VDD 0xFE 00182 #define A_SCL_VSS_SCL 0x00 00183 #define A_SCL_VSS_SDA 0x02 00184 #define A_SCL_VDD_SCL 0x04 00185 #define A_SCL_VDD_SDA 0x06 00186 #define A_SDA_VSS_SCL 0x08 00187 #define A_SDA_VSS_SDA 0x0A 00188 #define A_SDA_VDD_SCL 0x0C 00189 #define A_SDA_VDD_SDA 0x0E 00190 00191
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