This Automatic mode is the most simple lib for MCU Gear with LPC1114FN28. You don't need to think about Bank.
Dependents: MCUGearALPC1114FN28
Fork of MCUGearA by
commonA.h@0:12d93184b350, 2014-03-09 (annotated)
- Committer:
- Info
- Date:
- Sun Mar 09 09:33:14 2014 +0000
- Revision:
- 0:12d93184b350
- Child:
- 1:95255bae41c8
Automatic module changer for MCU Gear. It make circuit each time. You don't need to think about the Bank.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Info | 0:12d93184b350 | 1 | /* MCU Gear Library, only for testing MCUGear without any circuit you connected. |
Info | 0:12d93184b350 | 2 | * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/ |
Info | 0:12d93184b350 | 3 | * |
Info | 0:12d93184b350 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
Info | 0:12d93184b350 | 5 | * of this software and associated documentation files (the "Software"), to deal |
Info | 0:12d93184b350 | 6 | * in the Software without restriction, including without limitation the rights |
Info | 0:12d93184b350 | 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
Info | 0:12d93184b350 | 8 | * copies of the Software, and to permit persons to whom the Software is |
Info | 0:12d93184b350 | 9 | * furnished to do so, subject to the following conditions: |
Info | 0:12d93184b350 | 10 | * |
Info | 0:12d93184b350 | 11 | * The above copyright notice and this permission notice shall be included in |
Info | 0:12d93184b350 | 12 | * all copies or substantial portions of the Software. |
Info | 0:12d93184b350 | 13 | * |
Info | 0:12d93184b350 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
Info | 0:12d93184b350 | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
Info | 0:12d93184b350 | 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
Info | 0:12d93184b350 | 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
Info | 0:12d93184b350 | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
Info | 0:12d93184b350 | 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
Info | 0:12d93184b350 | 20 | * THE SOFTWARE. |
Info | 0:12d93184b350 | 21 | */ |
Info | 0:12d93184b350 | 22 | |
Info | 0:12d93184b350 | 23 | #define numBaseboardIO 48 |
Info | 0:12d93184b350 | 24 | #define numMaxModuleIO 12 |
Info | 0:12d93184b350 | 25 | |
Info | 0:12d93184b350 | 26 | //#define DEBUG //If you need to debug, define this. |
Info | 0:12d93184b350 | 27 | #if defined TARGET_LPC1768 |
Info | 0:12d93184b350 | 28 | |
Info | 0:12d93184b350 | 29 | #define BaudRate 9600 |
Info | 0:12d93184b350 | 30 | #define FPGA_I2C_CLOCK 1000000 |
Info | 0:12d93184b350 | 31 | #define MODULE_I2C_CLOCK 1000000 |
Info | 0:12d93184b350 | 32 | |
Info | 0:12d93184b350 | 33 | #endif |
Info | 0:12d93184b350 | 34 | |
Info | 0:12d93184b350 | 35 | #if defined TARGET_KL25Z |
Info | 0:12d93184b350 | 36 | |
Info | 0:12d93184b350 | 37 | #define BaudRate 19200 |
Info | 0:12d93184b350 | 38 | #define FPGA_I2C_CLOCK 2000000 //about 769kHz |
Info | 0:12d93184b350 | 39 | #define MODULE_I2C_CLOCK 2000000 |
Info | 0:12d93184b350 | 40 | |
Info | 0:12d93184b350 | 41 | #endif |
Info | 0:12d93184b350 | 42 | |
Info | 0:12d93184b350 | 43 | |
Info | 0:12d93184b350 | 44 | #define FPGA_I2C_ADR 0x78 |
Info | 0:12d93184b350 | 45 | |
Info | 0:12d93184b350 | 46 | #ifdef DEBUG |
Info | 0:12d93184b350 | 47 | #define BankMaxNum 3 //you can set 1 to 7 BANKs for Debug Mode. |
Info | 0:12d93184b350 | 48 | |
Info | 0:12d93184b350 | 49 | #else |
Info | 0:12d93184b350 | 50 | #define BankMaxNum 7 //BANK layers |
Info | 0:12d93184b350 | 51 | |
Info | 0:12d93184b350 | 52 | #endif |
Info | 0:12d93184b350 | 53 | |
Info | 0:12d93184b350 | 54 | //PCA9674 |
Info | 0:12d93184b350 | 55 | //VSS = GND VDD = +3.3V |
Info | 0:12d93184b350 | 56 | //AD2 AD1 AD0 |
Info | 0:12d93184b350 | 57 | #define N_VSS_SCL_VSS 0x20 |
Info | 0:12d93184b350 | 58 | #define N_VSS_SCL_VDD 0x22 |
Info | 0:12d93184b350 | 59 | #define N_VSS_SDA_VSS 0x24 |
Info | 0:12d93184b350 | 60 | #define N_VSS_SDA_VDD 0x26 |
Info | 0:12d93184b350 | 61 | #define N_VDD_SCL_VSS 0x28 |
Info | 0:12d93184b350 | 62 | #define N_VDD_SCL_VDD 0x2A |
Info | 0:12d93184b350 | 63 | #define N_VDD_SDA_VSS 0x2C |
Info | 0:12d93184b350 | 64 | #define N_VDD_SDA_VDD 0x2E |
Info | 0:12d93184b350 | 65 | #define N_VSS_SCL_SCL 0x30 |
Info | 0:12d93184b350 | 66 | #define N_VSS_SCL_SDA 0x32 |
Info | 0:12d93184b350 | 67 | #define N_VSS_SDA_SCL 0x34 |
Info | 0:12d93184b350 | 68 | #define N_VSS_SDA_SDA 0x36 |
Info | 0:12d93184b350 | 69 | #define N_VDD_SCL_SCL 0x38 |
Info | 0:12d93184b350 | 70 | #define N_VDD_SCL_SDA 0x3A |
Info | 0:12d93184b350 | 71 | #define N_VDD_SDA_SCL 0x3C |
Info | 0:12d93184b350 | 72 | #define N_VDD_SDA_SDA 0x3E |
Info | 0:12d93184b350 | 73 | #define N_VSS_VSS_VSS 0x40 |
Info | 0:12d93184b350 | 74 | #define N_VSS_VSS_VDD 0x42 |
Info | 0:12d93184b350 | 75 | #define N_VSS_VDD_VSS 0x44 |
Info | 0:12d93184b350 | 76 | #define N_VSS_VDD_VDD 0x46 |
Info | 0:12d93184b350 | 77 | #define N_VDD_VSS_VSS 0x48 |
Info | 0:12d93184b350 | 78 | #define N_VDD_VSS_VDD 0x4A |
Info | 0:12d93184b350 | 79 | #define N_VDD_VDD_VSS 0x4C |
Info | 0:12d93184b350 | 80 | #define N_VDD_VDD_VDD 0x4E |
Info | 0:12d93184b350 | 81 | #define N_VSS_VSS_SCL 0x50 |
Info | 0:12d93184b350 | 82 | #define N_VSS_VSS_SDA 0x52 |
Info | 0:12d93184b350 | 83 | #define N_VSS_VDD_SCL 0x54 |
Info | 0:12d93184b350 | 84 | #define N_VSS_VDD_SDA 0x56 |
Info | 0:12d93184b350 | 85 | #define N_VDD_VSS_SCL 0x58 |
Info | 0:12d93184b350 | 86 | #define N_VDD_VSS_SDA 0x5A |
Info | 0:12d93184b350 | 87 | #define N_VDD_VDD_SCL 0x5C |
Info | 0:12d93184b350 | 88 | #define N_VDD_VDD_SDA 0x5E |
Info | 0:12d93184b350 | 89 | #define N_SCL_SCL_VSS 0xA0 |
Info | 0:12d93184b350 | 90 | #define N_SCL_SCL_VDD 0xA2 |
Info | 0:12d93184b350 | 91 | #define N_SCL_SDA_VSS 0xA4 |
Info | 0:12d93184b350 | 92 | #define N_SCL_SDA_VDD 0xA6 |
Info | 0:12d93184b350 | 93 | #define N_SDA_SCL_VSS 0xA8 |
Info | 0:12d93184b350 | 94 | #define N_SDA_SCL_VDD 0xAA |
Info | 0:12d93184b350 | 95 | #define N_SDA_SDA_VSS 0xAC |
Info | 0:12d93184b350 | 96 | #define N_SDA_SDA_VDD 0xAE |
Info | 0:12d93184b350 | 97 | #define N_SCL_SCL_SCL 0xB0 |
Info | 0:12d93184b350 | 98 | #define N_SCL_SCL_SDA 0xB2 |
Info | 0:12d93184b350 | 99 | #define N_SCL_SDA_SCL 0xB4 |
Info | 0:12d93184b350 | 100 | #define N_SCL_SDA_SDA 0xB6 |
Info | 0:12d93184b350 | 101 | #define N_SDA_SCL_SCL 0xB8 |
Info | 0:12d93184b350 | 102 | #define N_SDA_SCL_SDA 0xBA |
Info | 0:12d93184b350 | 103 | #define N_SDA_SDA_SCL 0xBC |
Info | 0:12d93184b350 | 104 | #define N_SDA_SDA_SDA 0xBE |
Info | 0:12d93184b350 | 105 | #define N_SCL_VSS_VSS 0xC0 |
Info | 0:12d93184b350 | 106 | #define N_SCL_VSS_VDD 0xC2 |
Info | 0:12d93184b350 | 107 | #define N_SCL_VDD_VSS 0xC4 |
Info | 0:12d93184b350 | 108 | #define N_SCL_VDD_VDD 0xC6 |
Info | 0:12d93184b350 | 109 | #define N_SDA_VSS_VSS 0xC8 |
Info | 0:12d93184b350 | 110 | #define N_SDA_VSS_VDD 0xCA |
Info | 0:12d93184b350 | 111 | #define N_SDA_VDD_VSS 0xCC |
Info | 0:12d93184b350 | 112 | #define N_SDA_VDD_VDD 0xCE |
Info | 0:12d93184b350 | 113 | #define N_SCL_VSS_SCL 0xE0 |
Info | 0:12d93184b350 | 114 | #define N_SCL_VSS_SDA 0xE2 |
Info | 0:12d93184b350 | 115 | #define N_SCL_VDD_SCL 0xE4 |
Info | 0:12d93184b350 | 116 | #define N_SCL_VDD_SDA 0xE6 |
Info | 0:12d93184b350 | 117 | #define N_SDA_VSS_SCL 0xE8 |
Info | 0:12d93184b350 | 118 | #define N_SDA_VSS_SDA 0xEA |
Info | 0:12d93184b350 | 119 | #define N_SDA_VDD_SCL 0xEC |
Info | 0:12d93184b350 | 120 | #define N_SDA_VDD_SDA 0xEE |
Info | 0:12d93184b350 | 121 | |
Info | 0:12d93184b350 | 122 | |
Info | 0:12d93184b350 | 123 | //PCA9674A |
Info | 0:12d93184b350 | 124 | //VSS = GND VDD = +3.3V |
Info | 0:12d93184b350 | 125 | //AD2 AD1 AD0 |
Info | 0:12d93184b350 | 126 | #define A_VSS_SCL_VSS 0x10 |
Info | 0:12d93184b350 | 127 | #define A_VSS_SCL_VDD 0x12 |
Info | 0:12d93184b350 | 128 | #define A_VSS_SDA_VSS 0x14 |
Info | 0:12d93184b350 | 129 | #define A_VSS_SDA_VDD 0x16 |
Info | 0:12d93184b350 | 130 | #define A_VDD_SCL_VSS 0x18 |
Info | 0:12d93184b350 | 131 | #define A_VDD_SCL_VDD 0x1A |
Info | 0:12d93184b350 | 132 | #define A_VDD_SDA_VSS 0x1C |
Info | 0:12d93184b350 | 133 | #define A_VDD_SDA_VDD 0x1E |
Info | 0:12d93184b350 | 134 | #define A_VSS_SCL_SCL 0x60 |
Info | 0:12d93184b350 | 135 | #define A_VSS_SCL_SDA 0x62 |
Info | 0:12d93184b350 | 136 | #define A_VSS_SDA_SCL 0x64 |
Info | 0:12d93184b350 | 137 | #define A_VSS_SDA_SDA 0x66 |
Info | 0:12d93184b350 | 138 | #define A_VDD_SCL_SCL 0x68 |
Info | 0:12d93184b350 | 139 | #define A_VDD_SCL_SDA 0x6A |
Info | 0:12d93184b350 | 140 | #define A_VDD_SDA_SCL 0x6C |
Info | 0:12d93184b350 | 141 | #define A_VDD_SDA_SDA 0x6E |
Info | 0:12d93184b350 | 142 | #define A_VSS_VSS_VSS 0x70 |
Info | 0:12d93184b350 | 143 | #define A_VSS_VSS_VDD 0x72 |
Info | 0:12d93184b350 | 144 | #define A_VSS_VDD_VSS 0x74 |
Info | 0:12d93184b350 | 145 | #define A_VSS_VDD_VDD 0x76 |
Info | 0:12d93184b350 | 146 | //#define A_VDD_VSS_VSS 0x78 //This is baseboard address. It is reserved. |
Info | 0:12d93184b350 | 147 | #define A_VDD_VSS_VDD 0x7A |
Info | 0:12d93184b350 | 148 | #define A_VDD_VDD_VSS 0x7C |
Info | 0:12d93184b350 | 149 | #define A_VDD_VDD_VDD 0x7E |
Info | 0:12d93184b350 | 150 | #define A_VSS_VSS_SCL 0x80 |
Info | 0:12d93184b350 | 151 | #define A_VSS_VSS_SDA 0x82 |
Info | 0:12d93184b350 | 152 | #define A_VSS_VDD_SCL 0x84 |
Info | 0:12d93184b350 | 153 | #define A_VSS_VDD_SDA 0x86 |
Info | 0:12d93184b350 | 154 | #define A_VDD_VSS_SCL 0x88 |
Info | 0:12d93184b350 | 155 | #define A_VDD_VSS_SDA 0x8A |
Info | 0:12d93184b350 | 156 | #define A_VDD_VDD_SCL 0x8C |
Info | 0:12d93184b350 | 157 | #define A_VDD_VDD_SDA 0x8E |
Info | 0:12d93184b350 | 158 | #define A_SCL_SCL_VSS 0x90 |
Info | 0:12d93184b350 | 159 | #define A_SCL_SCL_VDD 0x92 |
Info | 0:12d93184b350 | 160 | #define A_SCL_SDA_VSS 0x94 |
Info | 0:12d93184b350 | 161 | #define A_SCL_SDA_VDD 0x96 |
Info | 0:12d93184b350 | 162 | #define A_SDA_SCL_VSS 0x98 |
Info | 0:12d93184b350 | 163 | #define A_SDA_SCL_VDD 0x9A |
Info | 0:12d93184b350 | 164 | #define A_SDA_SDA_VSS 0x9C |
Info | 0:12d93184b350 | 165 | #define A_SDA_SDA_VDD 0x9E |
Info | 0:12d93184b350 | 166 | #define A_SCL_SCL_SCL 0xD0 |
Info | 0:12d93184b350 | 167 | #define A_SCL_SCL_SDA 0xD2 |
Info | 0:12d93184b350 | 168 | #define A_SCL_SDA_SCL 0xD4 |
Info | 0:12d93184b350 | 169 | #define A_SCL_SDA_SDA 0xD6 |
Info | 0:12d93184b350 | 170 | #define A_SDA_SCL_SCL 0xD8 |
Info | 0:12d93184b350 | 171 | #define A_SDA_SCL_SDA 0xDA |
Info | 0:12d93184b350 | 172 | #define A_SDA_SDA_SCL 0xDC |
Info | 0:12d93184b350 | 173 | #define A_SDA_SDA_SDA 0xDE |
Info | 0:12d93184b350 | 174 | #define A_SCL_VSS_VSS 0xF0 |
Info | 0:12d93184b350 | 175 | #define A_SCL_VSS_VDD 0xF2 |
Info | 0:12d93184b350 | 176 | #define A_SCL_VDD_VSS 0xF4 |
Info | 0:12d93184b350 | 177 | #define A_SCL_VDD_VDD 0xF6 |
Info | 0:12d93184b350 | 178 | #define A_SDA_VSS_VSS 0xF8 |
Info | 0:12d93184b350 | 179 | #define A_SDA_VSS_VDD 0xFA |
Info | 0:12d93184b350 | 180 | #define A_SDA_VDD_VSS 0xFC |
Info | 0:12d93184b350 | 181 | #define A_SDA_VDD_VDD 0xFE |
Info | 0:12d93184b350 | 182 | #define A_SCL_VSS_SCL 0x00 |
Info | 0:12d93184b350 | 183 | #define A_SCL_VSS_SDA 0x02 |
Info | 0:12d93184b350 | 184 | #define A_SCL_VDD_SCL 0x04 |
Info | 0:12d93184b350 | 185 | #define A_SCL_VDD_SDA 0x06 |
Info | 0:12d93184b350 | 186 | #define A_SDA_VSS_SCL 0x08 |
Info | 0:12d93184b350 | 187 | #define A_SDA_VSS_SDA 0x0A |
Info | 0:12d93184b350 | 188 | #define A_SDA_VDD_SCL 0x0C |
Info | 0:12d93184b350 | 189 | #define A_SDA_VDD_SDA 0x0E |
Info | 0:12d93184b350 | 190 | |
Info | 0:12d93184b350 | 191 |