MCUGearBase.h

00001 /* MCU Gear Library, only for testing MCUGear without any circuit you connected.
00002  * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a copy
00005  * of this software and associated documentation files (the "Software"), to deal
00006  * in the Software without restriction, including without limitation the rights
00007  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
00008  * copies of the Software, and to permit persons to whom the Software is
00009  * furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included in
00012  * all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00017  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00019  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
00020  * THE SOFTWARE.
00021  */
00022 
00023 #include "common.h"
00024 
00025 
00026 #define FPGA_SYSINFO_0 0x00
00027 #define FPGA_SYSINFO_1 0x04
00028 #define FPGA_ENABLE    0x08
00029 #define FPGA_DETECT    0x14
00030 
00031 /*
00032 // cpu port mapping
00033 #define P5 0
00034 //
00035 #define CON1_1 0
00036 #define CON1_2 0
00037 #define CON1_3 0
00038 #define CON1_4 0
00039 */
00040 void fpga_write(int dev_adr,unsigned char adr, unsigned char data);
00041 unsigned char fpga_read(int dev_adr,unsigned char adr);
00042 void initBase(void);
00043 int detect_module(char addr);
00044 
00045 
00046 // FGPGA CPU I/O
00047 typedef enum {
00048 
00049 #ifdef LPC1768_mbed
00050   IO_MBED_P15 = 0x80,
00051   IO_MBED_P13,
00052   IO_MBED_P16,
00053   IO_MBED_P12,
00054   IO_MBED_P5,
00055   IO_MBED_P11,
00056   IO_MBED_P23,
00057   IO_MBED_P22,
00058   IO_MBED_P26,
00059   IO_MBED_P10,
00060   IO_MBED_P21,
00061   IO_MBED_P9,
00062   IO_MBED_P6,
00063   IO_MBED_P7,
00064   IO_MBED_P8,
00065   IO_MBED_P14,
00066   IO_MBED_P24,
00067   IO_MBED_P25,
00068   IO_MBED_P28,
00069   IO_MBED_P27
00070 #endif
00071 
00072 #ifdef FS_KL25Z
00073 
00074   IO_MBED_PTA5 = 0x80,
00075   IO_MBED_PTC8,
00076   IO_MBED_PTC9,
00077   IO_MBED_PTD5,
00078   IO_MBED_PTA13,
00079   IO_MBED_PTD2,
00080   IO_MBED_PTB1,
00081   IO_MBED_PTB2,
00082   IO_MBED_PTA2,
00083   IO_MBED_PTD4,
00084   IO_MBED_PTB3,
00085   IO_MBED_PTA12,
00086   IO_MBED_PTD0,
00087   IO_MBED_PTD3,
00088   IO_MBED_PTD1,
00089   IO_MBED_PTA4,
00090   IO_MBED_PTB0,
00091   IO_MBED_PTA1,
00092   IO_MBED_PTE0, //SDA
00093   IO_MBED_PTE1  //SCL
00094 #endif
00095   
00096 } en_cpu_io;
00097 
00098 // FPGA EXT I/O
00099 typedef enum {
00100   IO_CON1_1 = 0,
00101   IO_CON1_2,
00102   IO_CON1_3,
00103   IO_CON1_4,
00104   IO_CON2_1,
00105   IO_CON2_2,
00106   IO_CON2_3,
00107   IO_CON2_4,
00108   IO_CON3_1,
00109   IO_CON3_2,
00110   IO_CON3_3,
00111   IO_CON3_4,
00112   IO_CON4_1,
00113   IO_CON4_2,
00114   IO_CON4_3,
00115   IO_CON4_4,
00116   IO_CON5_1,
00117   IO_CON5_2,
00118   IO_CON5_3,
00119   IO_CON5_4,
00120   IO_CON6_1,
00121   IO_CON6_2,
00122   IO_CON6_3,
00123   IO_CON6_4,
00124   IO_CON7_1,
00125   IO_CON7_2,
00126   IO_CON7_3,
00127   IO_CON7_4,
00128   IO_CON8_1,
00129   IO_CON8_2,
00130   IO_CON8_3,
00131   IO_CON8_4,
00132   IO_CON9_1,
00133   IO_CON9_2,
00134   IO_CON9_3,
00135   IO_CON9_4,
00136   IO_CON10_1,
00137   IO_CON10_2,
00138   IO_CON10_3,
00139   IO_CON10_4,
00140   IO_CON11_1,
00141   IO_CON11_2,
00142   IO_CON11_3,
00143   IO_CON11_4,
00144   IO_CON12_1,
00145   IO_CON12_2,
00146   IO_CON12_3,
00147   IO_CON12_4
00148 } en_fpga_io;
00149 
00150 typedef enum {
00151   IO_REG_EN = 0x80,
00152   IO_REG_OUT_DIR = 0x40,
00153   IO_REG_IN_DIR  = 0x00,
00154   IO_REG_DISABLE = 0x3f
00155 } en_fpga_io_reg;
00156 
00157