Helmut Tschemernjak
mbed library sources. Supersedes mbed-src.
Fork of
mbed-dev
by 
mbed official
Revision 152:9a67f0b066fc, committed 2016-12-15
- Comitter:
- <>
- Date:
- Thu Dec 15 11:48:27 2016 +0000
- Parent:
- 151:5eaa88a5bcc7
- Child:
- 153:fa9ff456f731
- Commit message:
- This updates the lib to the mbed lib v131
Changed in this revision
--- a/cmsis/core_cm0.h Thu Nov 24 17:03:03 2016 +0000
+++ b/cmsis/core_cm0.h Thu Dec 15 11:48:27 2016 +0000
@@ -589,6 +589,8 @@
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
}
--- a/cmsis/core_cm0plus.h Thu Nov 24 17:03:03 2016 +0000
+++ b/cmsis/core_cm0plus.h Thu Dec 15 11:48:27 2016 +0000
@@ -703,6 +703,8 @@
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
}
--- a/cmsis/core_cm3.h Thu Nov 24 17:03:03 2016 +0000
+++ b/cmsis/core_cm3.h Thu Dec 15 11:48:27 2016 +0000
@@ -1431,6 +1431,8 @@
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
}
--- a/cmsis/core_cm4.h Thu Nov 24 17:03:03 2016 +0000
+++ b/cmsis/core_cm4.h Thu Dec 15 11:48:27 2016 +0000
@@ -1597,6 +1597,8 @@
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
}
--- a/cmsis/core_cm7.h Thu Nov 24 17:03:03 2016 +0000
+++ b/cmsis/core_cm7.h Thu Dec 15 11:48:27 2016 +0000
@@ -1754,6 +1754,8 @@
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
}
--- a/cmsis/core_sc000.h Thu Nov 24 17:03:03 2016 +0000
+++ b/cmsis/core_sc000.h Thu Dec 15 11:48:27 2016 +0000
@@ -705,6 +705,8 @@
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
}
--- a/cmsis/core_sc300.h Thu Nov 24 17:03:03 2016 +0000
+++ b/cmsis/core_sc300.h Thu Dec 15 11:48:27 2016 +0000
@@ -1376,6 +1376,8 @@
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/emac_api.h Thu Dec 15 11:48:27 2016 +0000
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_EMAC_API_H
+#define MBED_EMAC_API_H
+
+#if DEVICE_EMAC
+
+#include <stdbool.h>
+#include "emac_stack_mem.h"
+
+typedef struct emac_interface emac_interface_t;
+
+/**
+ * EmacInterface
+ *
+ * This interface should be used to abstract low level access to networking hardware
+ */
+
+/**
+ * Callback to be register with Emac interface and to be called fore received packets
+ *
+ * @param data Arbitrary user data (IP stack)
+ * @param buf Received data
+ */
+typedef void (*emac_link_input_fn)(void *data, emac_stack_mem_chain_t *buf);
+
+/**
+ * Callback to be register with Emac interface and to be called for link status changes
+ *
+ * @param data Arbitrary user data (IP stack)
+ * @param up Link status
+ */
+typedef void (*emac_link_state_change_fn)(void *data, bool up);
+
+/**
+ * Return maximum transmission unit
+ *
+ * @param emac Emac interface
+ * @return MTU in bytes
+ */
+typedef uint32_t (*emac_get_mtu_size_fn)(emac_interface_t *emac);
+
+/**
+ * Return interface name
+ *
+ * @param emac Emac interface
+ * @param name Pointer to where the name should be written
+ * @param size Maximum number of character to copy
+ */
+typedef void (*emac_get_ifname_fn)(emac_interface_t *emac, char *name, uint8_t size);
+
+/**
+ * Returns size of the underlying interface HW address size
+ *
+ * @param emac Emac interface
+ * @return HW address size in bytes
+ */
+typedef uint8_t (*emac_get_hwaddr_size_fn)(emac_interface_t *emac);
+
+/**
+ * Return interface hw address
+ *
+ * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size
+ *
+ * @param emac Emac interface
+ * @param addr HW address for underlying interface
+ */
+typedef void (*emac_get_hwaddr_fn)(emac_interface_t *emac, uint8_t *addr);
+
+/**
+ * Set HW address for interface
+ *
+ * Provided address has to be of correct size, see @a get_hwaddr_size
+ *
+ * @param emac Emac interface
+ * @param addr Address to be set
+ */
+typedef void (*emac_set_hwaddr_fn)(emac_interface_t *emac, uint8_t *addr);
+
+/**
+ * Sends the packet over the link
+ *
+ * That can not be called from an interrupt context.
+ *
+ * @param emac Emac interface
+ * @param buf Packet to be send
+ * @return True if the packet was send successfully, False otherwise
+ */
+typedef bool (*emac_link_out_fn)(emac_interface_t *emac, emac_stack_mem_t *buf);
+
+/**
+ * Initializes the HW
+ *
+ * @return True on success, False in case of an error.
+ */
+typedef bool (*emac_power_up_fn)(emac_interface_t *emac);
+
+/**
+ * Deinitializes the HW
+ *
+ * @param emac Emac interface
+ */
+typedef void (*emac_power_down_fn)(emac_interface_t *emac);
+
+/**
+ * Sets a callback that needs to be called for packets received for that interface
+ *
+ * @param emac Emac interface
+ * @param input_cb Function to be register as a callback
+ * @param data Arbitrary user data to be passed to the callback
+ */
+typedef void (*emac_set_link_input_cb_fn)(emac_interface_t *emac, emac_link_input_fn input_cb, void *data);
+
+/**
+ * Sets a callback that needs to be called on link status changes for given interface
+ *
+ * @param emac Emac interface
+ * @param state_cb Function to be register as a callback
+ * @param data Arbitrary user data to be passed to the callback
+ */
+typedef void (*emac_set_link_state_cb_fn)(emac_interface_t *emac, emac_link_state_change_fn state_cb, void *data);
+
+typedef struct emac_interface_ops {
+ emac_get_mtu_size_fn get_mtu_size;
+ emac_get_ifname_fn get_ifname;
+ emac_get_hwaddr_size_fn get_hwaddr_size;
+ emac_get_hwaddr_fn get_hwaddr;
+ emac_set_hwaddr_fn set_hwaddr;
+ emac_link_out_fn link_out;
+ emac_power_up_fn power_up;
+ emac_power_down_fn power_down;
+ emac_set_link_input_cb_fn set_link_input_cb;
+ emac_set_link_state_cb_fn set_link_state_cb;
+} emac_interface_ops_t;
+
+typedef struct emac_interface {
+ const emac_interface_ops_t ops;
+ void *hw;
+} emac_interface_t;
+
+#else
+
+typedef void *emac_interface_t;
+
+#endif /* DEVICE_EMAC */
+#endif /* MBED_EMAC_API_H */
--- a/mbed.h Thu Nov 24 17:03:03 2016 +0000 +++ b/mbed.h Thu Dec 15 11:48:27 2016 +0000 @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 130 +#define MBED_LIBRARY_VERSION 131 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 -#define MBED_MINOR_VERSION 2 -#define MBED_PATCH_VERSION 3 +#define MBED_MINOR_VERSION 3 +#define MBED_PATCH_VERSION 0 #else // mbed 2
--- a/platform/mbed_alloc_wrappers.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/platform/mbed_alloc_wrappers.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -57,6 +57,9 @@
void mbed_stats_heap_get(mbed_stats_heap_t *stats)
{
#ifdef MBED_HEAP_STATS_ENABLED
+ extern uint32_t mbed_heap_size;
+ heap_stats.reserved_size = mbed_heap_size;
+
malloc_stats_mutex->lock();
memcpy(stats, &heap_stats, sizeof(mbed_stats_heap_t));
malloc_stats_mutex->unlock();
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_stats.c Thu Dec 15 11:48:27 2016 +0000
@@ -0,0 +1,69 @@
+#include "mbed_stats.h"
+#include <string.h>
+
+#if MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#endif
+
+// note: mbed_stats_heap_get defined in mbed_alloc_wrappers.cpp
+
+void mbed_stats_stack_get(mbed_stats_stack_t *stats)
+{
+ memset(stats, 0, sizeof(mbed_stats_stack_t));
+
+#if MBED_STACK_STATS_ENABLED && MBED_CONF_RTOS_PRESENT
+ osThreadEnumId enumid = _osThreadsEnumStart();
+ osThreadId threadid;
+
+ while ((threadid = _osThreadEnumNext(enumid))) {
+ osEvent e;
+
+ e = _osThreadGetInfo(threadid, osThreadInfoStackMax);
+ if (e.status == osOK) {
+ stats->max_size += (uint32_t)e.value.p;
+ }
+
+ e = _osThreadGetInfo(threadid, osThreadInfoStackSize);
+ if (e.status == osOK) {
+ stats->reserved_size += (uint32_t)e.value.p;
+ }
+
+ stats->stack_cnt += 1;
+ }
+#endif
+}
+
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count)
+{
+ memset(stats, 0, count*sizeof(mbed_stats_stack_t));
+ size_t i = 0;
+
+#if MBED_STACK_STATS_ENABLED && MBED_CONF_RTOS_PRESENT
+ osThreadEnumId enumid = _osThreadsEnumStart();
+ osThreadId threadid;
+
+ while ((threadid = _osThreadEnumNext(enumid)) && i < count) {
+ osEvent e;
+
+ e = _osThreadGetInfo(threadid, osThreadInfoStackMax);
+ if (e.status == osOK) {
+ stats[i].max_size = (uint32_t)e.value.p;
+ }
+
+ e = _osThreadGetInfo(threadid, osThreadInfoStackSize);
+ if (e.status == osOK) {
+ stats[i].reserved_size = (uint32_t)e.value.p;
+ }
+
+ stats[i].thread_id = (uint32_t)threadid;
+ stats[i].stack_cnt = 1;
+ i += 1;
+ }
+#endif
+
+ return i;
+}
+
+#if MBED_STACK_STATS_ENABLED && !MBED_CONF_RTOS_PRESENT
+#warning Stack statistics are currently not supported without the rtos.
+#endif
--- a/platform/mbed_stats.h Thu Nov 24 17:03:03 2016 +0000
+++ b/platform/mbed_stats.h Thu Dec 15 11:48:27 2016 +0000
@@ -18,6 +18,8 @@
*/
#ifndef MBED_STATS_H
#define MBED_STATS_H
+#include <stdint.h>
+#include <stddef.h>
#ifdef __cplusplus
extern "C" {
@@ -27,15 +29,43 @@
uint32_t current_size; /**< Bytes allocated currently. */
uint32_t max_size; /**< Max bytes allocated at a given time. */
uint32_t total_size; /**< Cumulative sum of bytes ever allocated. */
+ uint32_t reserved_size; /**< Current number of bytes allocated for the heap. */
uint32_t alloc_cnt; /**< Current number of allocations. */
uint32_t alloc_fail_cnt; /**< Number of failed allocations. */
} mbed_stats_heap_t;
/**
- * Fill the passed in structure with heap stats.
+ * Fill the passed in heap stat structure with heap stats.
+ *
+ * @param stats A pointer to the mbed_stats_heap_t structure to fill
*/
void mbed_stats_heap_get(mbed_stats_heap_t *stats);
+typedef struct {
+ uint32_t thread_id; /**< Identifier for thread that owns the stack. */
+ uint32_t max_size; /**< Sum of the maximum number of bytes used in each stack. */
+ uint32_t reserved_size; /**< Current number of bytes allocated for all stacks. */
+ uint32_t stack_cnt; /**< Number of stacks currently allocated. */
+} mbed_stats_stack_t;
+
+/**
+ * Fill the passed in structure with stack stats.
+ *
+ * @param stats A pointer to the mbed_stats_stack_t structure to fill
+ */
+void mbed_stats_stack_get(mbed_stats_stack_t *stats);
+
+/**
+ * Fill the passed array of stat structures with the stack stats
+ * for each available stack.
+ *
+ * @param stats A pointer to an array of mbed_stats_stack_t structures to fill
+ * @param count The number of mbed_stats_stack_t structures in the provided array
+ * @return The number of mbed_stats_stack_t structures that have been filled,
+ * this is equal to the number of stacks on the system.
+ */
+size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of FTM peripheral base address. */
static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -93,7 +96,8 @@
FTM_SetSoftwareTrigger(base, true);
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK;
uint16_t mod = base->MOD & FTM_MOD_MOD_MASK;
@@ -104,16 +108,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -122,15 +129,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -41,7 +41,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -74,16 +75,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
UART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
UART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -111,7 +115,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
UART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -130,36 +135,43 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = UART0->S1;
uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = UART1->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1);
}
-void uart2_irq() {
+void uart2_irq()
+{
uint32_t status_flags = UART2->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2);
}
-void uart3_irq() {
+void uart3_irq()
+{
uint32_t status_flags = UART3->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 3);
}
-void uart4_irq() {
+void uart4_irq()
+{
uint32_t status_flags = UART4->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 4);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = UART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -225,7 +237,8 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
while (!serial_readable(obj));
uint8_t data;
data = UART_ReadByte(uart_addrs[obj->index]);
@@ -233,37 +246,44 @@
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
UART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,11 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
DSPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@@ -84,18 +87,21 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
//Half clock period delay after SPI transfer
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
dspi_command_data_config_t command;
uint32_t rx_data;
DSPI_GetDefaultDataCommandConfig(&command);
@@ -112,11 +118,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -125,7 +133,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -51,7 +52,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -59,15 +61,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_IAR/MK82FN256xxx15.icf Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/TOOLCHAIN_IAR/MK82FN256xxx15.icf Thu Dec 15 11:48:27 2016 +0000
@@ -1,124 +1,124 @@
-/*
-** ###################################################################
-** Processors: MK82FN256CAx15
-** MK82FN256VDC15
-** MK82FN256VLL15
-** MK82FN256VLQ15
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
-** Version: rev. 1.2, 2015-07-29
-** Build: b160406
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright (c) 2016 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** ###################################################################
-*/
-
-define symbol __ram_vector_table__ = 1;
+/*
+** ###################################################################
+** Processors: MK82FN256CAx15
+** MK82FN256VDC15
+** MK82FN256VLL15
+** MK82FN256VLQ15
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
+** Version: rev. 1.2, 2015-07-29
+** Build: b160406
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright (c) 2016 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** ###################################################################
+*/
+
+define symbol __ram_vector_table__ = 1;
/* Heap 1/4 of ram and stack 1/8 */
define symbol __stack_size__=0x8000;
-define symbol __heap_size__=0x10000;
-
-define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003C0 : 0;
-define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003BF : 0;
-
-define symbol m_interrupts_start = 0x00000000;
-define symbol m_interrupts_end = 0x000003BF;
-
-define symbol m_bootloader_config_start = 0x000003C0;
-define symbol m_bootloader_config_end = 0x000003FF;
-
-define symbol m_flash_config_start = 0x00000400;
-define symbol m_flash_config_end = 0x0000040F;
-
-define symbol m_text_start = 0x00000410;
-define symbol m_text_end = 0x0003FFFF;
-
-define symbol m_interrupts_ram_start = 0x1FFF0000;
-define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__;
-
-define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
-define symbol m_data_end = 0x1FFFFFFF;
-
-define symbol m_data_2_start = 0x20000000;
-define symbol m_data_2_end = 0x2002FFFF;
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
-
-define memory mem with size = 4G;
-define region m_bootloader_config_region = mem:[from m_bootloader_config_start to m_bootloader_config_end];
-define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-define region DATA_region = mem:[from m_data_start to m_data_end]
- | mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
-define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-place in m_bootloader_config_region { section BootloaderConfig };
-place in m_flash_config_region { section FlashConfig };
-place in TEXT_region { readonly };
-place in DATA_region { block RW };
-place in DATA_region { block ZI };
-place in DATA_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
-place in m_interrupts_ram_region { section m_interrupts_ram };
-
+define symbol __heap_size__=0x10000;
+
+define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003C0 : 0;
+define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003BF : 0;
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x000003BF;
+
+define symbol m_bootloader_config_start = 0x000003C0;
+define symbol m_bootloader_config_end = 0x000003FF;
+
+define symbol m_flash_config_start = 0x00000400;
+define symbol m_flash_config_end = 0x0000040F;
+
+define symbol m_text_start = 0x00000410;
+define symbol m_text_end = 0x0003FFFF;
+
+define symbol m_interrupts_ram_start = 0x1FFF0000;
+define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__;
+
+define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
+define symbol m_data_end = 0x1FFFFFFF;
+
+define symbol m_data_2_start = 0x20000000;
+define symbol m_data_2_end = 0x2002FFFF;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
+
+define memory mem with size = 4G;
+define region m_bootloader_config_region = mem:[from m_bootloader_config_start to m_bootloader_config_end];
+define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end]
+ | mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
+define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+place in m_bootloader_config_region { section BootloaderConfig };
+place in m_flash_config_region { section FlashConfig };
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+place in m_interrupts_ram_region { section m_interrupts_ram };
+
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of FTM peripheral base address. */
static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -93,7 +96,8 @@
FTM_SetSoftwareTrigger(base, true);
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK;
uint16_t mod = base->MOD & FTM_MOD_MOD_MASK;
@@ -104,16 +108,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -122,15 +129,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -40,7 +40,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -75,16 +76,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
LPUART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
LPUART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -114,7 +118,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
LPUART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -134,37 +139,44 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = LPUART0->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = LPUART1->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1);
}
-void uart2_irq() {
+void uart2_irq()
+{
uint32_t status_flags = LPUART2->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 2);
}
-void uart3_irq() {
+void uart3_irq()
+{
uint32_t status_flags = LPUART3->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 3);
}
-void uart4_irq() {
+void uart4_irq()
+{
uint32_t status_flags = LPUART4->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 4);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -230,44 +242,52 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
uint8_t data;
LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1);
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,11 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
DSPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@@ -84,18 +87,21 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
//Half clock period delay after SPI transfer
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
dspi_command_data_config_t command;
uint32_t rx_data;
DSPI_GetDefaultDataCommandConfig(&command);
@@ -112,11 +118,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -125,7 +133,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K82F/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -51,7 +52,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -59,15 +61,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of TPM peripheral base address. */
static TPM_Type *const tpm_addrs[] = TPM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
TPM_Deinit(tpm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -91,7 +94,8 @@
base->CNT = 0;
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & TPM_CnV_VAL_MASK;
uint16_t mod = base->MOD & TPM_MOD_MOD_MASK;
@@ -102,16 +106,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -120,15 +127,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -40,7 +40,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -79,16 +80,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
LPUART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
LPUART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -118,7 +122,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
LPUART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -138,22 +143,26 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = LPUART0->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = LPUART1->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -210,44 +219,52 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
uint8_t data;
LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1);
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,11 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
SPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
spi_master_config_t master_config;
spi_slave_config_t slave_config;
@@ -87,15 +90,18 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
SPI_MasterSetBaudRate(spi_address[obj->instance], (uint32_t)hz, CLOCK_GetFreq(spi_clocks[obj->instance]));
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (SPI_GetStatusFlags(spi_address[obj->instance]) & kSPI_RxBufferFullFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
spi_transfer_t xfer = {0};
uint32_t rx_data;
SPI_Type *base = spi_address[obj->instance];
@@ -109,11 +115,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -122,7 +130,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
SPI_Type *base = spi_address[obj->instance];
size_t size = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
SPI_WriteBlocking(spi_address[obj->instance], (uint8_t *)&value, size);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -22,7 +22,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -60,7 +61,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -68,15 +70,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of TPM peripheral base address. */
static TPM_Type *const tpm_addrs[] = TPM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
TPM_Deinit(tpm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -91,7 +94,8 @@
base->CNT = 0;
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & TPM_CnV_VAL_MASK;
uint16_t mod = base->MOD & TPM_MOD_MOD_MASK;
@@ -102,16 +106,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -120,15 +127,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -40,7 +40,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -79,16 +80,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
LPUART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
LPUART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -118,7 +122,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
LPUART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -138,22 +143,26 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = LPUART0->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = LPUART1->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -210,44 +219,52 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
uint8_t data;
LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1);
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,11 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
SPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
spi_master_config_t master_config;
spi_slave_config_t slave_config;
@@ -87,15 +90,18 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
SPI_MasterSetBaudRate(spi_address[obj->instance], (uint32_t)hz, CLOCK_GetFreq(spi_clocks[obj->instance]));
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (SPI_GetStatusFlags(spi_address[obj->instance]) & kSPI_RxBufferFullFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
spi_transfer_t xfer = {0};
uint32_t rx_data;
SPI_Type *base = spi_address[obj->instance];
@@ -109,11 +115,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -122,7 +130,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
SPI_Type *base = spi_address[obj->instance];
size_t size = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U;
SPI_WriteBlocking(spi_address[obj->instance], (uint8_t *)&value, size);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -22,7 +22,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -60,7 +61,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -68,15 +70,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/MKL82Z128xxx7.icf Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/MKL82Z128xxx7.icf Thu Dec 15 11:48:27 2016 +0000
@@ -1,139 +1,139 @@
-/*
-** ###################################################################
-** Processors: MKL82Z128VLH7
-** MKL82Z128VLK7
-** MKL82Z128VLL7
-** MKL82Z128VMC7
-** MKL82Z128VMP7
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: KL82P121M72SF0RM, Rev.2 November 2015
-** Version: rev. 1.5, 2015-09-24
-** Build: b160406
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright (c) 2016 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** ###################################################################
-*/
+/*
+** ###################################################################
+** Processors: MKL82Z128VLH7
+** MKL82Z128VLK7
+** MKL82Z128VLL7
+** MKL82Z128VMC7
+** MKL82Z128VMP7
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: KL82P121M72SF0RM, Rev.2 November 2015
+** Version: rev. 1.5, 2015-09-24
+** Build: b160406
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright (c) 2016 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** ###################################################################
+*/
define symbol __ram_vector_table__ = 1;
/* Heap 1/4 of ram and stack 1/8 */
-define symbol __stack_size__=0x3000;
-define symbol __heap_size__=0x6000;
-
-define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000140 : 0;
-define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x0000013F : 0;
-
-define symbol m_interrupts_start = 0x00000000;
-define symbol m_interrupts_end = 0x0000013F;
-
-define symbol m_bootloader_config_start = 0x000003C0;
-define symbol m_bootloader_config_end = 0x000003FF;
-
-define symbol m_flash_config_start = 0x00000400;
-define symbol m_flash_config_end = 0x0000040F;
-
-define symbol m_text_start = 0x00000410;
-define symbol m_text_end = 0x0001FFFF;
-
-define symbol m_interrupts_ram_start = 0x1FFFA000;
-define symbol m_interrupts_ram_end = 0x1FFFA000 + __ram_vector_table_offset__;
-
-define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
-define symbol m_data_end = 0x20011FFF;
-
-if (isdefinedsymbol(__usb_use_usbram__)) {
- define symbol m_usb_sram_start = 0x40100000;
- define symbol m_usb_sram_end = 0x401007FF;
-}
-
-/* USB BDT size */
-define symbol usb_bdt_size = 0x200;
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
-
-define memory mem with size = 4G;
-define region m_bootloader_config_region = mem:[from m_bootloader_config_start to m_bootloader_config_end];
-define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
-define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-
-/* regions for USB */
-if (isdefinedsymbol(__usb_use_usbram__)) {
- define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
- define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
- place in USB_BDT_region { section m_usb_bdt };
- place in USB_SRAM_region { section m_usb_global };
-}
-
-initialize by copy { readwrite, section .textrw };
-if (isdefinedsymbol(__usb_use_usbram__)) {
- do not initialize { section .noinit, section m_usb_bdt, section m_usb_global };
-} else {
- do not initialize { section .noinit };
-}
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-place in m_bootloader_config_region { section BootloaderConfig };
-place in m_flash_config_region { section FlashConfig };
-place in TEXT_region { readonly };
-place in DATA_region { block RW };
-place in DATA_region { block ZI };
-place in DATA_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
-place in m_interrupts_ram_region { section m_interrupts_ram };
-
+define symbol __stack_size__=0x3000;
+define symbol __heap_size__=0x6000;
+
+define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000140 : 0;
+define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x0000013F : 0;
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x0000013F;
+
+define symbol m_bootloader_config_start = 0x000003C0;
+define symbol m_bootloader_config_end = 0x000003FF;
+
+define symbol m_flash_config_start = 0x00000400;
+define symbol m_flash_config_end = 0x0000040F;
+
+define symbol m_text_start = 0x00000410;
+define symbol m_text_end = 0x0001FFFF;
+
+define symbol m_interrupts_ram_start = 0x1FFFA000;
+define symbol m_interrupts_ram_end = 0x1FFFA000 + __ram_vector_table_offset__;
+
+define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
+define symbol m_data_end = 0x20011FFF;
+
+if (isdefinedsymbol(__usb_use_usbram__)) {
+ define symbol m_usb_sram_start = 0x40100000;
+ define symbol m_usb_sram_end = 0x401007FF;
+}
+
+/* USB BDT size */
+define symbol usb_bdt_size = 0x200;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
+
+define memory mem with size = 4G;
+define region m_bootloader_config_region = mem:[from m_bootloader_config_start to m_bootloader_config_end];
+define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+
+/* regions for USB */
+if (isdefinedsymbol(__usb_use_usbram__)) {
+ define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+ define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+ place in USB_BDT_region { section m_usb_bdt };
+ place in USB_SRAM_region { section m_usb_global };
+}
+
+initialize by copy { readwrite, section .textrw };
+if (isdefinedsymbol(__usb_use_usbram__)) {
+ do not initialize { section .noinit, section m_usb_bdt, section m_usb_global };
+} else {
+ do not initialize { section .noinit };
+}
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+place in m_bootloader_config_region { section BootloaderConfig };
+place in m_flash_config_region { section FlashConfig };
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+place in m_interrupts_ram_region { section m_interrupts_ram };
+
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of TPM peripheral base address. */
static TPM_Type *const tpm_addrs[] = TPM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
TPM_Deinit(tpm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -91,7 +94,8 @@
base->CNT = 0;
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & TPM_CnV_VAL_MASK;
uint16_t mod = base->MOD & TPM_MOD_MOD_MASK;
@@ -102,16 +106,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -120,15 +127,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -40,7 +40,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -75,16 +76,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
LPUART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
LPUART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -114,7 +118,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
LPUART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -134,27 +139,32 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = LPUART0->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = LPUART1->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1);
}
-void uart2_irq() {
+void uart2_irq()
+{
uint32_t status_flags = LPUART2->STAT;
uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 2);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -214,44 +224,52 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
uint8_t data;
LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1);
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kLPUART_RxOverrunFlag)
LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
return (status_flags & kLPUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,12 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
DSPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@@ -84,18 +86,21 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
//Half clock period delay after SPI transfer
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
dspi_command_data_config_t command;
uint32_t rx_data;
DSPI_GetDefaultDataCommandConfig(&command);
@@ -112,11 +117,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -125,7 +132,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -51,7 +52,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -59,15 +61,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of FTM peripheral base address. */
static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -93,7 +96,8 @@
FTM_SetSoftwareTrigger(base, true);
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK;
uint16_t mod = base->MOD & FTM_MOD_MOD_MASK;
@@ -104,16 +108,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -122,15 +129,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -41,7 +41,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -74,16 +75,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
UART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
UART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -111,7 +115,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
UART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -130,27 +135,32 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = UART0->S1;
uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = UART1->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1);
}
-void uart2_irq() {
+void uart2_irq()
+{
uint32_t status_flags = UART2->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = UART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -210,7 +220,8 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
while (!serial_readable(obj));
uint8_t data;
data = UART_ReadByte(uart_addrs[obj->index]);
@@ -218,37 +229,44 @@
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
UART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,12 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
DSPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@@ -84,18 +86,21 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
//Half clock period delay after SPI transfer
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
dspi_command_data_config_t command;
uint32_t rx_data;
DSPI_GetDefaultDataCommandConfig(&command);
@@ -112,11 +117,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -125,7 +132,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KW24D/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -51,7 +52,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -59,15 +61,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of FTM peripheral base address. */
static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -93,7 +96,8 @@
FTM_SetSoftwareTrigger(base, true);
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK;
uint16_t mod = base->MOD & FTM_MOD_MOD_MASK;
@@ -104,16 +108,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -122,15 +129,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -41,7 +41,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -74,16 +75,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
UART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
UART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -111,7 +115,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
UART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -130,27 +135,32 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = UART0->S1;
uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = UART1->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1);
}
-void uart2_irq() {
+void uart2_irq()
+{
uint32_t status_flags = UART2->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = UART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -210,7 +220,8 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
while (!serial_readable(obj));
uint8_t data;
data = UART_ReadByte(uart_addrs[obj->index]);
@@ -218,37 +229,44 @@
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
UART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,12 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
DSPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@@ -84,18 +86,21 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
//Half clock period delay after SPI transfer
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
dspi_command_data_config_t command;
uint32_t rx_data;
DSPI_GetDefaultDataCommandConfig(&command);
@@ -112,11 +117,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -125,7 +132,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K22F/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -51,7 +52,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -59,15 +61,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
@@ -14,7 +14,8 @@
extern char Image$$RW_IRAM1$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/device/cmsis_nvic.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,11 +32,13 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
InstallIRQHandler(IRQn, vector);
}
-uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_common.h Thu Nov 24 17:03:03 2016 +0000 +++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_common.h Thu Dec 15 11:48:27 2016 +0000 @@ -34,6 +34,7 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> +#include <stddef.h> #include <string.h> #include "fsl_device_registers.h"
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/pwmout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -27,7 +27,8 @@
/* Array of FTM peripheral base address. */
static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS;
-void pwmout_init(pwmout_t* obj, PinName pin) {
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
@@ -72,11 +73,13 @@
pinmap_pinout(pin, PinMap_PWM);
}
-void pwmout_free(pwmout_t* obj) {
+void pwmout_free(pwmout_t* obj)
+{
FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]);
}
-void pwmout_write(pwmout_t* obj, float value) {
+void pwmout_write(pwmout_t* obj, float value)
+{
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
@@ -93,7 +96,8 @@
FTM_SetSoftwareTrigger(base, true);
}
-float pwmout_read(pwmout_t* obj) {
+float pwmout_read(pwmout_t* obj)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK;
uint16_t mod = base->MOD & FTM_MOD_MOD_MASK;
@@ -104,16 +108,19 @@
return (v > 1.0f) ? (1.0f) : (v);
}
-void pwmout_period(pwmout_t* obj, float seconds) {
+void pwmout_period(pwmout_t* obj, float seconds)
+{
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms) {
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
+void pwmout_period_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
float dc = pwmout_read(obj);
@@ -122,15 +129,18 @@
pwmout_write(obj, dc);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT];
uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/serial_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/serial_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -41,7 +41,8 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
obj->index = pinmap_merge(uart_tx, uart_rx);
@@ -74,16 +75,19 @@
}
}
-void serial_free(serial_t *obj) {
+void serial_free(serial_t *obj)
+{
UART_Deinit(uart_addrs[obj->index]);
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate) {
+void serial_baud(serial_t *obj, int baudrate)
+{
UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
UART_Type *base = uart_addrs[obj->index];
uint8_t temp;
/* Set bit count and parity mode. */
@@ -111,7 +115,8 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
UART_Type *base = uart_addrs[index];
/* If RX overrun. */
@@ -130,42 +135,50 @@
}
}
-void uart0_irq() {
+void uart0_irq()
+{
uint32_t status_flags = UART0->S1;
uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0);
}
-void uart1_irq() {
+void uart1_irq()
+{
uint32_t status_flags = UART1->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1);
}
-void uart2_irq() {
+void uart2_irq()
+{
uint32_t status_flags = UART2->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2);
}
-void uart3_irq() {
+void uart3_irq()
+{
uint32_t status_flags = UART3->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 3);
}
-void uart4_irq() {
+void uart4_irq()
+{
uint32_t status_flags = UART4->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 4);
}
-void uart5_irq() {
+void uart5_irq()
+{
uint32_t status_flags = UART5->S1;
uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 5);
}
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
IRQn_Type uart_irqs[] = UART_RX_TX_IRQS;
uint32_t vector = 0;
@@ -234,7 +247,8 @@
}
}
-int serial_getc(serial_t *obj) {
+int serial_getc(serial_t *obj)
+{
while (!serial_readable(obj));
uint8_t data;
data = UART_ReadByte(uart_addrs[obj->index]);
@@ -242,37 +256,44 @@
return data;
}
-void serial_putc(serial_t *obj, int c) {
+void serial_putc(serial_t *obj, int c)
+{
while (!serial_writable(obj));
UART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
}
-int serial_readable(serial_t *obj) {
+int serial_readable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_RxDataRegFullFlag);
}
-int serial_writable(serial_t *obj) {
+int serial_writable(serial_t *obj)
+{
uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]);
if (status_flags & kUART_RxOverrunFlag)
UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag);
return (status_flags & kUART_TxDataRegEmptyFlag);
}
-void serial_clear(serial_t *obj) {
+void serial_clear(serial_t *obj)
+{
}
-void serial_pinout_tx(PinName tx) {
+void serial_pinout_tx(PinName tx)
+{
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj) {
+void serial_break_set(serial_t *obj)
+{
uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK;
}
-void serial_break_clear(serial_t *obj) {
+void serial_break_clear(serial_t *obj)
+{
uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/spi_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/spi_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of SPI bus clock frequencies */
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -53,12 +54,13 @@
}
}
-void spi_free(spi_t *obj) {
+void spi_free(spi_t *obj)
+{
DSPI_Deinit(spi_address[obj->instance]);
}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@@ -84,18 +86,21 @@
}
}
-void spi_frequency(spi_t *obj, int hz) {
+void spi_frequency(spi_t *obj, int hz)
+{
uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
//Half clock period delay after SPI transfer
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
-static inline int spi_readable(spi_t * obj) {
+static inline int spi_readable(spi_t * obj)
+{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}
-int spi_master_write(spi_t *obj, int value) {
+int spi_master_write(spi_t *obj, int value)
+{
dspi_command_data_config_t command;
uint32_t rx_data;
DSPI_GetDefaultDataCommandConfig(&command);
@@ -112,11 +117,13 @@
return rx_data & 0xffff;
}
-int spi_slave_receive(spi_t *obj) {
+int spi_slave_receive(spi_t *obj)
+{
return spi_readable(obj);
}
-int spi_slave_read(spi_t *obj) {
+int spi_slave_read(spi_t *obj)
+{
uint32_t rx_data;
while (!spi_readable(obj));
@@ -125,7 +132,8 @@
return rx_data & 0xffff;
}
-void spi_slave_write(spi_t *obj, int value) {
+void spi_slave_write(spi_t *obj, int value)
+{
DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/storage_driver.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/storage_driver.c Thu Dec 15 11:48:27 2016 +0000
@@ -902,7 +902,8 @@
return ARM_DRIVER_OK;
}
-static int32_t blockIsProgrammable(const ARM_STORAGE_BLOCK *blockP) {
+static int32_t blockIsProgrammable(const ARM_STORAGE_BLOCK *blockP)
+{
if (!blockP->attributes.programmable) {
return ARM_STORAGE_ERROR_NOT_PROGRAMMABLE;
}
@@ -910,7 +911,8 @@
return ARM_DRIVER_OK;
}
-static int32_t blockIsErasable(const ARM_STORAGE_BLOCK *blockP) {
+static int32_t blockIsErasable(const ARM_STORAGE_BLOCK *blockP)
+{
if (!blockP->attributes.erasable) {
return ARM_STORAGE_ERROR_NOT_ERASABLE;
}
@@ -964,7 +966,8 @@
return 1; /* synchronous completion. */
}
-static int32_t uninitialize(void) {
+static int32_t uninitialize(void)
+{
tr_debug("called uninitialize");
struct mtd_k64f_data *context = &mtd_k64f_data;
@@ -1170,7 +1173,8 @@
return ARM_DRIVER_OK;
}
-static uint32_t resolveAddress(uint64_t addr) {
+static uint32_t resolveAddress(uint64_t addr)
+{
return (uint32_t)addr;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/us_ticker.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
static int us_ticker_inited = 0;
-void us_ticker_init(void) {
+void us_ticker_init(void)
+{
if (us_ticker_inited) {
return;
}
@@ -51,7 +52,8 @@
}
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read()
+{
if (!us_ticker_inited) {
us_ticker_init();
}
@@ -59,15 +61,18 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void)
+{
PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void)
+{
PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
}
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
int delta = (int)(timestamp - us_ticker_read());
if (delta <= 0) {
// This event was in the past.
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogin_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogin_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -29,7 +29,8 @@
#define MAX_FADC 6000000
-void analogin_init(analogin_t *obj, PinName pin) {
+void analogin_init(analogin_t *obj, PinName pin)
+{
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
@@ -57,7 +58,8 @@
pinmap_pinout(pin, PinMap_ADC);
}
-uint16_t analogin_read_u16(analogin_t *obj) {
+uint16_t analogin_read_u16(analogin_t *obj)
+{
uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
adc16_channel_config_t adc16_channel_config;
@@ -83,7 +85,8 @@
return ADC16_GetChannelConversionValue(adc_addrs[instance], 0);
}
-float analogin_read(analogin_t *obj) {
+float analogin_read(analogin_t *obj)
+{
uint16_t value = analogin_read_u16(obj);
return (float)value * (1.0f / (float)0xFFFF);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogout_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/analogout_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -28,7 +28,8 @@
#define RANGE_12BIT 0xFFF
-void analogout_init(dac_t *obj, PinName pin) {
+void analogout_init(dac_t *obj, PinName pin)
+{
dac_config_t dac_config;
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
if (obj->dac == (DACName)NC) {
@@ -41,17 +42,22 @@
DAC_SetBufferValue(dac_bases[obj->dac], 0, 0);
}
-void analogout_free(dac_t *obj) {}
+void analogout_free(dac_t *obj)
+{
+}
-static inline void dac_write(dac_t *obj, int value) {
+static inline void dac_write(dac_t *obj, int value)
+{
DAC_SetBufferValue(dac_bases[obj->dac], 0, (uint16_t)value);
}
-static inline int dac_read(dac_t *obj) {
+static inline int dac_read(dac_t *obj)
+{
return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL);
}
-void analogout_write(dac_t *obj, float value) {
+void analogout_write(dac_t *obj, float value)
+{
if (value < 0.0f) {
dac_write(obj, 0);
} else if (value > 1.0f) {
@@ -61,16 +67,19 @@
}
}
-void analogout_write_u16(dac_t *obj, uint16_t value) {
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
dac_write(obj, value >> 4); // 12-bit
}
-float analogout_read(dac_t *obj) {
+float analogout_read(dac_t *obj)
+{
uint32_t value = dac_read(obj);
return (float)value * (1.0f / (float)RANGE_12BIT);
}
-uint16_t analogout_read_u16(dac_t *obj) {
+uint16_t analogout_read_u16(dac_t *obj)
+{
uint32_t value = dac_read(obj); // 12-bit
return (value << 4) | ((value >> 8) & 0x003F);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
static GPIO_Type * const gpio_addrs[] = GPIO_BASE_PTRS;
-uint32_t gpio_set(PinName pin) {
+uint32_t gpio_set(PinName pin)
+{
MBED_ASSERT(pin != (PinName)NC);
uint32_t pin_num = pin & 0xFF;
@@ -29,7 +30,8 @@
return 1 << pin_num;
}
-void gpio_init(gpio_t *obj, PinName pin) {
+void gpio_init(gpio_t *obj, PinName pin)
+{
obj->pin = pin;
if (pin == (PinName)NC)
return;
@@ -37,11 +39,13 @@
pin_function(pin, (int)kPORT_MuxAsGpio);
}
-void gpio_mode(gpio_t *obj, PinMode mode) {
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
pin_mode(obj->pin, mode);
}
-void gpio_dir(gpio_t *obj, PinDirection direction) {
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
MBED_ASSERT(obj->pin != (PinName)NC);
uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
uint32_t pin_num = obj->pin & 0xFF;
@@ -57,7 +61,8 @@
}
}
-void gpio_write(gpio_t *obj, int value) {
+void gpio_write(gpio_t *obj, int value)
+{
MBED_ASSERT(obj->pin != (PinName)NC);
uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
uint32_t pin = obj->pin & 0xFF;
@@ -65,7 +70,8 @@
GPIO_WritePinOutput(gpio_addrs[port], pin, value);
}
-int gpio_read(gpio_t *obj) {
+int gpio_read(gpio_t *obj)
+{
MBED_ASSERT(obj->pin != (PinName)NC);
uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
uint32_t pin = obj->pin & 0xFF;
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_irq_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_irq_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -40,7 +40,8 @@
#define IRQ_FALLING_EDGE (10)
#define IRQ_EITHER_EDGE (11)
-static void handle_interrupt_in(PortName port, int ch_base) {
+static void handle_interrupt_in(PortName port, int ch_base)
+{
uint32_t i;
uint32_t interrupt_flags;
PORT_Type *port_base = port_addrs[port];
@@ -79,13 +80,33 @@
PORT_ClearPinsInterruptFlags(port_base, interrupt_flags);
}
-void gpio_irqA(void) {handle_interrupt_in(PortA, 0);}
-void gpio_irqB(void) {handle_interrupt_in(PortB, 32);}
-void gpio_irqC(void) {handle_interrupt_in(PortC, 64);}
-void gpio_irqD(void) {handle_interrupt_in(PortD, 96);}
-void gpio_irqE(void) {handle_interrupt_in(PortE, 128);}
+void gpio_irqA(void)
+{
+ handle_interrupt_in(PortA, 0);
+}
+
+void gpio_irqB(void)
+{
+ handle_interrupt_in(PortB, 32);
+}
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+void gpio_irqC(void)
+{
+ handle_interrupt_in(PortC, 64);
+}
+
+void gpio_irqD(void)
+{
+ handle_interrupt_in(PortD, 96);
+}
+
+void gpio_irqE(void)
+{
+ handle_interrupt_in(PortE, 128);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
if (pin == NC) {
return -1;
}
@@ -131,11 +152,13 @@
return 0;
}
-void gpio_irq_free(gpio_irq_t *obj) {
+void gpio_irq_free(gpio_irq_t *obj)
+{
channel_ids[obj->ch] = 0;
}
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
PORT_Type *base = port_addrs[obj->port];
port_interrupt_t irq_settings = kPORT_InterruptOrDMADisabled;
@@ -176,11 +199,13 @@
base->PCR[obj->pin] |= PORT_PCR_ISF_MASK;
}
-void gpio_irq_enable(gpio_irq_t *obj) {
+void gpio_irq_enable(gpio_irq_t *obj)
+{
NVIC_EnableIRQ(port_irqs[obj->port]);
}
-void gpio_irq_disable(gpio_irq_t *obj) {
+void gpio_irq_disable(gpio_irq_t *obj)
+{
NVIC_DisableIRQ(port_irqs[obj->port]);
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_object.h Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/gpio_object.h Thu Dec 15 11:48:27 2016 +0000
@@ -24,7 +24,8 @@
PinName pin;
} gpio_t;
-static inline int gpio_is_connected(const gpio_t *obj) {
+static inline int gpio_is_connected(const gpio_t *obj)
+{
return obj->pin != (PinName)NC;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/i2c_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/i2c_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -32,7 +32,8 @@
/* Array of I2C bus clock frequencies */
static clock_name_t const i2c_clocks[] = I2C_CLOCK_FREQS;
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->instance = pinmap_merge(i2c_sda, i2c_scl);
@@ -57,7 +58,8 @@
#endif
}
-int i2c_start(i2c_t *obj) {
+int i2c_start(i2c_t *obj)
+{
I2C_Type *base = i2c_addrs[obj->instance];
uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
@@ -77,7 +79,8 @@
return 0;
}
-int i2c_stop(i2c_t *obj) {
+int i2c_stop(i2c_t *obj)
+{
if (I2C_MasterStop(i2c_addrs[obj->instance]) != kStatus_Success) {
obj->next_repeated_start = 0;
return 1;
@@ -86,14 +89,16 @@
return 0;
}
-void i2c_frequency(i2c_t *obj, int hz) {
+void i2c_frequency(i2c_t *obj, int hz)
+{
uint32_t busClock;
busClock = CLOCK_GetFreq(i2c_clocks[obj->instance]);
I2C_MasterSetBaudRate(i2c_addrs[obj->instance], hz, busClock);
}
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
I2C_Type *base = i2c_addrs[obj->instance];
i2c_master_transfer_t master_xfer;
@@ -121,7 +126,8 @@
return length;
}
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
I2C_Type *base = i2c_addrs[obj->instance];
i2c_master_transfer_t master_xfer;
@@ -145,11 +151,13 @@
return length;
}
-void i2c_reset(i2c_t *obj) {
+void i2c_reset(i2c_t *obj)
+{
i2c_stop(obj);
}
-int i2c_byte_read(i2c_t *obj, int last) {
+int i2c_byte_read(i2c_t *obj, int last)
+{
uint8_t data;
I2C_Type *base = i2c_addrs[obj->instance];
i2c_master_transfer_t master_xfer;
@@ -169,7 +177,8 @@
return data;
}
-int i2c_byte_write(i2c_t *obj, int data) {
+int i2c_byte_write(i2c_t *obj, int data)
+{
#if FSL_I2C_DRIVER_VERSION > MAKE_VERSION(2, 0, 1)
if (I2C_MasterWriteBlocking(i2c_addrs[obj->instance], (uint8_t *)(&data), 1, kI2C_TransferNoStopFlag) == kStatus_Success) {
return 1;
@@ -184,7 +193,8 @@
#if DEVICE_I2CSLAVE
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
i2c_slave_config_t slave_config;
I2C_SlaveGetDefaultConfig(&slave_config);
slave_config.slaveAddress = 0;
@@ -196,7 +206,8 @@
#endif
}
-int i2c_slave_receive(i2c_t *obj) {
+int i2c_slave_receive(i2c_t *obj)
+{
uint32_t status_flags = I2C_SlaveGetStatusFlags(i2c_addrs[obj->instance]);
if (status_flags & kI2C_AddressMatchFlag) {
@@ -213,7 +224,8 @@
}
}
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
I2C_Type *base = i2c_addrs[obj->instance];
if (base->S & kI2C_AddressMatchFlag) {
@@ -228,7 +240,8 @@
return length;
}
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
I2C_Type *base = i2c_addrs[obj->instance];
I2C_SlaveWriteBlocking(base, (uint8_t *)data, length);
@@ -241,7 +254,8 @@
return length;
}
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
i2c_addrs[obj->instance]->A1 = address & 0xfe;
}
#endif
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pinmap.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/pinmap.c Thu Dec 15 11:48:27 2016 +0000
@@ -21,7 +21,8 @@
/* Array of PORT peripheral base address. */
static PORT_Type *const port_addrs[] = PORT_BASE_PTRS;
-void pin_function(PinName pin, int function) {
+void pin_function(PinName pin, int function)
+{
MBED_ASSERT(pin != (PinName)NC);
clock_ip_name_t port_clocks[] = PORT_CLOCKS;
@@ -30,7 +31,8 @@
PORT_SetPinMux(port_addrs[pin >> GPIO_PORT_SHIFT], pin & 0xFF, (port_mux_t)function);
}
-void pin_mode(PinName pin, PinMode mode) {
+void pin_mode(PinName pin, PinMode mode)
+{
MBED_ASSERT(pin != (PinName)NC);
uint32_t instance = pin >> GPIO_PORT_SHIFT;
uint32_t pinName = pin & 0xFF;
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/port_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/port_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -23,11 +23,13 @@
/* Array of GPIO peripheral base address. */
static GPIO_Type *const port_addrs[] = GPIO_BASE_PTRS;
-PinName port_pin(PortName port, int pin_n) {
+PinName port_pin(PortName port, int pin_n)
+{
return (PinName)((port << GPIO_PORT_SHIFT) | pin_n);
}
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
obj->port = port;
obj->mask = mask;
@@ -41,8 +43,8 @@
port_dir(obj, dir);
}
-void port_mode(port_t *obj, PinMode mode) {
-
+void port_mode(port_t *obj, PinMode mode)
+{
// The mode is set per pin: reuse pinmap logic
for (uint32_t i = 0; i < 32; i++) {
if (obj->mask & (1 << i)) {
@@ -51,7 +53,8 @@
}
}
-void port_dir(port_t *obj, PinDirection dir) {
+void port_dir(port_t *obj, PinDirection dir)
+{
GPIO_Type *base = port_addrs[obj->port];
uint32_t direction = base->PDDR;
@@ -66,14 +69,16 @@
base->PDDR = direction;
}
-void port_write(port_t *obj, int value) {
+void port_write(port_t *obj, int value)
+{
GPIO_Type *base = port_addrs[obj->port];
uint32_t input = base->PDIR & ~obj->mask;
base->PDOR = (input | (uint32_t)(value & obj->mask));
}
-int port_read(port_t *obj) {
+int port_read(port_t *obj)
+{
GPIO_Type *base = port_addrs[obj->port];
return (int)(base->PDIR & obj->mask);
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/rtc_api.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/rtc_api.c Thu Dec 15 11:48:27 2016 +0000
@@ -23,7 +23,8 @@
extern void rtc_setup_oscillator(RTC_Type *base);
-void rtc_init(void) {
+void rtc_init(void)
+{
rtc_config_t rtcConfig;
RTC_GetDefaultConfig(&rtcConfig);
@@ -34,7 +35,8 @@
RTC_StartTimer(RTC);
}
-void rtc_free(void) {
+void rtc_free(void)
+{
RTC_Deinit(RTC);
}
@@ -42,16 +44,19 @@
* Little check routine to see if the RTC has been enabled
* 0 = Disabled, 1 = Enabled
*/
-int rtc_isenabled(void) {
+int rtc_isenabled(void)
+{
CLOCK_EnableClock(kCLOCK_Rtc0);
return (int)((RTC->SR & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT);
}
-time_t rtc_read(void) {
+time_t rtc_read(void)
+{
return (time_t)RTC->TSR;
}
-void rtc_write(time_t t) {
+void rtc_write(time_t t)
+{
if (t == 0) {
t = 1;
}
--- a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/sleep.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/api/sleep.c Thu Dec 15 11:48:27 2016 +0000
@@ -18,13 +18,15 @@
#include "fsl_smc.h"
#include "fsl_clock_config.h"
-void sleep(void) {
+void sleep(void)
+{
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeWait(SMC);
}
-void deepsleep(void) {
+void deepsleep(void)
+{
#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT)
mcg_mode_t mode = CLOCK_GetMode();
#endif
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_IAR/TARGET_MAX32625MBED/MAX32625.icf Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_IAR/TARGET_MAX32625MBED/MAX32625.icf Thu Dec 15 11:48:27 2016 +0000
@@ -1,29 +1,29 @@
-/* [ROM] */
-define symbol __intvec_start__ = 0x00000000;
-define symbol __region_ROM_start__ = 0x00000000;
-define symbol __region_ROM_end__ = 0x0007FFFF;
-
-/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */
-define symbol __NVIC_start__ = 0x00000000;
-define symbol __NVIC_end__ = 0x00000110; /* to be aligned on 8 bytes */
-define symbol __region_RAM_start__ = 0x20000000;
-define symbol __region_RAM_end__ = 0x20027FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x5000;
-define symbol __size_heap__ = 0xA000;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
+/* [ROM] */
+define symbol __intvec_start__ = 0x00000000;
+define symbol __region_ROM_start__ = 0x00000000;
+define symbol __region_ROM_end__ = 0x0007FFFF;
+
+/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */
+define symbol __NVIC_start__ = 0x00000000;
+define symbol __NVIC_end__ = 0x00000110; /* to be aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000000;
+define symbol __region_RAM_end__ = 0x20027FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x5000;
+define symbol __size_heap__ = 0xA000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
--- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_IAR/TARGET_MAX32625NEXPAQ/MAX32625.icf Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_IAR/TARGET_MAX32625NEXPAQ/MAX32625.icf Thu Dec 15 11:48:27 2016 +0000
@@ -1,29 +1,29 @@
-/* [ROM] */
-define symbol __intvec_start__ = 0x00010000;
-define symbol __region_ROM_start__ = 0x00010000;
-define symbol __region_ROM_end__ = 0x0007FFFF;
-
-/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */
-define symbol __NVIC_start__ = 0x00010000;
-define symbol __NVIC_end__ = 0x00010110; /* to be aligned on 8 bytes */
-define symbol __region_RAM_start__ = 0x20003100;
-define symbol __region_RAM_end__ = 0x20027FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x5000;
-define symbol __size_heap__ = 0xA000;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
+/* [ROM] */
+define symbol __intvec_start__ = 0x00010000;
+define symbol __region_ROM_start__ = 0x00010000;
+define symbol __region_ROM_end__ = 0x0007FFFF;
+
+/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */
+define symbol __NVIC_start__ = 0x00010000;
+define symbol __NVIC_end__ = 0x00010110; /* to be aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20003100;
+define symbol __region_RAM_end__ = 0x20027FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x5000;
+define symbol __size_heap__ = 0xA000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c Thu Dec 15 11:48:27 2016 +0000
@@ -136,6 +136,20 @@
{NC, NC, 0}
};
+const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},
+ {NC, NC, 0}
+};
+
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar has changed
Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a has changed
Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a has changed
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h Thu Dec 15 11:48:27 2016 +0000
@@ -49,6 +49,12 @@
const cb_char* filename,
cb_uint32 line);
+typedef struct
+{
+ cbWLAN_MACAddress mac; /**< MAC of WLAN interface, set to all zeros if hardware programmed address should be used. */
+ cbWM_TxPowerSettings txPowerSettings; /**< Transmission power settings. */
+} cbMAIN_WlanStartParams;
+
/*---------------------------------------------------------------------------
* Callback to indicate that initialization of BT stack is completed.
*-------------------------------------------------------------------------*/
@@ -89,7 +95,7 @@
* @param params Start parameters passed to WLAN driver instance.
* @return cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR.
*/
-extern cb_int32 cbMAIN_startWlan(cb_int32 targetId, cbWLAN_StartParameters *params);
+extern cb_int32 cbMAIN_startWlan(cb_int32 targetId, cbMAIN_WlanStartParams *params);
/**
* Register error handler function.
--- a/targets/targets.json Thu Nov 24 17:03:03 2016 +0000
+++ b/targets/targets.json Thu Dec 15 11:48:27 2016 +0000
@@ -1292,7 +1292,7 @@
"extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx"],
"macros": ["HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
"inherits": ["Target"],
- "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+ "device_has": ["ANALOGIN", "CAN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
"features": ["LWIP"],
"release_versions": ["5"],
"device_name": "STM32F439ZI"