Kim GiJeong / Mbed 2 deprecated try15_flash_write_register

flash

Dependencies:   mbed

stm32f4xx_flash.h@0:d885866e7cbf, 2019-08-12 (annotated)

Committer:
GiJeongKim
Date:
Mon Aug 12 09:16:40 2019 +0000
Revision:
0:d885866e7cbf
flash memory;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GiJeongKim 0:d885866e7cbf 1 /**
GiJeongKim 0:d885866e7cbf 2 ******************************************************************************
GiJeongKim 0:d885866e7cbf 3 * @file stm32f4xx_flash.h
GiJeongKim 0:d885866e7cbf 4 * @author MCD Application Team
GiJeongKim 0:d885866e7cbf 5 * @version V1.7.1
GiJeongKim 0:d885866e7cbf 6 * @date 20-May-2016
GiJeongKim 0:d885866e7cbf 7 * @brief This file contains all the functions prototypes for the FLASH
GiJeongKim 0:d885866e7cbf 8 * firmware library.
GiJeongKim 0:d885866e7cbf 9 ******************************************************************************
GiJeongKim 0:d885866e7cbf 10 * @attention
GiJeongKim 0:d885866e7cbf 11 *
GiJeongKim 0:d885866e7cbf 12 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
GiJeongKim 0:d885866e7cbf 13 *
GiJeongKim 0:d885866e7cbf 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
GiJeongKim 0:d885866e7cbf 15 * You may not use this file except in compliance with the License.
GiJeongKim 0:d885866e7cbf 16 * You may obtain a copy of the License at:
GiJeongKim 0:d885866e7cbf 17 *
GiJeongKim 0:d885866e7cbf 18 * http://www.st.com/software_license_agreement_liberty_v2
GiJeongKim 0:d885866e7cbf 19 *
GiJeongKim 0:d885866e7cbf 20 * Unless required by applicable law or agreed to in writing, software
GiJeongKim 0:d885866e7cbf 21 * distributed under the License is distributed on an "AS IS" BASIS,
GiJeongKim 0:d885866e7cbf 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
GiJeongKim 0:d885866e7cbf 23 * See the License for the specific language governing permissions and
GiJeongKim 0:d885866e7cbf 24 * limitations under the License.
GiJeongKim 0:d885866e7cbf 25 *
GiJeongKim 0:d885866e7cbf 26 ******************************************************************************
GiJeongKim 0:d885866e7cbf 27 */
GiJeongKim 0:d885866e7cbf 28
GiJeongKim 0:d885866e7cbf 29 /* Define to prevent recursive inclusion -------------------------------------*/
GiJeongKim 0:d885866e7cbf 30 #ifndef __STM32F4xx_FLASH_H
GiJeongKim 0:d885866e7cbf 31 #define __STM32F4xx_FLASH_H
GiJeongKim 0:d885866e7cbf 32
GiJeongKim 0:d885866e7cbf 33 #ifdef __cplusplus
GiJeongKim 0:d885866e7cbf 34 extern "C" {
GiJeongKim 0:d885866e7cbf 35 #endif
GiJeongKim 0:d885866e7cbf 36
GiJeongKim 0:d885866e7cbf 37 /* Includes ------------------------------------------------------------------*/
GiJeongKim 0:d885866e7cbf 38 #include "stm32f4xx.h"
GiJeongKim 0:d885866e7cbf 39
GiJeongKim 0:d885866e7cbf 40 /** @addtogroup STM32F4xx_StdPeriph_Driver
GiJeongKim 0:d885866e7cbf 41 * @{
GiJeongKim 0:d885866e7cbf 42 */
GiJeongKim 0:d885866e7cbf 43
GiJeongKim 0:d885866e7cbf 44 /** @addtogroup FLASH
GiJeongKim 0:d885866e7cbf 45 * @{
GiJeongKim 0:d885866e7cbf 46 */
GiJeongKim 0:d885866e7cbf 47
GiJeongKim 0:d885866e7cbf 48 /* Exported types ------------------------------------------------------------*/
GiJeongKim 0:d885866e7cbf 49 /**
GiJeongKim 0:d885866e7cbf 50 * @brief FLASH Status
GiJeongKim 0:d885866e7cbf 51 */
GiJeongKim 0:d885866e7cbf 52 typedef enum
GiJeongKim 0:d885866e7cbf 53 {
GiJeongKim 0:d885866e7cbf 54 FLASH_BUSY2 = 1,
GiJeongKim 0:d885866e7cbf 55 FLASH_ERROR_RD2,
GiJeongKim 0:d885866e7cbf 56 FLASH_ERROR_PGS2,
GiJeongKim 0:d885866e7cbf 57 FLASH_ERROR_PGP2,
GiJeongKim 0:d885866e7cbf 58 FLASH_ERROR_PGA2,
GiJeongKim 0:d885866e7cbf 59 FLASH_ERROR_WRP2,
GiJeongKim 0:d885866e7cbf 60 FLASH_ERROR_PROGRAM2,
GiJeongKim 0:d885866e7cbf 61 FLASH_ERROR_OPERATION2,
GiJeongKim 0:d885866e7cbf 62 FLASH_COMPLETE2
GiJeongKim 0:d885866e7cbf 63 }FLASH_Status;
GiJeongKim 0:d885866e7cbf 64
GiJeongKim 0:d885866e7cbf 65 /* Exported constants --------------------------------------------------------*/
GiJeongKim 0:d885866e7cbf 66
GiJeongKim 0:d885866e7cbf 67 /** @defgroup FLASH_Exported_Constants
GiJeongKim 0:d885866e7cbf 68 * @{
GiJeongKim 0:d885866e7cbf 69 */
GiJeongKim 0:d885866e7cbf 70
GiJeongKim 0:d885866e7cbf 71 /** @defgroup Flash_Latency
GiJeongKim 0:d885866e7cbf 72 * @{
GiJeongKim 0:d885866e7cbf 73 */
GiJeongKim 0:d885866e7cbf 74 #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
GiJeongKim 0:d885866e7cbf 75 #define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
GiJeongKim 0:d885866e7cbf 76 #define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
GiJeongKim 0:d885866e7cbf 77 #define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
GiJeongKim 0:d885866e7cbf 78 #define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
GiJeongKim 0:d885866e7cbf 79 #define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
GiJeongKim 0:d885866e7cbf 80 #define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
GiJeongKim 0:d885866e7cbf 81 #define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
GiJeongKim 0:d885866e7cbf 82 #define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */
GiJeongKim 0:d885866e7cbf 83 #define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */
GiJeongKim 0:d885866e7cbf 84 #define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */
GiJeongKim 0:d885866e7cbf 85 #define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */
GiJeongKim 0:d885866e7cbf 86 #define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */
GiJeongKim 0:d885866e7cbf 87 #define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */
GiJeongKim 0:d885866e7cbf 88 #define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */
GiJeongKim 0:d885866e7cbf 89 #define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */
GiJeongKim 0:d885866e7cbf 90
GiJeongKim 0:d885866e7cbf 91 /**
GiJeongKim 0:d885866e7cbf 92 * @}
GiJeongKim 0:d885866e7cbf 93 */
GiJeongKim 0:d885866e7cbf 94
GiJeongKim 0:d885866e7cbf 95 /** @defgroup FLASH_Voltage_Range
GiJeongKim 0:d885866e7cbf 96 * @{
GiJeongKim 0:d885866e7cbf 97 */
GiJeongKim 0:d885866e7cbf 98 #define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
GiJeongKim 0:d885866e7cbf 99 #define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */
GiJeongKim 0:d885866e7cbf 100 #define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */
GiJeongKim 0:d885866e7cbf 101 #define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */
GiJeongKim 0:d885866e7cbf 102
GiJeongKim 0:d885866e7cbf 103 /*
GiJeongKim 0:d885866e7cbf 104 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
GiJeongKim 0:d885866e7cbf 105 ((RANGE) == VoltageRange_2) || \
GiJeongKim 0:d885866e7cbf 106 ((RANGE) == VoltageRange_3) || \
GiJeongKim 0:d885866e7cbf 107 ((RANGE) == VoltageRange_4))
GiJeongKim 0:d885866e7cbf 108 */
GiJeongKim 0:d885866e7cbf 109
GiJeongKim 0:d885866e7cbf 110 /**
GiJeongKim 0:d885866e7cbf 111 * @}
GiJeongKim 0:d885866e7cbf 112 */
GiJeongKim 0:d885866e7cbf 113
GiJeongKim 0:d885866e7cbf 114 /** @defgroup FLASH_Sectors
GiJeongKim 0:d885866e7cbf 115 * @{
GiJeongKim 0:d885866e7cbf 116 */
GiJeongKim 0:d885866e7cbf 117 #define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
GiJeongKim 0:d885866e7cbf 118 #define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
GiJeongKim 0:d885866e7cbf 119 #define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
GiJeongKim 0:d885866e7cbf 120 #define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
GiJeongKim 0:d885866e7cbf 121 #define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
GiJeongKim 0:d885866e7cbf 122 #define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
GiJeongKim 0:d885866e7cbf 123 #define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
GiJeongKim 0:d885866e7cbf 124 #define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
GiJeongKim 0:d885866e7cbf 125 #define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
GiJeongKim 0:d885866e7cbf 126 #define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
GiJeongKim 0:d885866e7cbf 127 #define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
GiJeongKim 0:d885866e7cbf 128 #define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
GiJeongKim 0:d885866e7cbf 129 #define FLASH_Sector_12 ((uint16_t)0x0080) /*!< Sector Number 12 */
GiJeongKim 0:d885866e7cbf 130 #define FLASH_Sector_13 ((uint16_t)0x0088) /*!< Sector Number 13 */
GiJeongKim 0:d885866e7cbf 131 #define FLASH_Sector_14 ((uint16_t)0x0090) /*!< Sector Number 14 */
GiJeongKim 0:d885866e7cbf 132 #define FLASH_Sector_15 ((uint16_t)0x0098) /*!< Sector Number 15 */
GiJeongKim 0:d885866e7cbf 133 #define FLASH_Sector_16 ((uint16_t)0x00A0) /*!< Sector Number 16 */
GiJeongKim 0:d885866e7cbf 134 #define FLASH_Sector_17 ((uint16_t)0x00A8) /*!< Sector Number 17 */
GiJeongKim 0:d885866e7cbf 135 #define FLASH_Sector_18 ((uint16_t)0x00B0) /*!< Sector Number 18 */
GiJeongKim 0:d885866e7cbf 136 #define FLASH_Sector_19 ((uint16_t)0x00B8) /*!< Sector Number 19 */
GiJeongKim 0:d885866e7cbf 137 #define FLASH_Sector_20 ((uint16_t)0x00C0) /*!< Sector Number 20 */
GiJeongKim 0:d885866e7cbf 138 #define FLASH_Sector_21 ((uint16_t)0x00C8) /*!< Sector Number 21 */
GiJeongKim 0:d885866e7cbf 139 #define FLASH_Sector_22 ((uint16_t)0x00D0) /*!< Sector Number 22 */
GiJeongKim 0:d885866e7cbf 140 #define FLASH_Sector_23 ((uint16_t)0x00D8) /*!< Sector Number 23 */
GiJeongKim 0:d885866e7cbf 141
GiJeongKim 0:d885866e7cbf 142 #if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F469_479xx)
GiJeongKim 0:d885866e7cbf 143 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
GiJeongKim 0:d885866e7cbf 144 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
GiJeongKim 0:d885866e7cbf 145 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
GiJeongKim 0:d885866e7cbf 146
GiJeongKim 0:d885866e7cbf 147 #if defined (STM32F40_41xxx) || defined(STM32F412xG)
GiJeongKim 0:d885866e7cbf 148 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
GiJeongKim 0:d885866e7cbf 149 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
GiJeongKim 0:d885866e7cbf 150 #endif /* STM32F40_41xxx || STM32F412xG */
GiJeongKim 0:d885866e7cbf 151
GiJeongKim 0:d885866e7cbf 152 #if defined (STM32F401xx)
GiJeongKim 0:d885866e7cbf 153 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
GiJeongKim 0:d885866e7cbf 154 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
GiJeongKim 0:d885866e7cbf 155 #endif /* STM32F401xx */
GiJeongKim 0:d885866e7cbf 156
GiJeongKim 0:d885866e7cbf 157 #if defined (STM32F411xE) || defined (STM32F446xx)
GiJeongKim 0:d885866e7cbf 158 //#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
GiJeongKim 0:d885866e7cbf 159 // (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
GiJeongKim 0:d885866e7cbf 160 #endif /* STM32F411xE || STM32F446xx */
GiJeongKim 0:d885866e7cbf 161
GiJeongKim 0:d885866e7cbf 162 #if defined (STM32F410xx)
GiJeongKim 0:d885866e7cbf 163 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) ||\
GiJeongKim 0:d885866e7cbf 164 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
GiJeongKim 0:d885866e7cbf 165 #endif /* STM32F410xx */
GiJeongKim 0:d885866e7cbf 166
GiJeongKim 0:d885866e7cbf 167 /**
GiJeongKim 0:d885866e7cbf 168 * @}
GiJeongKim 0:d885866e7cbf 169 */
GiJeongKim 0:d885866e7cbf 170
GiJeongKim 0:d885866e7cbf 171 /** @defgroup Option_Bytes_Write_Protection
GiJeongKim 0:d885866e7cbf 172 * @{
GiJeongKim 0:d885866e7cbf 173 */
GiJeongKim 0:d885866e7cbf 174 #define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
GiJeongKim 0:d885866e7cbf 175 #define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
GiJeongKim 0:d885866e7cbf 176 #define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
GiJeongKim 0:d885866e7cbf 177 #define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
GiJeongKim 0:d885866e7cbf 178 #define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
GiJeongKim 0:d885866e7cbf 179 #define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
GiJeongKim 0:d885866e7cbf 180 #define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
GiJeongKim 0:d885866e7cbf 181 #define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
GiJeongKim 0:d885866e7cbf 182 #define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
GiJeongKim 0:d885866e7cbf 183 #define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
GiJeongKim 0:d885866e7cbf 184 #define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
GiJeongKim 0:d885866e7cbf 185 #define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
GiJeongKim 0:d885866e7cbf 186 #define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */
GiJeongKim 0:d885866e7cbf 187 #define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */
GiJeongKim 0:d885866e7cbf 188 #define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */
GiJeongKim 0:d885866e7cbf 189 #define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */
GiJeongKim 0:d885866e7cbf 190 #define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */
GiJeongKim 0:d885866e7cbf 191 #define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */
GiJeongKim 0:d885866e7cbf 192 #define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */
GiJeongKim 0:d885866e7cbf 193 #define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */
GiJeongKim 0:d885866e7cbf 194 #define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */
GiJeongKim 0:d885866e7cbf 195 #define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */
GiJeongKim 0:d885866e7cbf 196 #define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */
GiJeongKim 0:d885866e7cbf 197 #define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */
GiJeongKim 0:d885866e7cbf 198 #define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
GiJeongKim 0:d885866e7cbf 199
GiJeongKim 0:d885866e7cbf 200 #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
GiJeongKim 0:d885866e7cbf 201 /**
GiJeongKim 0:d885866e7cbf 202 * @}
GiJeongKim 0:d885866e7cbf 203 */
GiJeongKim 0:d885866e7cbf 204
GiJeongKim 0:d885866e7cbf 205 /** @defgroup Selection_Protection_Mode
GiJeongKim 0:d885866e7cbf 206 * @{
GiJeongKim 0:d885866e7cbf 207 */
GiJeongKim 0:d885866e7cbf 208 #define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
GiJeongKim 0:d885866e7cbf 209 #define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
GiJeongKim 0:d885866e7cbf 210
GiJeongKim 0:d885866e7cbf 211 /**
GiJeongKim 0:d885866e7cbf 212 * @}
GiJeongKim 0:d885866e7cbf 213 */
GiJeongKim 0:d885866e7cbf 214
GiJeongKim 0:d885866e7cbf 215 /** @defgroup Option_Bytes_PC_ReadWrite_Protection
GiJeongKim 0:d885866e7cbf 216 * @{
GiJeongKim 0:d885866e7cbf 217 */
GiJeongKim 0:d885866e7cbf 218 #define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
GiJeongKim 0:d885866e7cbf 219 #define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
GiJeongKim 0:d885866e7cbf 220 #define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
GiJeongKim 0:d885866e7cbf 221 #define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
GiJeongKim 0:d885866e7cbf 222 #define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
GiJeongKim 0:d885866e7cbf 223 #define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
GiJeongKim 0:d885866e7cbf 224 #define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
GiJeongKim 0:d885866e7cbf 225 #define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
GiJeongKim 0:d885866e7cbf 226 #define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
GiJeongKim 0:d885866e7cbf 227 #define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
GiJeongKim 0:d885866e7cbf 228 #define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
GiJeongKim 0:d885866e7cbf 229 #define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
GiJeongKim 0:d885866e7cbf 230 #define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
GiJeongKim 0:d885866e7cbf 231 #define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
GiJeongKim 0:d885866e7cbf 232 #define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
GiJeongKim 0:d885866e7cbf 233 #define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
GiJeongKim 0:d885866e7cbf 234 #define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
GiJeongKim 0:d885866e7cbf 235 #define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
GiJeongKim 0:d885866e7cbf 236 #define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
GiJeongKim 0:d885866e7cbf 237 #define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
GiJeongKim 0:d885866e7cbf 238 #define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
GiJeongKim 0:d885866e7cbf 239 #define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
GiJeongKim 0:d885866e7cbf 240 #define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
GiJeongKim 0:d885866e7cbf 241 #define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
GiJeongKim 0:d885866e7cbf 242 #define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
GiJeongKim 0:d885866e7cbf 243
GiJeongKim 0:d885866e7cbf 244 /**
GiJeongKim 0:d885866e7cbf 245 * @}
GiJeongKim 0:d885866e7cbf 246 */
GiJeongKim 0:d885866e7cbf 247
GiJeongKim 0:d885866e7cbf 248 /** @defgroup FLASH_Option_Bytes_Read_Protection
GiJeongKim 0:d885866e7cbf 249 * @{
GiJeongKim 0:d885866e7cbf 250 */
GiJeongKim 0:d885866e7cbf 251 #define OB_RDP_Level_0 ((uint8_t)0xAA)
GiJeongKim 0:d885866e7cbf 252 #define OB_RDP_Level_1 ((uint8_t)0x55)
GiJeongKim 0:d885866e7cbf 253 /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
GiJeongKim 0:d885866e7cbf 254 it's no more possible to go back to level 1 or 0 */
GiJeongKim 0:d885866e7cbf 255 #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
GiJeongKim 0:d885866e7cbf 256 ((LEVEL) == OB_RDP_Level_1))/*||\
GiJeongKim 0:d885866e7cbf 257 ((LEVEL) == OB_RDP_Level_2))*/
GiJeongKim 0:d885866e7cbf 258 /**
GiJeongKim 0:d885866e7cbf 259 * @}
GiJeongKim 0:d885866e7cbf 260 */
GiJeongKim 0:d885866e7cbf 261
GiJeongKim 0:d885866e7cbf 262 /** @defgroup FLASH_Option_Bytes_IWatchdog
GiJeongKim 0:d885866e7cbf 263 * @{
GiJeongKim 0:d885866e7cbf 264 */
GiJeongKim 0:d885866e7cbf 265
GiJeongKim 0:d885866e7cbf 266 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
GiJeongKim 0:d885866e7cbf 267 /**
GiJeongKim 0:d885866e7cbf 268 * @}
GiJeongKim 0:d885866e7cbf 269 */
GiJeongKim 0:d885866e7cbf 270
GiJeongKim 0:d885866e7cbf 271 /** @defgroup FLASH_Option_Bytes_nRST_STOP
GiJeongKim 0:d885866e7cbf 272 * @{
GiJeongKim 0:d885866e7cbf 273 */
GiJeongKim 0:d885866e7cbf 274 #define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
GiJeongKim 0:d885866e7cbf 275
GiJeongKim 0:d885866e7cbf 276 /**
GiJeongKim 0:d885866e7cbf 277 * @}
GiJeongKim 0:d885866e7cbf 278 */
GiJeongKim 0:d885866e7cbf 279
GiJeongKim 0:d885866e7cbf 280
GiJeongKim 0:d885866e7cbf 281 /** @defgroup FLASH_Option_Bytes_nRST_STDBY
GiJeongKim 0:d885866e7cbf 282 * @{
GiJeongKim 0:d885866e7cbf 283 */
GiJeongKim 0:d885866e7cbf 284 #define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
GiJeongKim 0:d885866e7cbf 285 //#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
GiJeongKim 0:d885866e7cbf 286 //#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
GiJeongKim 0:d885866e7cbf 287 /**
GiJeongKim 0:d885866e7cbf 288 * @}
GiJeongKim 0:d885866e7cbf 289 */
GiJeongKim 0:d885866e7cbf 290
GiJeongKim 0:d885866e7cbf 291 /** @defgroup FLASH_BOR_Reset_Level
GiJeongKim 0:d885866e7cbf 292 * @{
GiJeongKim 0:d885866e7cbf 293 */
GiJeongKim 0:d885866e7cbf 294
GiJeongKim 0:d885866e7cbf 295 #define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
GiJeongKim 0:d885866e7cbf 296 ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
GiJeongKim 0:d885866e7cbf 297 /**
GiJeongKim 0:d885866e7cbf 298 * @}
GiJeongKim 0:d885866e7cbf 299 */
GiJeongKim 0:d885866e7cbf 300
GiJeongKim 0:d885866e7cbf 301 /** @defgroup FLASH_Dual_Boot
GiJeongKim 0:d885866e7cbf 302 * @{
GiJeongKim 0:d885866e7cbf 303 */
GiJeongKim 0:d885866e7cbf 304 #define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
GiJeongKim 0:d885866e7cbf 305 #define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
GiJeongKim 0:d885866e7cbf 306 #define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
GiJeongKim 0:d885866e7cbf 307 /**
GiJeongKim 0:d885866e7cbf 308 * @}
GiJeongKim 0:d885866e7cbf 309 */
GiJeongKim 0:d885866e7cbf 310
GiJeongKim 0:d885866e7cbf 311 /** @defgroup FLASH_Interrupts
GiJeongKim 0:d885866e7cbf 312 * @{
GiJeongKim 0:d885866e7cbf 313 */
GiJeongKim 0:d885866e7cbf 314
GiJeongKim 0:d885866e7cbf 315 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
GiJeongKim 0:d885866e7cbf 316 /**
GiJeongKim 0:d885866e7cbf 317 * @}
GiJeongKim 0:d885866e7cbf 318 */
GiJeongKim 0:d885866e7cbf 319
GiJeongKim 0:d885866e7cbf 320 /** @defgroup FLASH_Flags
GiJeongKim 0:d885866e7cbf 321 * @{
GiJeongKim 0:d885866e7cbf 322 */
GiJeongKim 0:d885866e7cbf 323
GiJeongKim 0:d885866e7cbf 324 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
GiJeongKim 0:d885866e7cbf 325 #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
GiJeongKim 0:d885866e7cbf 326 ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
GiJeongKim 0:d885866e7cbf 327 ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
GiJeongKim 0:d885866e7cbf 328 ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR))
GiJeongKim 0:d885866e7cbf 329
GiJeongKim 0:d885866e7cbf 330 /**
GiJeongKim 0:d885866e7cbf 331 * @brief ACR register byte 0 (Bits[7:0]) base address
GiJeongKim 0:d885866e7cbf 332 */
GiJeongKim 0:d885866e7cbf 333 //#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
GiJeongKim 0:d885866e7cbf 334 /**
GiJeongKim 0:d885866e7cbf 335 * @brief OPTCR register byte 0 (Bits[7:0]) base address
GiJeongKim 0:d885866e7cbf 336 */
GiJeongKim 0:d885866e7cbf 337 //#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
GiJeongKim 0:d885866e7cbf 338 /**
GiJeongKim 0:d885866e7cbf 339 * @brief OPTCR register byte 1 (Bits[15:8]) base address
GiJeongKim 0:d885866e7cbf 340 */
GiJeongKim 0:d885866e7cbf 341 //#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
GiJeongKim 0:d885866e7cbf 342 /**
GiJeongKim 0:d885866e7cbf 343 * @brief OPTCR register byte 2 (Bits[23:16]) base address
GiJeongKim 0:d885866e7cbf 344 */
GiJeongKim 0:d885866e7cbf 345 //#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
GiJeongKim 0:d885866e7cbf 346 /**
GiJeongKim 0:d885866e7cbf 347 * @brief OPTCR register byte 3 (Bits[31:24]) base address
GiJeongKim 0:d885866e7cbf 348 */
GiJeongKim 0:d885866e7cbf 349 //#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
GiJeongKim 0:d885866e7cbf 350
GiJeongKim 0:d885866e7cbf 351 /**
GiJeongKim 0:d885866e7cbf 352 * @brief OPTCR1 register byte 0 (Bits[7:0]) base address
GiJeongKim 0:d885866e7cbf 353 */
GiJeongKim 0:d885866e7cbf 354 #define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
GiJeongKim 0:d885866e7cbf 355
GiJeongKim 0:d885866e7cbf 356 /**
GiJeongKim 0:d885866e7cbf 357 * @}
GiJeongKim 0:d885866e7cbf 358 */
GiJeongKim 0:d885866e7cbf 359
GiJeongKim 0:d885866e7cbf 360 /* Exported macro ------------------------------------------------------------*/
GiJeongKim 0:d885866e7cbf 361 /* Exported functions --------------------------------------------------------*/
GiJeongKim 0:d885866e7cbf 362
GiJeongKim 0:d885866e7cbf 363 /* FLASH Interface configuration functions ************************************/
GiJeongKim 0:d885866e7cbf 364 void FLASH_SetLatency(uint32_t FLASH_Latency);
GiJeongKim 0:d885866e7cbf 365 void FLASH_PrefetchBufferCmd(FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 366 void FLASH_InstructionCacheCmd(FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 367 void FLASH_DataCacheCmd(FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 368 void FLASH_InstructionCacheReset(void);
GiJeongKim 0:d885866e7cbf 369 void FLASH_DataCacheReset(void);
GiJeongKim 0:d885866e7cbf 370
GiJeongKim 0:d885866e7cbf 371 /* FLASH Memory Programming functions *****************************************/
GiJeongKim 0:d885866e7cbf 372 void FLASH_Unlock(void);
GiJeongKim 0:d885866e7cbf 373 void FLASH_Lock(void);
GiJeongKim 0:d885866e7cbf 374 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
GiJeongKim 0:d885866e7cbf 375 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
GiJeongKim 0:d885866e7cbf 376 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
GiJeongKim 0:d885866e7cbf 377 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
GiJeongKim 0:d885866e7cbf 378 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
GiJeongKim 0:d885866e7cbf 379 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
GiJeongKim 0:d885866e7cbf 380 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
GiJeongKim 0:d885866e7cbf 381 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
GiJeongKim 0:d885866e7cbf 382
GiJeongKim 0:d885866e7cbf 383 /* Option Bytes Programming functions *****************************************/
GiJeongKim 0:d885866e7cbf 384 void FLASH_OB_Unlock(void);
GiJeongKim 0:d885866e7cbf 385 void FLASH_OB_Lock(void);
GiJeongKim 0:d885866e7cbf 386 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 387 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 388 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
GiJeongKim 0:d885866e7cbf 389 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 390 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 391 void FLASH_OB_RDPConfig(uint8_t OB_RDP);
GiJeongKim 0:d885866e7cbf 392 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
GiJeongKim 0:d885866e7cbf 393 void FLASH_OB_BORConfig(uint8_t OB_BOR);
GiJeongKim 0:d885866e7cbf 394 void FLASH_OB_BootConfig(uint8_t OB_BOOT);
GiJeongKim 0:d885866e7cbf 395 FLASH_Status FLASH_OB_Launch(void);
GiJeongKim 0:d885866e7cbf 396 uint8_t FLASH_OB_GetUser(void);
GiJeongKim 0:d885866e7cbf 397 uint16_t FLASH_OB_GetWRP(void);
GiJeongKim 0:d885866e7cbf 398 uint16_t FLASH_OB_GetWRP1(void);
GiJeongKim 0:d885866e7cbf 399 uint16_t FLASH_OB_GetPCROP(void);
GiJeongKim 0:d885866e7cbf 400 uint16_t FLASH_OB_GetPCROP1(void);
GiJeongKim 0:d885866e7cbf 401 FlagStatus FLASH_OB_GetRDP(void);
GiJeongKim 0:d885866e7cbf 402 uint8_t FLASH_OB_GetBOR(void);
GiJeongKim 0:d885866e7cbf 403
GiJeongKim 0:d885866e7cbf 404 /* Interrupts and flags management functions **********************************/
GiJeongKim 0:d885866e7cbf 405 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
GiJeongKim 0:d885866e7cbf 406 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
GiJeongKim 0:d885866e7cbf 407 void FLASH_ClearFlag(uint32_t FLASH_FLAG);
GiJeongKim 0:d885866e7cbf 408 FLASH_Status FLASH_GetStatus(void);
GiJeongKim 0:d885866e7cbf 409 FLASH_Status FLASH_WaitForLastOperation2(void);
GiJeongKim 0:d885866e7cbf 410
GiJeongKim 0:d885866e7cbf 411 #ifdef __cplusplus
GiJeongKim 0:d885866e7cbf 412 }
GiJeongKim 0:d885866e7cbf 413 #endif
GiJeongKim 0:d885866e7cbf 414
GiJeongKim 0:d885866e7cbf 415 #endif /* __STM32F4xx_FLASH_H */
GiJeongKim 0:d885866e7cbf 416
GiJeongKim 0:d885866e7cbf 417 /**
GiJeongKim 0:d885866e7cbf 418 * @}
GiJeongKim 0:d885866e7cbf 419 */
GiJeongKim 0:d885866e7cbf 420
GiJeongKim 0:d885866e7cbf 421 /**
GiJeongKim 0:d885866e7cbf 422 * @}
GiJeongKim 0:d885866e7cbf 423 */
GiJeongKim 0:d885866e7cbf 424
GiJeongKim 0:d885866e7cbf 425 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/