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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/drivers/fsl_lpuart.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_lpuart.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 /*******************************************************************************
<> 154:37f96f9d4de2 34 * Definitions
<> 154:37f96f9d4de2 35 ******************************************************************************/
<> 154:37f96f9d4de2 36 /* LPUART transfer state. */
<> 154:37f96f9d4de2 37 enum _lpuart_transfer_states
<> 154:37f96f9d4de2 38 {
<> 154:37f96f9d4de2 39 kLPUART_TxIdle, /*!< TX idle. */
<> 154:37f96f9d4de2 40 kLPUART_TxBusy, /*!< TX busy. */
<> 154:37f96f9d4de2 41 kLPUART_RxIdle, /*!< RX idle. */
<> 154:37f96f9d4de2 42 kLPUART_RxBusy /*!< RX busy. */
<> 154:37f96f9d4de2 43 };
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /* Typedef for interrupt handler. */
<> 154:37f96f9d4de2 46 typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 /*******************************************************************************
<> 154:37f96f9d4de2 49 * Prototypes
<> 154:37f96f9d4de2 50 ******************************************************************************/
<> 154:37f96f9d4de2 51 /*!
<> 154:37f96f9d4de2 52 * @brief Get the LPUART instance from peripheral base address.
<> 154:37f96f9d4de2 53 *
<> 154:37f96f9d4de2 54 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 55 * @return LPUART instance.
<> 154:37f96f9d4de2 56 */
<> 154:37f96f9d4de2 57 uint32_t LPUART_GetInstance(LPUART_Type *base);
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /*!
<> 154:37f96f9d4de2 60 * @brief Get the length of received data in RX ring buffer.
<> 154:37f96f9d4de2 61 *
<> 154:37f96f9d4de2 62 * @userData handle LPUART handle pointer.
<> 154:37f96f9d4de2 63 * @return Length of received data in RX ring buffer.
<> 154:37f96f9d4de2 64 */
<> 154:37f96f9d4de2 65 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 /*!
<> 154:37f96f9d4de2 68 * @brief Check whether the RX ring buffer is full.
<> 154:37f96f9d4de2 69 *
<> 154:37f96f9d4de2 70 * @userData handle LPUART handle pointer.
<> 154:37f96f9d4de2 71 * @retval true RX ring buffer is full.
<> 154:37f96f9d4de2 72 * @retval false RX ring buffer is not full.
<> 154:37f96f9d4de2 73 */
<> 154:37f96f9d4de2 74 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 75
<> 154:37f96f9d4de2 76 /*!
<> 154:37f96f9d4de2 77 * @brief Write to TX register using non-blocking method.
<> 154:37f96f9d4de2 78 *
<> 154:37f96f9d4de2 79 * This function writes data to the TX register directly, upper layer must make
<> 154:37f96f9d4de2 80 * sure the TX register is empty or TX FIFO has empty room before calling this function.
<> 154:37f96f9d4de2 81 *
<> 154:37f96f9d4de2 82 * @note This function does not check whether all the data has been sent out to bus,
<> 154:37f96f9d4de2 83 * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
<> 154:37f96f9d4de2 84 * finished.
<> 154:37f96f9d4de2 85 *
<> 154:37f96f9d4de2 86 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 87 * @param data Start addresss of the data to write.
<> 154:37f96f9d4de2 88 * @param length Size of the buffer to be sent.
<> 154:37f96f9d4de2 89 */
<> 154:37f96f9d4de2 90 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
<> 154:37f96f9d4de2 91
<> 154:37f96f9d4de2 92 /*!
<> 154:37f96f9d4de2 93 * @brief Read RX register using non-blocking method.
<> 154:37f96f9d4de2 94 *
<> 154:37f96f9d4de2 95 * This function reads data from the TX register directly, upper layer must make
<> 154:37f96f9d4de2 96 * sure the RX register is full or TX FIFO has data before calling this function.
<> 154:37f96f9d4de2 97 *
<> 154:37f96f9d4de2 98 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 99 * @param data Start addresss of the buffer to store the received data.
<> 154:37f96f9d4de2 100 * @param length Size of the buffer.
<> 154:37f96f9d4de2 101 */
<> 154:37f96f9d4de2 102 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
<> 154:37f96f9d4de2 103
<> 154:37f96f9d4de2 104 /*******************************************************************************
<> 154:37f96f9d4de2 105 * Variables
<> 154:37f96f9d4de2 106 ******************************************************************************/
<> 154:37f96f9d4de2 107 /* Array of LPUART handle. */
<> 154:37f96f9d4de2 108 static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT];
<> 154:37f96f9d4de2 109 /* Array of LPUART peripheral base address. */
<> 154:37f96f9d4de2 110 static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
<> 154:37f96f9d4de2 111 /* Array of LPUART IRQ number. */
<> 154:37f96f9d4de2 112 static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
<> 154:37f96f9d4de2 113 /* Array of LPUART clock name. */
<> 154:37f96f9d4de2 114 static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
<> 154:37f96f9d4de2 115 /* LPUART ISR for transactional APIs. */
<> 154:37f96f9d4de2 116 static lpuart_isr_t s_lpuartIsr;
<> 154:37f96f9d4de2 117
<> 154:37f96f9d4de2 118 /*******************************************************************************
<> 154:37f96f9d4de2 119 * Code
<> 154:37f96f9d4de2 120 ******************************************************************************/
<> 154:37f96f9d4de2 121 uint32_t LPUART_GetInstance(LPUART_Type *base)
<> 154:37f96f9d4de2 122 {
<> 154:37f96f9d4de2 123 uint32_t instance;
<> 154:37f96f9d4de2 124
<> 154:37f96f9d4de2 125 /* Find the instance index from base address mappings. */
<> 154:37f96f9d4de2 126 for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++)
<> 154:37f96f9d4de2 127 {
<> 154:37f96f9d4de2 128 if (s_lpuartBases[instance] == base)
<> 154:37f96f9d4de2 129 {
<> 154:37f96f9d4de2 130 break;
<> 154:37f96f9d4de2 131 }
<> 154:37f96f9d4de2 132 }
<> 154:37f96f9d4de2 133
<> 154:37f96f9d4de2 134 assert(instance < FSL_FEATURE_SOC_LPUART_COUNT);
<> 154:37f96f9d4de2 135
<> 154:37f96f9d4de2 136 return instance;
<> 154:37f96f9d4de2 137 }
<> 154:37f96f9d4de2 138
<> 154:37f96f9d4de2 139 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 140 {
<> 154:37f96f9d4de2 141 size_t size;
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 if (handle->rxRingBufferTail > handle->rxRingBufferHead)
<> 154:37f96f9d4de2 144 {
<> 154:37f96f9d4de2 145 size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
<> 154:37f96f9d4de2 146 }
<> 154:37f96f9d4de2 147 else
<> 154:37f96f9d4de2 148 {
<> 154:37f96f9d4de2 149 size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
<> 154:37f96f9d4de2 150 }
<> 154:37f96f9d4de2 151
<> 154:37f96f9d4de2 152 return size;
<> 154:37f96f9d4de2 153 }
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 156 {
<> 154:37f96f9d4de2 157 bool full;
<> 154:37f96f9d4de2 158
<> 154:37f96f9d4de2 159 if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
<> 154:37f96f9d4de2 160 {
<> 154:37f96f9d4de2 161 full = true;
<> 154:37f96f9d4de2 162 }
<> 154:37f96f9d4de2 163 else
<> 154:37f96f9d4de2 164 {
<> 154:37f96f9d4de2 165 full = false;
<> 154:37f96f9d4de2 166 }
<> 154:37f96f9d4de2 167 return full;
<> 154:37f96f9d4de2 168 }
<> 154:37f96f9d4de2 169
<> 154:37f96f9d4de2 170 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
<> 154:37f96f9d4de2 171 {
<> 154:37f96f9d4de2 172 size_t i;
<> 154:37f96f9d4de2 173
<> 154:37f96f9d4de2 174 /* The Non Blocking write data API assume user have ensured there is enough space in
<> 154:37f96f9d4de2 175 peripheral to write. */
<> 154:37f96f9d4de2 176 for (i = 0; i < length; i++)
<> 154:37f96f9d4de2 177 {
<> 154:37f96f9d4de2 178 base->DATA = data[i];
<> 154:37f96f9d4de2 179 }
<> 154:37f96f9d4de2 180 }
<> 154:37f96f9d4de2 181
<> 154:37f96f9d4de2 182 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
<> 154:37f96f9d4de2 183 {
<> 154:37f96f9d4de2 184 size_t i;
<> 154:37f96f9d4de2 185
<> 154:37f96f9d4de2 186 /* The Non Blocking read data API assume user have ensured there is enough space in
<> 154:37f96f9d4de2 187 peripheral to write. */
<> 154:37f96f9d4de2 188 for (i = 0; i < length; i++)
<> 154:37f96f9d4de2 189 {
<> 154:37f96f9d4de2 190 data[i] = base->DATA;
<> 154:37f96f9d4de2 191 }
<> 154:37f96f9d4de2 192 }
<> 154:37f96f9d4de2 193
<> 154:37f96f9d4de2 194 void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
<> 154:37f96f9d4de2 195 {
<> 154:37f96f9d4de2 196 assert(config);
<> 154:37f96f9d4de2 197 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 198 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
<> 154:37f96f9d4de2 199 assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
<> 154:37f96f9d4de2 200 #endif
<> 154:37f96f9d4de2 201 uint32_t temp;
<> 154:37f96f9d4de2 202 uint16_t sbr, sbrTemp;
<> 154:37f96f9d4de2 203 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
<> 154:37f96f9d4de2 204
<> 154:37f96f9d4de2 205 /* Enable lpuart clock */
<> 154:37f96f9d4de2 206 CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]);
<> 154:37f96f9d4de2 207
<> 154:37f96f9d4de2 208 /* Disable LPUART TX RX before setting. */
<> 154:37f96f9d4de2 209 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
<> 154:37f96f9d4de2 210
<> 154:37f96f9d4de2 211 /* This LPUART instantiation uses a slightly different baud rate calculation
<> 154:37f96f9d4de2 212 * The idea is to use the best OSR (over-sampling rate) possible
<> 154:37f96f9d4de2 213 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
<> 154:37f96f9d4de2 214 * loop to find the best OSR value possible, one that generates minimum baudDiff
<> 154:37f96f9d4de2 215 * iterate through the rest of the supported values of OSR */
<> 154:37f96f9d4de2 216
<> 154:37f96f9d4de2 217 baudDiff = config->baudRate_Bps;
<> 154:37f96f9d4de2 218 osr = 0;
<> 154:37f96f9d4de2 219 sbr = 0;
<> 154:37f96f9d4de2 220 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
<> 154:37f96f9d4de2 221 {
<> 154:37f96f9d4de2 222 /* calculate the temporary sbr value */
<> 154:37f96f9d4de2 223 sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
<> 154:37f96f9d4de2 224 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
<> 154:37f96f9d4de2 225 if (sbrTemp == 0)
<> 154:37f96f9d4de2 226 {
<> 154:37f96f9d4de2 227 sbrTemp = 1;
<> 154:37f96f9d4de2 228 }
<> 154:37f96f9d4de2 229 /* Calculate the baud rate based on the temporary OSR and SBR values */
<> 154:37f96f9d4de2 230 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
<> 154:37f96f9d4de2 231
<> 154:37f96f9d4de2 232 tempDiff = calculatedBaud - config->baudRate_Bps;
<> 154:37f96f9d4de2 233
<> 154:37f96f9d4de2 234 /* Select the better value between srb and (sbr + 1) */
<> 154:37f96f9d4de2 235 if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
<> 154:37f96f9d4de2 236 {
<> 154:37f96f9d4de2 237 tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
<> 154:37f96f9d4de2 238 sbrTemp++;
<> 154:37f96f9d4de2 239 }
<> 154:37f96f9d4de2 240
<> 154:37f96f9d4de2 241 if (tempDiff <= baudDiff)
<> 154:37f96f9d4de2 242 {
<> 154:37f96f9d4de2 243 baudDiff = tempDiff;
<> 154:37f96f9d4de2 244 osr = osrTemp; /* update and store the best OSR value calculated */
<> 154:37f96f9d4de2 245 sbr = sbrTemp; /* update store the best SBR value calculated */
<> 154:37f96f9d4de2 246 }
<> 154:37f96f9d4de2 247 }
<> 154:37f96f9d4de2 248
<> 154:37f96f9d4de2 249 /* Check to see if actual baud rate is within 3% of desired baud rate
<> 154:37f96f9d4de2 250 * based on the best calculate OSR value */
<> 154:37f96f9d4de2 251 if (baudDiff < ((config->baudRate_Bps / 100) * 3))
<> 154:37f96f9d4de2 252 {
<> 154:37f96f9d4de2 253 temp = base->BAUD;
<> 154:37f96f9d4de2 254
<> 154:37f96f9d4de2 255 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
<> 154:37f96f9d4de2 256 * If so, then "BOTHEDGE" sampling must be turned on */
<> 154:37f96f9d4de2 257 if ((osr > 3) && (osr < 8))
<> 154:37f96f9d4de2 258 {
<> 154:37f96f9d4de2 259 temp |= LPUART_BAUD_BOTHEDGE_MASK;
<> 154:37f96f9d4de2 260 }
<> 154:37f96f9d4de2 261
<> 154:37f96f9d4de2 262 /* program the osr value (bit value is one less than actual value) */
<> 154:37f96f9d4de2 263 temp &= ~LPUART_BAUD_OSR_MASK;
<> 154:37f96f9d4de2 264 temp |= LPUART_BAUD_OSR(osr - 1);
<> 154:37f96f9d4de2 265
<> 154:37f96f9d4de2 266 /* write the sbr value to the BAUD registers */
<> 154:37f96f9d4de2 267 temp &= ~LPUART_BAUD_SBR_MASK;
<> 154:37f96f9d4de2 268 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
<> 154:37f96f9d4de2 269 }
<> 154:37f96f9d4de2 270
<> 154:37f96f9d4de2 271 /* Set bit count and parity mode. */
<> 154:37f96f9d4de2 272 base->BAUD &= ~LPUART_BAUD_M10_MASK;
<> 154:37f96f9d4de2 273
<> 154:37f96f9d4de2 274 temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
<> 154:37f96f9d4de2 275
<> 154:37f96f9d4de2 276 if (kLPUART_ParityDisabled != config->parityMode)
<> 154:37f96f9d4de2 277 {
<> 154:37f96f9d4de2 278 temp |= (LPUART_CTRL_M_MASK | (uint8_t)config->parityMode);
<> 154:37f96f9d4de2 279 }
<> 154:37f96f9d4de2 280
<> 154:37f96f9d4de2 281 base->CTRL = temp;
<> 154:37f96f9d4de2 282
<> 154:37f96f9d4de2 283 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 154:37f96f9d4de2 284 /* set stop bit per char */
<> 154:37f96f9d4de2 285 temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
<> 154:37f96f9d4de2 286 base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
<> 154:37f96f9d4de2 287 #endif
<> 154:37f96f9d4de2 288
<> 154:37f96f9d4de2 289 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 290 /* Set tx/rx WATER watermark */
<> 154:37f96f9d4de2 291 base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
<> 154:37f96f9d4de2 292
<> 154:37f96f9d4de2 293 /* Enable tx/rx FIFO */
<> 154:37f96f9d4de2 294 base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
<> 154:37f96f9d4de2 295
<> 154:37f96f9d4de2 296 /* Flush FIFO */
<> 154:37f96f9d4de2 297 base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
<> 154:37f96f9d4de2 298 #endif
<> 154:37f96f9d4de2 299
<> 154:37f96f9d4de2 300 /* Clear all status flags */
<> 154:37f96f9d4de2 301 temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 154:37f96f9d4de2 302 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 154:37f96f9d4de2 303
<> 154:37f96f9d4de2 304 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 305 temp |= LPUART_STAT_IDLE_MASK;
<> 154:37f96f9d4de2 306 #endif
<> 154:37f96f9d4de2 307
<> 154:37f96f9d4de2 308 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 154:37f96f9d4de2 309 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
<> 154:37f96f9d4de2 310 #endif
<> 154:37f96f9d4de2 311
<> 154:37f96f9d4de2 312 base->STAT |= temp;
<> 154:37f96f9d4de2 313
<> 154:37f96f9d4de2 314 /* Enable TX/RX base on configure structure. */
<> 154:37f96f9d4de2 315 temp = base->CTRL;
<> 154:37f96f9d4de2 316 if (config->enableTx)
<> 154:37f96f9d4de2 317 {
<> 154:37f96f9d4de2 318 temp |= LPUART_CTRL_TE_MASK;
<> 154:37f96f9d4de2 319 }
<> 154:37f96f9d4de2 320
<> 154:37f96f9d4de2 321 if (config->enableRx)
<> 154:37f96f9d4de2 322 {
<> 154:37f96f9d4de2 323 temp |= LPUART_CTRL_RE_MASK;
<> 154:37f96f9d4de2 324 }
<> 154:37f96f9d4de2 325
<> 154:37f96f9d4de2 326 base->CTRL = temp;
<> 154:37f96f9d4de2 327 }
<> 154:37f96f9d4de2 328 void LPUART_Deinit(LPUART_Type *base)
<> 154:37f96f9d4de2 329 {
<> 154:37f96f9d4de2 330 uint32_t temp;
<> 154:37f96f9d4de2 331
<> 154:37f96f9d4de2 332 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 333 /* Wait tx FIFO send out*/
<> 154:37f96f9d4de2 334 while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
<> 154:37f96f9d4de2 335 {
<> 154:37f96f9d4de2 336 }
<> 154:37f96f9d4de2 337 #endif
<> 154:37f96f9d4de2 338 /* Wait last char shoft out */
<> 154:37f96f9d4de2 339 while (0 == (base->STAT & LPUART_STAT_TC_MASK))
<> 154:37f96f9d4de2 340 {
<> 154:37f96f9d4de2 341 }
<> 154:37f96f9d4de2 342
<> 154:37f96f9d4de2 343 /* Clear all status flags */
<> 154:37f96f9d4de2 344 temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
<> 154:37f96f9d4de2 345 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
<> 154:37f96f9d4de2 346
<> 154:37f96f9d4de2 347 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 348 temp |= LPUART_STAT_IDLE_MASK;
<> 154:37f96f9d4de2 349 #endif
<> 154:37f96f9d4de2 350
<> 154:37f96f9d4de2 351 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 154:37f96f9d4de2 352 temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
<> 154:37f96f9d4de2 353 #endif
<> 154:37f96f9d4de2 354
<> 154:37f96f9d4de2 355 base->STAT |= temp;
<> 154:37f96f9d4de2 356
<> 154:37f96f9d4de2 357 /* Disable the module. */
<> 154:37f96f9d4de2 358 base->CTRL = 0;
<> 154:37f96f9d4de2 359
<> 154:37f96f9d4de2 360 /* Disable lpuart clock */
<> 154:37f96f9d4de2 361 CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]);
<> 154:37f96f9d4de2 362 }
<> 154:37f96f9d4de2 363
<> 154:37f96f9d4de2 364 void LPUART_GetDefaultConfig(lpuart_config_t *config)
<> 154:37f96f9d4de2 365 {
<> 154:37f96f9d4de2 366 assert(config);
<> 154:37f96f9d4de2 367 config->baudRate_Bps = 115200U;
<> 154:37f96f9d4de2 368 config->parityMode = kLPUART_ParityDisabled;
<> 154:37f96f9d4de2 369 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 154:37f96f9d4de2 370 config->stopBitCount = kLPUART_OneStopBit;
<> 154:37f96f9d4de2 371 #endif
<> 154:37f96f9d4de2 372 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 373 config->txFifoWatermark = 0;
<> 154:37f96f9d4de2 374 config->rxFifoWatermark = 0;
<> 154:37f96f9d4de2 375 #endif
<> 154:37f96f9d4de2 376 config->enableTx = false;
<> 154:37f96f9d4de2 377 config->enableRx = false;
<> 154:37f96f9d4de2 378 }
<> 154:37f96f9d4de2 379
<> 154:37f96f9d4de2 380 void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
<> 154:37f96f9d4de2 381 {
<> 154:37f96f9d4de2 382 uint32_t temp, oldCtrl;
<> 154:37f96f9d4de2 383 uint16_t sbr, sbrTemp;
<> 154:37f96f9d4de2 384 uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
<> 154:37f96f9d4de2 385
<> 154:37f96f9d4de2 386 /* Store CTRL before disable Tx and Rx */
<> 154:37f96f9d4de2 387 oldCtrl = base->CTRL;
<> 154:37f96f9d4de2 388
<> 154:37f96f9d4de2 389 /* Disable LPUART TX RX before setting. */
<> 154:37f96f9d4de2 390 base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
<> 154:37f96f9d4de2 391
<> 154:37f96f9d4de2 392 /* This LPUART instantiation uses a slightly different baud rate calculation
<> 154:37f96f9d4de2 393 * The idea is to use the best OSR (over-sampling rate) possible
<> 154:37f96f9d4de2 394 * Note, OSR is typically hard-set to 16 in other LPUART instantiations
<> 154:37f96f9d4de2 395 * loop to find the best OSR value possible, one that generates minimum baudDiff
<> 154:37f96f9d4de2 396 * iterate through the rest of the supported values of OSR */
<> 154:37f96f9d4de2 397
<> 154:37f96f9d4de2 398 baudDiff = baudRate_Bps;
<> 154:37f96f9d4de2 399 osr = 0;
<> 154:37f96f9d4de2 400 sbr = 0;
<> 154:37f96f9d4de2 401 for (osrTemp = 4; osrTemp <= 32; osrTemp++)
<> 154:37f96f9d4de2 402 {
<> 154:37f96f9d4de2 403 /* calculate the temporary sbr value */
<> 154:37f96f9d4de2 404 sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
<> 154:37f96f9d4de2 405 /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
<> 154:37f96f9d4de2 406 if (sbrTemp == 0)
<> 154:37f96f9d4de2 407 {
<> 154:37f96f9d4de2 408 sbrTemp = 1;
<> 154:37f96f9d4de2 409 }
<> 154:37f96f9d4de2 410 /* Calculate the baud rate based on the temporary OSR and SBR values */
<> 154:37f96f9d4de2 411 calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
<> 154:37f96f9d4de2 412
<> 154:37f96f9d4de2 413 tempDiff = calculatedBaud - baudRate_Bps;
<> 154:37f96f9d4de2 414
<> 154:37f96f9d4de2 415 /* Select the better value between srb and (sbr + 1) */
<> 154:37f96f9d4de2 416 if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
<> 154:37f96f9d4de2 417 {
<> 154:37f96f9d4de2 418 tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
<> 154:37f96f9d4de2 419 sbrTemp++;
<> 154:37f96f9d4de2 420 }
<> 154:37f96f9d4de2 421
<> 154:37f96f9d4de2 422 if (tempDiff <= baudDiff)
<> 154:37f96f9d4de2 423 {
<> 154:37f96f9d4de2 424 baudDiff = tempDiff;
<> 154:37f96f9d4de2 425 osr = osrTemp; /* update and store the best OSR value calculated */
<> 154:37f96f9d4de2 426 sbr = sbrTemp; /* update store the best SBR value calculated */
<> 154:37f96f9d4de2 427 }
<> 154:37f96f9d4de2 428 }
<> 154:37f96f9d4de2 429
<> 154:37f96f9d4de2 430 /* Check to see if actual baud rate is within 3% of desired baud rate
<> 154:37f96f9d4de2 431 * based on the best calculate OSR value */
<> 154:37f96f9d4de2 432 if (baudDiff < ((baudRate_Bps / 100) * 3))
<> 154:37f96f9d4de2 433 {
<> 154:37f96f9d4de2 434 temp = base->BAUD;
<> 154:37f96f9d4de2 435
<> 154:37f96f9d4de2 436 /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
<> 154:37f96f9d4de2 437 * If so, then "BOTHEDGE" sampling must be turned on */
<> 154:37f96f9d4de2 438 if ((osr > 3) && (osr < 8))
<> 154:37f96f9d4de2 439 {
<> 154:37f96f9d4de2 440 temp |= LPUART_BAUD_BOTHEDGE_MASK;
<> 154:37f96f9d4de2 441 }
<> 154:37f96f9d4de2 442
<> 154:37f96f9d4de2 443 /* program the osr value (bit value is one less than actual value) */
<> 154:37f96f9d4de2 444 temp &= ~LPUART_BAUD_OSR_MASK;
<> 154:37f96f9d4de2 445 temp |= LPUART_BAUD_OSR(osr - 1);
<> 154:37f96f9d4de2 446
<> 154:37f96f9d4de2 447 /* write the sbr value to the BAUD registers */
<> 154:37f96f9d4de2 448 temp &= ~LPUART_BAUD_SBR_MASK;
<> 154:37f96f9d4de2 449 base->BAUD = temp | LPUART_BAUD_SBR(sbr);
<> 154:37f96f9d4de2 450 }
<> 154:37f96f9d4de2 451
<> 154:37f96f9d4de2 452 /* Restore CTRL. */
<> 154:37f96f9d4de2 453 base->CTRL = oldCtrl;
<> 154:37f96f9d4de2 454 }
<> 154:37f96f9d4de2 455
<> 154:37f96f9d4de2 456 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 457 {
<> 154:37f96f9d4de2 458 base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
<> 154:37f96f9d4de2 459 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 460 base->FIFO |= ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
<> 154:37f96f9d4de2 461 #endif
<> 154:37f96f9d4de2 462 mask &= 0xFFFFFF00U;
<> 154:37f96f9d4de2 463 base->CTRL |= mask;
<> 154:37f96f9d4de2 464 }
<> 154:37f96f9d4de2 465
<> 154:37f96f9d4de2 466 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 467 {
<> 154:37f96f9d4de2 468 base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
<> 154:37f96f9d4de2 469 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 470 base->FIFO &= ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
<> 154:37f96f9d4de2 471 #endif
<> 154:37f96f9d4de2 472 mask &= 0xFFFFFF00U;
<> 154:37f96f9d4de2 473 base->CTRL &= ~mask;
<> 154:37f96f9d4de2 474 }
<> 154:37f96f9d4de2 475
<> 154:37f96f9d4de2 476 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
<> 154:37f96f9d4de2 477 {
<> 154:37f96f9d4de2 478 uint32_t temp;
<> 154:37f96f9d4de2 479 temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
<> 154:37f96f9d4de2 480 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 481 temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
<> 154:37f96f9d4de2 482 #endif
<> 154:37f96f9d4de2 483 temp |= (base->CTRL & 0xFF0C000);
<> 154:37f96f9d4de2 484
<> 154:37f96f9d4de2 485 return temp;
<> 154:37f96f9d4de2 486 }
<> 154:37f96f9d4de2 487
<> 154:37f96f9d4de2 488 uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
<> 154:37f96f9d4de2 489 {
<> 154:37f96f9d4de2 490 uint32_t temp;
<> 154:37f96f9d4de2 491 temp = base->STAT;
<> 154:37f96f9d4de2 492 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 493 temp |= (base->FIFO &
<> 154:37f96f9d4de2 494 (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
<> 154:37f96f9d4de2 495 16;
<> 154:37f96f9d4de2 496 #endif
<> 154:37f96f9d4de2 497 return temp;
<> 154:37f96f9d4de2 498 }
<> 154:37f96f9d4de2 499
<> 154:37f96f9d4de2 500 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 501 {
<> 154:37f96f9d4de2 502 uint32_t temp;
<> 154:37f96f9d4de2 503 status_t status;
<> 154:37f96f9d4de2 504 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 505 temp = (uint32_t)base->FIFO;
<> 154:37f96f9d4de2 506 temp &= (uint32_t)(~(kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag));
<> 154:37f96f9d4de2 507 temp |= mask & (kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag);
<> 154:37f96f9d4de2 508 base->FIFO = temp;
<> 154:37f96f9d4de2 509 #endif
<> 154:37f96f9d4de2 510 temp = (uint32_t)base->STAT;
<> 154:37f96f9d4de2 511 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 512 temp &= (uint32_t)(~(kLPUART_LinBreakFlag));
<> 154:37f96f9d4de2 513 temp |= mask & kLPUART_LinBreakFlag;
<> 154:37f96f9d4de2 514 #endif
<> 154:37f96f9d4de2 515 temp &= (uint32_t)(~(kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag |
<> 154:37f96f9d4de2 516 kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag));
<> 154:37f96f9d4de2 517 temp |= mask & (kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_NoiseErrorFlag |
<> 154:37f96f9d4de2 518 kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag);
<> 154:37f96f9d4de2 519 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 154:37f96f9d4de2 520 temp &= (uint32_t)(~(kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag));
<> 154:37f96f9d4de2 521 temp |= mask & (kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag);
<> 154:37f96f9d4de2 522 #endif
<> 154:37f96f9d4de2 523 base->STAT |= temp;
<> 154:37f96f9d4de2 524 /* If some flags still pending. */
<> 154:37f96f9d4de2 525 if (mask & LPUART_GetStatusFlags(base))
<> 154:37f96f9d4de2 526 {
<> 154:37f96f9d4de2 527 /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
<> 154:37f96f9d4de2 528 kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
<> 154:37f96f9d4de2 529 kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
<> 154:37f96f9d4de2 530 kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */
<> 154:37f96f9d4de2 531 status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */
<> 154:37f96f9d4de2 532 }
<> 154:37f96f9d4de2 533 else
<> 154:37f96f9d4de2 534 {
<> 154:37f96f9d4de2 535 status = kStatus_Success;
<> 154:37f96f9d4de2 536 }
<> 154:37f96f9d4de2 537
<> 154:37f96f9d4de2 538 return status;
<> 154:37f96f9d4de2 539 }
<> 154:37f96f9d4de2 540
<> 154:37f96f9d4de2 541 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
<> 154:37f96f9d4de2 542 {
<> 154:37f96f9d4de2 543 /* This API can only ensure that the data is written into the data buffer but can't
<> 154:37f96f9d4de2 544 ensure all data in the data buffer are sent into the transmit shift buffer. */
<> 154:37f96f9d4de2 545 while (length--)
<> 154:37f96f9d4de2 546 {
<> 154:37f96f9d4de2 547 while (!(base->STAT & LPUART_STAT_TDRE_MASK))
<> 154:37f96f9d4de2 548 {
<> 154:37f96f9d4de2 549 }
<> 154:37f96f9d4de2 550 base->DATA = *(data++);
<> 154:37f96f9d4de2 551 }
<> 154:37f96f9d4de2 552 }
<> 154:37f96f9d4de2 553
<> 154:37f96f9d4de2 554 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
<> 154:37f96f9d4de2 555 {
<> 154:37f96f9d4de2 556 uint32_t statusFlag;
<> 154:37f96f9d4de2 557
<> 154:37f96f9d4de2 558 while (length--)
<> 154:37f96f9d4de2 559 {
<> 154:37f96f9d4de2 560 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 561 while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
<> 154:37f96f9d4de2 562 #else
<> 154:37f96f9d4de2 563 while (!(base->STAT & LPUART_STAT_RDRF_MASK))
<> 154:37f96f9d4de2 564 #endif
<> 154:37f96f9d4de2 565 {
<> 154:37f96f9d4de2 566 statusFlag = LPUART_GetStatusFlags(base);
<> 154:37f96f9d4de2 567
<> 154:37f96f9d4de2 568 if (statusFlag & kLPUART_RxOverrunFlag)
<> 154:37f96f9d4de2 569 {
<> 154:37f96f9d4de2 570 LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
<> 154:37f96f9d4de2 571 return kStatus_LPUART_RxHardwareOverrun;
<> 154:37f96f9d4de2 572 }
<> 154:37f96f9d4de2 573
<> 154:37f96f9d4de2 574 if (statusFlag & kLPUART_NoiseErrorFlag)
<> 154:37f96f9d4de2 575 {
<> 154:37f96f9d4de2 576 LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
<> 154:37f96f9d4de2 577 return kStatus_LPUART_NoiseError;
<> 154:37f96f9d4de2 578 }
<> 154:37f96f9d4de2 579
<> 154:37f96f9d4de2 580 if (statusFlag & kLPUART_FramingErrorFlag)
<> 154:37f96f9d4de2 581 {
<> 154:37f96f9d4de2 582 LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
<> 154:37f96f9d4de2 583 return kStatus_LPUART_FramingError;
<> 154:37f96f9d4de2 584 }
<> 154:37f96f9d4de2 585
<> 154:37f96f9d4de2 586 if (statusFlag & kLPUART_ParityErrorFlag)
<> 154:37f96f9d4de2 587 {
<> 154:37f96f9d4de2 588 LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
<> 154:37f96f9d4de2 589 return kStatus_LPUART_ParityError;
<> 154:37f96f9d4de2 590 }
<> 154:37f96f9d4de2 591 }
<> 154:37f96f9d4de2 592 *(data++) = base->DATA;
<> 154:37f96f9d4de2 593 }
<> 154:37f96f9d4de2 594
<> 154:37f96f9d4de2 595 return kStatus_Success;
<> 154:37f96f9d4de2 596 }
<> 154:37f96f9d4de2 597
<> 154:37f96f9d4de2 598 void LPUART_TransferCreateHandle(LPUART_Type *base,
<> 154:37f96f9d4de2 599 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 600 lpuart_transfer_callback_t callback,
<> 154:37f96f9d4de2 601 void *userData)
<> 154:37f96f9d4de2 602 {
<> 154:37f96f9d4de2 603 assert(handle);
<> 154:37f96f9d4de2 604
<> 154:37f96f9d4de2 605 uint32_t instance;
<> 154:37f96f9d4de2 606
<> 154:37f96f9d4de2 607 /* Zero the handle. */
<> 154:37f96f9d4de2 608 memset(handle, 0, sizeof(lpuart_handle_t));
<> 154:37f96f9d4de2 609
<> 154:37f96f9d4de2 610 /* Set the TX/RX state. */
<> 154:37f96f9d4de2 611 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 612 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 613
<> 154:37f96f9d4de2 614 /* Set the callback and user data. */
<> 154:37f96f9d4de2 615 handle->callback = callback;
<> 154:37f96f9d4de2 616 handle->userData = userData;
<> 154:37f96f9d4de2 617
<> 154:37f96f9d4de2 618 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 619 /* Note:
<> 154:37f96f9d4de2 620 Take care of the RX FIFO, RX interrupt request only assert when received bytes
<> 154:37f96f9d4de2 621 equal or more than RX water mark, there is potential issue if RX water
<> 154:37f96f9d4de2 622 mark larger than 1.
<> 154:37f96f9d4de2 623 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
<> 154:37f96f9d4de2 624 5 bytes are received. the last byte will be saved in FIFO but not trigger
<> 154:37f96f9d4de2 625 RX interrupt because the water mark is 2.
<> 154:37f96f9d4de2 626 */
<> 154:37f96f9d4de2 627 base->WATER &= (~LPUART_WATER_RXWATER_SHIFT);
<> 154:37f96f9d4de2 628 #endif
<> 154:37f96f9d4de2 629
<> 154:37f96f9d4de2 630 /* Get instance from peripheral base address. */
<> 154:37f96f9d4de2 631 instance = LPUART_GetInstance(base);
<> 154:37f96f9d4de2 632
<> 154:37f96f9d4de2 633 /* Save the handle in global variables to support the double weak mechanism. */
<> 154:37f96f9d4de2 634 s_lpuartHandle[instance] = handle;
<> 154:37f96f9d4de2 635
<> 154:37f96f9d4de2 636 s_lpuartIsr = LPUART_TransferHandleIRQ;
<> 154:37f96f9d4de2 637
<> 154:37f96f9d4de2 638 /* Enable interrupt in NVIC. */
<> 154:37f96f9d4de2 639 EnableIRQ(s_lpuartIRQ[instance]);
<> 154:37f96f9d4de2 640 }
<> 154:37f96f9d4de2 641
<> 154:37f96f9d4de2 642 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
<> 154:37f96f9d4de2 643 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 644 uint8_t *ringBuffer,
<> 154:37f96f9d4de2 645 size_t ringBufferSize)
<> 154:37f96f9d4de2 646 {
<> 154:37f96f9d4de2 647 assert(handle);
<> 154:37f96f9d4de2 648
<> 154:37f96f9d4de2 649 /* Setup the ring buffer address */
<> 154:37f96f9d4de2 650 if (ringBuffer)
<> 154:37f96f9d4de2 651 {
<> 154:37f96f9d4de2 652 handle->rxRingBuffer = ringBuffer;
<> 154:37f96f9d4de2 653 handle->rxRingBufferSize = ringBufferSize;
<> 154:37f96f9d4de2 654 handle->rxRingBufferHead = 0U;
<> 154:37f96f9d4de2 655 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 656
<> 154:37f96f9d4de2 657 /* Enable the interrupt to accept the data when user need the ring buffer. */
<> 154:37f96f9d4de2 658 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 659 }
<> 154:37f96f9d4de2 660 }
<> 154:37f96f9d4de2 661
<> 154:37f96f9d4de2 662 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 663 {
<> 154:37f96f9d4de2 664 assert(handle);
<> 154:37f96f9d4de2 665
<> 154:37f96f9d4de2 666 if (handle->rxState == kLPUART_RxIdle)
<> 154:37f96f9d4de2 667 {
<> 154:37f96f9d4de2 668 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 669 }
<> 154:37f96f9d4de2 670
<> 154:37f96f9d4de2 671 handle->rxRingBuffer = NULL;
<> 154:37f96f9d4de2 672 handle->rxRingBufferSize = 0U;
<> 154:37f96f9d4de2 673 handle->rxRingBufferHead = 0U;
<> 154:37f96f9d4de2 674 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 675 }
<> 154:37f96f9d4de2 676
<> 154:37f96f9d4de2 677 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
<> 154:37f96f9d4de2 678 {
<> 154:37f96f9d4de2 679 status_t status;
<> 154:37f96f9d4de2 680
<> 154:37f96f9d4de2 681 /* Return error if xfer invalid. */
<> 154:37f96f9d4de2 682 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 154:37f96f9d4de2 683 {
<> 154:37f96f9d4de2 684 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 685 }
<> 154:37f96f9d4de2 686
<> 154:37f96f9d4de2 687 /* Return error if current TX busy. */
<> 154:37f96f9d4de2 688 if (kLPUART_TxBusy == handle->txState)
<> 154:37f96f9d4de2 689 {
<> 154:37f96f9d4de2 690 status = kStatus_LPUART_TxBusy;
<> 154:37f96f9d4de2 691 }
<> 154:37f96f9d4de2 692 else
<> 154:37f96f9d4de2 693 {
<> 154:37f96f9d4de2 694 handle->txData = xfer->data;
<> 154:37f96f9d4de2 695 handle->txDataSize = xfer->dataSize;
<> 154:37f96f9d4de2 696 handle->txDataSizeAll = xfer->dataSize;
<> 154:37f96f9d4de2 697 handle->txState = kLPUART_TxBusy;
<> 154:37f96f9d4de2 698
<> 154:37f96f9d4de2 699 /* Enable transmiter interrupt. */
<> 154:37f96f9d4de2 700 LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
<> 154:37f96f9d4de2 701
<> 154:37f96f9d4de2 702 status = kStatus_Success;
<> 154:37f96f9d4de2 703 }
<> 154:37f96f9d4de2 704
<> 154:37f96f9d4de2 705 return status;
<> 154:37f96f9d4de2 706 }
<> 154:37f96f9d4de2 707
<> 154:37f96f9d4de2 708 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 709 {
<> 154:37f96f9d4de2 710 LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
<> 154:37f96f9d4de2 711
<> 154:37f96f9d4de2 712 handle->txDataSize = 0;
<> 154:37f96f9d4de2 713 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 714 }
<> 154:37f96f9d4de2 715
<> 154:37f96f9d4de2 716 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
<> 154:37f96f9d4de2 717 {
<> 154:37f96f9d4de2 718 if (kLPUART_TxIdle == handle->txState)
<> 154:37f96f9d4de2 719 {
<> 154:37f96f9d4de2 720 return kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 721 }
<> 154:37f96f9d4de2 722
<> 154:37f96f9d4de2 723 if (!count)
<> 154:37f96f9d4de2 724 {
<> 154:37f96f9d4de2 725 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 726 }
<> 154:37f96f9d4de2 727
<> 154:37f96f9d4de2 728 *count = handle->txDataSizeAll - handle->txDataSize;
<> 154:37f96f9d4de2 729
<> 154:37f96f9d4de2 730 return kStatus_Success;
<> 154:37f96f9d4de2 731 }
<> 154:37f96f9d4de2 732
<> 154:37f96f9d4de2 733 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
<> 154:37f96f9d4de2 734 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 735 lpuart_transfer_t *xfer,
<> 154:37f96f9d4de2 736 size_t *receivedBytes)
<> 154:37f96f9d4de2 737 {
<> 154:37f96f9d4de2 738 uint32_t i;
<> 154:37f96f9d4de2 739 status_t status;
<> 154:37f96f9d4de2 740 /* How many bytes to copy from ring buffer to user memory. */
<> 154:37f96f9d4de2 741 size_t bytesToCopy = 0U;
<> 154:37f96f9d4de2 742 /* How many bytes to receive. */
<> 154:37f96f9d4de2 743 size_t bytesToReceive;
<> 154:37f96f9d4de2 744 /* How many bytes currently have received. */
<> 154:37f96f9d4de2 745 size_t bytesCurrentReceived;
<> 154:37f96f9d4de2 746 uint32_t regPrimask = 0U;
<> 154:37f96f9d4de2 747
<> 154:37f96f9d4de2 748 /* Return error if xfer invalid. */
<> 154:37f96f9d4de2 749 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 154:37f96f9d4de2 750 {
<> 154:37f96f9d4de2 751 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 752 }
<> 154:37f96f9d4de2 753
<> 154:37f96f9d4de2 754 /* How to get data:
<> 154:37f96f9d4de2 755 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
<> 154:37f96f9d4de2 756 to lpuart handle, enable interrupt to store received data to xfer->data. When
<> 154:37f96f9d4de2 757 all data received, trigger callback.
<> 154:37f96f9d4de2 758 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
<> 154:37f96f9d4de2 759 If there are enough data in ring buffer, copy them to xfer->data and return.
<> 154:37f96f9d4de2 760 If there are not enough data in ring buffer, copy all of them to xfer->data,
<> 154:37f96f9d4de2 761 save the xfer->data remained empty space to lpuart handle, receive data
<> 154:37f96f9d4de2 762 to this empty space and trigger callback when finished. */
<> 154:37f96f9d4de2 763
<> 154:37f96f9d4de2 764 if (kLPUART_RxBusy == handle->rxState)
<> 154:37f96f9d4de2 765 {
<> 154:37f96f9d4de2 766 status = kStatus_LPUART_RxBusy;
<> 154:37f96f9d4de2 767 }
<> 154:37f96f9d4de2 768 else
<> 154:37f96f9d4de2 769 {
<> 154:37f96f9d4de2 770 bytesToReceive = xfer->dataSize;
<> 154:37f96f9d4de2 771 bytesCurrentReceived = 0;
<> 154:37f96f9d4de2 772
<> 154:37f96f9d4de2 773 /* If RX ring buffer is used. */
<> 154:37f96f9d4de2 774 if (handle->rxRingBuffer)
<> 154:37f96f9d4de2 775 {
<> 154:37f96f9d4de2 776 /* Disable IRQ, protect ring buffer. */
<> 154:37f96f9d4de2 777 regPrimask = DisableGlobalIRQ();
<> 154:37f96f9d4de2 778
<> 154:37f96f9d4de2 779 /* How many bytes in RX ring buffer currently. */
<> 154:37f96f9d4de2 780 bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
<> 154:37f96f9d4de2 781
<> 154:37f96f9d4de2 782 if (bytesToCopy)
<> 154:37f96f9d4de2 783 {
<> 154:37f96f9d4de2 784 bytesToCopy = MIN(bytesToReceive, bytesToCopy);
<> 154:37f96f9d4de2 785
<> 154:37f96f9d4de2 786 bytesToReceive -= bytesToCopy;
<> 154:37f96f9d4de2 787
<> 154:37f96f9d4de2 788 /* Copy data from ring buffer to user memory. */
<> 154:37f96f9d4de2 789 for (i = 0U; i < bytesToCopy; i++)
<> 154:37f96f9d4de2 790 {
<> 154:37f96f9d4de2 791 xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
<> 154:37f96f9d4de2 792
<> 154:37f96f9d4de2 793 /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
<> 154:37f96f9d4de2 794 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
<> 154:37f96f9d4de2 795 {
<> 154:37f96f9d4de2 796 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 797 }
<> 154:37f96f9d4de2 798 else
<> 154:37f96f9d4de2 799 {
<> 154:37f96f9d4de2 800 handle->rxRingBufferTail++;
<> 154:37f96f9d4de2 801 }
<> 154:37f96f9d4de2 802 }
<> 154:37f96f9d4de2 803 }
<> 154:37f96f9d4de2 804
<> 154:37f96f9d4de2 805 /* If ring buffer does not have enough data, still need to read more data. */
<> 154:37f96f9d4de2 806 if (bytesToReceive)
<> 154:37f96f9d4de2 807 {
<> 154:37f96f9d4de2 808 /* No data in ring buffer, save the request to LPUART handle. */
<> 154:37f96f9d4de2 809 handle->rxData = xfer->data + bytesCurrentReceived;
<> 154:37f96f9d4de2 810 handle->rxDataSize = bytesToReceive;
<> 154:37f96f9d4de2 811 handle->rxDataSizeAll = bytesToReceive;
<> 154:37f96f9d4de2 812 handle->rxState = kLPUART_RxBusy;
<> 154:37f96f9d4de2 813 }
<> 154:37f96f9d4de2 814 /* Enable IRQ if previously enabled. */
<> 154:37f96f9d4de2 815 EnableGlobalIRQ(regPrimask);
<> 154:37f96f9d4de2 816
<> 154:37f96f9d4de2 817 /* Call user callback since all data are received. */
<> 154:37f96f9d4de2 818 if (0 == bytesToReceive)
<> 154:37f96f9d4de2 819 {
<> 154:37f96f9d4de2 820 if (handle->callback)
<> 154:37f96f9d4de2 821 {
<> 154:37f96f9d4de2 822 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
<> 154:37f96f9d4de2 823 }
<> 154:37f96f9d4de2 824 }
<> 154:37f96f9d4de2 825 }
<> 154:37f96f9d4de2 826 /* Ring buffer not used. */
<> 154:37f96f9d4de2 827 else
<> 154:37f96f9d4de2 828 {
<> 154:37f96f9d4de2 829 handle->rxData = xfer->data + bytesCurrentReceived;
<> 154:37f96f9d4de2 830 handle->rxDataSize = bytesToReceive;
<> 154:37f96f9d4de2 831 handle->rxDataSizeAll = bytesToReceive;
<> 154:37f96f9d4de2 832 handle->rxState = kLPUART_RxBusy;
<> 154:37f96f9d4de2 833
<> 154:37f96f9d4de2 834 /* Enable RX interrupt. */
<> 154:37f96f9d4de2 835 LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 836 }
<> 154:37f96f9d4de2 837
<> 154:37f96f9d4de2 838 /* Return the how many bytes have read. */
<> 154:37f96f9d4de2 839 if (receivedBytes)
<> 154:37f96f9d4de2 840 {
<> 154:37f96f9d4de2 841 *receivedBytes = bytesCurrentReceived;
<> 154:37f96f9d4de2 842 }
<> 154:37f96f9d4de2 843
<> 154:37f96f9d4de2 844 status = kStatus_Success;
<> 154:37f96f9d4de2 845 }
<> 154:37f96f9d4de2 846
<> 154:37f96f9d4de2 847 return status;
<> 154:37f96f9d4de2 848 }
<> 154:37f96f9d4de2 849
<> 154:37f96f9d4de2 850 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 851 {
<> 154:37f96f9d4de2 852 /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
<> 154:37f96f9d4de2 853 if (!handle->rxRingBuffer)
<> 154:37f96f9d4de2 854 {
<> 154:37f96f9d4de2 855 /* Disable RX interrupt. */
<> 154:37f96f9d4de2 856 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 857 }
<> 154:37f96f9d4de2 858
<> 154:37f96f9d4de2 859 handle->rxDataSize = 0U;
<> 154:37f96f9d4de2 860 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 861 }
<> 154:37f96f9d4de2 862
<> 154:37f96f9d4de2 863 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
<> 154:37f96f9d4de2 864 {
<> 154:37f96f9d4de2 865 if (kLPUART_RxIdle == handle->rxState)
<> 154:37f96f9d4de2 866 {
<> 154:37f96f9d4de2 867 return kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 868 }
<> 154:37f96f9d4de2 869
<> 154:37f96f9d4de2 870 if (!count)
<> 154:37f96f9d4de2 871 {
<> 154:37f96f9d4de2 872 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 873 }
<> 154:37f96f9d4de2 874
<> 154:37f96f9d4de2 875 *count = handle->rxDataSizeAll - handle->rxDataSize;
<> 154:37f96f9d4de2 876
<> 154:37f96f9d4de2 877 return kStatus_Success;
<> 154:37f96f9d4de2 878 }
<> 154:37f96f9d4de2 879
<> 154:37f96f9d4de2 880 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 881 {
<> 154:37f96f9d4de2 882 uint8_t count;
<> 154:37f96f9d4de2 883 uint8_t tempCount;
<> 154:37f96f9d4de2 884 volatile uint8_t dummy;
<> 154:37f96f9d4de2 885
<> 154:37f96f9d4de2 886 assert(handle);
<> 154:37f96f9d4de2 887
<> 154:37f96f9d4de2 888 /* If RX overrun. */
<> 154:37f96f9d4de2 889 if (LPUART_STAT_OR_MASK & base->STAT)
<> 154:37f96f9d4de2 890 {
<> 154:37f96f9d4de2 891 /* Read base->DATA, otherwise the RX does not work. */
<> 154:37f96f9d4de2 892 dummy = base->DATA;
<> 154:37f96f9d4de2 893 /* Avoid optimization */
<> 154:37f96f9d4de2 894 dummy++;
<> 154:37f96f9d4de2 895 /* Trigger callback. */
<> 154:37f96f9d4de2 896 if (handle->callback)
<> 154:37f96f9d4de2 897 {
<> 154:37f96f9d4de2 898 handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
<> 154:37f96f9d4de2 899 }
<> 154:37f96f9d4de2 900 }
<> 154:37f96f9d4de2 901
<> 154:37f96f9d4de2 902 /* Receive data register full */
<> 154:37f96f9d4de2 903 if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
<> 154:37f96f9d4de2 904 {
<> 154:37f96f9d4de2 905 /* Get the size that can be stored into buffer for this interrupt. */
<> 154:37f96f9d4de2 906 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 907 count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
<> 154:37f96f9d4de2 908 #else
<> 154:37f96f9d4de2 909 count = 1;
<> 154:37f96f9d4de2 910 #endif
<> 154:37f96f9d4de2 911
<> 154:37f96f9d4de2 912 /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
<> 154:37f96f9d4de2 913 while ((count) && (handle->rxDataSize))
<> 154:37f96f9d4de2 914 {
<> 154:37f96f9d4de2 915 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 916 tempCount = MIN(handle->rxDataSize, count);
<> 154:37f96f9d4de2 917 #else
<> 154:37f96f9d4de2 918 tempCount = 1;
<> 154:37f96f9d4de2 919 #endif
<> 154:37f96f9d4de2 920
<> 154:37f96f9d4de2 921 /* Using non block API to read the data from the registers. */
<> 154:37f96f9d4de2 922 LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
<> 154:37f96f9d4de2 923 handle->rxData += tempCount;
<> 154:37f96f9d4de2 924 handle->rxDataSize -= tempCount;
<> 154:37f96f9d4de2 925 count -= tempCount;
<> 154:37f96f9d4de2 926
<> 154:37f96f9d4de2 927 /* If all the data required for upper layer is ready, trigger callback. */
<> 154:37f96f9d4de2 928 if (!handle->rxDataSize)
<> 154:37f96f9d4de2 929 {
<> 154:37f96f9d4de2 930 handle->rxState = kLPUART_RxIdle;
<> 154:37f96f9d4de2 931
<> 154:37f96f9d4de2 932 if (handle->callback)
<> 154:37f96f9d4de2 933 {
<> 154:37f96f9d4de2 934 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
<> 154:37f96f9d4de2 935 }
<> 154:37f96f9d4de2 936 }
<> 154:37f96f9d4de2 937 }
<> 154:37f96f9d4de2 938
<> 154:37f96f9d4de2 939 /* If use RX ring buffer, receive data to ring buffer. */
<> 154:37f96f9d4de2 940 if (handle->rxRingBuffer)
<> 154:37f96f9d4de2 941 {
<> 154:37f96f9d4de2 942 while (count--)
<> 154:37f96f9d4de2 943 {
<> 154:37f96f9d4de2 944 /* If RX ring buffer is full, trigger callback to notify over run. */
<> 154:37f96f9d4de2 945 if (LPUART_TransferIsRxRingBufferFull(base, handle))
<> 154:37f96f9d4de2 946 {
<> 154:37f96f9d4de2 947 if (handle->callback)
<> 154:37f96f9d4de2 948 {
<> 154:37f96f9d4de2 949 handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
<> 154:37f96f9d4de2 950 }
<> 154:37f96f9d4de2 951 }
<> 154:37f96f9d4de2 952
<> 154:37f96f9d4de2 953 /* If ring buffer is still full after callback function, the oldest data is overrided. */
<> 154:37f96f9d4de2 954 if (LPUART_TransferIsRxRingBufferFull(base, handle))
<> 154:37f96f9d4de2 955 {
<> 154:37f96f9d4de2 956 /* Increase handle->rxRingBufferTail to make room for new data. */
<> 154:37f96f9d4de2 957 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
<> 154:37f96f9d4de2 958 {
<> 154:37f96f9d4de2 959 handle->rxRingBufferTail = 0U;
<> 154:37f96f9d4de2 960 }
<> 154:37f96f9d4de2 961 else
<> 154:37f96f9d4de2 962 {
<> 154:37f96f9d4de2 963 handle->rxRingBufferTail++;
<> 154:37f96f9d4de2 964 }
<> 154:37f96f9d4de2 965 }
<> 154:37f96f9d4de2 966
<> 154:37f96f9d4de2 967 /* Read data. */
<> 154:37f96f9d4de2 968 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
<> 154:37f96f9d4de2 969
<> 154:37f96f9d4de2 970 /* Increase handle->rxRingBufferHead. */
<> 154:37f96f9d4de2 971 if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
<> 154:37f96f9d4de2 972 {
<> 154:37f96f9d4de2 973 handle->rxRingBufferHead = 0U;
<> 154:37f96f9d4de2 974 }
<> 154:37f96f9d4de2 975 else
<> 154:37f96f9d4de2 976 {
<> 154:37f96f9d4de2 977 handle->rxRingBufferHead++;
<> 154:37f96f9d4de2 978 }
<> 154:37f96f9d4de2 979 }
<> 154:37f96f9d4de2 980 }
<> 154:37f96f9d4de2 981 /* If no receive requst pending, stop RX interrupt. */
<> 154:37f96f9d4de2 982 else if (!handle->rxDataSize)
<> 154:37f96f9d4de2 983 {
<> 154:37f96f9d4de2 984 LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
<> 154:37f96f9d4de2 985 }
<> 154:37f96f9d4de2 986 else
<> 154:37f96f9d4de2 987 {
<> 154:37f96f9d4de2 988 }
<> 154:37f96f9d4de2 989 }
<> 154:37f96f9d4de2 990
<> 154:37f96f9d4de2 991 /* Send data register empty and the interrupt is enabled. */
<> 154:37f96f9d4de2 992 if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
<> 154:37f96f9d4de2 993 {
<> 154:37f96f9d4de2 994 /* Get the bytes that available at this moment. */
<> 154:37f96f9d4de2 995 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 996 count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
<> 154:37f96f9d4de2 997 ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
<> 154:37f96f9d4de2 998 #else
<> 154:37f96f9d4de2 999 count = 1;
<> 154:37f96f9d4de2 1000 #endif
<> 154:37f96f9d4de2 1001
<> 154:37f96f9d4de2 1002 while ((count) && (handle->txDataSize))
<> 154:37f96f9d4de2 1003 {
<> 154:37f96f9d4de2 1004 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 1005 tempCount = MIN(handle->txDataSize, count);
<> 154:37f96f9d4de2 1006 #else
<> 154:37f96f9d4de2 1007 tempCount = 1;
<> 154:37f96f9d4de2 1008 #endif
<> 154:37f96f9d4de2 1009
<> 154:37f96f9d4de2 1010 /* Using non block API to write the data to the registers. */
<> 154:37f96f9d4de2 1011 LPUART_WriteNonBlocking(base, handle->txData, tempCount);
<> 154:37f96f9d4de2 1012 handle->txData += tempCount;
<> 154:37f96f9d4de2 1013 handle->txDataSize -= tempCount;
<> 154:37f96f9d4de2 1014 count -= tempCount;
<> 154:37f96f9d4de2 1015
<> 154:37f96f9d4de2 1016 /* If all the data are written to data register, notify user with the callback, then TX finished. */
<> 154:37f96f9d4de2 1017 if (!handle->txDataSize)
<> 154:37f96f9d4de2 1018 {
<> 154:37f96f9d4de2 1019 handle->txState = kLPUART_TxIdle;
<> 154:37f96f9d4de2 1020
<> 154:37f96f9d4de2 1021 /* Disable TX register empty interrupt. */
<> 154:37f96f9d4de2 1022 base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
<> 154:37f96f9d4de2 1023
<> 154:37f96f9d4de2 1024 /* Trigger callback. */
<> 154:37f96f9d4de2 1025 if (handle->callback)
<> 154:37f96f9d4de2 1026 {
<> 154:37f96f9d4de2 1027 handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
<> 154:37f96f9d4de2 1028 }
<> 154:37f96f9d4de2 1029 }
<> 154:37f96f9d4de2 1030 }
<> 154:37f96f9d4de2 1031 }
<> 154:37f96f9d4de2 1032 }
<> 154:37f96f9d4de2 1033
<> 154:37f96f9d4de2 1034 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
<> 154:37f96f9d4de2 1035 {
<> 154:37f96f9d4de2 1036 /* TODO: To be implemented. */
<> 154:37f96f9d4de2 1037 }
<> 154:37f96f9d4de2 1038
<> 154:37f96f9d4de2 1039 #if defined(LPUART0)
<> 154:37f96f9d4de2 1040 void LPUART0_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1041 {
<> 154:37f96f9d4de2 1042 s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
<> 154:37f96f9d4de2 1043 }
<> 154:37f96f9d4de2 1044 void LPUART0_RX_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1045 {
<> 154:37f96f9d4de2 1046 LPUART0_DriverIRQHandler();
<> 154:37f96f9d4de2 1047 }
<> 154:37f96f9d4de2 1048 #endif
<> 154:37f96f9d4de2 1049
<> 154:37f96f9d4de2 1050 #if defined(LPUART1)
<> 154:37f96f9d4de2 1051 void LPUART1_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1052 {
<> 154:37f96f9d4de2 1053 s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
<> 154:37f96f9d4de2 1054 }
<> 154:37f96f9d4de2 1055 void LPUART1_RX_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1056 {
<> 154:37f96f9d4de2 1057 LPUART1_DriverIRQHandler();
<> 154:37f96f9d4de2 1058 }
<> 154:37f96f9d4de2 1059 #endif
<> 154:37f96f9d4de2 1060
<> 154:37f96f9d4de2 1061 #if defined(LPUART2)
<> 154:37f96f9d4de2 1062 void LPUART2_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1063 {
<> 154:37f96f9d4de2 1064 s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
<> 154:37f96f9d4de2 1065 }
<> 154:37f96f9d4de2 1066 void LPUART2_RX_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1067 {
<> 154:37f96f9d4de2 1068 LPUART2_DriverIRQHandler();
<> 154:37f96f9d4de2 1069 }
<> 154:37f96f9d4de2 1070 #endif
<> 154:37f96f9d4de2 1071
<> 154:37f96f9d4de2 1072 #if defined(LPUART3)
<> 154:37f96f9d4de2 1073 void LPUART3_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1074 {
<> 154:37f96f9d4de2 1075 s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
<> 154:37f96f9d4de2 1076 }
<> 154:37f96f9d4de2 1077 void LPUART3_RX_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1078 {
<> 154:37f96f9d4de2 1079 LPUART3_DriverIRQHandler();
<> 154:37f96f9d4de2 1080 }
<> 154:37f96f9d4de2 1081 #endif
<> 154:37f96f9d4de2 1082
<> 154:37f96f9d4de2 1083 #if defined(LPUART4)
<> 154:37f96f9d4de2 1084 void LPUART4_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1085 {
<> 154:37f96f9d4de2 1086 s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
<> 154:37f96f9d4de2 1087 }
<> 154:37f96f9d4de2 1088 void LPUART4_RX_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1089 {
<> 154:37f96f9d4de2 1090 LPUART4_DriverIRQHandler();
<> 154:37f96f9d4de2 1091 }
<> 154:37f96f9d4de2 1092 #endif
<> 154:37f96f9d4de2 1093
<> 154:37f96f9d4de2 1094 #if defined(LPUART5)
<> 154:37f96f9d4de2 1095 void LPUART5_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1096 {
<> 154:37f96f9d4de2 1097 s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
<> 154:37f96f9d4de2 1098 }
<> 154:37f96f9d4de2 1099 void LPUART5_RX_TX_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1100 {
<> 154:37f96f9d4de2 1101 LPUART5_DriverIRQHandler();
<> 154:37f96f9d4de2 1102 }
<> 154:37f96f9d4de2 1103 #endif