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targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c@163:74e0ce7f98e8, 2017-04-28 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 28 14:04:18 2017 +0100
Revision:
163:74e0ce7f98e8
Parent:
160:d5399cc887bb
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v141

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*
<> 149:156823d33999 2 * Copyright (c) 2013 Nordic Semiconductor ASA
<> 149:156823d33999 3 * All rights reserved.
<> 149:156823d33999 4 *
<> 149:156823d33999 5 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 6 * are permitted provided that the following conditions are met:
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * 1. Redistributions of source code must retain the above copyright notice, this list
<> 149:156823d33999 9 * of conditions and the following disclaimer.
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
<> 149:156823d33999 12 * integrated circuit in a product or a software update for such product, must reproduce
<> 149:156823d33999 13 * the above copyright notice, this list of conditions and the following disclaimer in
<> 149:156823d33999 14 * the documentation and/or other materials provided with the distribution.
<> 149:156823d33999 15 *
<> 149:156823d33999 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
<> 149:156823d33999 17 * used to endorse or promote products derived from this software without specific prior
<> 149:156823d33999 18 * written permission.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * 4. This software, with or without modification, must only be used with a
<> 149:156823d33999 21 * Nordic Semiconductor ASA integrated circuit.
<> 149:156823d33999 22 *
<> 149:156823d33999 23 * 5. Any software provided in binary or object form under this license must not be reverse
<> 149:156823d33999 24 * engineered, decompiled, modified and/or disassembled.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 149:156823d33999 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 149:156823d33999 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 149:156823d33999 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 149:156823d33999 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 149:156823d33999 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 149:156823d33999 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 149:156823d33999 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 149:156823d33999 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 36 *
<> 149:156823d33999 37 */
<> 149:156823d33999 38
<> 149:156823d33999 39 #include "us_ticker_api.h"
<> 149:156823d33999 40 #include "common_rtc.h"
<> 149:156823d33999 41 #include "app_util.h"
<> 149:156823d33999 42 #include "nrf_drv_common.h"
<> 150:02e0a0aed4ec 43 #include "nrf_drv_config.h"
<> 149:156823d33999 44 #include "lp_ticker_api.h"
Anna Bridge 163:74e0ce7f98e8 45 #include "mbed_critical.h"
<> 149:156823d33999 46
<> 149:156823d33999 47
<> 149:156823d33999 48 //------------------------------------------------------------------------------
<> 149:156823d33999 49 // Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h").
<> 149:156823d33999 50 //
<> 149:156823d33999 51 #include "app_util_platform.h"
<> 149:156823d33999 52
<> 149:156823d33999 53 bool m_common_rtc_enabled = false;
<> 149:156823d33999 54 uint32_t volatile m_common_rtc_overflows = 0;
<> 149:156823d33999 55
Anna Bridge 163:74e0ce7f98e8 56 __STATIC_INLINE void rtc_ovf_event_check(void)
Anna Bridge 163:74e0ce7f98e8 57 {
Anna Bridge 163:74e0ce7f98e8 58 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
Anna Bridge 163:74e0ce7f98e8 59 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
Anna Bridge 163:74e0ce7f98e8 60 // Don't disable this event. It shall occur periodically.
Anna Bridge 163:74e0ce7f98e8 61
Anna Bridge 163:74e0ce7f98e8 62 ++m_common_rtc_overflows;
Anna Bridge 163:74e0ce7f98e8 63 }
Anna Bridge 163:74e0ce7f98e8 64 }
Anna Bridge 163:74e0ce7f98e8 65
<> 149:156823d33999 66 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 67 void common_rtc_irq_handler(void)
<> 149:156823d33999 68 #else
<> 149:156823d33999 69 void COMMON_RTC_IRQ_HANDLER(void)
<> 149:156823d33999 70 #endif
<> 149:156823d33999 71 {
Anna Bridge 163:74e0ce7f98e8 72
Anna Bridge 163:74e0ce7f98e8 73 rtc_ovf_event_check();
Anna Bridge 163:74e0ce7f98e8 74
<> 149:156823d33999 75 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
<> 149:156823d33999 76 us_ticker_irq_handler();
<> 149:156823d33999 77 }
<> 149:156823d33999 78
<> 149:156823d33999 79 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 80 if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) {
<> 149:156823d33999 81
<> 149:156823d33999 82 lp_ticker_irq_handler();
<> 149:156823d33999 83 }
<> 149:156823d33999 84 #endif
<> 149:156823d33999 85
<> 149:156823d33999 86 }
<> 149:156823d33999 87
<> 150:02e0a0aed4ec 88 #if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR
<> 150:02e0a0aed4ec 89 __stackless __task
<> 150:02e0a0aed4ec 90 #endif
<> 150:02e0a0aed4ec 91 void RTC1_IRQHandler(void);
<> 150:02e0a0aed4ec 92
<> 149:156823d33999 93 void common_rtc_init(void)
<> 149:156823d33999 94 {
<> 149:156823d33999 95 if (m_common_rtc_enabled) {
<> 149:156823d33999 96 return;
<> 149:156823d33999 97 }
<> 149:156823d33999 98
<> 150:02e0a0aed4ec 99 NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler);
<> 150:02e0a0aed4ec 100
<> 149:156823d33999 101 // RTC is driven by the low frequency (32.768 kHz) clock, a proper request
<> 149:156823d33999 102 // must be made to have it running.
<> 149:156823d33999 103 // Currently this clock is started in 'SystemInit' (see "system_nrf51.c"
<> 149:156823d33999 104 // or "system_nrf52.c", respectively).
<> 149:156823d33999 105
<> 149:156823d33999 106 nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0);
<> 149:156823d33999 107
<> 149:156823d33999 108 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
<> 149:156823d33999 109 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 110 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
<> 149:156823d33999 111 #endif
<> 149:156823d33999 112 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 113 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT);
<> 149:156823d33999 114 #endif
<> 149:156823d33999 115 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
<> 149:156823d33999 116
<> 149:156823d33999 117 // Interrupts on all related events are enabled permanently. Particular
<> 149:156823d33999 118 // events will be enabled or disabled as needed (such approach is more
<> 149:156823d33999 119 // energy efficient).
<> 149:156823d33999 120 nrf_rtc_int_enable(COMMON_RTC_INSTANCE,
<> 149:156823d33999 121 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 122 LP_TICKER_INT_MASK |
<> 149:156823d33999 123 #endif
<> 149:156823d33999 124 US_TICKER_INT_MASK |
<> 149:156823d33999 125 NRF_RTC_INT_OVERFLOW_MASK);
<> 149:156823d33999 126
<> 149:156823d33999 127 // This event is enabled permanently, since overflow indications are needed
<> 149:156823d33999 128 // continuously.
<> 149:156823d33999 129 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK);
<> 149:156823d33999 130 // All other relevant events are initially disabled.
<> 149:156823d33999 131 nrf_rtc_event_disable(COMMON_RTC_INSTANCE,
<> 149:156823d33999 132 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 133 OS_TICK_INT_MASK |
<> 149:156823d33999 134 #endif
<> 149:156823d33999 135 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 136 LP_TICKER_INT_MASK |
<> 149:156823d33999 137 #endif
<> 149:156823d33999 138 US_TICKER_INT_MASK);
<> 149:156823d33999 139
<> 149:156823d33999 140 nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE),
<> 150:02e0a0aed4ec 141 #ifdef NRF51
<> 150:02e0a0aed4ec 142 APP_IRQ_PRIORITY_LOW
<> 150:02e0a0aed4ec 143 #elif defined(NRF52)
<> 150:02e0a0aed4ec 144 APP_IRQ_PRIORITY_LOWEST
<> 150:02e0a0aed4ec 145 #endif
<> 150:02e0a0aed4ec 146 );
<> 149:156823d33999 147
<> 149:156823d33999 148 nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START);
<> 149:156823d33999 149
<> 149:156823d33999 150 m_common_rtc_enabled = true;
<> 149:156823d33999 151 }
<> 149:156823d33999 152
Anna Bridge 163:74e0ce7f98e8 153 __STATIC_INLINE void rtc_ovf_event_safe_check(void)
Anna Bridge 163:74e0ce7f98e8 154 {
Anna Bridge 163:74e0ce7f98e8 155 core_util_critical_section_enter();
Anna Bridge 163:74e0ce7f98e8 156
Anna Bridge 163:74e0ce7f98e8 157 rtc_ovf_event_check();
Anna Bridge 163:74e0ce7f98e8 158
Anna Bridge 163:74e0ce7f98e8 159 core_util_critical_section_exit();
Anna Bridge 163:74e0ce7f98e8 160 }
Anna Bridge 163:74e0ce7f98e8 161
Anna Bridge 163:74e0ce7f98e8 162
<> 149:156823d33999 163 uint32_t common_rtc_32bit_ticks_get(void)
<> 149:156823d33999 164 {
Anna Bridge 163:74e0ce7f98e8 165 uint32_t ticks;
Anna Bridge 163:74e0ce7f98e8 166 uint32_t prev_overflows;
Anna Bridge 163:74e0ce7f98e8 167
Anna Bridge 163:74e0ce7f98e8 168 do {
Anna Bridge 163:74e0ce7f98e8 169 prev_overflows = m_common_rtc_overflows;
Anna Bridge 163:74e0ce7f98e8 170
Anna Bridge 163:74e0ce7f98e8 171 ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
Anna Bridge 163:74e0ce7f98e8 172 // The counter used for time measurements is less than 32 bit wide,
Anna Bridge 163:74e0ce7f98e8 173 // so its value is complemented with the number of registered overflows
Anna Bridge 163:74e0ce7f98e8 174 // of the counter.
Anna Bridge 163:74e0ce7f98e8 175 ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
Anna Bridge 163:74e0ce7f98e8 176
Anna Bridge 163:74e0ce7f98e8 177 // Check in case that OVF occurred during execution of a RTC handler (apply if call was from RTC handler)
Anna Bridge 163:74e0ce7f98e8 178 // m_common_rtc_overflows might been updated in this call.
Anna Bridge 163:74e0ce7f98e8 179 rtc_ovf_event_safe_check();
Anna Bridge 163:74e0ce7f98e8 180
Anna Bridge 163:74e0ce7f98e8 181 // If call was made from a low priority level m_common_rtc_overflows might have been updated in RTC handler.
Anna Bridge 163:74e0ce7f98e8 182 } while (m_common_rtc_overflows != prev_overflows);
Anna Bridge 163:74e0ce7f98e8 183
<> 149:156823d33999 184 return ticks;
<> 149:156823d33999 185 }
<> 149:156823d33999 186
<> 149:156823d33999 187 uint64_t common_rtc_64bit_us_get(void)
<> 149:156823d33999 188 {
<> 149:156823d33999 189 uint32_t ticks = common_rtc_32bit_ticks_get();
<> 149:156823d33999 190 // [ticks -> microseconds]
<> 149:156823d33999 191 return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ);
<> 149:156823d33999 192 }
<> 149:156823d33999 193
<> 149:156823d33999 194 void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
<> 149:156823d33999 195 uint32_t int_mask)
<> 149:156823d33999 196 {
<> 149:156823d33999 197 // The internal counter is clocked with a frequency that cannot be easily
<> 149:156823d33999 198 // multiplied to 1 MHz, therefore besides the translation of values
<> 149:156823d33999 199 // (microsecond <-> ticks) a special care of overflows handling must be
<> 149:156823d33999 200 // taken. Here the 32-bit timestamp value is complemented with information
<> 149:156823d33999 201 // about current the system up time of (ticks + number of overflows of tick
<> 149:156823d33999 202 // counter on upper bits, converted to microseconds), and such 64-bit value
<> 149:156823d33999 203 // is then translated to counter ticks. Finally, the lower 24 bits of thus
<> 149:156823d33999 204 // calculated value is written to the counter compare register to prepare
<> 149:156823d33999 205 // the interrupt generation.
<> 149:156823d33999 206 uint64_t current_time64 = common_rtc_64bit_us_get();
<> 149:156823d33999 207 // [add upper 32 bits from the current time to the timestamp value]
<> 149:156823d33999 208 uint64_t timestamp64 = us_timestamp +
<> 149:156823d33999 209 (current_time64 & ~(uint64_t)0xFFFFFFFF);
<> 149:156823d33999 210 // [if the original timestamp value happens to be after the 32 bit counter
<> 149:156823d33999 211 // of microsends overflows, correct the upper 32 bits accordingly]
<> 149:156823d33999 212 if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) {
<> 149:156823d33999 213 timestamp64 += ((uint64_t)1 << 32);
<> 149:156823d33999 214 }
<> 149:156823d33999 215 // [microseconds -> ticks, always round the result up to avoid too early
<> 149:156823d33999 216 // interrupt generation]
<> 149:156823d33999 217 uint32_t compare_value =
<> 149:156823d33999 218 (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000);
<> 149:156823d33999 219
Anna Bridge 163:74e0ce7f98e8 220
Anna Bridge 163:74e0ce7f98e8 221 core_util_critical_section_enter();
<> 149:156823d33999 222 // The COMPARE event occurs when the value in compare register is N and
<> 149:156823d33999 223 // the counter value changes from N-1 to N. Therefore, the minimal safe
<> 149:156823d33999 224 // difference between the compare value to be set and the current counter
<> 149:156823d33999 225 // value is 2 ticks. This guarantees that the compare trigger is properly
<> 149:156823d33999 226 // setup before the compare condition occurs.
<> 149:156823d33999 227 uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
<> 149:156823d33999 228 if ((int)(compare_value - closest_safe_compare) <= 0) {
<> 149:156823d33999 229 compare_value = closest_safe_compare;
<> 149:156823d33999 230 }
<> 149:156823d33999 231
<> 149:156823d33999 232 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value));
<> 149:156823d33999 233 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask);
Anna Bridge 163:74e0ce7f98e8 234
Anna Bridge 163:74e0ce7f98e8 235 core_util_critical_section_exit();
<> 149:156823d33999 236 }
<> 149:156823d33999 237 //------------------------------------------------------------------------------
<> 149:156823d33999 238
<> 149:156823d33999 239
<> 149:156823d33999 240 void us_ticker_init(void)
<> 149:156823d33999 241 {
<> 149:156823d33999 242 common_rtc_init();
<> 149:156823d33999 243 }
<> 149:156823d33999 244
<> 149:156823d33999 245 uint32_t us_ticker_read()
<> 149:156823d33999 246 {
<> 149:156823d33999 247 us_ticker_init();
<> 149:156823d33999 248 return (uint32_t)common_rtc_64bit_us_get();
<> 149:156823d33999 249 }
<> 149:156823d33999 250
<> 149:156823d33999 251 void us_ticker_set_interrupt(timestamp_t timestamp)
<> 149:156823d33999 252 {
<> 149:156823d33999 253 common_rtc_set_interrupt(timestamp,
<> 149:156823d33999 254 US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK);
<> 149:156823d33999 255 }
<> 149:156823d33999 256
<> 149:156823d33999 257 void us_ticker_disable_interrupt(void)
<> 149:156823d33999 258 {
<> 149:156823d33999 259 nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
<> 149:156823d33999 260 }
<> 149:156823d33999 261
<> 149:156823d33999 262 void us_ticker_clear_interrupt(void)
<> 149:156823d33999 263 {
<> 149:156823d33999 264 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
<> 149:156823d33999 265 }
<> 149:156823d33999 266
<> 149:156823d33999 267
<> 149:156823d33999 268 // Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an
<> 149:156823d33999 269 // alternative source of RTOS ticks.
<> 149:156823d33999 270 #if defined(TARGET_MCU_NRF51822)
<> 149:156823d33999 271
<> 160:d5399cc887bb 272 #include "mbed_toolchain.h"
<> 149:156823d33999 273
<> 149:156823d33999 274
<> 149:156823d33999 275 #define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1)
<> 149:156823d33999 276
<> 149:156823d33999 277 /**
<> 149:156823d33999 278 * The value previously set in the capture compare register of channel 1
<> 149:156823d33999 279 */
<> 149:156823d33999 280 static uint32_t previous_tick_cc_value = 0;
<> 149:156823d33999 281
<> 149:156823d33999 282 /*
<> 149:156823d33999 283 RTX provide the following definitions which are used by the tick code:
<> 149:156823d33999 284 * os_trv: The number (minus 1) of clock cycle between two tick.
<> 149:156823d33999 285 * os_clockrate: Time duration between two ticks (in us).
<> 149:156823d33999 286 * OS_Tick_Handler: The function which handle a tick event.
<> 149:156823d33999 287 This function is special because it never returns.
<> 149:156823d33999 288 Those definitions are used by the code which handle the os tick.
<> 149:156823d33999 289 To allow compilation of us_ticker programs without RTOS, those symbols are
<> 149:156823d33999 290 exported from this module as weak ones.
<> 149:156823d33999 291 */
<> 149:156823d33999 292 MBED_WEAK uint32_t const os_trv;
<> 149:156823d33999 293 MBED_WEAK uint32_t const os_clockrate;
<> 149:156823d33999 294 MBED_WEAK void OS_Tick_Handler() { }
<> 149:156823d33999 295
<> 149:156823d33999 296
<> 149:156823d33999 297 #if defined (__CC_ARM) /* ARMCC Compiler */
<> 149:156823d33999 298
<> 149:156823d33999 299 __asm void COMMON_RTC_IRQ_HANDLER(void)
<> 149:156823d33999 300 {
<> 149:156823d33999 301 IMPORT OS_Tick_Handler
<> 149:156823d33999 302 IMPORT common_rtc_irq_handler
<> 149:156823d33999 303
<> 149:156823d33999 304 /**
<> 149:156823d33999 305 * Chanel 1 of RTC1 is used by RTX as a systick.
<> 149:156823d33999 306 * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
<> 149:156823d33999 307 * Otherwise, just execute common_rtc_irq_handler.
<> 149:156823d33999 308 * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
<> 149:156823d33999 309 * will never return.
<> 149:156823d33999 310 * A c function would put lr on the stack before calling OS_Tick_Handler and this value
<> 149:156823d33999 311 * would never been dequeued.
<> 149:156823d33999 312 *
<> 149:156823d33999 313 * \code
<> 149:156823d33999 314 * void COMMON_RTC_IRQ_HANDLER(void) {
<> 149:156823d33999 315 if(NRF_RTC1->EVENTS_COMPARE[1]) {
<> 149:156823d33999 316 // never return...
<> 149:156823d33999 317 OS_Tick_Handler();
<> 149:156823d33999 318 } else {
<> 149:156823d33999 319 common_rtc_irq_handler();
<> 149:156823d33999 320 }
<> 149:156823d33999 321 }
<> 149:156823d33999 322 * \endcode
<> 149:156823d33999 323 */
<> 149:156823d33999 324 ldr r0,=0x40011144
<> 149:156823d33999 325 ldr r1, [r0, #0]
<> 149:156823d33999 326 cmp r1, #0
<> 149:156823d33999 327 beq US_TICKER_HANDLER
<> 149:156823d33999 328 bl OS_Tick_Handler
<> 149:156823d33999 329 US_TICKER_HANDLER
<> 149:156823d33999 330 push {r3, lr}
<> 149:156823d33999 331 bl common_rtc_irq_handler
<> 149:156823d33999 332 pop {r3, pc}
<> 149:156823d33999 333 ; ALIGN ;
<> 149:156823d33999 334 }
<> 149:156823d33999 335
<> 149:156823d33999 336 #elif defined (__GNUC__) /* GNU Compiler */
<> 149:156823d33999 337
<> 149:156823d33999 338 __attribute__((naked)) void COMMON_RTC_IRQ_HANDLER(void)
<> 149:156823d33999 339 {
<> 149:156823d33999 340 /**
<> 149:156823d33999 341 * Chanel 1 of RTC1 is used by RTX as a systick.
<> 149:156823d33999 342 * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
<> 149:156823d33999 343 * Otherwise, just execute common_rtc_irq_handler.
<> 149:156823d33999 344 * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
<> 149:156823d33999 345 * will never return.
<> 149:156823d33999 346 * A c function would put lr on the stack before calling OS_Tick_Handler and this value
<> 149:156823d33999 347 * would never been dequeued.
<> 149:156823d33999 348 *
<> 149:156823d33999 349 * \code
<> 149:156823d33999 350 * void COMMON_RTC_IRQ_HANDLER(void) {
<> 149:156823d33999 351 if(NRF_RTC1->EVENTS_COMPARE[1]) {
<> 149:156823d33999 352 // never return...
<> 149:156823d33999 353 OS_Tick_Handler();
<> 149:156823d33999 354 } else {
<> 149:156823d33999 355 common_rtc_irq_handler();
<> 149:156823d33999 356 }
<> 149:156823d33999 357 }
<> 149:156823d33999 358 * \endcode
<> 149:156823d33999 359 */
<> 149:156823d33999 360 __asm__ (
<> 149:156823d33999 361 "ldr r0,=0x40011144\n"
<> 149:156823d33999 362 "ldr r1, [r0, #0]\n"
<> 149:156823d33999 363 "cmp r1, #0\n"
<> 149:156823d33999 364 "beq US_TICKER_HANDLER\n"
<> 149:156823d33999 365 "bl OS_Tick_Handler\n"
<> 149:156823d33999 366 "US_TICKER_HANDLER:\n"
<> 149:156823d33999 367 "push {r3, lr}\n"
<> 149:156823d33999 368 "bl common_rtc_irq_handler\n"
<> 149:156823d33999 369 "pop {r3, pc}\n"
<> 149:156823d33999 370 "nop"
<> 149:156823d33999 371 );
<> 149:156823d33999 372 }
<> 149:156823d33999 373
<> 149:156823d33999 374 #elif defined (__ICCARM__)//IAR
<> 149:156823d33999 375 void common_rtc_irq_handler(void);
<> 149:156823d33999 376
<> 149:156823d33999 377 __stackless __task void COMMON_RTC_IRQ_HANDLER(void)
<> 149:156823d33999 378 {
<> 149:156823d33999 379 uint32_t temp;
<> 149:156823d33999 380
<> 149:156823d33999 381 __asm volatile(
<> 149:156823d33999 382 " ldr %[temp], [%[reg2check]] \n"
<> 149:156823d33999 383 " cmp %[temp], #0 \n"
<> 149:156823d33999 384 " beq 1f \n"
<> 149:156823d33999 385 " bl.w OS_Tick_Handler \n"
<> 149:156823d33999 386 "1: \n"
<> 149:156823d33999 387 " push {r3, lr}\n"
<> 149:156823d33999 388 " blx %[rtc_irq] \n"
<> 149:156823d33999 389 " pop {r3, pc}\n"
<> 149:156823d33999 390
<> 149:156823d33999 391 : /* Outputs */
<> 149:156823d33999 392 [temp] "=&r"(temp)
<> 149:156823d33999 393 : /* Inputs */
<> 149:156823d33999 394 [reg2check] "r"(0x40011144),
<> 149:156823d33999 395 [rtc_irq] "r"(common_rtc_irq_handler)
<> 149:156823d33999 396 : /* Clobbers */
<> 149:156823d33999 397 "cc"
<> 149:156823d33999 398 );
<> 149:156823d33999 399 (void)temp;
<> 149:156823d33999 400 }
<> 149:156823d33999 401
<> 149:156823d33999 402
<> 149:156823d33999 403 #else
<> 149:156823d33999 404
<> 149:156823d33999 405 #error Compiler not supported.
<> 149:156823d33999 406 #error Provide a definition of COMMON_RTC_IRQ_HANDLER.
<> 149:156823d33999 407
<> 149:156823d33999 408 /*
<> 149:156823d33999 409 * Chanel 1 of RTC1 is used by RTX as a systick.
<> 149:156823d33999 410 * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
<> 149:156823d33999 411 * Otherwise, just execute common_rtc_irq_handler.
<> 149:156823d33999 412 * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
<> 149:156823d33999 413 * will never return.
<> 149:156823d33999 414 * A c function would put lr on the stack before calling OS_Tick_Handler and this value
<> 149:156823d33999 415 * will never been dequeued. After a certain time a stack overflow will happen.
<> 149:156823d33999 416 *
<> 149:156823d33999 417 * \code
<> 149:156823d33999 418 * void COMMON_RTC_IRQ_HANDLER(void) {
<> 149:156823d33999 419 if(NRF_RTC1->EVENTS_COMPARE[1]) {
<> 149:156823d33999 420 // never return...
<> 149:156823d33999 421 OS_Tick_Handler();
<> 149:156823d33999 422 } else {
<> 149:156823d33999 423 common_rtc_irq_handler();
<> 149:156823d33999 424 }
<> 149:156823d33999 425 }
<> 149:156823d33999 426 * \endcode
<> 149:156823d33999 427 */
<> 149:156823d33999 428
<> 149:156823d33999 429 #endif
<> 149:156823d33999 430
<> 149:156823d33999 431 /**
<> 149:156823d33999 432 * Return the next number of clock cycle needed for the next tick.
<> 149:156823d33999 433 * @note This function has been carrefuly optimized for a systick occuring every 1000us.
<> 149:156823d33999 434 */
<> 149:156823d33999 435 static uint32_t get_next_tick_cc_delta() {
<> 149:156823d33999 436 uint32_t delta = 0;
<> 149:156823d33999 437
<> 149:156823d33999 438 if (os_clockrate != 1000) {
<> 149:156823d33999 439 // In RTX, by default SYSTICK is is used.
<> 149:156823d33999 440 // A tick event is generated every os_trv + 1 clock cycles of the system timer.
<> 149:156823d33999 441 delta = os_trv + 1;
<> 149:156823d33999 442 } else {
<> 149:156823d33999 443 // If the clockrate is set to 1000us then 1000 tick should happen every second.
<> 149:156823d33999 444 // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
<> 149:156823d33999 445 // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
<> 149:156823d33999 446 // generated in 32000 clock cycle instead of 32768 clock cycles.
<> 149:156823d33999 447 // As a result, if a user schedule an OS timer to start in 100s, the timer will start
<> 149:156823d33999 448 // instead after 97.656s
<> 149:156823d33999 449 // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
<> 149:156823d33999 450 // clock cycles.
<> 149:156823d33999 451 // The strategy is simple, for 1000 ticks:
<> 149:156823d33999 452 // * 768 ticks will occur 33 clock cycles after the previous tick
<> 149:156823d33999 453 // * 232 ticks will occur 32 clock cycles after the previous tick
<> 149:156823d33999 454 // By default every delta is equal to 33.
<> 149:156823d33999 455 // Every five ticks (20%, 200 delta in one second), the delta is equal to 32
<> 149:156823d33999 456 // The remaining (32) deltas equal to 32 are distributed using primes numbers.
<> 149:156823d33999 457 static uint32_t counter = 0;
<> 149:156823d33999 458 if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
<> 149:156823d33999 459 delta = 32;
<> 149:156823d33999 460 } else {
<> 149:156823d33999 461 delta = 33;
<> 149:156823d33999 462 }
<> 149:156823d33999 463 ++counter;
<> 149:156823d33999 464 if (counter == 1000) {
<> 149:156823d33999 465 counter = 0;
<> 149:156823d33999 466 }
<> 149:156823d33999 467 }
<> 149:156823d33999 468 return delta;
<> 149:156823d33999 469 }
<> 149:156823d33999 470
<> 149:156823d33999 471 static inline void clear_tick_interrupt() {
<> 149:156823d33999 472 nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
<> 149:156823d33999 473 nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 149:156823d33999 474 }
<> 149:156823d33999 475
<> 149:156823d33999 476 /**
<> 149:156823d33999 477 * Indicate if a value is included in a range which can be wrapped.
<> 149:156823d33999 478 * @param begin start of the range
<> 149:156823d33999 479 * @param end end of the range
<> 149:156823d33999 480 * @param val value to check
<> 149:156823d33999 481 * @return true if the value is included in the range and false otherwise.
<> 149:156823d33999 482 */
<> 149:156823d33999 483 static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) {
<> 149:156823d33999 484 // regular case, begin < end
<> 149:156823d33999 485 // return true if begin <= val < end
<> 149:156823d33999 486 if (begin < end) {
<> 149:156823d33999 487 if (begin <= val && val < end) {
<> 149:156823d33999 488 return true;
<> 149:156823d33999 489 } else {
<> 149:156823d33999 490 return false;
<> 149:156823d33999 491 }
<> 149:156823d33999 492 } else {
<> 149:156823d33999 493 // In this case end < begin because it has wrap around the limits
<> 149:156823d33999 494 // return false if end < val < begin
<> 149:156823d33999 495 if (end < val && val < begin) {
<> 149:156823d33999 496 return false;
<> 149:156823d33999 497 } else {
<> 149:156823d33999 498 return true;
<> 149:156823d33999 499 }
<> 149:156823d33999 500 }
<> 149:156823d33999 501
<> 149:156823d33999 502 }
<> 149:156823d33999 503
<> 149:156823d33999 504 /**
<> 149:156823d33999 505 * Register the next tick.
<> 149:156823d33999 506 */
<> 149:156823d33999 507 static void register_next_tick() {
<> 149:156823d33999 508 previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
<> 149:156823d33999 509 uint32_t delta = get_next_tick_cc_delta();
<> 149:156823d33999 510 uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
<> 149:156823d33999 511
<> 149:156823d33999 512 // Disable irq directly for few cycles,
<> 149:156823d33999 513 // Validation of the new CC value against the COUNTER,
<> 149:156823d33999 514 // Setting the new CC value and enabling CC IRQ should be an atomic operation
<> 149:156823d33999 515 // Otherwise, there is a possibility to set an invalid CC value because
<> 149:156823d33999 516 // the RTC1 keeps running.
<> 149:156823d33999 517 // This code is very short 20-38 cycles in the worst case, it shouldn't
<> 149:156823d33999 518 // disturb softdevice.
<> 149:156823d33999 519 __disable_irq();
<> 149:156823d33999 520 uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
<> 149:156823d33999 521
<> 149:156823d33999 522 // If an overflow occur, set the next tick in COUNTER + delta clock cycles
<> 149:156823d33999 523 if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) {
<> 149:156823d33999 524 new_compare_value = current_counter + delta;
<> 149:156823d33999 525 }
<> 149:156823d33999 526 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
<> 149:156823d33999 527 // Enable generation of the compare event for the value set above (this
<> 149:156823d33999 528 // event will trigger the interrupt).
<> 149:156823d33999 529 nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 149:156823d33999 530 __enable_irq();
<> 149:156823d33999 531 }
<> 149:156823d33999 532
<> 149:156823d33999 533 /**
<> 149:156823d33999 534 * Initialize alternative hardware timer as RTX kernel timer
<> 149:156823d33999 535 * This function is directly called by RTX.
<> 149:156823d33999 536 * @note this function shouldn't be called directly.
<> 149:156823d33999 537 * @return IRQ number of the alternative hardware timer
<> 149:156823d33999 538 */
<> 149:156823d33999 539 int os_tick_init (void)
<> 149:156823d33999 540 {
<> 149:156823d33999 541 common_rtc_init();
<> 151:5eaa88a5bcc7 542 nrf_rtc_int_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
<> 149:156823d33999 543
<> 149:156823d33999 544 nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, 0);
<> 149:156823d33999 545 register_next_tick();
<> 149:156823d33999 546
<> 149:156823d33999 547 return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE);
<> 149:156823d33999 548 }
<> 149:156823d33999 549
<> 149:156823d33999 550 /**
<> 149:156823d33999 551 * Acknowledge the tick interrupt.
<> 149:156823d33999 552 * This function is called by the function OS_Tick_Handler of RTX.
<> 149:156823d33999 553 * @note this function shouldn't be called directly.
<> 149:156823d33999 554 */
<> 149:156823d33999 555 void os_tick_irqack(void)
<> 149:156823d33999 556 {
<> 149:156823d33999 557 clear_tick_interrupt();
<> 149:156823d33999 558 register_next_tick();
<> 149:156823d33999 559 }
<> 149:156823d33999 560
<> 149:156823d33999 561 /**
<> 149:156823d33999 562 * Returns the overflow flag of the alternative hardware timer.
<> 149:156823d33999 563 * @note This function is exposed by RTX kernel.
<> 149:156823d33999 564 * @return 1 if the timer has overflowed and 0 otherwise.
<> 149:156823d33999 565 */
<> 149:156823d33999 566 uint32_t os_tick_ovf(void) {
<> 149:156823d33999 567 uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
<> 149:156823d33999 568 uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
<> 149:156823d33999 569
<> 149:156823d33999 570 return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
<> 149:156823d33999 571 }
<> 149:156823d33999 572
<> 149:156823d33999 573 /**
<> 149:156823d33999 574 * Return the value of the alternative hardware timer.
<> 149:156823d33999 575 * @note The documentation is not very clear about what is expected as a result,
<> 149:156823d33999 576 * is it an ascending counter, a descending one ?
<> 149:156823d33999 577 * None of this is specified.
<> 149:156823d33999 578 * The default systick is a descending counter and this function return values in
<> 149:156823d33999 579 * descending order, even if the internal counter used is an ascending one.
<> 149:156823d33999 580 * @return the value of the alternative hardware timer.
<> 149:156823d33999 581 */
<> 149:156823d33999 582 uint32_t os_tick_val(void) {
<> 149:156823d33999 583 uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
<> 149:156823d33999 584 uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
<> 149:156823d33999 585
<> 149:156823d33999 586 // do not use os_tick_ovf because its counter value can be different
<> 149:156823d33999 587 if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
<> 149:156823d33999 588 if (next_tick_cc_value > previous_tick_cc_value) {
<> 149:156823d33999 589 return next_tick_cc_value - current_counter;
<> 149:156823d33999 590 } else if(current_counter <= next_tick_cc_value) {
<> 149:156823d33999 591 return next_tick_cc_value - current_counter;
<> 149:156823d33999 592 } else {
<> 149:156823d33999 593 return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
<> 149:156823d33999 594 }
<> 149:156823d33999 595 } else {
<> 149:156823d33999 596 // use (os_trv + 1) has the base step, can be totally inacurate ...
<> 149:156823d33999 597 uint32_t clock_cycles_by_tick = os_trv + 1;
<> 149:156823d33999 598
<> 149:156823d33999 599 // if current counter has wrap arround, add the limit to it.
<> 149:156823d33999 600 if (current_counter < next_tick_cc_value) {
<> 149:156823d33999 601 current_counter = current_counter + MAX_RTC_COUNTER_VAL;
<> 149:156823d33999 602 }
<> 149:156823d33999 603
<> 149:156823d33999 604 return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick);
<> 149:156823d33999 605 }
<> 149:156823d33999 606
<> 149:156823d33999 607 }
<> 149:156823d33999 608
<> 149:156823d33999 609 #endif // defined(TARGET_MCU_NRF51822)