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targets/TARGET_ONSEMI/TARGET_NCS36510/test_map.h@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
149:156823d33999 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file test_map.h
<> 144:ef7eb2e8f9f7 4 * @brief Test hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2848 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup test
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #ifndef TEST_MAP_H_
<> 144:ef7eb2e8f9f7 33 #define TEST_MAP_H_
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 36 * *
<> 144:ef7eb2e8f9f7 37 * Header files *
<> 144:ef7eb2e8f9f7 38 * *
<> 144:ef7eb2e8f9f7 39 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include "architecture.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 44 * *
<> 144:ef7eb2e8f9f7 45 * Type definitions *
<> 144:ef7eb2e8f9f7 46 * *
<> 144:ef7eb2e8f9f7 47 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** General test registers
<> 144:ef7eb2e8f9f7 50 *
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef struct {
<> 144:ef7eb2e8f9f7 53 __IO uint32_t UNLOCK;
<> 144:ef7eb2e8f9f7 54 __IO uint32_t ANA_TEST_MUX;
<> 144:ef7eb2e8f9f7 55 __IO uint32_t OVD_ENA_MODE;
<> 144:ef7eb2e8f9f7 56 __IO uint32_t OVD_VAL;
<> 144:ef7eb2e8f9f7 57 __IO uint32_t ANA_TEST_MODE;
<> 144:ef7eb2e8f9f7 58 __IO uint32_t CLK_TEST_MODE;
<> 144:ef7eb2e8f9f7 59 union {
<> 144:ef7eb2e8f9f7 60 struct {
<> 144:ef7eb2e8f9f7 61 __IO uint32_t PAD0:1;
<> 144:ef7eb2e8f9f7 62 __IO uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 63 __IO uint32_t FORCE_SOURCE:1;
<> 144:ef7eb2e8f9f7 64 __IO uint32_t FORCE_SINK:1;
<> 144:ef7eb2e8f9f7 65 __IO uint32_t PD_CONTROL:3;
<> 144:ef7eb2e8f9f7 66 __IO uint32_t PAD3:1;
<> 144:ef7eb2e8f9f7 67 __IO uint32_t BYPASS_PLL_REG:1;
<> 144:ef7eb2e8f9f7 68 __IO uint32_t PAD4:4;
<> 144:ef7eb2e8f9f7 69 __IO uint32_t DITHER_MODE:1;
<> 144:ef7eb2e8f9f7 70 __IO uint32_t PLL_MODE:1;
<> 144:ef7eb2e8f9f7 71 __IO uint32_t FORCE_LOCK:1;
<> 144:ef7eb2e8f9f7 72 } BITS;
<> 144:ef7eb2e8f9f7 73 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 74 } PLL_TEST_MODE;
<> 144:ef7eb2e8f9f7 75 __IO uint32_t RX_TEST_MODE;
<> 144:ef7eb2e8f9f7 76 __IO uint32_t PMU_TEST_MODE;
<> 144:ef7eb2e8f9f7 77 } TestReg_t, *TestReg_pt;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** Digital test registers
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 typedef struct {
<> 144:ef7eb2e8f9f7 83 union {
<> 144:ef7eb2e8f9f7 84 struct {
<> 144:ef7eb2e8f9f7 85 __IO uint32_t PAD0 :4; /**< */
<> 144:ef7eb2e8f9f7 86 __IO uint32_t DIO4 :4; /**< DIO4 Test Mux Control */
<> 144:ef7eb2e8f9f7 87 __IO uint32_t DIO5 :4; /**< DIO5 Test Mux Control */
<> 144:ef7eb2e8f9f7 88 __IO uint32_t DIO6 :4; /**< DIO6 Test Mux Control */
<> 144:ef7eb2e8f9f7 89 __IO uint32_t DIO7 :4; /**< DIO7 Test Mux Control */
<> 144:ef7eb2e8f9f7 90 __IO uint32_t DIO8 :4; /**< DIO8 Test Mux Control */
<> 144:ef7eb2e8f9f7 91 __IO uint32_t DIO9 :4; /**< DIO9 Test Mux Control */
<> 144:ef7eb2e8f9f7 92 __IO uint32_t DIO10 :4; /**< DIO10 Test Mux Control */
<> 144:ef7eb2e8f9f7 93 } BITS;
<> 144:ef7eb2e8f9f7 94 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 95 } DIG_TEST_MUX;
<> 144:ef7eb2e8f9f7 96 __IO uint32_t DIG_TEST_MODE;
<> 144:ef7eb2e8f9f7 97 union {
<> 144:ef7eb2e8f9f7 98 struct {
<> 144:ef7eb2e8f9f7 99 __IO uint32_t PAD0 :12; /**< */
<> 144:ef7eb2e8f9f7 100 __IO uint32_t DIO5 :3; /**< DIO5 Input Test Mux Control */
<> 144:ef7eb2e8f9f7 101 __IO uint32_t DIO6 :3; /**< DIO6 Input Test Mux Control */
<> 144:ef7eb2e8f9f7 102 __IO uint32_t DIO7 :3; /**< DIO7 Input Test Mux Control */
<> 144:ef7eb2e8f9f7 103 __IO uint32_t DIO8 :3; /**< DIO8 Input Test Mux Control */
<> 144:ef7eb2e8f9f7 104 __IO uint32_t DIO9 :3; /**< DIO9 Input Test Mux Control */
<> 144:ef7eb2e8f9f7 105 __IO uint32_t DIO10 :3; /**< DIO10 Input Test Mux Control */
<> 144:ef7eb2e8f9f7 106 } BITS;
<> 144:ef7eb2e8f9f7 107 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 108 } DIG_IN_TEST_MUX;
<> 144:ef7eb2e8f9f7 109 __IO uint32_t SCAN_MODE;
<> 144:ef7eb2e8f9f7 110 __IO uint32_t BIST_TEST_MUX;
<> 144:ef7eb2e8f9f7 111 __IO uint32_t RAM_DIAG_ADDR;
<> 144:ef7eb2e8f9f7 112 __IO uint32_t RAM_DIAG_DATA;
<> 144:ef7eb2e8f9f7 113 __IO uint32_t SRAMA_DIAG_COMP;
<> 144:ef7eb2e8f9f7 114 __IO uint32_t SRAMB_DIAG_COMP;
<> 144:ef7eb2e8f9f7 115 __IO uint32_t RAM_BUF_TEST_MODE;
<> 144:ef7eb2e8f9f7 116 } TestDigReg_t, *TestDigReg_pt;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /** NVM test registers
<> 144:ef7eb2e8f9f7 119 *
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 typedef struct {
<> 144:ef7eb2e8f9f7 122 __O uint32_t PAD;
<> 144:ef7eb2e8f9f7 123 } TestNvmReg_t, *TestNvmReg_pt;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #endif /* TEST_MAP_H_ */