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targets/TARGET_NXP/TARGET_LPC11U6X/analogin_api.c@174:ed647f63e28d, 2017-12-19 (annotated)
- Committer:
- Dollyparton
- Date:
- Tue Dec 19 12:50:13 2017 +0000
- Revision:
- 174:ed647f63e28d
- Parent:
- 149:156823d33999
Added RAW socket.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include "mbed_assert.h" |
<> | 144:ef7eb2e8f9f7 | 17 | #include "analogin_api.h" |
<> | 144:ef7eb2e8f9f7 | 18 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 19 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | #if DEVICE_ANALOGIN |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | #define ANALOGIN_MEDIAN_FILTER 1 |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | #define ADC_10BIT_RANGE 0x3FF |
<> | 144:ef7eb2e8f9f7 | 27 | #define ADC_12BIT_RANGE 0xFFF |
<> | 144:ef7eb2e8f9f7 | 28 | #define PDRUN_VALID_BITS 0x000025FFL |
<> | 144:ef7eb2e8f9f7 | 29 | #define PDRUN_RESERVED_ONE 0x0000C800L |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #define ADC_RANGE ADC_12BIT_RANGE |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | static const PinMap PinMap_ADC[] = { |
<> | 144:ef7eb2e8f9f7 | 34 | {P1_9 , ADC_0, 3}, |
<> | 144:ef7eb2e8f9f7 | 35 | {P0_23, ADC_1, 1}, |
<> | 144:ef7eb2e8f9f7 | 36 | {P0_16, ADC_2, 1}, |
<> | 144:ef7eb2e8f9f7 | 37 | {P0_15, ADC_3, 3}, |
<> | 144:ef7eb2e8f9f7 | 38 | {P1_22, ADC_4, 3}, |
<> | 144:ef7eb2e8f9f7 | 39 | {P1_3 , ADC_5, 4}, |
<> | 144:ef7eb2e8f9f7 | 40 | {P0_14, ADC_6, 2}, |
<> | 144:ef7eb2e8f9f7 | 41 | {P0_13, ADC_7, 2}, |
<> | 144:ef7eb2e8f9f7 | 42 | {P0_12, ADC_8, 2}, |
<> | 144:ef7eb2e8f9f7 | 43 | {P0_11, ADC_9, 2}, |
<> | 144:ef7eb2e8f9f7 | 44 | {P1_29, ADC_10,4}, |
<> | 144:ef7eb2e8f9f7 | 45 | {P0_22, ADC_11,1}, |
<> | 144:ef7eb2e8f9f7 | 46 | {NC , NC ,0} |
<> | 144:ef7eb2e8f9f7 | 47 | }; |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | void analogin_init(analogin_t *obj, PinName pin) { |
<> | 144:ef7eb2e8f9f7 | 51 | volatile uint32_t tmp; |
<> | 144:ef7eb2e8f9f7 | 52 | obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); |
<> | 144:ef7eb2e8f9f7 | 53 | MBED_ASSERT(obj->adc != (ADCName)NC); |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | pinmap_pinout(pin, PinMap_ADC); |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF)); |
<> | 144:ef7eb2e8f9f7 | 58 | // set pin to ADC mode |
<> | 144:ef7eb2e8f9f7 | 59 | *reg &= ~(1 << 7); // set ADMODE = 0 (analog mode) |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | // ADC Powered |
<> | 144:ef7eb2e8f9f7 | 62 | tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS); |
<> | 144:ef7eb2e8f9f7 | 63 | tmp &= ~((1 << 4) & PDRUN_VALID_BITS); |
<> | 144:ef7eb2e8f9f7 | 64 | LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE); |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | // Enable clock for ADC |
<> | 144:ef7eb2e8f9f7 | 67 | LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 13); |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | // Determine the clock divider for a 500kHz ADC clock during calibration |
<> | 144:ef7eb2e8f9f7 | 70 | uint32_t clkdiv = (SystemCoreClock / 500000) - 1; |
<> | 144:ef7eb2e8f9f7 | 71 | |
<> | 144:ef7eb2e8f9f7 | 72 | // Perform a self-calibration |
<> | 144:ef7eb2e8f9f7 | 73 | LPC_ADC->CTRL = (1UL << 30) | (clkdiv & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 74 | while ((LPC_ADC->CTRL & (1UL << 30)) != 0); |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | // Sampling clock: SystemClock divided by 1 |
<> | 144:ef7eb2e8f9f7 | 77 | LPC_ADC->CTRL = 0; |
<> | 144:ef7eb2e8f9f7 | 78 | } |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | static inline uint32_t adc_read(analogin_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | // select channel |
<> | 144:ef7eb2e8f9f7 | 83 | LPC_ADC->SEQA_CTRL &= ~(0xFFF); |
<> | 144:ef7eb2e8f9f7 | 84 | LPC_ADC->SEQA_CTRL |= (1UL << obj->adc); |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | // start conversion, sequence enable with async mode |
<> | 144:ef7eb2e8f9f7 | 87 | LPC_ADC->SEQA_CTRL |= ((1UL << 26) | (1UL << 31) | (1UL << 19)); |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | // Repeatedly get the sample data until DONE bit |
<> | 144:ef7eb2e8f9f7 | 90 | volatile uint32_t data; |
<> | 144:ef7eb2e8f9f7 | 91 | do { |
<> | 144:ef7eb2e8f9f7 | 92 | data = LPC_ADC->SEQA_GDAT; |
<> | 144:ef7eb2e8f9f7 | 93 | } while ((data & (1UL << 31)) == 0); |
<> | 144:ef7eb2e8f9f7 | 94 | data = LPC_ADC->DAT[obj->adc]; |
<> | 144:ef7eb2e8f9f7 | 95 | |
<> | 144:ef7eb2e8f9f7 | 96 | // Stop conversion |
<> | 144:ef7eb2e8f9f7 | 97 | LPC_ADC->SEQA_CTRL &= ~(1UL << 31); |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | return ((data >> 4) & ADC_RANGE); |
<> | 144:ef7eb2e8f9f7 | 100 | } |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | static inline void order(uint32_t *a, uint32_t *b) { |
<> | 144:ef7eb2e8f9f7 | 103 | if (*a > *b) { |
<> | 144:ef7eb2e8f9f7 | 104 | uint32_t t = *a; |
<> | 144:ef7eb2e8f9f7 | 105 | *a = *b; |
<> | 144:ef7eb2e8f9f7 | 106 | *b = t; |
<> | 144:ef7eb2e8f9f7 | 107 | } |
<> | 144:ef7eb2e8f9f7 | 108 | } |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | static inline uint32_t adc_read_u32(analogin_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 111 | uint32_t value; |
<> | 144:ef7eb2e8f9f7 | 112 | #if ANALOGIN_MEDIAN_FILTER |
<> | 144:ef7eb2e8f9f7 | 113 | uint32_t v1 = adc_read(obj); |
<> | 144:ef7eb2e8f9f7 | 114 | uint32_t v2 = adc_read(obj); |
<> | 144:ef7eb2e8f9f7 | 115 | uint32_t v3 = adc_read(obj); |
<> | 144:ef7eb2e8f9f7 | 116 | order(&v1, &v2); |
<> | 144:ef7eb2e8f9f7 | 117 | order(&v2, &v3); |
<> | 144:ef7eb2e8f9f7 | 118 | order(&v1, &v2); |
<> | 144:ef7eb2e8f9f7 | 119 | value = v2; |
<> | 144:ef7eb2e8f9f7 | 120 | #else |
<> | 144:ef7eb2e8f9f7 | 121 | value = adc_read(obj); |
<> | 144:ef7eb2e8f9f7 | 122 | #endif |
<> | 144:ef7eb2e8f9f7 | 123 | return value; |
<> | 144:ef7eb2e8f9f7 | 124 | } |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | uint16_t analogin_read_u16(analogin_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 127 | uint32_t value = adc_read_u32(obj); |
<> | 144:ef7eb2e8f9f7 | 128 | return (value << 4) | ((value >> 8) & 0x000F); // 12 bit |
<> | 144:ef7eb2e8f9f7 | 129 | } |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | float analogin_read(analogin_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 132 | uint32_t value = adc_read_u32(obj); |
<> | 144:ef7eb2e8f9f7 | 133 | return (float)value * (1.0f / (float)ADC_RANGE); |
<> | 144:ef7eb2e8f9f7 | 134 | } |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | #endif |