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targets/TARGET_NUVOTON/TARGET_M451/serial_api.c@172:7d866c31b3c5, 2017-08-31 (annotated)

Committer:
AnnaBridge
Date:
Thu Aug 31 17:27:04 2017 +0100
Revision:
172:7d866c31b3c5
Parent:
165:e614a9f1c9e2 
This updates the lib to the mbed lib v 150

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "serial_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_SERIAL
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "cmsis.h"
<> 149:156823d33999 22 #include "mbed_error.h"
<> 149:156823d33999 23 #include "mbed_assert.h"
<> 149:156823d33999 24 #include "PeripheralPins.h"
<> 149:156823d33999 25 #include "nu_modutil.h"
<> 149:156823d33999 26 #include "nu_bitutil.h"
AnnaBridge 165:e614a9f1c9e2 27 #include <string.h>
<> 149:156823d33999 28
<> 149:156823d33999 29 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 30 #include "dma_api.h"
<> 149:156823d33999 31 #include "dma.h"
<> 149:156823d33999 32 #endif
<> 149:156823d33999 33
<> 149:156823d33999 34 struct nu_uart_var {
<> 151:5eaa88a5bcc7 35 uint32_t ref_cnt; // Reference count of the H/W module
<> 149:156823d33999 36 serial_t * obj;
<> 149:156823d33999 37 uint32_t fifo_size_tx;
<> 149:156823d33999 38 uint32_t fifo_size_rx;
<> 149:156823d33999 39 void (*vec)(void);
<> 149:156823d33999 40 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 41 void (*vec_async)(void);
<> 149:156823d33999 42 uint8_t pdma_perp_tx;
<> 149:156823d33999 43 uint8_t pdma_perp_rx;
<> 149:156823d33999 44 #endif
<> 149:156823d33999 45 };
<> 149:156823d33999 46
<> 149:156823d33999 47 static void uart0_vec(void);
<> 149:156823d33999 48 static void uart1_vec(void);
<> 149:156823d33999 49 static void uart2_vec(void);
<> 149:156823d33999 50 static void uart3_vec(void);
<> 149:156823d33999 51 static void uart_irq(serial_t *obj);
<> 149:156823d33999 52
<> 149:156823d33999 53 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 54 static void uart0_vec_async(void);
<> 149:156823d33999 55 static void uart1_vec_async(void);
<> 149:156823d33999 56 static void uart2_vec_async(void);
<> 149:156823d33999 57 static void uart3_vec_async(void);
<> 149:156823d33999 58 static void uart_irq_async(serial_t *obj);
<> 149:156823d33999 59
<> 149:156823d33999 60 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
<> 149:156823d33999 61 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
<> 149:156823d33999 62
<> 149:156823d33999 63 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
<> 149:156823d33999 64 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
AnnaBridge 165:e614a9f1c9e2 65 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable);
AnnaBridge 165:e614a9f1c9e2 66 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq);
<> 149:156823d33999 67 static int serial_write_async(serial_t *obj);
<> 149:156823d33999 68 static int serial_read_async(serial_t *obj);
<> 149:156823d33999 69
<> 149:156823d33999 70 static uint32_t serial_rx_event_check(serial_t *obj);
<> 149:156823d33999 71 static uint32_t serial_tx_event_check(serial_t *obj);
<> 149:156823d33999 72
<> 149:156823d33999 73 static int serial_is_tx_complete(serial_t *obj);
<> 149:156823d33999 74 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 149:156823d33999 75
<> 149:156823d33999 76 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
<> 149:156823d33999 77 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
<> 149:156823d33999 78 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
<> 149:156823d33999 79 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 149:156823d33999 80 static int serial_is_rx_complete(serial_t *obj);
<> 149:156823d33999 81
<> 149:156823d33999 82 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
<> 149:156823d33999 83 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
<> 149:156823d33999 84 #endif
<> 149:156823d33999 85
<> 149:156823d33999 86 static struct nu_uart_var uart0_var = {
<> 151:5eaa88a5bcc7 87 .ref_cnt = 0,
<> 149:156823d33999 88 .obj = NULL,
<> 149:156823d33999 89 .fifo_size_tx = 16,
<> 149:156823d33999 90 .fifo_size_rx = 16,
<> 149:156823d33999 91 .vec = uart0_vec,
<> 149:156823d33999 92 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 93 .vec_async = uart0_vec_async,
<> 149:156823d33999 94 .pdma_perp_tx = PDMA_UART0_TX,
<> 149:156823d33999 95 .pdma_perp_rx = PDMA_UART0_RX
<> 149:156823d33999 96 #endif
<> 149:156823d33999 97 };
<> 149:156823d33999 98 static struct nu_uart_var uart1_var = {
<> 151:5eaa88a5bcc7 99 .ref_cnt = 0,
<> 149:156823d33999 100 .obj = NULL,
<> 149:156823d33999 101 .fifo_size_tx = 16,
<> 149:156823d33999 102 .fifo_size_rx = 16,
<> 149:156823d33999 103 .vec = uart1_vec,
<> 149:156823d33999 104 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 105 .vec_async = uart1_vec_async,
<> 149:156823d33999 106 .pdma_perp_tx = PDMA_UART1_TX,
<> 149:156823d33999 107 .pdma_perp_rx = PDMA_UART1_RX
<> 149:156823d33999 108 #endif
<> 149:156823d33999 109 };
<> 149:156823d33999 110 static struct nu_uart_var uart2_var = {
<> 151:5eaa88a5bcc7 111 .ref_cnt = 0,
<> 149:156823d33999 112 .obj = NULL,
<> 149:156823d33999 113 .fifo_size_tx = 16,
<> 149:156823d33999 114 .fifo_size_rx = 16,
<> 149:156823d33999 115 .vec = uart2_vec,
<> 149:156823d33999 116 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 117 .vec_async = uart2_vec_async,
<> 149:156823d33999 118 .pdma_perp_tx = PDMA_UART2_TX,
<> 149:156823d33999 119 .pdma_perp_rx = PDMA_UART2_RX
<> 149:156823d33999 120 #endif
<> 149:156823d33999 121 };
<> 149:156823d33999 122 static struct nu_uart_var uart3_var = {
<> 151:5eaa88a5bcc7 123 .ref_cnt = 0,
<> 149:156823d33999 124 .obj = NULL,
<> 149:156823d33999 125 .fifo_size_tx = 16,
<> 149:156823d33999 126 .fifo_size_rx = 16,
<> 149:156823d33999 127 .vec = uart3_vec,
<> 149:156823d33999 128 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 129 .vec_async = uart3_vec_async,
<> 149:156823d33999 130 .pdma_perp_tx = PDMA_UART3_TX,
<> 149:156823d33999 131 .pdma_perp_rx = PDMA_UART3_RX
<> 149:156823d33999 132 #endif
<> 149:156823d33999 133 };
<> 149:156823d33999 134
<> 149:156823d33999 135
<> 149:156823d33999 136 int stdio_uart_inited = 0;
<> 149:156823d33999 137 serial_t stdio_uart;
<> 149:156823d33999 138 static uint32_t uart_modinit_mask = 0;
<> 149:156823d33999 139
<> 149:156823d33999 140 static const struct nu_modinit_s uart_modinit_tab[] = {
<> 149:156823d33999 141 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
<> 149:156823d33999 142 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
<> 149:156823d33999 143 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
<> 149:156823d33999 144 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
<> 149:156823d33999 145
<> 149:156823d33999 146 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 149:156823d33999 147 };
<> 149:156823d33999 148
<> 149:156823d33999 149 extern void mbed_sdk_init(void);
<> 149:156823d33999 150
<> 149:156823d33999 151 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 149:156823d33999 152 {
<> 151:5eaa88a5bcc7 153 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
<> 149:156823d33999 154 mbed_sdk_init();
<> 149:156823d33999 155
<> 149:156823d33999 156 // Determine which UART_x the pins are used for
<> 149:156823d33999 157 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
<> 149:156823d33999 158 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
<> 149:156823d33999 159 // Get the peripheral name (UART_x) from the pins and assign it to the object
<> 149:156823d33999 160 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
<> 149:156823d33999 161 MBED_ASSERT((int)obj->serial.uart != NC);
<> 149:156823d33999 162
<> 149:156823d33999 163 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 164 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 165 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 166
<> 151:5eaa88a5bcc7 167 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 168
<> 151:5eaa88a5bcc7 169 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 170 // Reset this module
<> 151:5eaa88a5bcc7 171 SYS_ResetModule(modinit->rsetidx);
<> 151:5eaa88a5bcc7 172
<> 151:5eaa88a5bcc7 173 // Select IP clock source
<> 151:5eaa88a5bcc7 174 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
<> 151:5eaa88a5bcc7 175 // Enable IP clock
<> 151:5eaa88a5bcc7 176 CLK_EnableModuleClock(modinit->clkidx);
<> 149:156823d33999 177
<> 151:5eaa88a5bcc7 178 pinmap_pinout(tx, PinMap_UART_TX);
<> 151:5eaa88a5bcc7 179 pinmap_pinout(rx, PinMap_UART_RX);
<> 151:5eaa88a5bcc7 180
<> 151:5eaa88a5bcc7 181 obj->serial.pin_tx = tx;
<> 151:5eaa88a5bcc7 182 obj->serial.pin_rx = rx;
<> 151:5eaa88a5bcc7 183 }
<> 151:5eaa88a5bcc7 184 var->ref_cnt ++;
<> 149:156823d33999 185
<> 149:156823d33999 186 // Configure the UART module and set its baudrate
<> 149:156823d33999 187 serial_baud(obj, 9600);
<> 149:156823d33999 188 // Configure data bits, parity, and stop bits
<> 149:156823d33999 189 serial_format(obj, 8, ParityNone, 1);
<> 149:156823d33999 190
<> 151:5eaa88a5bcc7 191 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 192 obj->serial.irq_en = 0;
<> 149:156823d33999 193
<> 149:156823d33999 194 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 195 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
<> 149:156823d33999 196 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 149:156823d33999 197 obj->serial.event = 0;
<> 149:156823d33999 198 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 199 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 200 #endif
<> 149:156823d33999 201
<> 149:156823d33999 202 // For stdio management
<> 151:5eaa88a5bcc7 203 if (obj->serial.uart == STDIO_UART) {
<> 149:156823d33999 204 stdio_uart_inited = 1;
<> 151:5eaa88a5bcc7 205 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 149:156823d33999 206 }
<> 149:156823d33999 207
<> 151:5eaa88a5bcc7 208 if (var->ref_cnt) {
<> 151:5eaa88a5bcc7 209 // Mark this module to be inited.
<> 151:5eaa88a5bcc7 210 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 211 uart_modinit_mask |= 1 << i;
<> 151:5eaa88a5bcc7 212 }
<> 149:156823d33999 213 }
<> 149:156823d33999 214
<> 149:156823d33999 215 void serial_free(serial_t *obj)
<> 149:156823d33999 216 {
<> 149:156823d33999 217 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 218 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 219 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 220
<> 151:5eaa88a5bcc7 221 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 222
<> 151:5eaa88a5bcc7 223 var->ref_cnt --;
<> 151:5eaa88a5bcc7 224 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 225 #if DEVICE_SERIAL_ASYNCH
<> 151:5eaa88a5bcc7 226 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 227 dma_channel_free(obj->serial.dma_chn_id_tx);
<> 151:5eaa88a5bcc7 228 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 229 }
<> 151:5eaa88a5bcc7 230 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 231 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 151:5eaa88a5bcc7 232 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 233 }
<> 151:5eaa88a5bcc7 234 #endif
<> 151:5eaa88a5bcc7 235
<> 151:5eaa88a5bcc7 236 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
<> 149:156823d33999 237
<> 151:5eaa88a5bcc7 238 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 151:5eaa88a5bcc7 239 NVIC_DisableIRQ(modinit->irq_n);
<> 149:156823d33999 240
<> 151:5eaa88a5bcc7 241 // Disable IP clock
<> 151:5eaa88a5bcc7 242 CLK_DisableModuleClock(modinit->clkidx);
<> 151:5eaa88a5bcc7 243 }
<> 151:5eaa88a5bcc7 244
<> 151:5eaa88a5bcc7 245 if (var->obj == obj) {
<> 151:5eaa88a5bcc7 246 var->obj = NULL;
<> 151:5eaa88a5bcc7 247 }
<> 151:5eaa88a5bcc7 248
<> 151:5eaa88a5bcc7 249 if (obj->serial.uart == STDIO_UART) {
<> 149:156823d33999 250 stdio_uart_inited = 0;
<> 149:156823d33999 251 }
<> 149:156823d33999 252
<> 151:5eaa88a5bcc7 253 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 254 // Mark this module to be deinited.
<> 151:5eaa88a5bcc7 255 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 256 uart_modinit_mask &= ~(1 << i);
<> 151:5eaa88a5bcc7 257 }
<> 149:156823d33999 258 }
<> 149:156823d33999 259
<> 149:156823d33999 260 void serial_baud(serial_t *obj, int baudrate) {
<> 149:156823d33999 261 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 262 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 263
<> 149:156823d33999 264 obj->serial.baudrate = baudrate;
<> 149:156823d33999 265 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
<> 149:156823d33999 266 }
<> 149:156823d33999 267
<> 149:156823d33999 268 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
<> 149:156823d33999 269 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 270 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 271
AnnaBridge 172:7d866c31b3c5 272 // Sanity check arguments
AnnaBridge 172:7d866c31b3c5 273 MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
AnnaBridge 172:7d866c31b3c5 274 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
AnnaBridge 172:7d866c31b3c5 275 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
AnnaBridge 172:7d866c31b3c5 276
<> 149:156823d33999 277 obj->serial.databits = data_bits;
<> 149:156823d33999 278 obj->serial.parity = parity;
<> 149:156823d33999 279 obj->serial.stopbits = stop_bits;
<> 149:156823d33999 280
<> 149:156823d33999 281 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
<> 149:156823d33999 282 (data_bits == 6) ? UART_WORD_LEN_6 :
<> 149:156823d33999 283 (data_bits == 7) ? UART_WORD_LEN_7 :
<> 149:156823d33999 284 UART_WORD_LEN_8;
<> 149:156823d33999 285 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
<> 149:156823d33999 286 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
<> 149:156823d33999 287 UART_PARITY_NONE;
<> 149:156823d33999 288 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
<> 149:156823d33999 289 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
<> 149:156823d33999 290 0, // Don't change baudrate
<> 149:156823d33999 291 databits_intern,
<> 149:156823d33999 292 parity_intern,
<> 149:156823d33999 293 stopbits_intern);
<> 149:156823d33999 294 }
<> 149:156823d33999 295
<> 149:156823d33999 296 #if DEVICE_SERIAL_FC
<> 149:156823d33999 297
<> 149:156823d33999 298 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 149:156823d33999 299 {
<> 149:156823d33999 300 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 301
<> 149:156823d33999 302 // First, disable flow control completely.
<> 149:156823d33999 303 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
<> 149:156823d33999 304
<> 149:156823d33999 305 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
<> 149:156823d33999 306 // Check if RTS pin matches.
<> 149:156823d33999 307 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 149:156823d33999 308 MBED_ASSERT(uart_rts == obj->serial.uart);
<> 149:156823d33999 309 // Enable the pin for RTS function
<> 149:156823d33999 310 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 153:fa9ff456f731 311 // nRTS pin output is low level active
<> 153:fa9ff456f731 312 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
<> 149:156823d33999 313 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
<> 149:156823d33999 314 // Enable RTS
<> 149:156823d33999 315 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
<> 149:156823d33999 316 }
<> 149:156823d33999 317
<> 149:156823d33999 318 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
<> 149:156823d33999 319 // Check if CTS pin matches.
<> 149:156823d33999 320 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 149:156823d33999 321 MBED_ASSERT(uart_cts == obj->serial.uart);
<> 149:156823d33999 322 // Enable the pin for CTS function
<> 149:156823d33999 323 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 153:fa9ff456f731 324 // nCTS pin input is low level active
<> 153:fa9ff456f731 325 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
<> 149:156823d33999 326 // Enable CTS
<> 149:156823d33999 327 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
<> 149:156823d33999 328 }
<> 149:156823d33999 329 }
<> 149:156823d33999 330
<> 149:156823d33999 331 #endif //DEVICE_SERIAL_FC
<> 149:156823d33999 332
<> 149:156823d33999 333 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 149:156823d33999 334 {
<> 149:156823d33999 335 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 336 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 337
<> 149:156823d33999 338 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 339 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 340 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 341
<> 149:156823d33999 342 obj->serial.irq_handler = (uint32_t) handler;
<> 149:156823d33999 343 obj->serial.irq_id = id;
<> 149:156823d33999 344
<> 149:156823d33999 345 // Restore sync-mode vector
<> 149:156823d33999 346 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
<> 149:156823d33999 347 }
<> 149:156823d33999 348
<> 149:156823d33999 349 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 149:156823d33999 350 {
AnnaBridge 165:e614a9f1c9e2 351 obj->serial.irq_en = enable;
AnnaBridge 165:e614a9f1c9e2 352 serial_enable_interrupt(obj, irq, enable);
<> 149:156823d33999 353 }
<> 149:156823d33999 354
<> 149:156823d33999 355 int serial_getc(serial_t *obj)
<> 149:156823d33999 356 {
AnnaBridge 165:e614a9f1c9e2 357 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 149:156823d33999 358 while (! serial_readable(obj));
<> 149:156823d33999 359 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 360
AnnaBridge 165:e614a9f1c9e2 361 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 362 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 149:156823d33999 363 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 364 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 365 }
<> 149:156823d33999 366
<> 149:156823d33999 367 return c;
<> 149:156823d33999 368 }
<> 149:156823d33999 369
<> 149:156823d33999 370 void serial_putc(serial_t *obj, int c)
<> 149:156823d33999 371 {
AnnaBridge 165:e614a9f1c9e2 372 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 149:156823d33999 373 while (! serial_writable(obj));
<> 149:156823d33999 374 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
<> 149:156823d33999 375
AnnaBridge 165:e614a9f1c9e2 376 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 377 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 149:156823d33999 378 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 379 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 380 }
<> 149:156823d33999 381 }
<> 149:156823d33999 382
<> 149:156823d33999 383 int serial_readable(serial_t *obj)
<> 149:156823d33999 384 {
<> 149:156823d33999 385 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 386 return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 387 }
<> 149:156823d33999 388
<> 149:156823d33999 389 int serial_writable(serial_t *obj)
<> 149:156823d33999 390 {
<> 149:156823d33999 391 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 392 }
<> 149:156823d33999 393
<> 149:156823d33999 394 void serial_pinout_tx(PinName tx)
<> 149:156823d33999 395 {
<> 149:156823d33999 396 pinmap_pinout(tx, PinMap_UART_TX);
<> 149:156823d33999 397 }
<> 149:156823d33999 398
<> 149:156823d33999 399 void serial_break_set(serial_t *obj)
<> 149:156823d33999 400 {
<> 149:156823d33999 401 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
<> 149:156823d33999 402 }
<> 149:156823d33999 403
<> 149:156823d33999 404 void serial_break_clear(serial_t *obj)
<> 149:156823d33999 405 {
<> 149:156823d33999 406 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
<> 149:156823d33999 407 }
<> 149:156823d33999 408
<> 149:156823d33999 409 static void uart0_vec(void)
<> 149:156823d33999 410 {
<> 149:156823d33999 411 uart_irq(uart0_var.obj);
<> 149:156823d33999 412 }
<> 149:156823d33999 413
<> 149:156823d33999 414 static void uart1_vec(void)
<> 149:156823d33999 415 {
<> 149:156823d33999 416 uart_irq(uart1_var.obj);
<> 149:156823d33999 417 }
<> 149:156823d33999 418
<> 149:156823d33999 419 static void uart2_vec(void)
<> 149:156823d33999 420 {
<> 149:156823d33999 421 uart_irq(uart2_var.obj);
<> 149:156823d33999 422 }
<> 149:156823d33999 423
<> 149:156823d33999 424 static void uart3_vec(void)
<> 149:156823d33999 425 {
<> 149:156823d33999 426 uart_irq(uart3_var.obj);
<> 149:156823d33999 427 }
<> 149:156823d33999 428
<> 149:156823d33999 429 static void uart_irq(serial_t *obj)
<> 149:156823d33999 430 {
<> 149:156823d33999 431 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 432
<> 149:156823d33999 433 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 149:156823d33999 434 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 149:156823d33999 435 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 436 if (obj->serial.irq_handler) {
<> 149:156823d33999 437 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
<> 149:156823d33999 438 }
<> 149:156823d33999 439 }
<> 149:156823d33999 440
<> 149:156823d33999 441 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 149:156823d33999 442 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 149:156823d33999 443 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 444 if (obj->serial.irq_handler) {
<> 149:156823d33999 445 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
<> 149:156823d33999 446 }
<> 149:156823d33999 447 }
<> 149:156823d33999 448
<> 149:156823d33999 449 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
<> 149:156823d33999 450 uart_base->INTSTS = uart_base->INTSTS;
<> 149:156823d33999 451 uart_base->FIFOSTS = uart_base->FIFOSTS;
<> 149:156823d33999 452 }
<> 149:156823d33999 453
<> 149:156823d33999 454
<> 149:156823d33999 455 #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 456 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 457 {
<> 149:156823d33999 458 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
<> 149:156823d33999 459
<> 149:156823d33999 460 obj->serial.dma_usage_tx = hint;
<> 149:156823d33999 461 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
<> 149:156823d33999 462
<> 149:156823d33999 463 // UART IRQ is necessary for both interrupt way and DMA way
<> 149:156823d33999 464 serial_tx_enable_event(obj, event, 1);
<> 149:156823d33999 465 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
<> 149:156823d33999 466 //UART_HAL_DisableTransmitter(obj->serial.address);
<> 149:156823d33999 467 //UART_HAL_FlushTxFifo(obj->serial.address);
<> 149:156823d33999 468 //UART_HAL_EnableTransmitter(obj->serial.address);
<> 149:156823d33999 469
<> 149:156823d33999 470 int n_word = 0;
<> 149:156823d33999 471 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 149:156823d33999 472 // Interrupt way
<> 149:156823d33999 473 n_word = serial_write_async(obj);
<> 149:156823d33999 474 serial_tx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 475 } else {
<> 149:156823d33999 476 // DMA way
<> 149:156823d33999 477 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 478 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 479 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 480
<> 161:2cc1468da177 481 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 482
<> 161:2cc1468da177 483 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
<> 149:156823d33999 484 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 485 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
<> 149:156823d33999 486 0, // Scatter-gather disabled
<> 149:156823d33999 487 0); // Scatter-gather descriptor address
<> 149:156823d33999 488 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 489 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 490 tx_length);
<> 149:156823d33999 491 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 492 (uint32_t) tx, // NOTE:
<> 149:156823d33999 493 // NUC472: End of source address
<> 149:156823d33999 494 // M451: Start of source address
<> 149:156823d33999 495 PDMA_SAR_INC, // Source address incremental
<> 161:2cc1468da177 496 (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
<> 149:156823d33999 497 PDMA_DAR_FIX); // Destination address fixed
<> 149:156823d33999 498 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 499 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 500 0); // Burst size
<> 149:156823d33999 501 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
<> 149:156823d33999 502 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 503 // Register DMA event handler
<> 149:156823d33999 504 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
<> 149:156823d33999 505 serial_tx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 506 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
<> 149:156823d33999 507 }
<> 149:156823d33999 508
<> 149:156823d33999 509 return n_word;
<> 149:156823d33999 510 }
<> 149:156823d33999 511
<> 149:156823d33999 512 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
<> 149:156823d33999 513 {
<> 149:156823d33999 514 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
<> 149:156823d33999 515
<> 149:156823d33999 516 obj->serial.dma_usage_rx = hint;
<> 149:156823d33999 517 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
<> 149:156823d33999 518 // DMA doesn't support char match, so fall back to IRQ if it is requested.
<> 149:156823d33999 519 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
<> 149:156823d33999 520 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 149:156823d33999 521 char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 149:156823d33999 522 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 149:156823d33999 523 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 149:156823d33999 524 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 525 }
<> 149:156823d33999 526
<> 149:156823d33999 527 // UART IRQ is necessary for both interrupt way and DMA way
<> 149:156823d33999 528 serial_rx_enable_event(obj, event, 1);
<> 149:156823d33999 529 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
<> 149:156823d33999 530 serial_rx_set_char_match(obj, char_match);
<> 149:156823d33999 531 //UART_HAL_DisableReceiver(obj->serial.address);
<> 149:156823d33999 532 //UART_HAL_FlushRxFifo(obj->serial.address);
<> 149:156823d33999 533 //UART_HAL_EnableReceiver(obj->serial.address);
<> 149:156823d33999 534
<> 149:156823d33999 535 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 149:156823d33999 536 // Interrupt way
<> 149:156823d33999 537 serial_rx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 538 } else {
<> 149:156823d33999 539 // DMA way
<> 149:156823d33999 540 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 541 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 542 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 543
<> 161:2cc1468da177 544 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 545
<> 161:2cc1468da177 546 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
<> 149:156823d33999 547 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 548 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
<> 149:156823d33999 549 0, // Scatter-gather disabled
<> 149:156823d33999 550 0); // Scatter-gather descriptor address
<> 149:156823d33999 551 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 552 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 149:156823d33999 553 rx_length);
<> 149:156823d33999 554 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
<> 161:2cc1468da177 555 (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
<> 149:156823d33999 556 PDMA_SAR_FIX, // Source address fixed
<> 149:156823d33999 557 (uint32_t) rx, // NOTE:
<> 149:156823d33999 558 // NUC472: End of destination address
<> 149:156823d33999 559 // M451: Start of destination address
<> 149:156823d33999 560 PDMA_DAR_INC); // Destination address incremental
<> 149:156823d33999 561 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 562 PDMA_REQ_SINGLE, // Single mode
<> 149:156823d33999 563 0); // Burst size
<> 149:156823d33999 564 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
<> 149:156823d33999 565 PDMA_INT_TRANS_DONE); // Interrupt type
<> 149:156823d33999 566 // Register DMA event handler
<> 149:156823d33999 567 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
<> 149:156823d33999 568 serial_rx_enable_interrupt(obj, handler, 1);
<> 149:156823d33999 569 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
<> 149:156823d33999 570 }
<> 149:156823d33999 571 }
<> 149:156823d33999 572
<> 149:156823d33999 573 void serial_tx_abort_asynch(serial_t *obj)
<> 149:156823d33999 574 {
<> 149:156823d33999 575 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 576 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 149:156823d33999 577
<> 149:156823d33999 578 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 579 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 580
<> 149:156823d33999 581 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 582 PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
<> 149:156823d33999 583 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 149:156823d33999 584 //PDMA_STOP(obj->serial.dma_chn_id_tx);
<> 161:2cc1468da177 585 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
<> 149:156823d33999 586 }
<> 149:156823d33999 587 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
<> 149:156823d33999 588 }
<> 149:156823d33999 589
<> 149:156823d33999 590 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 591 serial_enable_interrupt(obj, TxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 592 serial_rollback_interrupt(obj, TxIrq);
<> 149:156823d33999 593 }
<> 149:156823d33999 594
<> 149:156823d33999 595 void serial_rx_abort_asynch(serial_t *obj)
<> 149:156823d33999 596 {
<> 149:156823d33999 597 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 598 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 599
<> 149:156823d33999 600 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 601 PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
<> 149:156823d33999 602 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 149:156823d33999 603 //PDMA_STOP(obj->serial.dma_chn_id_rx);
<> 161:2cc1468da177 604 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
<> 149:156823d33999 605 }
<> 149:156823d33999 606 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
<> 149:156823d33999 607 }
<> 149:156823d33999 608
<> 149:156823d33999 609 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 610 serial_enable_interrupt(obj, RxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 611 serial_rollback_interrupt(obj, RxIrq);
<> 149:156823d33999 612 }
<> 149:156823d33999 613
<> 149:156823d33999 614 uint8_t serial_tx_active(serial_t *obj)
<> 149:156823d33999 615 {
AnnaBridge 165:e614a9f1c9e2 616 // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 617 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 618 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 619 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 620
AnnaBridge 165:e614a9f1c9e2 621 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 622 return (obj->serial.vec == var->vec_async);
<> 149:156823d33999 623 }
<> 149:156823d33999 624
<> 149:156823d33999 625 uint8_t serial_rx_active(serial_t *obj)
<> 149:156823d33999 626 {
AnnaBridge 165:e614a9f1c9e2 627 // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 628 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 629 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 630 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 631
AnnaBridge 165:e614a9f1c9e2 632 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 633 return (obj->serial.vec == var->vec_async);
<> 149:156823d33999 634 }
<> 149:156823d33999 635
<> 149:156823d33999 636 int serial_irq_handler_asynch(serial_t *obj)
<> 149:156823d33999 637 {
<> 149:156823d33999 638 int event_rx = 0;
<> 149:156823d33999 639 int event_tx = 0;
<> 149:156823d33999 640
<> 151:5eaa88a5bcc7 641 // Necessary for both interrupt way and DMA way
<> 149:156823d33999 642 if (serial_is_irq_en(obj, RxIrq)) {
<> 149:156823d33999 643 event_rx = serial_rx_event_check(obj);
<> 149:156823d33999 644 if (event_rx) {
<> 149:156823d33999 645 serial_rx_abort_asynch(obj);
<> 149:156823d33999 646 }
<> 149:156823d33999 647 }
<> 149:156823d33999 648
<> 149:156823d33999 649 if (serial_is_irq_en(obj, TxIrq)) {
<> 149:156823d33999 650 event_tx = serial_tx_event_check(obj);
<> 149:156823d33999 651 if (event_tx) {
<> 149:156823d33999 652 serial_tx_abort_asynch(obj);
<> 149:156823d33999 653 }
<> 149:156823d33999 654 }
<> 149:156823d33999 655
<> 149:156823d33999 656 return (obj->serial.event & (event_rx | event_tx));
<> 149:156823d33999 657 }
<> 149:156823d33999 658
<> 149:156823d33999 659 int serial_allow_powerdown(void)
<> 149:156823d33999 660 {
<> 149:156823d33999 661 uint32_t modinit_mask = uart_modinit_mask;
<> 149:156823d33999 662 while (modinit_mask) {
<> 149:156823d33999 663 int uart_idx = nu_ctz(modinit_mask);
<> 149:156823d33999 664 const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
<> 149:156823d33999 665 if (modinit->modname != NC) {
<> 149:156823d33999 666 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
<> 149:156823d33999 667 // Disallow entering power-down mode if Tx FIFO has data to flush
<> 149:156823d33999 668 if (! UART_IS_TX_EMPTY((uart_base))) {
<> 149:156823d33999 669 return 0;
<> 149:156823d33999 670 }
<> 149:156823d33999 671 // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
<> 149:156823d33999 672 if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 673 return 0;
<> 149:156823d33999 674 }
<> 149:156823d33999 675 // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
<> 149:156823d33999 676 if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
<> 149:156823d33999 677 return 0;
<> 149:156823d33999 678 }
<> 149:156823d33999 679 }
<> 149:156823d33999 680 modinit_mask &= ~(1 << uart_idx);
<> 149:156823d33999 681 }
<> 149:156823d33999 682
<> 149:156823d33999 683 return 1;
<> 149:156823d33999 684 }
<> 149:156823d33999 685
<> 149:156823d33999 686 static void uart0_vec_async(void)
<> 149:156823d33999 687 {
<> 149:156823d33999 688 uart_irq_async(uart0_var.obj);
<> 149:156823d33999 689 }
<> 149:156823d33999 690
<> 149:156823d33999 691 static void uart1_vec_async(void)
<> 149:156823d33999 692 {
<> 149:156823d33999 693 uart_irq_async(uart1_var.obj);
<> 149:156823d33999 694 }
<> 149:156823d33999 695
<> 149:156823d33999 696 static void uart2_vec_async(void)
<> 149:156823d33999 697 {
<> 149:156823d33999 698 uart_irq_async(uart2_var.obj);
<> 149:156823d33999 699 }
<> 149:156823d33999 700
<> 149:156823d33999 701 static void uart3_vec_async(void)
<> 149:156823d33999 702 {
<> 149:156823d33999 703 uart_irq_async(uart3_var.obj);
<> 149:156823d33999 704 }
<> 149:156823d33999 705
<> 149:156823d33999 706 static void uart_irq_async(serial_t *obj)
<> 149:156823d33999 707 {
<> 149:156823d33999 708 if (serial_is_irq_en(obj, RxIrq)) {
<> 149:156823d33999 709 (*obj->serial.irq_handler_rx_async)();
<> 149:156823d33999 710 }
<> 149:156823d33999 711 if (serial_is_irq_en(obj, TxIrq)) {
<> 149:156823d33999 712 (*obj->serial.irq_handler_tx_async)();
<> 149:156823d33999 713 }
<> 149:156823d33999 714 }
<> 149:156823d33999 715
<> 149:156823d33999 716 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
<> 149:156823d33999 717 {
<> 149:156823d33999 718 obj->char_match = char_match;
<> 149:156823d33999 719 obj->char_found = 0;
<> 149:156823d33999 720 }
<> 149:156823d33999 721
<> 149:156823d33999 722 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 149:156823d33999 723 {
<> 149:156823d33999 724 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
<> 149:156823d33999 725 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
<> 149:156823d33999 726
<> 149:156823d33999 727 //if (event & SERIAL_EVENT_TX_COMPLETE) {
<> 149:156823d33999 728 //}
<> 149:156823d33999 729 }
<> 149:156823d33999 730
<> 149:156823d33999 731 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 149:156823d33999 732 {
<> 149:156823d33999 733 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
<> 149:156823d33999 734 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
<> 149:156823d33999 735
<> 149:156823d33999 736 //if (event & SERIAL_EVENT_RX_COMPLETE) {
<> 149:156823d33999 737 //}
<> 149:156823d33999 738 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
<> 149:156823d33999 739 //}
<> 149:156823d33999 740 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
<> 149:156823d33999 741 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 149:156823d33999 742 }
<> 149:156823d33999 743 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
<> 149:156823d33999 744 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 149:156823d33999 745 }
<> 149:156823d33999 746 if (event & SERIAL_EVENT_RX_OVERFLOW) {
<> 149:156823d33999 747 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
<> 149:156823d33999 748 }
<> 149:156823d33999 749 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
<> 149:156823d33999 750 //}
<> 149:156823d33999 751 }
<> 149:156823d33999 752
<> 149:156823d33999 753 static int serial_is_tx_complete(serial_t *obj)
<> 149:156823d33999 754 {
<> 149:156823d33999 755 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
<> 149:156823d33999 756 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 757 // FIXME: Premature abort???
<> 149:156823d33999 758 return (obj->tx_buff.pos == obj->tx_buff.length);
<> 149:156823d33999 759 }
<> 149:156823d33999 760
<> 149:156823d33999 761 static int serial_is_rx_complete(serial_t *obj)
<> 149:156823d33999 762 {
<> 149:156823d33999 763 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 764 return (obj->rx_buff.pos == obj->rx_buff.length);
<> 149:156823d33999 765 }
<> 149:156823d33999 766
<> 149:156823d33999 767 static uint32_t serial_tx_event_check(serial_t *obj)
<> 149:156823d33999 768 {
<> 149:156823d33999 769 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 770
<> 149:156823d33999 771 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 149:156823d33999 772 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 149:156823d33999 773 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 774 }
<> 149:156823d33999 775
<> 149:156823d33999 776 uint32_t event = 0;
<> 149:156823d33999 777
<> 149:156823d33999 778 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 149:156823d33999 779 serial_write_async(obj);
<> 149:156823d33999 780 }
<> 149:156823d33999 781
<> 149:156823d33999 782 if (serial_is_tx_complete(obj)) {
<> 149:156823d33999 783 event |= SERIAL_EVENT_TX_COMPLETE;
<> 149:156823d33999 784 }
<> 149:156823d33999 785
<> 149:156823d33999 786 return event;
<> 149:156823d33999 787 }
<> 149:156823d33999 788
<> 149:156823d33999 789 static uint32_t serial_rx_event_check(serial_t *obj)
<> 149:156823d33999 790 {
<> 149:156823d33999 791 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 792
<> 149:156823d33999 793 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 149:156823d33999 794 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 149:156823d33999 795 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 796 }
<> 149:156823d33999 797
<> 149:156823d33999 798 uint32_t event = 0;
<> 149:156823d33999 799
<> 149:156823d33999 800 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
<> 149:156823d33999 801 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
<> 149:156823d33999 802 }
<> 149:156823d33999 803 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
<> 149:156823d33999 804 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
<> 149:156823d33999 805 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
<> 149:156823d33999 806 }
<> 149:156823d33999 807 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
<> 149:156823d33999 808 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
<> 149:156823d33999 809 event |= SERIAL_EVENT_RX_PARITY_ERROR;
<> 149:156823d33999 810 }
<> 149:156823d33999 811
<> 149:156823d33999 812 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
<> 149:156823d33999 813 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
<> 149:156823d33999 814 event |= SERIAL_EVENT_RX_OVERFLOW;
<> 149:156823d33999 815 }
<> 149:156823d33999 816
<> 149:156823d33999 817 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 149:156823d33999 818 serial_read_async(obj);
<> 149:156823d33999 819 }
<> 149:156823d33999 820
<> 149:156823d33999 821 if (serial_is_rx_complete(obj)) {
<> 149:156823d33999 822 event |= SERIAL_EVENT_RX_COMPLETE;
<> 149:156823d33999 823 }
<> 149:156823d33999 824 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
<> 149:156823d33999 825 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
<> 149:156823d33999 826 // FIXME: Timing to reset char_found?
<> 149:156823d33999 827 //obj->char_found = 0;
<> 149:156823d33999 828 }
<> 149:156823d33999 829
<> 149:156823d33999 830 return event;
<> 149:156823d33999 831 }
<> 149:156823d33999 832
<> 149:156823d33999 833 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 834 {
<> 149:156823d33999 835 serial_t *obj = (serial_t *) id;
<> 149:156823d33999 836
<> 149:156823d33999 837 // FIXME: Pass this error to caller
<> 149:156823d33999 838 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 839 }
<> 149:156823d33999 840 // Expect UART IRQ will catch this transfer done event
<> 149:156823d33999 841 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 842 obj->tx_buff.pos = obj->tx_buff.length;
<> 149:156823d33999 843 }
<> 149:156823d33999 844 // FIXME: Pass this error to caller
<> 149:156823d33999 845 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 846 }
<> 149:156823d33999 847
<> 149:156823d33999 848 uart_irq_async(obj);
<> 149:156823d33999 849 }
<> 149:156823d33999 850
<> 149:156823d33999 851 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
<> 149:156823d33999 852 {
<> 149:156823d33999 853 serial_t *obj = (serial_t *) id;
<> 149:156823d33999 854
<> 149:156823d33999 855 // FIXME: Pass this error to caller
<> 149:156823d33999 856 if (event_dma & DMA_EVENT_ABORT) {
<> 149:156823d33999 857 }
<> 149:156823d33999 858 // Expect UART IRQ will catch this transfer done event
<> 149:156823d33999 859 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 149:156823d33999 860 obj->rx_buff.pos = obj->rx_buff.length;
<> 149:156823d33999 861 }
<> 149:156823d33999 862 // FIXME: Pass this error to caller
<> 149:156823d33999 863 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 149:156823d33999 864 }
<> 149:156823d33999 865
<> 149:156823d33999 866 uart_irq_async(obj);
<> 149:156823d33999 867 }
<> 149:156823d33999 868
<> 149:156823d33999 869 static int serial_write_async(serial_t *obj)
<> 149:156823d33999 870 {
<> 149:156823d33999 871 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 872 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 873 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 874
<> 149:156823d33999 875 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 149:156823d33999 876
<> 149:156823d33999 877 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
<> 149:156823d33999 878 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
<> 149:156823d33999 879 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
<> 149:156823d33999 880 tx_fifo_busy = tx_fifo_max;
<> 149:156823d33999 881 }
<> 149:156823d33999 882 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
<> 149:156823d33999 883 if (tx_fifo_free == 0) {
<> 149:156823d33999 884 // Simulate clear of the interrupt flag
<> 149:156823d33999 885 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 886 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 887 }
<> 149:156823d33999 888 return 0;
<> 149:156823d33999 889 }
<> 149:156823d33999 890
<> 149:156823d33999 891 uint32_t bytes_per_word = obj->tx_buff.width / 8;
<> 149:156823d33999 892
<> 149:156823d33999 893 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
<> 149:156823d33999 894 int n_words = 0;
<> 149:156823d33999 895 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
<> 149:156823d33999 896 switch (bytes_per_word) {
<> 149:156823d33999 897 case 4:
<> 149:156823d33999 898 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 899 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 900 case 2:
<> 149:156823d33999 901 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 902 case 1:
<> 149:156823d33999 903 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 149:156823d33999 904 }
<> 149:156823d33999 905
<> 149:156823d33999 906 n_words ++;
<> 149:156823d33999 907 tx_fifo_free -= bytes_per_word;
<> 149:156823d33999 908 obj->tx_buff.pos ++;
<> 149:156823d33999 909 }
<> 149:156823d33999 910
<> 149:156823d33999 911 if (n_words) {
<> 149:156823d33999 912 // Simulate clear of the interrupt flag
<> 149:156823d33999 913 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 149:156823d33999 914 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 149:156823d33999 915 }
<> 149:156823d33999 916 }
<> 149:156823d33999 917
<> 149:156823d33999 918 return n_words;
<> 149:156823d33999 919 }
<> 149:156823d33999 920
<> 149:156823d33999 921 static int serial_read_async(serial_t *obj)
<> 149:156823d33999 922 {
<> 149:156823d33999 923 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 924 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 925 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 926
<> 149:156823d33999 927 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
<> 149:156823d33999 928 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
<> 149:156823d33999 929 //if (rx_fifo_free == 0) {
<> 149:156823d33999 930 // return 0;
<> 149:156823d33999 931 //}
<> 149:156823d33999 932
<> 149:156823d33999 933 uint32_t bytes_per_word = obj->rx_buff.width / 8;
<> 149:156823d33999 934
<> 149:156823d33999 935 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
<> 149:156823d33999 936 int n_words = 0;
<> 149:156823d33999 937 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
<> 149:156823d33999 938 switch (bytes_per_word) {
<> 149:156823d33999 939 case 4:
<> 149:156823d33999 940 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 941 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 942 case 2:
<> 149:156823d33999 943 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 944 case 1:
<> 149:156823d33999 945 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 149:156823d33999 946 }
<> 149:156823d33999 947
<> 149:156823d33999 948 n_words ++;
<> 149:156823d33999 949 rx_fifo_busy -= bytes_per_word;
<> 149:156823d33999 950 obj->rx_buff.pos ++;
<> 149:156823d33999 951
<> 149:156823d33999 952 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 149:156823d33999 953 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 149:156823d33999 954 uint8_t *rx_cmp = rx;
<> 149:156823d33999 955 switch (bytes_per_word) {
<> 149:156823d33999 956 case 4:
<> 149:156823d33999 957 rx_cmp -= 2;
<> 149:156823d33999 958 case 2:
<> 149:156823d33999 959 rx_cmp --;
<> 149:156823d33999 960 case 1:
<> 149:156823d33999 961 rx_cmp --;
<> 149:156823d33999 962 }
<> 149:156823d33999 963 if (*rx_cmp == obj->char_match) {
<> 149:156823d33999 964 obj->char_found = 1;
<> 149:156823d33999 965 break;
<> 149:156823d33999 966 }
<> 149:156823d33999 967 }
<> 149:156823d33999 968 }
<> 149:156823d33999 969
<> 149:156823d33999 970 if (n_words) {
<> 149:156823d33999 971 // Simulate clear of the interrupt flag
<> 149:156823d33999 972 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 149:156823d33999 973 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 149:156823d33999 974 }
<> 149:156823d33999 975 }
<> 149:156823d33999 976
<> 149:156823d33999 977 return n_words;
<> 149:156823d33999 978 }
<> 149:156823d33999 979
<> 149:156823d33999 980 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
<> 149:156823d33999 981 {
<> 149:156823d33999 982 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 983 obj->tx_buff.length = length;
<> 149:156823d33999 984 obj->tx_buff.pos = 0;
<> 149:156823d33999 985 obj->tx_buff.width = width;
<> 149:156823d33999 986 }
<> 149:156823d33999 987
<> 149:156823d33999 988 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
<> 149:156823d33999 989 {
<> 149:156823d33999 990 obj->rx_buff.buffer = rx;
<> 149:156823d33999 991 obj->rx_buff.length = length;
<> 149:156823d33999 992 obj->rx_buff.pos = 0;
<> 149:156823d33999 993 obj->rx_buff.width = width;
<> 149:156823d33999 994 }
<> 149:156823d33999 995
<> 149:156823d33999 996 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 149:156823d33999 997 {
<> 149:156823d33999 998 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 999 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1000 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 1001
<> 149:156823d33999 1002 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1003 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 1004 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1005 obj->serial.vec = var->vec_async;
<> 149:156823d33999 1006 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
AnnaBridge 165:e614a9f1c9e2 1007 serial_enable_interrupt(obj, TxIrq, enable);
<> 149:156823d33999 1008 }
<> 149:156823d33999 1009
<> 149:156823d33999 1010 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 149:156823d33999 1011 {
<> 149:156823d33999 1012 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 149:156823d33999 1013 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1014 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 149:156823d33999 1015
<> 149:156823d33999 1016 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1017 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 149:156823d33999 1018 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1019 obj->serial.vec = var->vec_async;
<> 149:156823d33999 1020 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
AnnaBridge 165:e614a9f1c9e2 1021 serial_enable_interrupt(obj, RxIrq, enable);
AnnaBridge 165:e614a9f1c9e2 1022 }
AnnaBridge 165:e614a9f1c9e2 1023
AnnaBridge 165:e614a9f1c9e2 1024 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
AnnaBridge 165:e614a9f1c9e2 1025 {
AnnaBridge 165:e614a9f1c9e2 1026 if (enable) {
AnnaBridge 165:e614a9f1c9e2 1027 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1028 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1029 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1030
AnnaBridge 165:e614a9f1c9e2 1031 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
AnnaBridge 165:e614a9f1c9e2 1032 NVIC_EnableIRQ(modinit->irq_n);
AnnaBridge 165:e614a9f1c9e2 1033
AnnaBridge 165:e614a9f1c9e2 1034 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1035 // Multiple serial S/W objects for single UART H/W module possibly.
AnnaBridge 165:e614a9f1c9e2 1036 // Bind serial S/W object to UART H/W module as interrupt is enabled.
AnnaBridge 165:e614a9f1c9e2 1037 var->obj = obj;
AnnaBridge 165:e614a9f1c9e2 1038
AnnaBridge 165:e614a9f1c9e2 1039 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1040 // NOTE: Setting inten_msk first to avoid race condition
AnnaBridge 165:e614a9f1c9e2 1041 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1042 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1043 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1044 break;
AnnaBridge 165:e614a9f1c9e2 1045 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1046 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1047 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1048 break;
AnnaBridge 165:e614a9f1c9e2 1049 }
AnnaBridge 165:e614a9f1c9e2 1050 }
AnnaBridge 165:e614a9f1c9e2 1051 else { // disable
AnnaBridge 165:e614a9f1c9e2 1052 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1053 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1054 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1055 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1056 break;
AnnaBridge 165:e614a9f1c9e2 1057 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1058 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1059 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1060 break;
AnnaBridge 165:e614a9f1c9e2 1061 }
AnnaBridge 165:e614a9f1c9e2 1062 }
AnnaBridge 165:e614a9f1c9e2 1063 }
AnnaBridge 165:e614a9f1c9e2 1064
AnnaBridge 165:e614a9f1c9e2 1065 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
AnnaBridge 165:e614a9f1c9e2 1066 {
AnnaBridge 165:e614a9f1c9e2 1067 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1068 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1069 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1070
AnnaBridge 165:e614a9f1c9e2 1071 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1072
AnnaBridge 165:e614a9f1c9e2 1073 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 1074 serial_enable_interrupt(obj, irq, obj->serial.irq_en);
<> 149:156823d33999 1075 }
<> 149:156823d33999 1076
<> 149:156823d33999 1077 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
<> 149:156823d33999 1078 {
<> 149:156823d33999 1079 if (*dma_usage != DMA_USAGE_NEVER) {
<> 149:156823d33999 1080 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 1081 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
<> 149:156823d33999 1082 }
<> 149:156823d33999 1083 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 1084 *dma_usage = DMA_USAGE_NEVER;
<> 149:156823d33999 1085 }
<> 149:156823d33999 1086 }
<> 149:156823d33999 1087 else {
<> 149:156823d33999 1088 dma_channel_free(*dma_ch);
<> 149:156823d33999 1089 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 1090 }
<> 149:156823d33999 1091 }
<> 149:156823d33999 1092
<> 149:156823d33999 1093 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
<> 149:156823d33999 1094 {
<> 149:156823d33999 1095 int inten_msk = 0;
<> 149:156823d33999 1096
<> 149:156823d33999 1097 switch (irq) {
<> 149:156823d33999 1098 case RxIrq:
<> 149:156823d33999 1099 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
<> 149:156823d33999 1100 break;
<> 149:156823d33999 1101 case TxIrq:
<> 149:156823d33999 1102 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
<> 149:156823d33999 1103 break;
<> 149:156823d33999 1104 }
<> 149:156823d33999 1105
<> 149:156823d33999 1106 return !! inten_msk;
<> 149:156823d33999 1107 }
<> 149:156823d33999 1108
<> 149:156823d33999 1109 #endif // #if DEVICE_SERIAL_ASYNCH
<> 149:156823d33999 1110 #endif // #if DEVICE_SERIAL