David Saul / mbed-dev-bin

R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more information

Fork of mbed-dev-bin by Lancaster University

spi_api.h@4:98796b85dcf3, 2017-05-23 (annotated)

Committer:
DavidMS
Date:
Tue May 23 12:27:33 2017 +0000
Revision:
4:98796b85dcf3
Parent:
0:e1a608bb55e8 
basic_microbit_tx_train_controller_code: R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more details

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 0:e1a608bb55e8 1 /* mbed Microcontroller Library
jamesadevine 0:e1a608bb55e8 2 * Copyright (c) 2006-2013 ARM Limited
jamesadevine 0:e1a608bb55e8 3 *
jamesadevine 0:e1a608bb55e8 4 * Licensed under the Apache License, Version 2.0 (the "License");
jamesadevine 0:e1a608bb55e8 5 * you may not use this file except in compliance with the License.
jamesadevine 0:e1a608bb55e8 6 * You may obtain a copy of the License at
jamesadevine 0:e1a608bb55e8 7 *
jamesadevine 0:e1a608bb55e8 8 * http://www.apache.org/licenses/LICENSE-2.0
jamesadevine 0:e1a608bb55e8 9 *
jamesadevine 0:e1a608bb55e8 10 * Unless required by applicable law or agreed to in writing, software
jamesadevine 0:e1a608bb55e8 11 * distributed under the License is distributed on an "AS IS" BASIS,
jamesadevine 0:e1a608bb55e8 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
jamesadevine 0:e1a608bb55e8 13 * See the License for the specific language governing permissions and
jamesadevine 0:e1a608bb55e8 14 * limitations under the License.
jamesadevine 0:e1a608bb55e8 15 */
jamesadevine 0:e1a608bb55e8 16 #ifndef MBED_SPI_API_H
jamesadevine 0:e1a608bb55e8 17 #define MBED_SPI_API_H
jamesadevine 0:e1a608bb55e8 18
jamesadevine 0:e1a608bb55e8 19 #include "device.h"
jamesadevine 0:e1a608bb55e8 20 #include "dma_api.h"
jamesadevine 0:e1a608bb55e8 21 #include "buffer.h"
jamesadevine 0:e1a608bb55e8 22
jamesadevine 0:e1a608bb55e8 23 #if DEVICE_SPI
jamesadevine 0:e1a608bb55e8 24
jamesadevine 0:e1a608bb55e8 25 #define SPI_EVENT_ERROR (1 << 1)
jamesadevine 0:e1a608bb55e8 26 #define SPI_EVENT_COMPLETE (1 << 2)
jamesadevine 0:e1a608bb55e8 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
jamesadevine 0:e1a608bb55e8 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
jamesadevine 0:e1a608bb55e8 29
jamesadevine 0:e1a608bb55e8 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
jamesadevine 0:e1a608bb55e8 31
jamesadevine 0:e1a608bb55e8 32 #define SPI_FILL_WORD (0xFFFF)
jamesadevine 0:e1a608bb55e8 33
jamesadevine 0:e1a608bb55e8 34 #if DEVICE_SPI_ASYNCH
jamesadevine 0:e1a608bb55e8 35 /** Asynch spi hal structure
jamesadevine 0:e1a608bb55e8 36 */
jamesadevine 0:e1a608bb55e8 37 typedef struct {
jamesadevine 0:e1a608bb55e8 38 struct spi_s spi; /**< Target specific spi structure */
jamesadevine 0:e1a608bb55e8 39 struct buffer_s tx_buff; /**< Tx buffer */
jamesadevine 0:e1a608bb55e8 40 struct buffer_s rx_buff; /**< Rx buffer */
jamesadevine 0:e1a608bb55e8 41 } spi_t;
jamesadevine 0:e1a608bb55e8 42
jamesadevine 0:e1a608bb55e8 43 #else
jamesadevine 0:e1a608bb55e8 44 /** Non-asynch spi hal structure
jamesadevine 0:e1a608bb55e8 45 */
jamesadevine 0:e1a608bb55e8 46 typedef struct spi_s spi_t;
jamesadevine 0:e1a608bb55e8 47
jamesadevine 0:e1a608bb55e8 48 #endif
jamesadevine 0:e1a608bb55e8 49
jamesadevine 0:e1a608bb55e8 50 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 51 extern "C" {
jamesadevine 0:e1a608bb55e8 52 #endif
jamesadevine 0:e1a608bb55e8 53
jamesadevine 0:e1a608bb55e8 54 /**
jamesadevine 0:e1a608bb55e8 55 * \defgroup GeneralSPI SPI Configuration Functions
jamesadevine 0:e1a608bb55e8 56 * @{
jamesadevine 0:e1a608bb55e8 57 */
jamesadevine 0:e1a608bb55e8 58
jamesadevine 0:e1a608bb55e8 59 /** Initialize the SPI peripheral
jamesadevine 0:e1a608bb55e8 60 *
jamesadevine 0:e1a608bb55e8 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
jamesadevine 0:e1a608bb55e8 62 * @param[out] obj The SPI object to initialize
jamesadevine 0:e1a608bb55e8 63 * @param[in] mosi The pin to use for MOSI
jamesadevine 0:e1a608bb55e8 64 * @param[in] miso The pin to use for MISO
jamesadevine 0:e1a608bb55e8 65 * @param[in] sclk The pin to use for SCLK
jamesadevine 0:e1a608bb55e8 66 * @param[in] ssel The pin to use for SSEL
jamesadevine 0:e1a608bb55e8 67 */
jamesadevine 0:e1a608bb55e8 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
jamesadevine 0:e1a608bb55e8 69
jamesadevine 0:e1a608bb55e8 70 /** Release a SPI object
jamesadevine 0:e1a608bb55e8 71 *
jamesadevine 0:e1a608bb55e8 72 * TODO: spi_free is currently unimplemented
jamesadevine 0:e1a608bb55e8 73 * This will require reference counting at the C++ level to be safe
jamesadevine 0:e1a608bb55e8 74 *
jamesadevine 0:e1a608bb55e8 75 * Return the pins owned by the SPI object to their reset state
jamesadevine 0:e1a608bb55e8 76 * Disable the SPI peripheral
jamesadevine 0:e1a608bb55e8 77 * Disable the SPI clock
jamesadevine 0:e1a608bb55e8 78 * @param[in] obj The SPI object to deinitialize
jamesadevine 0:e1a608bb55e8 79 */
jamesadevine 0:e1a608bb55e8 80 void spi_free(spi_t *obj);
jamesadevine 0:e1a608bb55e8 81
jamesadevine 0:e1a608bb55e8 82 /** Configure the SPI format
jamesadevine 0:e1a608bb55e8 83 *
jamesadevine 0:e1a608bb55e8 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
jamesadevine 0:e1a608bb55e8 85 * @param[in,out] obj The SPI object to configure
jamesadevine 0:e1a608bb55e8 86 * @param[in] bits The number of bits per frame
jamesadevine 0:e1a608bb55e8 87 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
jamesadevine 0:e1a608bb55e8 88 * @param[in] slave Zero for master mode or non-zero for slave mode
jamesadevine 0:e1a608bb55e8 89 */
jamesadevine 0:e1a608bb55e8 90 void spi_format(spi_t *obj, int bits, int mode, int slave);
jamesadevine 0:e1a608bb55e8 91
jamesadevine 0:e1a608bb55e8 92 /** Set the SPI baud rate
jamesadevine 0:e1a608bb55e8 93 *
jamesadevine 0:e1a608bb55e8 94 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
jamesadevine 0:e1a608bb55e8 95 * Configures the SPI peripheral's baud rate
jamesadevine 0:e1a608bb55e8 96 * @param[in,out] obj The SPI object to configure
jamesadevine 0:e1a608bb55e8 97 * @param[in] hz The baud rate in Hz
jamesadevine 0:e1a608bb55e8 98 */
jamesadevine 0:e1a608bb55e8 99 void spi_frequency(spi_t *obj, int hz);
jamesadevine 0:e1a608bb55e8 100
jamesadevine 0:e1a608bb55e8 101 /**@}*/
jamesadevine 0:e1a608bb55e8 102 /**
jamesadevine 0:e1a608bb55e8 103 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
jamesadevine 0:e1a608bb55e8 104 * @{
jamesadevine 0:e1a608bb55e8 105 */
jamesadevine 0:e1a608bb55e8 106
jamesadevine 0:e1a608bb55e8 107 /** Write a byte out in master mode and receive a value
jamesadevine 0:e1a608bb55e8 108 *
jamesadevine 0:e1a608bb55e8 109 * @param[in] obj The SPI peripheral to use for sending
jamesadevine 0:e1a608bb55e8 110 * @param[in] value The value to send
jamesadevine 0:e1a608bb55e8 111 * @return Returns the value received during send
jamesadevine 0:e1a608bb55e8 112 */
jamesadevine 0:e1a608bb55e8 113 int spi_master_write(spi_t *obj, int value);
jamesadevine 0:e1a608bb55e8 114
jamesadevine 0:e1a608bb55e8 115 /** Check if a value is available to read
jamesadevine 0:e1a608bb55e8 116 *
jamesadevine 0:e1a608bb55e8 117 * @param[in] obj The SPI peripheral to check
jamesadevine 0:e1a608bb55e8 118 * @return non-zero if a value is available
jamesadevine 0:e1a608bb55e8 119 */
jamesadevine 0:e1a608bb55e8 120 int spi_slave_receive(spi_t *obj);
jamesadevine 0:e1a608bb55e8 121
jamesadevine 0:e1a608bb55e8 122 /** Get a received value out of the SPI receive buffer in slave mode
jamesadevine 0:e1a608bb55e8 123 *
jamesadevine 0:e1a608bb55e8 124 * Blocks until a value is available
jamesadevine 0:e1a608bb55e8 125 * @param[in] obj The SPI peripheral to read
jamesadevine 0:e1a608bb55e8 126 * @return The value received
jamesadevine 0:e1a608bb55e8 127 */
jamesadevine 0:e1a608bb55e8 128 int spi_slave_read(spi_t *obj);
jamesadevine 0:e1a608bb55e8 129
jamesadevine 0:e1a608bb55e8 130 /** Write a value to the SPI peripheral in slave mode
jamesadevine 0:e1a608bb55e8 131 *
jamesadevine 0:e1a608bb55e8 132 * Blocks until the SPI peripheral can be written to
jamesadevine 0:e1a608bb55e8 133 * @param[in] obj The SPI peripheral to write
jamesadevine 0:e1a608bb55e8 134 * @param[in] value The value to write
jamesadevine 0:e1a608bb55e8 135 */
jamesadevine 0:e1a608bb55e8 136 void spi_slave_write(spi_t *obj, int value);
jamesadevine 0:e1a608bb55e8 137
jamesadevine 0:e1a608bb55e8 138 /** Checks if the specified SPI peripheral is in use
jamesadevine 0:e1a608bb55e8 139 *
jamesadevine 0:e1a608bb55e8 140 * @param[in] obj The SPI peripheral to check
jamesadevine 0:e1a608bb55e8 141 * @return non-zero if the peripheral is currently transmitting
jamesadevine 0:e1a608bb55e8 142 */
jamesadevine 0:e1a608bb55e8 143 int spi_busy(spi_t *obj);
jamesadevine 0:e1a608bb55e8 144
jamesadevine 0:e1a608bb55e8 145 /** Get the module number
jamesadevine 0:e1a608bb55e8 146 *
jamesadevine 0:e1a608bb55e8 147 * @param[in] obj The SPI peripheral to check
jamesadevine 0:e1a608bb55e8 148 * @return The module number
jamesadevine 0:e1a608bb55e8 149 */
jamesadevine 0:e1a608bb55e8 150 uint8_t spi_get_module(spi_t *obj);
jamesadevine 0:e1a608bb55e8 151
jamesadevine 0:e1a608bb55e8 152 /**@}*/
jamesadevine 0:e1a608bb55e8 153
jamesadevine 0:e1a608bb55e8 154 #if DEVICE_SPI_ASYNCH
jamesadevine 0:e1a608bb55e8 155 /**
jamesadevine 0:e1a608bb55e8 156 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
jamesadevine 0:e1a608bb55e8 157 * @{
jamesadevine 0:e1a608bb55e8 158 */
jamesadevine 0:e1a608bb55e8 159
jamesadevine 0:e1a608bb55e8 160 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
jamesadevine 0:e1a608bb55e8 161 *
jamesadevine 0:e1a608bb55e8 162 * @param[in] obj The SPI object which holds the transfer information
jamesadevine 0:e1a608bb55e8 163 * @param[in] tx The buffer to send
jamesadevine 0:e1a608bb55e8 164 * @param[in] tx_length The number of words to transmit
jamesadevine 0:e1a608bb55e8 165 * @param[in] rx The buffer to receive
jamesadevine 0:e1a608bb55e8 166 * @param[in] rx_length The number of words to receive
jamesadevine 0:e1a608bb55e8 167 * @param[in] bit_width The bit width of buffer words
jamesadevine 0:e1a608bb55e8 168 * @param[in] event The logical OR of events to be registered
jamesadevine 0:e1a608bb55e8 169 * @param[in] handler SPI interrupt handler
jamesadevine 0:e1a608bb55e8 170 * @param[in] hint A suggestion for how to use DMA with this transfer
jamesadevine 0:e1a608bb55e8 171 */
jamesadevine 0:e1a608bb55e8 172 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
jamesadevine 0:e1a608bb55e8 173
jamesadevine 0:e1a608bb55e8 174 /** The asynchronous IRQ handler
jamesadevine 0:e1a608bb55e8 175 *
jamesadevine 0:e1a608bb55e8 176 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
jamesadevine 0:e1a608bb55e8 177 * conditions, such as buffer overflows or transfer complete.
jamesadevine 0:e1a608bb55e8 178 * @param[in] obj The SPI object which holds the transfer information
jamesadevine 0:e1a608bb55e8 179 * @return event flags if a transfer termination condition was met or 0 otherwise.
jamesadevine 0:e1a608bb55e8 180 */
jamesadevine 0:e1a608bb55e8 181 uint32_t spi_irq_handler_asynch(spi_t *obj);
jamesadevine 0:e1a608bb55e8 182
jamesadevine 0:e1a608bb55e8 183 /** Attempts to determine if the SPI peripheral is already in use.
jamesadevine 0:e1a608bb55e8 184 *
jamesadevine 0:e1a608bb55e8 185 * If a temporary DMA channel has been allocated, peripheral is in use.
jamesadevine 0:e1a608bb55e8 186 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
jamesadevine 0:e1a608bb55e8 187 * channel were allocated.
jamesadevine 0:e1a608bb55e8 188 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
jamesadevine 0:e1a608bb55e8 189 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
jamesadevine 0:e1a608bb55e8 190 * there are any bytes in the FIFOs.
jamesadevine 0:e1a608bb55e8 191 * @param[in] obj The SPI object to check for activity
jamesadevine 0:e1a608bb55e8 192 * @return non-zero if the SPI port is active or zero if it is not.
jamesadevine 0:e1a608bb55e8 193 */
jamesadevine 0:e1a608bb55e8 194 uint8_t spi_active(spi_t *obj);
jamesadevine 0:e1a608bb55e8 195
jamesadevine 0:e1a608bb55e8 196 /** Abort an SPI transfer
jamesadevine 0:e1a608bb55e8 197 *
jamesadevine 0:e1a608bb55e8 198 * @param obj The SPI peripheral to stop
jamesadevine 0:e1a608bb55e8 199 */
jamesadevine 0:e1a608bb55e8 200 void spi_abort_asynch(spi_t *obj);
jamesadevine 0:e1a608bb55e8 201
jamesadevine 0:e1a608bb55e8 202
jamesadevine 0:e1a608bb55e8 203 #endif
jamesadevine 0:e1a608bb55e8 204
jamesadevine 0:e1a608bb55e8 205 /**@}*/
jamesadevine 0:e1a608bb55e8 206
jamesadevine 0:e1a608bb55e8 207 #ifdef __cplusplus
jamesadevine 0:e1a608bb55e8 208 }
jamesadevine 0:e1a608bb55e8 209 #endif // __cplusplus
jamesadevine 0:e1a608bb55e8 210
jamesadevine 0:e1a608bb55e8 211 #endif // SPI_DEVICE
jamesadevine 0:e1a608bb55e8 212
jamesadevine 0:e1a608bb55e8 213 #endif // MBED_SPI_API_H