R1 code for micro:bit based train controller code, requires second micro:bit running tx code to operate - see https://meanderingpi.wordpress.com/ for more information
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TARGET_NRF51_MICROBIT/TOOLCHAIN_ARM_STD/nRF51822.sct@4:1a27ae39e33f, 2017-05-23 (annotated)
- Committer:
- DavidMS
- Date:
- Tue May 23 10:42:56 2017 +0000
- Revision:
- 4:1a27ae39e33f
- Parent:
- 2:e32c8485c88f
First working micro:bit motor control rx code, need be run with matching tx code
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
jamesadevine | 2:e32c8485c88f | 1 | ;WITHOUT SOFTDEVICE: |
jamesadevine | 2:e32c8485c88f | 2 | ;LR_IROM1 0x00000000 0x00040000 { |
jamesadevine | 2:e32c8485c88f | 3 | ; ER_IROM1 0x00000000 0x00040000 { |
jamesadevine | 2:e32c8485c88f | 4 | ; *.o (RESET, +First) |
jamesadevine | 2:e32c8485c88f | 5 | ; *(InRoot$$Sections) |
jamesadevine | 2:e32c8485c88f | 6 | ; .ANY (+RO) |
jamesadevine | 2:e32c8485c88f | 7 | ; } |
jamesadevine | 2:e32c8485c88f | 8 | ; RW_IRAM1 0x20000000 0x00004000 { |
jamesadevine | 2:e32c8485c88f | 9 | ; .ANY (+RW +ZI) |
jamesadevine | 2:e32c8485c88f | 10 | ; } |
jamesadevine | 2:e32c8485c88f | 11 | ;} |
jamesadevine | 2:e32c8485c88f | 12 | ; |
jamesadevine | 2:e32c8485c88f | 13 | ;WITH SOFTDEVICE: |
jamesadevine | 1:a7c51b5e0534 | 14 | |
jamesadevine | 2:e32c8485c88f | 15 | LR_IROM1 0x18000 0x0028000 { |
jamesadevine | 2:e32c8485c88f | 16 | ER_IROM1 0x18000 0x0028000 { |
jamesadevine | 2:e32c8485c88f | 17 | *.o (RESET, +First) |
jamesadevine | 2:e32c8485c88f | 18 | *(InRoot$$Sections) |
jamesadevine | 2:e32c8485c88f | 19 | .ANY (+RO) |
jamesadevine | 2:e32c8485c88f | 20 | } |
jamesadevine | 2:e32c8485c88f | 21 | RW_IRAM1 0x20002000 0x00002000 { |
jamesadevine | 2:e32c8485c88f | 22 | .ANY (+RW +ZI) |
jamesadevine | 2:e32c8485c88f | 23 | } |
jamesadevine | 2:e32c8485c88f | 24 | } |