RFID_and_Bluetooth_testing - Reading a RFID tag (13.56MHz) and sending its dat…

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Clovis Fritzen / Mbed 2 deprecated RFID_and_Bluetooth_testing

Reading a RFID tag (13.56MHz) and sending its data through bluetooth (HC-05 module) to an Android cellphone (using the BlueTerm APP).

Dependencies: TextLCD beep mbed

Fork of RFID-RC522 by Thomas Kirchner

MFRC522.h@3:bf44d10e4904, 2014-09-23 (annotated)

Committer:: Clovis
Date:: Tue Sep 23 07:08:59 2014 +0000
Revision:: 3:bf44d10e4904
Parent:: 1:63d729186747

initial release: reads a RFID tag (13.56Mhz) and sends the data of the tag to a cellphone (through HC-05 bluetooth module). Tested for the FRDM-K64F (Freescale) platform.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AtomX	0:efd786b99a72	1	/**
AtomX	0:efd786b99a72	2	* MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
AtomX	0:efd786b99a72	3	* Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
AtomX	0:efd786b99a72	4	* Created by Miguel Balboa (circuitito.com), Jan, 2012.
AtomX	0:efd786b99a72	5	* Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
AtomX	0:efd786b99a72	6	* Ported to mbed by Martin Olejar, Dec, 2013
AtomX	0:efd786b99a72	7	*
AtomX	0:efd786b99a72	8	* Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
AtomX	0:efd786b99a72	9	* Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
AtomX	0:efd786b99a72	10	*
AtomX	0:efd786b99a72	11	* There are three hardware components involved:
AtomX	0:efd786b99a72	12	* 1) The micro controller: An Arduino
AtomX	0:efd786b99a72	13	* 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
AtomX	0:efd786b99a72	14	* 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
AtomX	0:efd786b99a72	15	*
AtomX	0:efd786b99a72	16	* The microcontroller and card reader uses SPI for communication.
AtomX	0:efd786b99a72	17	* The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
AtomX	0:efd786b99a72	18	*
AtomX	0:efd786b99a72	19	* The card reader and the tags communicate using a 13.56MHz electromagnetic field.
AtomX	0:efd786b99a72	20	* The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
AtomX	0:efd786b99a72	21	* A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
AtomX	0:efd786b99a72	22	* Details are found in chapter 6, Type A: Initialization and anticollision.
AtomX	0:efd786b99a72	23	*
AtomX	0:efd786b99a72	24	* If only the PICC UID is wanted, the above documents has all the needed information.
AtomX	0:efd786b99a72	25	* To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
AtomX	0:efd786b99a72	26	* The MIFARE Classic chips and protocol is described in the datasheets:
AtomX	0:efd786b99a72	27	* 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
AtomX	0:efd786b99a72	28	* 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
AtomX	0:efd786b99a72	29	* Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
AtomX	0:efd786b99a72	30	* The MIFARE Ultralight chip and protocol is described in the datasheets:
AtomX	0:efd786b99a72	31	* Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
AtomX	0:efd786b99a72	32	* Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
AtomX	0:efd786b99a72	33	*
AtomX	0:efd786b99a72	34	* MIFARE Classic 1K (MF1S503x):
AtomX	0:efd786b99a72	35	* Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
AtomX	0:efd786b99a72	36	* The blocks are numbered 0-63.
AtomX	0:efd786b99a72	37	* Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
AtomX	0:efd786b99a72	38	* Bytes 0-5: Key A
AtomX	0:efd786b99a72	39	* Bytes 6-8: Access Bits
AtomX	0:efd786b99a72	40	* Bytes 9: User data
AtomX	0:efd786b99a72	41	* Bytes 10-15: Key B (or user data)
AtomX	0:efd786b99a72	42	* Block 0 is read only manufacturer data.
AtomX	0:efd786b99a72	43	* To access a block, an authentication using a key from the block's sector must be performed first.
AtomX	0:efd786b99a72	44	* Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
AtomX	0:efd786b99a72	45	* All keys are set to FFFFFFFFFFFFh at chip delivery.
AtomX	0:efd786b99a72	46	* Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
AtomX	0:efd786b99a72	47	* To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
AtomX	0:efd786b99a72	48	* MIFARE Classic 4K (MF1S703x):
AtomX	0:efd786b99a72	49	* Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
AtomX	0:efd786b99a72	50	* The blocks are numbered 0-255.
AtomX	0:efd786b99a72	51	* The last block in each sector is the Sector Trailer like above.
AtomX	0:efd786b99a72	52	* MIFARE Classic Mini (MF1 IC S20):
AtomX	0:efd786b99a72	53	* Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
AtomX	0:efd786b99a72	54	* The blocks are numbered 0-19.
AtomX	0:efd786b99a72	55	* The last block in each sector is the Sector Trailer like above.
AtomX	0:efd786b99a72	56	*
AtomX	0:efd786b99a72	57	* MIFARE Ultralight (MF0ICU1):
AtomX	0:efd786b99a72	58	* Has 16 pages of 4 bytes = 64 bytes.
AtomX	0:efd786b99a72	59	* Pages 0 + 1 is used for the 7-byte UID.
AtomX	0:efd786b99a72	60	* Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
AtomX	0:efd786b99a72	61	* Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
AtomX	0:efd786b99a72	62	* Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
AtomX	0:efd786b99a72	63	* MIFARE Ultralight C (MF0ICU2):
AtomX	0:efd786b99a72	64	* Has 48 pages of 4 bytes = 64 bytes.
AtomX	0:efd786b99a72	65	* Pages 0 + 1 is used for the 7-byte UID.
AtomX	0:efd786b99a72	66	* Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
AtomX	0:efd786b99a72	67	* Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
AtomX	0:efd786b99a72	68	* Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
AtomX	0:efd786b99a72	69	* Page 40 Lock bytes
AtomX	0:efd786b99a72	70	* Page 41 16 bit one way counter
AtomX	0:efd786b99a72	71	* Pages 42-43 Authentication configuration
AtomX	0:efd786b99a72	72	* Pages 44-47 Authentication key
AtomX	0:efd786b99a72	73	*/
AtomX	0:efd786b99a72	74	#ifndef MFRC522_h
AtomX	0:efd786b99a72	75	#define MFRC522_h
AtomX	0:efd786b99a72	76
AtomX	0:efd786b99a72	77	#include "mbed.h"
AtomX	0:efd786b99a72	78
AtomX	0:efd786b99a72	79	class MFRC522 {
AtomX	0:efd786b99a72	80	public:
AtomX	0:efd786b99a72	81
AtomX	1:63d729186747	82	/**
AtomX	1:63d729186747	83	* MFRC522 registers (described in chapter 9 of the datasheet).
AtomX	1:63d729186747	84	* When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
AtomX	1:63d729186747	85	*/
AtomX	0:efd786b99a72	86	enum PCD_Register {
AtomX	0:efd786b99a72	87	// Page 0: Command and status
AtomX	0:efd786b99a72	88	// 0x00 // reserved for future use
AtomX	0:efd786b99a72	89	CommandReg = 0x01 << 1, // starts and stops command execution
AtomX	0:efd786b99a72	90	ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
AtomX	0:efd786b99a72	91	DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
AtomX	0:efd786b99a72	92	ComIrqReg = 0x04 << 1, // interrupt request bits
AtomX	0:efd786b99a72	93	DivIrqReg = 0x05 << 1, // interrupt request bits
AtomX	0:efd786b99a72	94	ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
AtomX	0:efd786b99a72	95	Status1Reg = 0x07 << 1, // communication status bits
AtomX	0:efd786b99a72	96	Status2Reg = 0x08 << 1, // receiver and transmitter status bits
AtomX	0:efd786b99a72	97	FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
AtomX	0:efd786b99a72	98	FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
AtomX	0:efd786b99a72	99	WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
AtomX	0:efd786b99a72	100	ControlReg = 0x0C << 1, // miscellaneous control registers
AtomX	0:efd786b99a72	101	BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
AtomX	0:efd786b99a72	102	CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
AtomX	0:efd786b99a72	103	// 0x0F // reserved for future use
AtomX	0:efd786b99a72	104
AtomX	0:efd786b99a72	105	// Page 1:Command
AtomX	0:efd786b99a72	106	// 0x10 // reserved for future use
AtomX	0:efd786b99a72	107	ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
AtomX	0:efd786b99a72	108	TxModeReg = 0x12 << 1, // defines transmission data rate and framing
AtomX	0:efd786b99a72	109	RxModeReg = 0x13 << 1, // defines reception data rate and framing
AtomX	0:efd786b99a72	110	TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
AtomX	0:efd786b99a72	111	TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
AtomX	0:efd786b99a72	112	TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
AtomX	0:efd786b99a72	113	RxSelReg = 0x17 << 1, // selects internal receiver settings
AtomX	0:efd786b99a72	114	RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
AtomX	0:efd786b99a72	115	DemodReg = 0x19 << 1, // defines demodulator settings
AtomX	0:efd786b99a72	116	// 0x1A // reserved for future use
AtomX	0:efd786b99a72	117	// 0x1B // reserved for future use
AtomX	0:efd786b99a72	118	MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
AtomX	0:efd786b99a72	119	MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
AtomX	0:efd786b99a72	120	// 0x1E // reserved for future use
AtomX	0:efd786b99a72	121	SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
AtomX	0:efd786b99a72	122
AtomX	0:efd786b99a72	123	// Page 2: Configuration
AtomX	0:efd786b99a72	124	// 0x20 // reserved for future use
AtomX	0:efd786b99a72	125	CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
AtomX	0:efd786b99a72	126	CRCResultRegL = 0x22 << 1,
AtomX	0:efd786b99a72	127	// 0x23 // reserved for future use
AtomX	0:efd786b99a72	128	ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
AtomX	0:efd786b99a72	129	// 0x25 // reserved for future use
AtomX	0:efd786b99a72	130	RFCfgReg = 0x26 << 1, // configures the receiver gain
AtomX	0:efd786b99a72	131	GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
AtomX	0:efd786b99a72	132	CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
AtomX	0:efd786b99a72	133	ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
AtomX	0:efd786b99a72	134	TModeReg = 0x2A << 1, // defines settings for the internal timer
AtomX	0:efd786b99a72	135	TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
AtomX	0:efd786b99a72	136	TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
AtomX	0:efd786b99a72	137	TReloadRegL = 0x2D << 1,
AtomX	0:efd786b99a72	138	TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
AtomX	0:efd786b99a72	139	TCntValueRegL = 0x2F << 1,
AtomX	0:efd786b99a72	140
AtomX	0:efd786b99a72	141	// Page 3:Test Registers
AtomX	0:efd786b99a72	142	// 0x30 // reserved for future use
AtomX	0:efd786b99a72	143	TestSel1Reg = 0x31 << 1, // general test signal configuration
AtomX	0:efd786b99a72	144	TestSel2Reg = 0x32 << 1, // general test signal configuration
AtomX	0:efd786b99a72	145	TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
AtomX	0:efd786b99a72	146	TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
AtomX	0:efd786b99a72	147	TestBusReg = 0x35 << 1, // shows the status of the internal test bus
AtomX	0:efd786b99a72	148	AutoTestReg = 0x36 << 1, // controls the digital self test
AtomX	0:efd786b99a72	149	VersionReg = 0x37 << 1, // shows the software version
AtomX	0:efd786b99a72	150	AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
AtomX	0:efd786b99a72	151	TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
AtomX	0:efd786b99a72	152	TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
AtomX	0:efd786b99a72	153	TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
AtomX	0:efd786b99a72	154	// 0x3C // reserved for production tests
AtomX	0:efd786b99a72	155	// 0x3D // reserved for production tests
AtomX	0:efd786b99a72	156	// 0x3E // reserved for production tests
AtomX	0:efd786b99a72	157	// 0x3F // reserved for production tests
AtomX	0:efd786b99a72	158	};
AtomX	0:efd786b99a72	159
AtomX	0:efd786b99a72	160	// MFRC522 commands Described in chapter 10 of the datasheet.
AtomX	0:efd786b99a72	161	enum PCD_Command {
AtomX	0:efd786b99a72	162	PCD_Idle = 0x00, // no action, cancels current command execution
AtomX	0:efd786b99a72	163	PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
AtomX	0:efd786b99a72	164	PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
AtomX	0:efd786b99a72	165	PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
AtomX	0:efd786b99a72	166	PCD_Transmit = 0x04, // transmits data from the FIFO buffer
AtomX	0:efd786b99a72	167	PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
AtomX	0:efd786b99a72	168	PCD_Receive = 0x08, // activates the receiver circuits
AtomX	0:efd786b99a72	169	PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
AtomX	0:efd786b99a72	170	PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
AtomX	0:efd786b99a72	171	PCD_SoftReset = 0x0F // resets the MFRC522
AtomX	0:efd786b99a72	172	};
AtomX	0:efd786b99a72	173
AtomX	0:efd786b99a72	174	// Commands sent to the PICC.
AtomX	0:efd786b99a72	175	enum PICC_Command {
AtomX	0:efd786b99a72	176	// The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
AtomX	0:efd786b99a72	177	PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
AtomX	0:efd786b99a72	178	PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
AtomX	0:efd786b99a72	179	PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
AtomX	0:efd786b99a72	180	PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
AtomX	0:efd786b99a72	181	PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
AtomX	0:efd786b99a72	182	PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
AtomX	0:efd786b99a72	183	PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
AtomX	0:efd786b99a72	184
AtomX	0:efd786b99a72	185	// The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
AtomX	0:efd786b99a72	186	// Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
AtomX	0:efd786b99a72	187	// The read/write commands can also be used for MIFARE Ultralight.
AtomX	0:efd786b99a72	188	PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
AtomX	0:efd786b99a72	189	PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
AtomX	0:efd786b99a72	190	PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
AtomX	0:efd786b99a72	191	PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
AtomX	0:efd786b99a72	192	PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
AtomX	0:efd786b99a72	193	PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
AtomX	0:efd786b99a72	194	PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
AtomX	0:efd786b99a72	195	PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
AtomX	0:efd786b99a72	196
AtomX	0:efd786b99a72	197	// The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
AtomX	0:efd786b99a72	198	// The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
AtomX	0:efd786b99a72	199	PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
AtomX	0:efd786b99a72	200	};
AtomX	0:efd786b99a72	201
AtomX	0:efd786b99a72	202	// MIFARE constants that does not fit anywhere else
AtomX	0:efd786b99a72	203	enum MIFARE_Misc {
AtomX	0:efd786b99a72	204	MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
AtomX	0:efd786b99a72	205	MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
AtomX	0:efd786b99a72	206	};
AtomX	0:efd786b99a72	207
AtomX	0:efd786b99a72	208	// PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
AtomX	0:efd786b99a72	209	enum PICC_Type {
AtomX	0:efd786b99a72	210	PICC_TYPE_UNKNOWN = 0,
AtomX	0:efd786b99a72	211	PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
AtomX	0:efd786b99a72	212	PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
AtomX	0:efd786b99a72	213	PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
AtomX	0:efd786b99a72	214	PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
AtomX	0:efd786b99a72	215	PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
AtomX	0:efd786b99a72	216	PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
AtomX	0:efd786b99a72	217	PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
AtomX	0:efd786b99a72	218	PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
AtomX	0:efd786b99a72	219	PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
AtomX	0:efd786b99a72	220	};
AtomX	0:efd786b99a72	221
AtomX	0:efd786b99a72	222	// Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
AtomX	0:efd786b99a72	223	enum StatusCode {
AtomX	0:efd786b99a72	224	STATUS_OK = 1, // Success
AtomX	0:efd786b99a72	225	STATUS_ERROR = 2, // Error in communication
AtomX	0:efd786b99a72	226	STATUS_COLLISION = 3, // Collision detected
AtomX	0:efd786b99a72	227	STATUS_TIMEOUT = 4, // Timeout in communication.
AtomX	0:efd786b99a72	228	STATUS_NO_ROOM = 5, // A buffer is not big enough.
AtomX	0:efd786b99a72	229	STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
AtomX	0:efd786b99a72	230	STATUS_INVALID = 7, // Invalid argument.
AtomX	0:efd786b99a72	231	STATUS_CRC_WRONG = 8, // The CRC_A does not match
AtomX	0:efd786b99a72	232	STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
AtomX	0:efd786b99a72	233	};
AtomX	0:efd786b99a72	234
AtomX	0:efd786b99a72	235	// A struct used for passing the UID of a PICC.
AtomX	0:efd786b99a72	236	typedef struct {
AtomX	0:efd786b99a72	237	uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
AtomX	0:efd786b99a72	238	uint8_t uidByte[10];
AtomX	0:efd786b99a72	239	uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
AtomX	0:efd786b99a72	240	} Uid;
AtomX	0:efd786b99a72	241
AtomX	0:efd786b99a72	242	// A struct used for passing a MIFARE Crypto1 key
AtomX	0:efd786b99a72	243	typedef struct {
AtomX	0:efd786b99a72	244	uint8_t keyByte[MF_KEY_SIZE];
AtomX	0:efd786b99a72	245	} MIFARE_Key;
AtomX	0:efd786b99a72	246
AtomX	0:efd786b99a72	247	// Member variables
AtomX	0:efd786b99a72	248	Uid uid; // Used by PICC_ReadCardSerial().
AtomX	0:efd786b99a72	249
AtomX	0:efd786b99a72	250	// Size of the MFRC522 FIFO
AtomX	0:efd786b99a72	251	static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
AtomX	0:efd786b99a72	252
AtomX	0:efd786b99a72	253	/**
AtomX	0:efd786b99a72	254	* MFRC522 constructor
AtomX	0:efd786b99a72	255	*
AtomX	0:efd786b99a72	256	* @param mosi SPI MOSI pin
AtomX	0:efd786b99a72	257	* @param miso SPI MISO pin
AtomX	0:efd786b99a72	258	* @param sclk SPI SCLK pin
AtomX	0:efd786b99a72	259	* @param cs SPI CS pin
AtomX	0:efd786b99a72	260	* @param reset Reset pin
AtomX	0:efd786b99a72	261	*/
AtomX	0:efd786b99a72	262	MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
AtomX	0:efd786b99a72	263
AtomX	0:efd786b99a72	264	/**
AtomX	0:efd786b99a72	265	* MFRC522 destructor
AtomX	0:efd786b99a72	266	*/
AtomX	0:efd786b99a72	267	~MFRC522();
AtomX	1:63d729186747	268
AtomX	1:63d729186747	269
AtomX	1:63d729186747	270	// ************************************************************************************
AtomX	1:63d729186747	271	//! @name Functions for manipulating the MFRC522
AtomX	1:63d729186747	272	// ************************************************************************************
AtomX	1:63d729186747	273	//@{
AtomX	0:efd786b99a72	274
AtomX	0:efd786b99a72	275	/**
AtomX	0:efd786b99a72	276	* Initializes the MFRC522 chip.
AtomX	0:efd786b99a72	277	*/
AtomX	0:efd786b99a72	278	void PCD_Init (void);
AtomX	0:efd786b99a72	279
AtomX	0:efd786b99a72	280	/**
AtomX	0:efd786b99a72	281	* Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
AtomX	0:efd786b99a72	282	*/
AtomX	0:efd786b99a72	283	void PCD_Reset (void);
AtomX	0:efd786b99a72	284
AtomX	0:efd786b99a72	285	/**
AtomX	0:efd786b99a72	286	* Turns the antenna on by enabling pins TX1 and TX2.
AtomX	0:efd786b99a72	287	* After a reset these pins disabled.
AtomX	0:efd786b99a72	288	*/
AtomX	0:efd786b99a72	289	void PCD_AntennaOn (void);
AtomX	0:efd786b99a72	290
AtomX	0:efd786b99a72	291	/**
AtomX	0:efd786b99a72	292	* Writes a byte to the specified register in the MFRC522 chip.
AtomX	0:efd786b99a72	293	* The interface is described in the datasheet section 8.1.2.
AtomX	0:efd786b99a72	294	*
AtomX	0:efd786b99a72	295	* @param reg The register to write to. One of the PCD_Register enums.
AtomX	0:efd786b99a72	296	* @param value The value to write.
AtomX	0:efd786b99a72	297	*/
AtomX	0:efd786b99a72	298	void PCD_WriteRegister (uint8_t reg, uint8_t value);
AtomX	0:efd786b99a72	299
AtomX	0:efd786b99a72	300	/**
AtomX	0:efd786b99a72	301	* Writes a number of bytes to the specified register in the MFRC522 chip.
AtomX	0:efd786b99a72	302	* The interface is described in the datasheet section 8.1.2.
AtomX	0:efd786b99a72	303	*
AtomX	0:efd786b99a72	304	* @param reg The register to write to. One of the PCD_Register enums.
AtomX	0:efd786b99a72	305	* @param count The number of bytes to write to the register
AtomX	0:efd786b99a72	306	* @param values The values to write. Byte array.
AtomX	0:efd786b99a72	307	*/
AtomX	0:efd786b99a72	308	void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
AtomX	0:efd786b99a72	309
AtomX	0:efd786b99a72	310	/**
AtomX	0:efd786b99a72	311	* Reads a byte from the specified register in the MFRC522 chip.
AtomX	0:efd786b99a72	312	* The interface is described in the datasheet section 8.1.2.
AtomX	0:efd786b99a72	313	*
AtomX	0:efd786b99a72	314	* @param reg The register to read from. One of the PCD_Register enums.
AtomX	0:efd786b99a72	315	* @returns Register value
AtomX	0:efd786b99a72	316	*/
AtomX	0:efd786b99a72	317	uint8_t PCD_ReadRegister (uint8_t reg);
AtomX	0:efd786b99a72	318
AtomX	0:efd786b99a72	319	/**
AtomX	0:efd786b99a72	320	* Reads a number of bytes from the specified register in the MFRC522 chip.
AtomX	0:efd786b99a72	321	* The interface is described in the datasheet section 8.1.2.
AtomX	0:efd786b99a72	322	*
AtomX	0:efd786b99a72	323	* @param reg The register to read from. One of the PCD_Register enums.
AtomX	0:efd786b99a72	324	* @param count The number of bytes to read.
AtomX	0:efd786b99a72	325	* @param values Byte array to store the values in.
AtomX	0:efd786b99a72	326	* @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
AtomX	0:efd786b99a72	327	*/
AtomX	0:efd786b99a72	328	void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
AtomX	0:efd786b99a72	329
AtomX	0:efd786b99a72	330	/**
AtomX	0:efd786b99a72	331	* Sets the bits given in mask in register reg.
AtomX	0:efd786b99a72	332	*
AtomX	0:efd786b99a72	333	* @param reg The register to update. One of the PCD_Register enums.
AtomX	0:efd786b99a72	334	* @param mask The bits to set.
AtomX	0:efd786b99a72	335	*/
AtomX	0:efd786b99a72	336	void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
AtomX	0:efd786b99a72	337
AtomX	0:efd786b99a72	338	/**
AtomX	0:efd786b99a72	339	* Clears the bits given in mask from register reg.
AtomX	0:efd786b99a72	340	*
AtomX	0:efd786b99a72	341	* @param reg The register to update. One of the PCD_Register enums.
AtomX	0:efd786b99a72	342	* @param mask The bits to clear.
AtomX	0:efd786b99a72	343	*/
AtomX	0:efd786b99a72	344	void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
AtomX	0:efd786b99a72	345
AtomX	0:efd786b99a72	346	/**
AtomX	0:efd786b99a72	347	* Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
AtomX	0:efd786b99a72	348	*
AtomX	0:efd786b99a72	349	* @param data Pointer to the data to transfer to the FIFO for CRC calculation.
AtomX	0:efd786b99a72	350	* @param length The number of bytes to transfer.
AtomX	0:efd786b99a72	351	* @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
AtomX	0:efd786b99a72	352	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	0:efd786b99a72	353	*/
AtomX	0:efd786b99a72	354	uint8_t PCD_CalculateCRC (uint8_t data, uint8_t length, uint8_t result);
AtomX	0:efd786b99a72	355
AtomX	0:efd786b99a72	356	/**
AtomX	0:efd786b99a72	357	* Executes the Transceive command.
AtomX	0:efd786b99a72	358	* CRC validation can only be done if backData and backLen are specified.
AtomX	0:efd786b99a72	359	*
AtomX	0:efd786b99a72	360	* @param sendData Pointer to the data to transfer to the FIFO.
AtomX	0:efd786b99a72	361	* @param sendLen Number of bytes to transfer to the FIFO.
AtomX	0:efd786b99a72	362	* @param backData NULL or pointer to buffer if data should be read back after executing the command.
AtomX	0:efd786b99a72	363	* @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX	0:efd786b99a72	364	* @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
AtomX	0:efd786b99a72	365	* @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX	0:efd786b99a72	366	* @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX	1:63d729186747	367	*
AtomX	0:efd786b99a72	368	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	0:efd786b99a72	369	*/
AtomX	0:efd786b99a72	370	uint8_t PCD_TransceiveData (uint8_t *sendData,
AtomX	0:efd786b99a72	371	uint8_t sendLen,
AtomX	0:efd786b99a72	372	uint8_t *backData,
AtomX	0:efd786b99a72	373	uint8_t *backLen,
AtomX	0:efd786b99a72	374	uint8_t *validBits = NULL,
AtomX	0:efd786b99a72	375	uint8_t rxAlign = 0,
AtomX	0:efd786b99a72	376	bool checkCRC = false);
AtomX	0:efd786b99a72	377
AtomX	0:efd786b99a72	378
AtomX	1:63d729186747	379	/**
AtomX	1:63d729186747	380	* Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
AtomX	1:63d729186747	381	* CRC validation can only be done if backData and backLen are specified.
AtomX	1:63d729186747	382	*
AtomX	1:63d729186747	383	* @param command The command to execute. One of the PCD_Command enums.
AtomX	1:63d729186747	384	* @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
AtomX	1:63d729186747	385	* @param sendData Pointer to the data to transfer to the FIFO.
AtomX	1:63d729186747	386	* @param sendLen Number of bytes to transfer to the FIFO.
AtomX	1:63d729186747	387	* @param backData NULL or pointer to buffer if data should be read back after executing the command.
AtomX	1:63d729186747	388	* @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX	1:63d729186747	389	* @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
AtomX	1:63d729186747	390	* @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX	1:63d729186747	391	* @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX	1:63d729186747	392	*
AtomX	1:63d729186747	393	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	394	*/
AtomX	0:efd786b99a72	395	uint8_t PCD_CommunicateWithPICC(uint8_t command,
AtomX	0:efd786b99a72	396	uint8_t waitIRq,
AtomX	0:efd786b99a72	397	uint8_t *sendData,
AtomX	0:efd786b99a72	398	uint8_t sendLen,
AtomX	0:efd786b99a72	399	uint8_t *backData = NULL,
AtomX	0:efd786b99a72	400	uint8_t *backLen = NULL,
AtomX	0:efd786b99a72	401	uint8_t *validBits = NULL,
AtomX	0:efd786b99a72	402	uint8_t rxAlign = 0,
AtomX	0:efd786b99a72	403	bool checkCRC = false);
AtomX	0:efd786b99a72	404
AtomX	1:63d729186747	405	/**
AtomX	1:63d729186747	406	* Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
AtomX	1:63d729186747	407	* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX	1:63d729186747	408	*
AtomX	1:63d729186747	409	* @param bufferATQA The buffer to store the ATQA (Answer to request) in
AtomX	1:63d729186747	410	* @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
AtomX	1:63d729186747	411	*
AtomX	1:63d729186747	412	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	413	*/
AtomX	0:efd786b99a72	414	uint8_t PICC_RequestA (uint8_t bufferATQA, uint8_t bufferSize);
AtomX	1:63d729186747	415
AtomX	1:63d729186747	416	/**
AtomX	1:63d729186747	417	* Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
AtomX	1:63d729186747	418	* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX	1:63d729186747	419	*
AtomX	1:63d729186747	420	* @param bufferATQA The buffer to store the ATQA (Answer to request) in
AtomX	1:63d729186747	421	* @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
AtomX	1:63d729186747	422	*
AtomX	1:63d729186747	423	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	424	*/
AtomX	0:efd786b99a72	425	uint8_t PICC_WakeupA (uint8_t bufferATQA, uint8_t bufferSize);
AtomX	1:63d729186747	426
AtomX	1:63d729186747	427	/**
AtomX	1:63d729186747	428	* Transmits REQA or WUPA commands.
AtomX	1:63d729186747	429	* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX	1:63d729186747	430	*
AtomX	1:63d729186747	431	* @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
AtomX	1:63d729186747	432	* @param bufferATQA The buffer to store the ATQA (Answer to request) in
AtomX	1:63d729186747	433	* @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
AtomX	1:63d729186747	434	*
AtomX	1:63d729186747	435	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	436	*/
AtomX	0:efd786b99a72	437	uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t bufferATQA, uint8_t bufferSize);
AtomX	1:63d729186747	438
AtomX	1:63d729186747	439	/**
AtomX	1:63d729186747	440	* Transmits SELECT/ANTICOLLISION commands to select a single PICC.
AtomX	1:63d729186747	441	* Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
AtomX	1:63d729186747	442	* On success:
AtomX	1:63d729186747	443	* - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
AtomX	1:63d729186747	444	* - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
AtomX	1:63d729186747	445	*
AtomX	1:63d729186747	446	* A PICC UID consists of 4, 7 or 10 bytes.
AtomX	1:63d729186747	447	* Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
AtomX	1:63d729186747	448	*
AtomX	1:63d729186747	449	* UID size Number of UID bytes Cascade levels Example of PICC
AtomX	1:63d729186747	450	* ======== =================== ============== ===============
AtomX	1:63d729186747	451	* single 4 1 MIFARE Classic
AtomX	1:63d729186747	452	* double 7 2 MIFARE Ultralight
AtomX	1:63d729186747	453	* triple 10 3 Not currently in use?
AtomX	1:63d729186747	454	*
AtomX	1:63d729186747	455	*
AtomX	1:63d729186747	456	* @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
AtomX	1:63d729186747	457	* @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
AtomX	1:63d729186747	458	*
AtomX	1:63d729186747	459	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	460	*/
AtomX	0:efd786b99a72	461	uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
AtomX	1:63d729186747	462
AtomX	1:63d729186747	463	/**
AtomX	1:63d729186747	464	* Instructs a PICC in state ACTIVE(*) to go to state HALT.
AtomX	1:63d729186747	465	*
AtomX	1:63d729186747	466	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	467	*/
AtomX	0:efd786b99a72	468	uint8_t PICC_HaltA (void);
AtomX	1:63d729186747	469
AtomX	1:63d729186747	470	// ************************************************************************************
AtomX	1:63d729186747	471	//@}
AtomX	0:efd786b99a72	472
AtomX	0:efd786b99a72	473
AtomX	1:63d729186747	474	// ************************************************************************************
AtomX	1:63d729186747	475	//! @name Functions for communicating with MIFARE PICCs
AtomX	1:63d729186747	476	// ************************************************************************************
AtomX	1:63d729186747	477	//@{
AtomX	1:63d729186747	478
AtomX	1:63d729186747	479	/**
AtomX	1:63d729186747	480	* Executes the MFRC522 MFAuthent command.
AtomX	1:63d729186747	481	* This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
AtomX	1:63d729186747	482	* The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
AtomX	1:63d729186747	483	* For use with MIFARE Classic PICCs.
AtomX	1:63d729186747	484	* The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
AtomX	1:63d729186747	485	* Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
AtomX	1:63d729186747	486	*
AtomX	1:63d729186747	487	* All keys are set to FFFFFFFFFFFFh at chip delivery.
AtomX	1:63d729186747	488	*
AtomX	1:63d729186747	489	* @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
AtomX	1:63d729186747	490	* @param blockAddr The block number. See numbering in the comments in the .h file.
AtomX	1:63d729186747	491	* @param key Pointer to the Crypteo1 key to use (6 bytes)
AtomX	1:63d729186747	492	* @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
AtomX	1:63d729186747	493	*
AtomX	1:63d729186747	494	* @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
AtomX	1:63d729186747	495	*/
AtomX	0:efd786b99a72	496	uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key key, Uid uid);
AtomX	1:63d729186747	497
AtomX	1:63d729186747	498	/**
AtomX	1:63d729186747	499	* Used to exit the PCD from its authenticated state.
AtomX	1:63d729186747	500	* Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
AtomX	1:63d729186747	501	*/
AtomX	0:efd786b99a72	502	void PCD_StopCrypto1 (void);
AtomX	1:63d729186747	503
AtomX	1:63d729186747	504	/**
AtomX	1:63d729186747	505	* Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
AtomX	1:63d729186747	506	*
AtomX	1:63d729186747	507	* For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX	1:63d729186747	508	*
AtomX	1:63d729186747	509	* For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
AtomX	1:63d729186747	510	* The MF0ICU1 returns a NAK for higher addresses.
AtomX	1:63d729186747	511	* The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
AtomX	1:63d729186747	512	* For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
AtomX	1:63d729186747	513	* A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
AtomX	1:63d729186747	514	*
AtomX	1:63d729186747	515	* The buffer must be at least 18 bytes because a CRC_A is also returned.
AtomX	1:63d729186747	516	* Checks the CRC_A before returning STATUS_OK.
AtomX	1:63d729186747	517	*
AtomX	1:63d729186747	518	* @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
AtomX	1:63d729186747	519	* @param buffer The buffer to store the data in
AtomX	1:63d729186747	520	* @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
AtomX	1:63d729186747	521	*
AtomX	1:63d729186747	522	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	523	*/
AtomX	0:efd786b99a72	524	uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t buffer, uint8_t bufferSize);
AtomX	1:63d729186747	525
AtomX	1:63d729186747	526	/**
AtomX	1:63d729186747	527	* Writes 16 bytes to the active PICC.
AtomX	1:63d729186747	528	*
AtomX	1:63d729186747	529	* For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX	1:63d729186747	530	*
AtomX	1:63d729186747	531	* For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
AtomX	1:63d729186747	532	* Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
AtomX	1:63d729186747	533	* are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
AtomX	1:63d729186747	534	*
AtomX	1:63d729186747	535	* @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
AtomX	1:63d729186747	536	* @param buffer The 16 bytes to write to the PICC
AtomX	1:63d729186747	537	* @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
AtomX	1:63d729186747	538	*
AtomX	1:63d729186747	539	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	540	*/
AtomX	0:efd786b99a72	541	uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
AtomX	1:63d729186747	542
AtomX	1:63d729186747	543	/**
AtomX	1:63d729186747	544	* Writes a 4 byte page to the active MIFARE Ultralight PICC.
AtomX	1:63d729186747	545	*
AtomX	1:63d729186747	546	* @param page The page (2-15) to write to.
AtomX	1:63d729186747	547	* @param buffer The 4 bytes to write to the PICC
AtomX	1:63d729186747	548	* @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
AtomX	1:63d729186747	549	*
AtomX	1:63d729186747	550	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	551	*/
AtomX	1:63d729186747	552	uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
AtomX	1:63d729186747	553
AtomX	1:63d729186747	554	/**
AtomX	1:63d729186747	555	* MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
AtomX	1:63d729186747	556	* For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX	1:63d729186747	557	* Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX	1:63d729186747	558	* Use MIFARE_Transfer() to store the result in a block.
AtomX	1:63d729186747	559	*
AtomX	1:63d729186747	560	* @param blockAddr The block (0-0xff) number.
AtomX	1:63d729186747	561	* @param delta This number is subtracted from the value of block blockAddr.
AtomX	1:63d729186747	562	*
AtomX	1:63d729186747	563	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	564	*/
AtomX	0:efd786b99a72	565	uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
AtomX	1:63d729186747	566
AtomX	1:63d729186747	567	/**
AtomX	1:63d729186747	568	* MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
AtomX	1:63d729186747	569	* For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX	1:63d729186747	570	* Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX	1:63d729186747	571	* Use MIFARE_Transfer() to store the result in a block.
AtomX	1:63d729186747	572	*
AtomX	1:63d729186747	573	* @param blockAddr The block (0-0xff) number.
AtomX	1:63d729186747	574	* @param delta This number is added to the value of block blockAddr.
AtomX	1:63d729186747	575	*
AtomX	1:63d729186747	576	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	577	*/
AtomX	0:efd786b99a72	578	uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
AtomX	1:63d729186747	579
AtomX	1:63d729186747	580	/**
AtomX	1:63d729186747	581	* MIFARE Restore copies the value of the addressed block into a volatile memory.
AtomX	1:63d729186747	582	* For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX	1:63d729186747	583	* Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX	1:63d729186747	584	* Use MIFARE_Transfer() to store the result in a block.
AtomX	1:63d729186747	585	*
AtomX	1:63d729186747	586	* @param blockAddr The block (0-0xff) number.
AtomX	1:63d729186747	587	*
AtomX	1:63d729186747	588	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	589	*/
AtomX	0:efd786b99a72	590	uint8_t MIFARE_Restore (uint8_t blockAddr);
AtomX	1:63d729186747	591
AtomX	1:63d729186747	592	/**
AtomX	1:63d729186747	593	* MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
AtomX	1:63d729186747	594	* For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX	1:63d729186747	595	* Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX	1:63d729186747	596	*
AtomX	1:63d729186747	597	* @param blockAddr The block (0-0xff) number.
AtomX	1:63d729186747	598	*
AtomX	1:63d729186747	599	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	600	*/
AtomX	0:efd786b99a72	601	uint8_t MIFARE_Transfer (uint8_t blockAddr);
AtomX	1:63d729186747	602
AtomX	1:63d729186747	603	// ************************************************************************************
AtomX	1:63d729186747	604	//@}
AtomX	0:efd786b99a72	605
AtomX	0:efd786b99a72	606
AtomX	1:63d729186747	607	// ************************************************************************************
AtomX	1:63d729186747	608	//! @name Support functions
AtomX	1:63d729186747	609	// ************************************************************************************
AtomX	1:63d729186747	610	//@{
AtomX	1:63d729186747	611
AtomX	1:63d729186747	612	/**
AtomX	1:63d729186747	613	* Wrapper for MIFARE protocol communication.
AtomX	1:63d729186747	614	* Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
AtomX	1:63d729186747	615	*
AtomX	1:63d729186747	616	* @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
AtomX	1:63d729186747	617	* @param sendLen Number of bytes in sendData.
AtomX	1:63d729186747	618	* @param acceptTimeout True => A timeout is also success
AtomX	1:63d729186747	619	*
AtomX	1:63d729186747	620	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	621	*/
AtomX	0:efd786b99a72	622	uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
AtomX	1:63d729186747	623
AtomX	1:63d729186747	624	/**
AtomX	1:63d729186747	625	* Translates the SAK (Select Acknowledge) to a PICC type.
AtomX	1:63d729186747	626	*
AtomX	1:63d729186747	627	* @param sak The SAK byte returned from PICC_Select().
AtomX	1:63d729186747	628	*
AtomX	1:63d729186747	629	* @return PICC_Type
AtomX	1:63d729186747	630	*/
AtomX	0:efd786b99a72	631	uint8_t PICC_GetType (uint8_t sak);
AtomX	1:63d729186747	632
AtomX	1:63d729186747	633	/**
AtomX	1:63d729186747	634	* Returns a string pointer to the PICC type name.
AtomX	1:63d729186747	635	*
AtomX	1:63d729186747	636	* @param type One of the PICC_Type enums.
AtomX	1:63d729186747	637	*
AtomX	1:63d729186747	638	* @return A string pointer to the PICC type name.
AtomX	1:63d729186747	639	*/
AtomX	0:efd786b99a72	640	char* PICC_GetTypeName (uint8_t type);
AtomX	1:63d729186747	641
AtomX	1:63d729186747	642	/**
AtomX	1:63d729186747	643	* Returns a string pointer to a status code name.
AtomX	1:63d729186747	644	*
AtomX	1:63d729186747	645	* @param code One of the StatusCode enums.
AtomX	1:63d729186747	646	*
AtomX	1:63d729186747	647	* @return A string pointer to a status code name.
AtomX	1:63d729186747	648	*/
AtomX	0:efd786b99a72	649	char* GetStatusCodeName (uint8_t code);
AtomX	1:63d729186747	650
AtomX	1:63d729186747	651	/**
AtomX	1:63d729186747	652	* Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
AtomX	1:63d729186747	653	*
AtomX	1:63d729186747	654	* @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
AtomX	1:63d729186747	655	* @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
AtomX	1:63d729186747	656	* @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
AtomX	1:63d729186747	657	* @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
AtomX	1:63d729186747	658	* @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
AtomX	1:63d729186747	659	*/
AtomX	0:efd786b99a72	660	void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
AtomX	0:efd786b99a72	661	uint8_t g0,
AtomX	0:efd786b99a72	662	uint8_t g1,
AtomX	0:efd786b99a72	663	uint8_t g2,
AtomX	0:efd786b99a72	664	uint8_t g3);
AtomX	1:63d729186747	665
AtomX	1:63d729186747	666	// ************************************************************************************
AtomX	1:63d729186747	667	//@}
AtomX	0:efd786b99a72	668
AtomX	0:efd786b99a72	669
AtomX	1:63d729186747	670	// ************************************************************************************
AtomX	1:63d729186747	671	//! @name Convenience functions - does not add extra functionality
AtomX	1:63d729186747	672	// ************************************************************************************
AtomX	1:63d729186747	673	//@{
AtomX	1:63d729186747	674
AtomX	1:63d729186747	675	/**
AtomX	1:63d729186747	676	* Returns true if a PICC responds to PICC_CMD_REQA.
AtomX	1:63d729186747	677	* Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
AtomX	1:63d729186747	678	*
AtomX	1:63d729186747	679	* @return bool
AtomX	1:63d729186747	680	*/
AtomX	0:efd786b99a72	681	bool PICC_IsNewCardPresent(void);
AtomX	1:63d729186747	682
AtomX	1:63d729186747	683	/**
AtomX	1:63d729186747	684	* Simple wrapper around PICC_Select.
AtomX	1:63d729186747	685	* Returns true if a UID could be read.
AtomX	1:63d729186747	686	* Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
AtomX	1:63d729186747	687	* The read UID is available in the class variable uid.
AtomX	1:63d729186747	688	*
AtomX	1:63d729186747	689	* @return bool
AtomX	1:63d729186747	690	*/
AtomX	0:efd786b99a72	691	bool PICC_ReadCardSerial (void);
AtomX	1:63d729186747	692
AtomX	1:63d729186747	693	// ************************************************************************************
AtomX	1:63d729186747	694	//@}
AtomX	0:efd786b99a72	695
AtomX	0:efd786b99a72	696
AtomX	0:efd786b99a72	697	private:
AtomX	0:efd786b99a72	698	SPI m_SPI;
AtomX	0:efd786b99a72	699	DigitalOut m_CS;
AtomX	0:efd786b99a72	700	DigitalOut m_RESET;
AtomX	0:efd786b99a72	701
AtomX	1:63d729186747	702	/**
AtomX	1:63d729186747	703	* Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
AtomX	1:63d729186747	704	*
AtomX	1:63d729186747	705	* @param command The command to use
AtomX	1:63d729186747	706	* @param blockAddr The block (0-0xff) number.
AtomX	1:63d729186747	707	* @param data The data to transfer in step 2
AtomX	1:63d729186747	708	*
AtomX	1:63d729186747	709	* @return STATUS_OK on success, STATUS_??? otherwise.
AtomX	1:63d729186747	710	*/
AtomX	0:efd786b99a72	711	uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
AtomX	0:efd786b99a72	712	};
AtomX	0:efd786b99a72	713
AtomX	0:efd786b99a72	714	#endif

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	23 Sep 2014
Imports:	17
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	3
Followers:	2

MFRC522.h@3:bf44d10e4904, 2014-09-23 (annotated)

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