Christiaan M
RX TX Flush methods added
Fork of
nRF24L01P
by 
Owen Edwards
nRF24L01P.cpp@1:054a50936ab6, 2013-03-07 (annotated)
- Committer:
- Christilut
- Date:
- Thu Mar 07 09:28:09 2013 +0000
- Revision:
- 1:054a50936ab6
- Parent:
- 0:8ae48233b4e4
Added rx and tx buffer flush methods
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Christilut | 1:054a50936ab6 | 1 | /** |
| Christilut | 1:054a50936ab6 | 2 | * @file nRF24L01P.cpp |
| Christilut | 1:054a50936ab6 | 3 | * |
| Christilut | 1:054a50936ab6 | 4 | * @author Owen Edwards |
| Christilut | 1:054a50936ab6 | 5 | * |
| Christilut | 1:054a50936ab6 | 6 | * @section LICENSE |
| Christilut | 1:054a50936ab6 | 7 | * |
| Christilut | 1:054a50936ab6 | 8 | * Copyright (c) 2010 Owen Edwards |
| Christilut | 1:054a50936ab6 | 9 | * |
| Christilut | 1:054a50936ab6 | 10 | * This program is free software: you can redistribute it and/or modify |
| Christilut | 1:054a50936ab6 | 11 | * it under the terms of the GNU General Public License as published by |
| Christilut | 1:054a50936ab6 | 12 | * the Free Software Foundation, either version 3 of the License, or |
| Christilut | 1:054a50936ab6 | 13 | * (at your option) any later version. |
| Christilut | 1:054a50936ab6 | 14 | * |
| Christilut | 1:054a50936ab6 | 15 | * This program is distributed in the hope that it will be useful, |
| Christilut | 1:054a50936ab6 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| Christilut | 1:054a50936ab6 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| Christilut | 1:054a50936ab6 | 18 | * GNU General Public License for more details. |
| Christilut | 1:054a50936ab6 | 19 | * |
| Christilut | 1:054a50936ab6 | 20 | * You should have received a copy of the GNU General Public License |
| Christilut | 1:054a50936ab6 | 21 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| Christilut | 1:054a50936ab6 | 22 | * |
| Christilut | 1:054a50936ab6 | 23 | * The above copyright notice and this permission notice shall be included in |
| Christilut | 1:054a50936ab6 | 24 | * all copies or substantial portions of the Software. |
| Christilut | 1:054a50936ab6 | 25 | * |
| Christilut | 1:054a50936ab6 | 26 | * @section DESCRIPTION |
| Christilut | 1:054a50936ab6 | 27 | * |
| Christilut | 1:054a50936ab6 | 28 | * nRF24L01+ Single Chip 2.4GHz Transceiver from Nordic Semiconductor. |
| Christilut | 1:054a50936ab6 | 29 | * |
| Christilut | 1:054a50936ab6 | 30 | * Datasheet: |
| Christilut | 1:054a50936ab6 | 31 | * |
| Christilut | 1:054a50936ab6 | 32 | * http://www.nordicsemi.no/files/Product/data_sheet/nRF24L01P_Product_Specification_1_0.pdf |
| Christilut | 1:054a50936ab6 | 33 | */ |
| Christilut | 1:054a50936ab6 | 34 | |
| Christilut | 1:054a50936ab6 | 35 | /** |
| Christilut | 1:054a50936ab6 | 36 | * Includes |
| Christilut | 1:054a50936ab6 | 37 | */ |
| Christilut | 1:054a50936ab6 | 38 | #include "nRF24L01P.h" |
| Christilut | 1:054a50936ab6 | 39 | |
| Christilut | 1:054a50936ab6 | 40 | /** |
| Christilut | 1:054a50936ab6 | 41 | * Defines |
| Christilut | 1:054a50936ab6 | 42 | * |
| Christilut | 1:054a50936ab6 | 43 | * (Note that all defines here start with an underscore, e.g. '_NRF24L01P_MODE_UNKNOWN', |
| Christilut | 1:054a50936ab6 | 44 | * and are local to this library. The defines in the nRF24L01P.h file do not start |
| Christilut | 1:054a50936ab6 | 45 | * with the underscore, and can be used by code to access this library.) |
| Christilut | 1:054a50936ab6 | 46 | */ |
| Christilut | 1:054a50936ab6 | 47 | |
| Christilut | 1:054a50936ab6 | 48 | typedef enum { |
| Christilut | 1:054a50936ab6 | 49 | _NRF24L01P_MODE_UNKNOWN, |
| Christilut | 1:054a50936ab6 | 50 | _NRF24L01P_MODE_POWER_DOWN, |
| Christilut | 1:054a50936ab6 | 51 | _NRF24L01P_MODE_STANDBY, |
| Christilut | 1:054a50936ab6 | 52 | _NRF24L01P_MODE_RX, |
| Christilut | 1:054a50936ab6 | 53 | _NRF24L01P_MODE_TX, |
| Christilut | 1:054a50936ab6 | 54 | } nRF24L01P_Mode_Type; |
| Christilut | 1:054a50936ab6 | 55 | |
| Christilut | 1:054a50936ab6 | 56 | /* |
| Christilut | 1:054a50936ab6 | 57 | * The following FIFOs are present in nRF24L01+: |
| Christilut | 1:054a50936ab6 | 58 | * TX three level, 32 byte FIFO |
| Christilut | 1:054a50936ab6 | 59 | * RX three level, 32 byte FIFO |
| Christilut | 1:054a50936ab6 | 60 | */ |
| Christilut | 1:054a50936ab6 | 61 | #define _NRF24L01P_TX_FIFO_COUNT 3 |
| Christilut | 1:054a50936ab6 | 62 | #define _NRF24L01P_RX_FIFO_COUNT 3 |
| Christilut | 1:054a50936ab6 | 63 | |
| Christilut | 1:054a50936ab6 | 64 | #define _NRF24L01P_TX_FIFO_SIZE 32 |
| Christilut | 1:054a50936ab6 | 65 | #define _NRF24L01P_RX_FIFO_SIZE 32 |
| Christilut | 1:054a50936ab6 | 66 | |
| Christilut | 1:054a50936ab6 | 67 | #define _NRF24L01P_SPI_MAX_DATA_RATE 10000000 |
| Christilut | 1:054a50936ab6 | 68 | |
| Christilut | 1:054a50936ab6 | 69 | #define _NRF24L01P_SPI_CMD_RD_REG 0x00 |
| Christilut | 1:054a50936ab6 | 70 | #define _NRF24L01P_SPI_CMD_WR_REG 0x20 |
| Christilut | 1:054a50936ab6 | 71 | #define _NRF24L01P_SPI_CMD_RD_RX_PAYLOAD 0x61 |
| Christilut | 1:054a50936ab6 | 72 | #define _NRF24L01P_SPI_CMD_WR_TX_PAYLOAD 0xa0 |
| Christilut | 1:054a50936ab6 | 73 | #define _NRF24L01P_SPI_CMD_FLUSH_TX 0xe1 |
| Christilut | 1:054a50936ab6 | 74 | #define _NRF24L01P_SPI_CMD_FLUSH_RX 0xe2 |
| Christilut | 1:054a50936ab6 | 75 | #define _NRF24L01P_SPI_CMD_REUSE_TX_PL 0xe3 |
| Christilut | 1:054a50936ab6 | 76 | #define _NRF24L01P_SPI_CMD_R_RX_PL_WID 0x60 |
| Christilut | 1:054a50936ab6 | 77 | #define _NRF24L01P_SPI_CMD_W_ACK_PAYLOAD 0xa8 |
| Christilut | 1:054a50936ab6 | 78 | #define _NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK 0xb0 |
| Christilut | 1:054a50936ab6 | 79 | #define _NRF24L01P_SPI_CMD_NOP 0xff |
| Christilut | 1:054a50936ab6 | 80 | |
| Christilut | 1:054a50936ab6 | 81 | |
| Christilut | 1:054a50936ab6 | 82 | #define _NRF24L01P_REG_CONFIG 0x00 |
| Christilut | 1:054a50936ab6 | 83 | #define _NRF24L01P_REG_EN_AA 0x01 |
| Christilut | 1:054a50936ab6 | 84 | #define _NRF24L01P_REG_EN_RXADDR 0x02 |
| Christilut | 1:054a50936ab6 | 85 | #define _NRF24L01P_REG_SETUP_AW 0x03 |
| Christilut | 1:054a50936ab6 | 86 | #define _NRF24L01P_REG_SETUP_RETR 0x04 |
| Christilut | 1:054a50936ab6 | 87 | #define _NRF24L01P_REG_RF_CH 0x05 |
| Christilut | 1:054a50936ab6 | 88 | #define _NRF24L01P_REG_RF_SETUP 0x06 |
| Christilut | 1:054a50936ab6 | 89 | #define _NRF24L01P_REG_STATUS 0x07 |
| Christilut | 1:054a50936ab6 | 90 | #define _NRF24L01P_REG_OBSERVE_TX 0x08 |
| Christilut | 1:054a50936ab6 | 91 | #define _NRF24L01P_REG_RPD 0x09 |
| Christilut | 1:054a50936ab6 | 92 | #define _NRF24L01P_REG_RX_ADDR_P0 0x0a |
| Christilut | 1:054a50936ab6 | 93 | #define _NRF24L01P_REG_RX_ADDR_P1 0x0b |
| Christilut | 1:054a50936ab6 | 94 | #define _NRF24L01P_REG_RX_ADDR_P2 0x0c |
| Christilut | 1:054a50936ab6 | 95 | #define _NRF24L01P_REG_RX_ADDR_P3 0x0d |
| Christilut | 1:054a50936ab6 | 96 | #define _NRF24L01P_REG_RX_ADDR_P4 0x0e |
| Christilut | 1:054a50936ab6 | 97 | #define _NRF24L01P_REG_RX_ADDR_P5 0x0f |
| Christilut | 1:054a50936ab6 | 98 | #define _NRF24L01P_REG_TX_ADDR 0x10 |
| Christilut | 1:054a50936ab6 | 99 | #define _NRF24L01P_REG_RX_PW_P0 0x11 |
| Christilut | 1:054a50936ab6 | 100 | #define _NRF24L01P_REG_RX_PW_P1 0x12 |
| Christilut | 1:054a50936ab6 | 101 | #define _NRF24L01P_REG_RX_PW_P2 0x13 |
| Christilut | 1:054a50936ab6 | 102 | #define _NRF24L01P_REG_RX_PW_P3 0x14 |
| Christilut | 1:054a50936ab6 | 103 | #define _NRF24L01P_REG_RX_PW_P4 0x15 |
| Christilut | 1:054a50936ab6 | 104 | #define _NRF24L01P_REG_RX_PW_P5 0x16 |
| Christilut | 1:054a50936ab6 | 105 | #define _NRF24L01P_REG_FIFO_STATUS 0x17 |
| Christilut | 1:054a50936ab6 | 106 | #define _NRF24L01P_REG_DYNPD 0x1c |
| Christilut | 1:054a50936ab6 | 107 | #define _NRF24L01P_REG_FEATURE 0x1d |
| Christilut | 1:054a50936ab6 | 108 | |
| Christilut | 1:054a50936ab6 | 109 | #define _NRF24L01P_REG_ADDRESS_MASK 0x1f |
| Christilut | 1:054a50936ab6 | 110 | |
| Christilut | 1:054a50936ab6 | 111 | // CONFIG register: |
| Christilut | 1:054a50936ab6 | 112 | #define _NRF24L01P_CONFIG_PRIM_RX (1<<0) |
| Christilut | 1:054a50936ab6 | 113 | #define _NRF24L01P_CONFIG_PWR_UP (1<<1) |
| Christilut | 1:054a50936ab6 | 114 | #define _NRF24L01P_CONFIG_CRC0 (1<<2) |
| Christilut | 1:054a50936ab6 | 115 | #define _NRF24L01P_CONFIG_EN_CRC (1<<3) |
| Christilut | 1:054a50936ab6 | 116 | #define _NRF24L01P_CONFIG_MASK_MAX_RT (1<<4) |
| Christilut | 1:054a50936ab6 | 117 | #define _NRF24L01P_CONFIG_MASK_TX_DS (1<<5) |
| Christilut | 1:054a50936ab6 | 118 | #define _NRF24L01P_CONFIG_MASK_RX_DR (1<<6) |
| Christilut | 1:054a50936ab6 | 119 | |
| Christilut | 1:054a50936ab6 | 120 | #define _NRF24L01P_CONFIG_CRC_MASK (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0) |
| Christilut | 1:054a50936ab6 | 121 | #define _NRF24L01P_CONFIG_CRC_NONE (0) |
| Christilut | 1:054a50936ab6 | 122 | #define _NRF24L01P_CONFIG_CRC_8BIT (_NRF24L01P_CONFIG_EN_CRC) |
| Christilut | 1:054a50936ab6 | 123 | #define _NRF24L01P_CONFIG_CRC_16BIT (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0) |
| Christilut | 1:054a50936ab6 | 124 | |
| Christilut | 1:054a50936ab6 | 125 | // EN_AA register: |
| Christilut | 1:054a50936ab6 | 126 | #define _NRF24L01P_EN_AA_NONE 0 |
| Christilut | 1:054a50936ab6 | 127 | |
| Christilut | 1:054a50936ab6 | 128 | // EN_RXADDR register: |
| Christilut | 1:054a50936ab6 | 129 | #define _NRF24L01P_EN_RXADDR_NONE 0 |
| Christilut | 1:054a50936ab6 | 130 | |
| Christilut | 1:054a50936ab6 | 131 | // SETUP_AW register: |
| Christilut | 1:054a50936ab6 | 132 | #define _NRF24L01P_SETUP_AW_AW_MASK (0x3<<0) |
| Christilut | 1:054a50936ab6 | 133 | #define _NRF24L01P_SETUP_AW_AW_3BYTE (0x1<<0) |
| Christilut | 1:054a50936ab6 | 134 | #define _NRF24L01P_SETUP_AW_AW_4BYTE (0x2<<0) |
| Christilut | 1:054a50936ab6 | 135 | #define _NRF24L01P_SETUP_AW_AW_5BYTE (0x3<<0) |
| Christilut | 1:054a50936ab6 | 136 | |
| Christilut | 1:054a50936ab6 | 137 | // SETUP_RETR register: |
| Christilut | 1:054a50936ab6 | 138 | #define _NRF24L01P_SETUP_RETR_NONE 0 |
| Christilut | 1:054a50936ab6 | 139 | |
| Christilut | 1:054a50936ab6 | 140 | // RF_SETUP register: |
| Christilut | 1:054a50936ab6 | 141 | #define _NRF24L01P_RF_SETUP_RF_PWR_MASK (0x3<<1) |
| Christilut | 1:054a50936ab6 | 142 | #define _NRF24L01P_RF_SETUP_RF_PWR_0DBM (0x3<<1) |
| Christilut | 1:054a50936ab6 | 143 | #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM (0x2<<1) |
| Christilut | 1:054a50936ab6 | 144 | #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM (0x1<<1) |
| Christilut | 1:054a50936ab6 | 145 | #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM (0x0<<1) |
| Christilut | 1:054a50936ab6 | 146 | |
| Christilut | 1:054a50936ab6 | 147 | #define _NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT (1 << 3) |
| Christilut | 1:054a50936ab6 | 148 | #define _NRF24L01P_RF_SETUP_RF_DR_LOW_BIT (1 << 5) |
| Christilut | 1:054a50936ab6 | 149 | #define _NRF24L01P_RF_SETUP_RF_DR_MASK (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT|_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT) |
| Christilut | 1:054a50936ab6 | 150 | #define _NRF24L01P_RF_SETUP_RF_DR_250KBPS (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT) |
| Christilut | 1:054a50936ab6 | 151 | #define _NRF24L01P_RF_SETUP_RF_DR_1MBPS (0) |
| Christilut | 1:054a50936ab6 | 152 | #define _NRF24L01P_RF_SETUP_RF_DR_2MBPS (_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT) |
| Christilut | 1:054a50936ab6 | 153 | |
| Christilut | 1:054a50936ab6 | 154 | // STATUS register: |
| Christilut | 1:054a50936ab6 | 155 | #define _NRF24L01P_STATUS_TX_FULL (1<<0) |
| Christilut | 1:054a50936ab6 | 156 | #define _NRF24L01P_STATUS_RX_P_NO (0x7<<1) |
| Christilut | 1:054a50936ab6 | 157 | #define _NRF24L01P_STATUS_MAX_RT (1<<4) |
| Christilut | 1:054a50936ab6 | 158 | #define _NRF24L01P_STATUS_TX_DS (1<<5) |
| Christilut | 1:054a50936ab6 | 159 | #define _NRF24L01P_STATUS_RX_DR (1<<6) |
| Christilut | 1:054a50936ab6 | 160 | |
| Christilut | 1:054a50936ab6 | 161 | // RX_PW_P0..RX_PW_P5 registers: |
| Christilut | 1:054a50936ab6 | 162 | #define _NRF24L01P_RX_PW_Px_MASK 0x3F |
| Christilut | 1:054a50936ab6 | 163 | |
| Christilut | 1:054a50936ab6 | 164 | #define _NRF24L01P_TIMING_Tundef2pd_us 100000 // 100mS |
| Christilut | 1:054a50936ab6 | 165 | #define _NRF24L01P_TIMING_Tstby2a_us 130 // 130uS |
| Christilut | 1:054a50936ab6 | 166 | #define _NRF24L01P_TIMING_Thce_us 10 // 10uS |
| Christilut | 1:054a50936ab6 | 167 | #define _NRF24L01P_TIMING_Tpd2stby_us 4500 // 4.5mS worst case |
| Christilut | 1:054a50936ab6 | 168 | #define _NRF24L01P_TIMING_Tpece2csn_us 4 // 4uS |
| Christilut | 1:054a50936ab6 | 169 | |
| Christilut | 1:054a50936ab6 | 170 | /** |
| Christilut | 1:054a50936ab6 | 171 | * Methods |
| Christilut | 1:054a50936ab6 | 172 | */ |
| Christilut | 1:054a50936ab6 | 173 | |
| Christilut | 1:054a50936ab6 | 174 | nRF24L01P::nRF24L01P(PinName mosi, |
| Christilut | 1:054a50936ab6 | 175 | PinName miso, |
| Christilut | 1:054a50936ab6 | 176 | PinName sck, |
| Christilut | 1:054a50936ab6 | 177 | PinName csn, |
| Christilut | 1:054a50936ab6 | 178 | PinName ce, |
| Christilut | 1:054a50936ab6 | 179 | PinName irq) : spi_(mosi, miso, sck), nCS_(csn), ce_(ce), nIRQ_(irq) |
| Christilut | 1:054a50936ab6 | 180 | { |
| Christilut | 1:054a50936ab6 | 181 | |
| Christilut | 1:054a50936ab6 | 182 | mode = _NRF24L01P_MODE_UNKNOWN; |
| Christilut | 1:054a50936ab6 | 183 | |
| Christilut | 1:054a50936ab6 | 184 | disable(); |
| Christilut | 1:054a50936ab6 | 185 | |
| Christilut | 1:054a50936ab6 | 186 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 187 | |
| Christilut | 1:054a50936ab6 | 188 | spi_.frequency(_NRF24L01P_SPI_MAX_DATA_RATE/5); // 2Mbit, 1/5th the maximum transfer rate for the SPI bus |
| Christilut | 1:054a50936ab6 | 189 | spi_.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0 |
| Christilut | 1:054a50936ab6 | 190 | |
| Christilut | 1:054a50936ab6 | 191 | wait_us(_NRF24L01P_TIMING_Tundef2pd_us); // Wait for Power-on reset |
| Christilut | 1:054a50936ab6 | 192 | |
| Christilut | 1:054a50936ab6 | 193 | setRegister(_NRF24L01P_REG_CONFIG, 0); // Power Down |
| Christilut | 1:054a50936ab6 | 194 | |
| Christilut | 1:054a50936ab6 | 195 | setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT|_NRF24L01P_STATUS_TX_DS|_NRF24L01P_STATUS_RX_DR); // Clear any pending interrupts |
| Christilut | 1:054a50936ab6 | 196 | |
| Christilut | 1:054a50936ab6 | 197 | // |
| Christilut | 1:054a50936ab6 | 198 | // Setup default configuration |
| Christilut | 1:054a50936ab6 | 199 | // |
| Christilut | 1:054a50936ab6 | 200 | disableAllRxPipes(); |
| Christilut | 1:054a50936ab6 | 201 | setRfFrequency(); |
| Christilut | 1:054a50936ab6 | 202 | setRfOutputPower(); |
| Christilut | 1:054a50936ab6 | 203 | setAirDataRate(); |
| Christilut | 1:054a50936ab6 | 204 | setCrcWidth(); |
| Christilut | 1:054a50936ab6 | 205 | setTxAddress(); |
| Christilut | 1:054a50936ab6 | 206 | setRxAddress(); |
| Christilut | 1:054a50936ab6 | 207 | disableAutoAcknowledge(); |
| Christilut | 1:054a50936ab6 | 208 | disableAutoRetransmit(); |
| Christilut | 1:054a50936ab6 | 209 | setTransferSize(); |
| Christilut | 1:054a50936ab6 | 210 | |
| Christilut | 1:054a50936ab6 | 211 | mode = _NRF24L01P_MODE_POWER_DOWN; |
| Christilut | 1:054a50936ab6 | 212 | |
| Christilut | 1:054a50936ab6 | 213 | } |
| Christilut | 1:054a50936ab6 | 214 | |
| Christilut | 1:054a50936ab6 | 215 | |
| Christilut | 1:054a50936ab6 | 216 | void nRF24L01P::powerUp(void) |
| Christilut | 1:054a50936ab6 | 217 | { |
| Christilut | 1:054a50936ab6 | 218 | |
| Christilut | 1:054a50936ab6 | 219 | int config = getRegister(_NRF24L01P_REG_CONFIG); |
| Christilut | 1:054a50936ab6 | 220 | |
| Christilut | 1:054a50936ab6 | 221 | config |= _NRF24L01P_CONFIG_PWR_UP; |
| Christilut | 1:054a50936ab6 | 222 | |
| Christilut | 1:054a50936ab6 | 223 | setRegister(_NRF24L01P_REG_CONFIG, config); |
| Christilut | 1:054a50936ab6 | 224 | |
| Christilut | 1:054a50936ab6 | 225 | // Wait until the nRF24L01+ powers up |
| Christilut | 1:054a50936ab6 | 226 | wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); |
| Christilut | 1:054a50936ab6 | 227 | |
| Christilut | 1:054a50936ab6 | 228 | mode = _NRF24L01P_MODE_STANDBY; |
| Christilut | 1:054a50936ab6 | 229 | |
| Christilut | 1:054a50936ab6 | 230 | } |
| Christilut | 1:054a50936ab6 | 231 | |
| Christilut | 1:054a50936ab6 | 232 | |
| Christilut | 1:054a50936ab6 | 233 | void nRF24L01P::powerDown(void) |
| Christilut | 1:054a50936ab6 | 234 | { |
| Christilut | 1:054a50936ab6 | 235 | |
| Christilut | 1:054a50936ab6 | 236 | int config = getRegister(_NRF24L01P_REG_CONFIG); |
| Christilut | 1:054a50936ab6 | 237 | |
| Christilut | 1:054a50936ab6 | 238 | config &= ~_NRF24L01P_CONFIG_PWR_UP; |
| Christilut | 1:054a50936ab6 | 239 | |
| Christilut | 1:054a50936ab6 | 240 | setRegister(_NRF24L01P_REG_CONFIG, config); |
| Christilut | 1:054a50936ab6 | 241 | |
| Christilut | 1:054a50936ab6 | 242 | // Wait until the nRF24L01+ powers down |
| Christilut | 1:054a50936ab6 | 243 | wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); // This *may* not be necessary (no timing is shown in the Datasheet), but just to be safe |
| Christilut | 1:054a50936ab6 | 244 | |
| Christilut | 1:054a50936ab6 | 245 | mode = _NRF24L01P_MODE_POWER_DOWN; |
| Christilut | 1:054a50936ab6 | 246 | |
| Christilut | 1:054a50936ab6 | 247 | } |
| Christilut | 1:054a50936ab6 | 248 | |
| Christilut | 1:054a50936ab6 | 249 | |
| Christilut | 1:054a50936ab6 | 250 | void nRF24L01P::setReceiveMode(void) |
| Christilut | 1:054a50936ab6 | 251 | { |
| Christilut | 1:054a50936ab6 | 252 | |
| Christilut | 1:054a50936ab6 | 253 | if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp(); |
| Christilut | 1:054a50936ab6 | 254 | |
| Christilut | 1:054a50936ab6 | 255 | int config = getRegister(_NRF24L01P_REG_CONFIG); |
| Christilut | 1:054a50936ab6 | 256 | |
| Christilut | 1:054a50936ab6 | 257 | config |= _NRF24L01P_CONFIG_PRIM_RX; |
| Christilut | 1:054a50936ab6 | 258 | |
| Christilut | 1:054a50936ab6 | 259 | setRegister(_NRF24L01P_REG_CONFIG, config); |
| Christilut | 1:054a50936ab6 | 260 | |
| Christilut | 1:054a50936ab6 | 261 | mode = _NRF24L01P_MODE_RX; |
| Christilut | 1:054a50936ab6 | 262 | |
| Christilut | 1:054a50936ab6 | 263 | } |
| Christilut | 1:054a50936ab6 | 264 | |
| Christilut | 1:054a50936ab6 | 265 | |
| Christilut | 1:054a50936ab6 | 266 | void nRF24L01P::setTransmitMode(void) |
| Christilut | 1:054a50936ab6 | 267 | { |
| Christilut | 1:054a50936ab6 | 268 | |
| Christilut | 1:054a50936ab6 | 269 | if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp(); |
| Christilut | 1:054a50936ab6 | 270 | |
| Christilut | 1:054a50936ab6 | 271 | int config = getRegister(_NRF24L01P_REG_CONFIG); |
| Christilut | 1:054a50936ab6 | 272 | |
| Christilut | 1:054a50936ab6 | 273 | config &= ~_NRF24L01P_CONFIG_PRIM_RX; |
| Christilut | 1:054a50936ab6 | 274 | |
| Christilut | 1:054a50936ab6 | 275 | setRegister(_NRF24L01P_REG_CONFIG, config); |
| Christilut | 1:054a50936ab6 | 276 | |
| Christilut | 1:054a50936ab6 | 277 | mode = _NRF24L01P_MODE_TX; |
| Christilut | 1:054a50936ab6 | 278 | |
| Christilut | 1:054a50936ab6 | 279 | } |
| Christilut | 1:054a50936ab6 | 280 | |
| Christilut | 1:054a50936ab6 | 281 | |
| Christilut | 1:054a50936ab6 | 282 | void nRF24L01P::enable(void) |
| Christilut | 1:054a50936ab6 | 283 | { |
| Christilut | 1:054a50936ab6 | 284 | |
| Christilut | 1:054a50936ab6 | 285 | ce_ = 1; |
| Christilut | 1:054a50936ab6 | 286 | wait_us( _NRF24L01P_TIMING_Tpece2csn_us ); |
| Christilut | 1:054a50936ab6 | 287 | |
| Christilut | 1:054a50936ab6 | 288 | } |
| Christilut | 1:054a50936ab6 | 289 | |
| Christilut | 1:054a50936ab6 | 290 | |
| Christilut | 1:054a50936ab6 | 291 | void nRF24L01P::disable(void) |
| Christilut | 1:054a50936ab6 | 292 | { |
| Christilut | 1:054a50936ab6 | 293 | |
| Christilut | 1:054a50936ab6 | 294 | ce_ = 0; |
| Christilut | 1:054a50936ab6 | 295 | |
| Christilut | 1:054a50936ab6 | 296 | } |
| Christilut | 1:054a50936ab6 | 297 | |
| Christilut | 1:054a50936ab6 | 298 | void nRF24L01P::setRfFrequency(int frequency) |
| Christilut | 1:054a50936ab6 | 299 | { |
| Christilut | 1:054a50936ab6 | 300 | |
| Christilut | 1:054a50936ab6 | 301 | if ( ( frequency < NRF24L01P_MIN_RF_FREQUENCY ) || ( frequency > NRF24L01P_MAX_RF_FREQUENCY ) ) { |
| Christilut | 1:054a50936ab6 | 302 | |
| Christilut | 1:054a50936ab6 | 303 | error( "nRF24L01P: Invalid RF Frequency setting %d\r\n", frequency ); |
| Christilut | 1:054a50936ab6 | 304 | return; |
| Christilut | 1:054a50936ab6 | 305 | |
| Christilut | 1:054a50936ab6 | 306 | } |
| Christilut | 1:054a50936ab6 | 307 | |
| Christilut | 1:054a50936ab6 | 308 | int channel = ( frequency - NRF24L01P_MIN_RF_FREQUENCY ) & 0x7F; |
| Christilut | 1:054a50936ab6 | 309 | |
| Christilut | 1:054a50936ab6 | 310 | setRegister(_NRF24L01P_REG_RF_CH, channel); |
| Christilut | 1:054a50936ab6 | 311 | |
| Christilut | 1:054a50936ab6 | 312 | } |
| Christilut | 1:054a50936ab6 | 313 | |
| Christilut | 1:054a50936ab6 | 314 | |
| Christilut | 1:054a50936ab6 | 315 | int nRF24L01P::getRfFrequency(void) |
| Christilut | 1:054a50936ab6 | 316 | { |
| Christilut | 1:054a50936ab6 | 317 | |
| Christilut | 1:054a50936ab6 | 318 | int channel = getRegister(_NRF24L01P_REG_RF_CH) & 0x7F; |
| Christilut | 1:054a50936ab6 | 319 | |
| Christilut | 1:054a50936ab6 | 320 | return ( channel + NRF24L01P_MIN_RF_FREQUENCY ); |
| Christilut | 1:054a50936ab6 | 321 | |
| Christilut | 1:054a50936ab6 | 322 | } |
| Christilut | 1:054a50936ab6 | 323 | |
| Christilut | 1:054a50936ab6 | 324 | |
| Christilut | 1:054a50936ab6 | 325 | void nRF24L01P::setRfOutputPower(int power) |
| Christilut | 1:054a50936ab6 | 326 | { |
| Christilut | 1:054a50936ab6 | 327 | |
| Christilut | 1:054a50936ab6 | 328 | int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_PWR_MASK; |
| Christilut | 1:054a50936ab6 | 329 | |
| Christilut | 1:054a50936ab6 | 330 | switch ( power ) { |
| Christilut | 1:054a50936ab6 | 331 | |
| Christilut | 1:054a50936ab6 | 332 | case NRF24L01P_TX_PWR_ZERO_DB: |
| Christilut | 1:054a50936ab6 | 333 | rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_0DBM; |
| Christilut | 1:054a50936ab6 | 334 | break; |
| Christilut | 1:054a50936ab6 | 335 | |
| Christilut | 1:054a50936ab6 | 336 | case NRF24L01P_TX_PWR_MINUS_6_DB: |
| Christilut | 1:054a50936ab6 | 337 | rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM; |
| Christilut | 1:054a50936ab6 | 338 | break; |
| Christilut | 1:054a50936ab6 | 339 | |
| Christilut | 1:054a50936ab6 | 340 | case NRF24L01P_TX_PWR_MINUS_12_DB: |
| Christilut | 1:054a50936ab6 | 341 | rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM; |
| Christilut | 1:054a50936ab6 | 342 | break; |
| Christilut | 1:054a50936ab6 | 343 | |
| Christilut | 1:054a50936ab6 | 344 | case NRF24L01P_TX_PWR_MINUS_18_DB: |
| Christilut | 1:054a50936ab6 | 345 | rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM; |
| Christilut | 1:054a50936ab6 | 346 | break; |
| Christilut | 1:054a50936ab6 | 347 | |
| Christilut | 1:054a50936ab6 | 348 | default: |
| Christilut | 1:054a50936ab6 | 349 | error( "nRF24L01P: Invalid RF Output Power setting %d\r\n", power ); |
| Christilut | 1:054a50936ab6 | 350 | return; |
| Christilut | 1:054a50936ab6 | 351 | |
| Christilut | 1:054a50936ab6 | 352 | } |
| Christilut | 1:054a50936ab6 | 353 | |
| Christilut | 1:054a50936ab6 | 354 | setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup); |
| Christilut | 1:054a50936ab6 | 355 | |
| Christilut | 1:054a50936ab6 | 356 | } |
| Christilut | 1:054a50936ab6 | 357 | |
| Christilut | 1:054a50936ab6 | 358 | |
| Christilut | 1:054a50936ab6 | 359 | int nRF24L01P::getRfOutputPower(void) |
| Christilut | 1:054a50936ab6 | 360 | { |
| Christilut | 1:054a50936ab6 | 361 | |
| Christilut | 1:054a50936ab6 | 362 | int rfPwr = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_PWR_MASK; |
| Christilut | 1:054a50936ab6 | 363 | |
| Christilut | 1:054a50936ab6 | 364 | switch ( rfPwr ) { |
| Christilut | 1:054a50936ab6 | 365 | |
| Christilut | 1:054a50936ab6 | 366 | case _NRF24L01P_RF_SETUP_RF_PWR_0DBM: |
| Christilut | 1:054a50936ab6 | 367 | return NRF24L01P_TX_PWR_ZERO_DB; |
| Christilut | 1:054a50936ab6 | 368 | |
| Christilut | 1:054a50936ab6 | 369 | case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM: |
| Christilut | 1:054a50936ab6 | 370 | return NRF24L01P_TX_PWR_MINUS_6_DB; |
| Christilut | 1:054a50936ab6 | 371 | |
| Christilut | 1:054a50936ab6 | 372 | case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM: |
| Christilut | 1:054a50936ab6 | 373 | return NRF24L01P_TX_PWR_MINUS_12_DB; |
| Christilut | 1:054a50936ab6 | 374 | |
| Christilut | 1:054a50936ab6 | 375 | case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM: |
| Christilut | 1:054a50936ab6 | 376 | return NRF24L01P_TX_PWR_MINUS_18_DB; |
| Christilut | 1:054a50936ab6 | 377 | |
| Christilut | 1:054a50936ab6 | 378 | default: |
| Christilut | 1:054a50936ab6 | 379 | error( "nRF24L01P: Unknown RF Output Power value %d\r\n", rfPwr ); |
| Christilut | 1:054a50936ab6 | 380 | return 0; |
| Christilut | 1:054a50936ab6 | 381 | |
| Christilut | 1:054a50936ab6 | 382 | } |
| Christilut | 1:054a50936ab6 | 383 | } |
| Christilut | 1:054a50936ab6 | 384 | |
| Christilut | 1:054a50936ab6 | 385 | |
| Christilut | 1:054a50936ab6 | 386 | void nRF24L01P::setAirDataRate(int rate) |
| Christilut | 1:054a50936ab6 | 387 | { |
| Christilut | 1:054a50936ab6 | 388 | |
| Christilut | 1:054a50936ab6 | 389 | int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_DR_MASK; |
| Christilut | 1:054a50936ab6 | 390 | |
| Christilut | 1:054a50936ab6 | 391 | switch ( rate ) { |
| Christilut | 1:054a50936ab6 | 392 | |
| Christilut | 1:054a50936ab6 | 393 | case NRF24L01P_DATARATE_250_KBPS: |
| Christilut | 1:054a50936ab6 | 394 | rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_250KBPS; |
| Christilut | 1:054a50936ab6 | 395 | break; |
| Christilut | 1:054a50936ab6 | 396 | |
| Christilut | 1:054a50936ab6 | 397 | case NRF24L01P_DATARATE_1_MBPS: |
| Christilut | 1:054a50936ab6 | 398 | rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_1MBPS; |
| Christilut | 1:054a50936ab6 | 399 | break; |
| Christilut | 1:054a50936ab6 | 400 | |
| Christilut | 1:054a50936ab6 | 401 | case NRF24L01P_DATARATE_2_MBPS: |
| Christilut | 1:054a50936ab6 | 402 | rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_2MBPS; |
| Christilut | 1:054a50936ab6 | 403 | break; |
| Christilut | 1:054a50936ab6 | 404 | |
| Christilut | 1:054a50936ab6 | 405 | default: |
| Christilut | 1:054a50936ab6 | 406 | error( "nRF24L01P: Invalid Air Data Rate setting %d\r\n", rate ); |
| Christilut | 1:054a50936ab6 | 407 | return; |
| Christilut | 1:054a50936ab6 | 408 | |
| Christilut | 1:054a50936ab6 | 409 | } |
| Christilut | 1:054a50936ab6 | 410 | |
| Christilut | 1:054a50936ab6 | 411 | setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup); |
| Christilut | 1:054a50936ab6 | 412 | |
| Christilut | 1:054a50936ab6 | 413 | } |
| Christilut | 1:054a50936ab6 | 414 | |
| Christilut | 1:054a50936ab6 | 415 | |
| Christilut | 1:054a50936ab6 | 416 | int nRF24L01P::getAirDataRate(void) |
| Christilut | 1:054a50936ab6 | 417 | { |
| Christilut | 1:054a50936ab6 | 418 | |
| Christilut | 1:054a50936ab6 | 419 | int rfDataRate = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_DR_MASK; |
| Christilut | 1:054a50936ab6 | 420 | |
| Christilut | 1:054a50936ab6 | 421 | switch ( rfDataRate ) { |
| Christilut | 1:054a50936ab6 | 422 | |
| Christilut | 1:054a50936ab6 | 423 | case _NRF24L01P_RF_SETUP_RF_DR_250KBPS: |
| Christilut | 1:054a50936ab6 | 424 | return NRF24L01P_DATARATE_250_KBPS; |
| Christilut | 1:054a50936ab6 | 425 | |
| Christilut | 1:054a50936ab6 | 426 | case _NRF24L01P_RF_SETUP_RF_DR_1MBPS: |
| Christilut | 1:054a50936ab6 | 427 | return NRF24L01P_DATARATE_1_MBPS; |
| Christilut | 1:054a50936ab6 | 428 | |
| Christilut | 1:054a50936ab6 | 429 | case _NRF24L01P_RF_SETUP_RF_DR_2MBPS: |
| Christilut | 1:054a50936ab6 | 430 | return NRF24L01P_DATARATE_2_MBPS; |
| Christilut | 1:054a50936ab6 | 431 | |
| Christilut | 1:054a50936ab6 | 432 | default: |
| Christilut | 1:054a50936ab6 | 433 | error( "nRF24L01P: Unknown Air Data Rate value %d\r\n", rfDataRate ); |
| Christilut | 1:054a50936ab6 | 434 | return 0; |
| Christilut | 1:054a50936ab6 | 435 | |
| Christilut | 1:054a50936ab6 | 436 | } |
| Christilut | 1:054a50936ab6 | 437 | } |
| Christilut | 1:054a50936ab6 | 438 | |
| Christilut | 1:054a50936ab6 | 439 | |
| Christilut | 1:054a50936ab6 | 440 | void nRF24L01P::setCrcWidth(int width) |
| Christilut | 1:054a50936ab6 | 441 | { |
| Christilut | 1:054a50936ab6 | 442 | |
| Christilut | 1:054a50936ab6 | 443 | int config = getRegister(_NRF24L01P_REG_CONFIG) & ~_NRF24L01P_CONFIG_CRC_MASK; |
| Christilut | 1:054a50936ab6 | 444 | |
| Christilut | 1:054a50936ab6 | 445 | switch ( width ) { |
| Christilut | 1:054a50936ab6 | 446 | |
| Christilut | 1:054a50936ab6 | 447 | case NRF24L01P_CRC_NONE: |
| Christilut | 1:054a50936ab6 | 448 | config |= _NRF24L01P_CONFIG_CRC_NONE; |
| Christilut | 1:054a50936ab6 | 449 | break; |
| Christilut | 1:054a50936ab6 | 450 | |
| Christilut | 1:054a50936ab6 | 451 | case NRF24L01P_CRC_8_BIT: |
| Christilut | 1:054a50936ab6 | 452 | config |= _NRF24L01P_CONFIG_CRC_8BIT; |
| Christilut | 1:054a50936ab6 | 453 | break; |
| Christilut | 1:054a50936ab6 | 454 | |
| Christilut | 1:054a50936ab6 | 455 | case NRF24L01P_CRC_16_BIT: |
| Christilut | 1:054a50936ab6 | 456 | config |= _NRF24L01P_CONFIG_CRC_16BIT; |
| Christilut | 1:054a50936ab6 | 457 | break; |
| Christilut | 1:054a50936ab6 | 458 | |
| Christilut | 1:054a50936ab6 | 459 | default: |
| Christilut | 1:054a50936ab6 | 460 | error( "nRF24L01P: Invalid CRC Width setting %d\r\n", width ); |
| Christilut | 1:054a50936ab6 | 461 | return; |
| Christilut | 1:054a50936ab6 | 462 | |
| Christilut | 1:054a50936ab6 | 463 | } |
| Christilut | 1:054a50936ab6 | 464 | |
| Christilut | 1:054a50936ab6 | 465 | setRegister(_NRF24L01P_REG_CONFIG, config); |
| Christilut | 1:054a50936ab6 | 466 | |
| Christilut | 1:054a50936ab6 | 467 | } |
| Christilut | 1:054a50936ab6 | 468 | |
| Christilut | 1:054a50936ab6 | 469 | |
| Christilut | 1:054a50936ab6 | 470 | int nRF24L01P::getCrcWidth(void) |
| Christilut | 1:054a50936ab6 | 471 | { |
| Christilut | 1:054a50936ab6 | 472 | |
| Christilut | 1:054a50936ab6 | 473 | int crcWidth = getRegister(_NRF24L01P_REG_CONFIG) & _NRF24L01P_CONFIG_CRC_MASK; |
| Christilut | 1:054a50936ab6 | 474 | |
| Christilut | 1:054a50936ab6 | 475 | switch ( crcWidth ) { |
| Christilut | 1:054a50936ab6 | 476 | |
| Christilut | 1:054a50936ab6 | 477 | case _NRF24L01P_CONFIG_CRC_NONE: |
| Christilut | 1:054a50936ab6 | 478 | return NRF24L01P_CRC_NONE; |
| Christilut | 1:054a50936ab6 | 479 | |
| Christilut | 1:054a50936ab6 | 480 | case _NRF24L01P_CONFIG_CRC_8BIT: |
| Christilut | 1:054a50936ab6 | 481 | return NRF24L01P_CRC_8_BIT; |
| Christilut | 1:054a50936ab6 | 482 | |
| Christilut | 1:054a50936ab6 | 483 | case _NRF24L01P_CONFIG_CRC_16BIT: |
| Christilut | 1:054a50936ab6 | 484 | return NRF24L01P_CRC_16_BIT; |
| Christilut | 1:054a50936ab6 | 485 | |
| Christilut | 1:054a50936ab6 | 486 | default: |
| Christilut | 1:054a50936ab6 | 487 | error( "nRF24L01P: Unknown CRC Width value %d\r\n", crcWidth ); |
| Christilut | 1:054a50936ab6 | 488 | return 0; |
| Christilut | 1:054a50936ab6 | 489 | |
| Christilut | 1:054a50936ab6 | 490 | } |
| Christilut | 1:054a50936ab6 | 491 | } |
| Christilut | 1:054a50936ab6 | 492 | |
| Christilut | 1:054a50936ab6 | 493 | |
| Christilut | 1:054a50936ab6 | 494 | void nRF24L01P::setTransferSize(int size, int pipe) |
| Christilut | 1:054a50936ab6 | 495 | { |
| Christilut | 1:054a50936ab6 | 496 | |
| Christilut | 1:054a50936ab6 | 497 | if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) { |
| Christilut | 1:054a50936ab6 | 498 | |
| Christilut | 1:054a50936ab6 | 499 | error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe ); |
| Christilut | 1:054a50936ab6 | 500 | return; |
| Christilut | 1:054a50936ab6 | 501 | |
| Christilut | 1:054a50936ab6 | 502 | } |
| Christilut | 1:054a50936ab6 | 503 | |
| Christilut | 1:054a50936ab6 | 504 | if ( ( size < 0 ) || ( size > _NRF24L01P_RX_FIFO_SIZE ) ) { |
| Christilut | 1:054a50936ab6 | 505 | |
| Christilut | 1:054a50936ab6 | 506 | error( "nRF24L01P: Invalid Transfer Size setting %d\r\n", size ); |
| Christilut | 1:054a50936ab6 | 507 | return; |
| Christilut | 1:054a50936ab6 | 508 | |
| Christilut | 1:054a50936ab6 | 509 | } |
| Christilut | 1:054a50936ab6 | 510 | |
| Christilut | 1:054a50936ab6 | 511 | int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 ); |
| Christilut | 1:054a50936ab6 | 512 | |
| Christilut | 1:054a50936ab6 | 513 | setRegister(rxPwPxRegister, ( size & _NRF24L01P_RX_PW_Px_MASK ) ); |
| Christilut | 1:054a50936ab6 | 514 | |
| Christilut | 1:054a50936ab6 | 515 | } |
| Christilut | 1:054a50936ab6 | 516 | |
| Christilut | 1:054a50936ab6 | 517 | |
| Christilut | 1:054a50936ab6 | 518 | int nRF24L01P::getTransferSize(int pipe) |
| Christilut | 1:054a50936ab6 | 519 | { |
| Christilut | 1:054a50936ab6 | 520 | |
| Christilut | 1:054a50936ab6 | 521 | if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) { |
| Christilut | 1:054a50936ab6 | 522 | |
| Christilut | 1:054a50936ab6 | 523 | error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe ); |
| Christilut | 1:054a50936ab6 | 524 | return 0; |
| Christilut | 1:054a50936ab6 | 525 | |
| Christilut | 1:054a50936ab6 | 526 | } |
| Christilut | 1:054a50936ab6 | 527 | |
| Christilut | 1:054a50936ab6 | 528 | int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 ); |
| Christilut | 1:054a50936ab6 | 529 | |
| Christilut | 1:054a50936ab6 | 530 | int size = getRegister(rxPwPxRegister); |
| Christilut | 1:054a50936ab6 | 531 | |
| Christilut | 1:054a50936ab6 | 532 | return ( size & _NRF24L01P_RX_PW_Px_MASK ); |
| Christilut | 1:054a50936ab6 | 533 | |
| Christilut | 1:054a50936ab6 | 534 | } |
| Christilut | 1:054a50936ab6 | 535 | |
| Christilut | 1:054a50936ab6 | 536 | |
| Christilut | 1:054a50936ab6 | 537 | void nRF24L01P::disableAllRxPipes(void) |
| Christilut | 1:054a50936ab6 | 538 | { |
| Christilut | 1:054a50936ab6 | 539 | |
| Christilut | 1:054a50936ab6 | 540 | setRegister(_NRF24L01P_REG_EN_RXADDR, _NRF24L01P_EN_RXADDR_NONE); |
| Christilut | 1:054a50936ab6 | 541 | |
| Christilut | 1:054a50936ab6 | 542 | } |
| Christilut | 1:054a50936ab6 | 543 | |
| Christilut | 1:054a50936ab6 | 544 | |
| Christilut | 1:054a50936ab6 | 545 | void nRF24L01P::disableAutoAcknowledge(void) |
| Christilut | 1:054a50936ab6 | 546 | { |
| Christilut | 1:054a50936ab6 | 547 | |
| Christilut | 1:054a50936ab6 | 548 | setRegister(_NRF24L01P_REG_EN_AA, _NRF24L01P_EN_AA_NONE); |
| Christilut | 1:054a50936ab6 | 549 | |
| Christilut | 1:054a50936ab6 | 550 | } |
| Christilut | 1:054a50936ab6 | 551 | |
| Christilut | 1:054a50936ab6 | 552 | |
| Christilut | 1:054a50936ab6 | 553 | void nRF24L01P::enableAutoAcknowledge(int pipe) |
| Christilut | 1:054a50936ab6 | 554 | { |
| Christilut | 1:054a50936ab6 | 555 | |
| Christilut | 1:054a50936ab6 | 556 | if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) { |
| Christilut | 1:054a50936ab6 | 557 | |
| Christilut | 1:054a50936ab6 | 558 | error( "nRF24L01P: Invalid Enable AutoAcknowledge pipe number %d\r\n", pipe ); |
| Christilut | 1:054a50936ab6 | 559 | return; |
| Christilut | 1:054a50936ab6 | 560 | |
| Christilut | 1:054a50936ab6 | 561 | } |
| Christilut | 1:054a50936ab6 | 562 | |
| Christilut | 1:054a50936ab6 | 563 | int enAA = getRegister(_NRF24L01P_REG_EN_AA); |
| Christilut | 1:054a50936ab6 | 564 | |
| Christilut | 1:054a50936ab6 | 565 | enAA |= ( 1 << (pipe - NRF24L01P_PIPE_P0) ); |
| Christilut | 1:054a50936ab6 | 566 | |
| Christilut | 1:054a50936ab6 | 567 | setRegister(_NRF24L01P_REG_EN_AA, enAA); |
| Christilut | 1:054a50936ab6 | 568 | |
| Christilut | 1:054a50936ab6 | 569 | } |
| Christilut | 1:054a50936ab6 | 570 | |
| Christilut | 1:054a50936ab6 | 571 | |
| Christilut | 1:054a50936ab6 | 572 | void nRF24L01P::disableAutoRetransmit(void) |
| Christilut | 1:054a50936ab6 | 573 | { |
| Christilut | 1:054a50936ab6 | 574 | |
| Christilut | 1:054a50936ab6 | 575 | setRegister(_NRF24L01P_REG_SETUP_RETR, _NRF24L01P_SETUP_RETR_NONE); |
| Christilut | 1:054a50936ab6 | 576 | |
| Christilut | 1:054a50936ab6 | 577 | } |
| Christilut | 1:054a50936ab6 | 578 | |
| Christilut | 1:054a50936ab6 | 579 | void nRF24L01P::setRxAddress(unsigned long long address, int width, int pipe) |
| Christilut | 1:054a50936ab6 | 580 | { |
| Christilut | 1:054a50936ab6 | 581 | |
| Christilut | 1:054a50936ab6 | 582 | if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) { |
| Christilut | 1:054a50936ab6 | 583 | |
| Christilut | 1:054a50936ab6 | 584 | error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe ); |
| Christilut | 1:054a50936ab6 | 585 | return; |
| Christilut | 1:054a50936ab6 | 586 | |
| Christilut | 1:054a50936ab6 | 587 | } |
| Christilut | 1:054a50936ab6 | 588 | |
| Christilut | 1:054a50936ab6 | 589 | if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) { |
| Christilut | 1:054a50936ab6 | 590 | |
| Christilut | 1:054a50936ab6 | 591 | int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK; |
| Christilut | 1:054a50936ab6 | 592 | |
| Christilut | 1:054a50936ab6 | 593 | switch ( width ) { |
| Christilut | 1:054a50936ab6 | 594 | |
| Christilut | 1:054a50936ab6 | 595 | case 3: |
| Christilut | 1:054a50936ab6 | 596 | setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE; |
| Christilut | 1:054a50936ab6 | 597 | break; |
| Christilut | 1:054a50936ab6 | 598 | |
| Christilut | 1:054a50936ab6 | 599 | case 4: |
| Christilut | 1:054a50936ab6 | 600 | setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE; |
| Christilut | 1:054a50936ab6 | 601 | break; |
| Christilut | 1:054a50936ab6 | 602 | |
| Christilut | 1:054a50936ab6 | 603 | case 5: |
| Christilut | 1:054a50936ab6 | 604 | setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE; |
| Christilut | 1:054a50936ab6 | 605 | break; |
| Christilut | 1:054a50936ab6 | 606 | |
| Christilut | 1:054a50936ab6 | 607 | default: |
| Christilut | 1:054a50936ab6 | 608 | error( "nRF24L01P: Invalid setRxAddress width setting %d\r\n", width ); |
| Christilut | 1:054a50936ab6 | 609 | return; |
| Christilut | 1:054a50936ab6 | 610 | |
| Christilut | 1:054a50936ab6 | 611 | } |
| Christilut | 1:054a50936ab6 | 612 | |
| Christilut | 1:054a50936ab6 | 613 | setRegister(_NRF24L01P_REG_SETUP_AW, setupAw); |
| Christilut | 1:054a50936ab6 | 614 | |
| Christilut | 1:054a50936ab6 | 615 | } else { |
| Christilut | 1:054a50936ab6 | 616 | |
| Christilut | 1:054a50936ab6 | 617 | width = 1; |
| Christilut | 1:054a50936ab6 | 618 | |
| Christilut | 1:054a50936ab6 | 619 | } |
| Christilut | 1:054a50936ab6 | 620 | |
| Christilut | 1:054a50936ab6 | 621 | int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 ); |
| Christilut | 1:054a50936ab6 | 622 | |
| Christilut | 1:054a50936ab6 | 623 | int cn = (_NRF24L01P_SPI_CMD_WR_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK)); |
| Christilut | 1:054a50936ab6 | 624 | |
| Christilut | 1:054a50936ab6 | 625 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 626 | |
| Christilut | 1:054a50936ab6 | 627 | int status = spi_.write(cn); |
| Christilut | 1:054a50936ab6 | 628 | |
| Christilut | 1:054a50936ab6 | 629 | while ( width-- > 0 ) { |
| Christilut | 1:054a50936ab6 | 630 | |
| Christilut | 1:054a50936ab6 | 631 | // |
| Christilut | 1:054a50936ab6 | 632 | // LSByte first |
| Christilut | 1:054a50936ab6 | 633 | // |
| Christilut | 1:054a50936ab6 | 634 | spi_.write((int) (address & 0xFF)); |
| Christilut | 1:054a50936ab6 | 635 | address >>= 8; |
| Christilut | 1:054a50936ab6 | 636 | |
| Christilut | 1:054a50936ab6 | 637 | } |
| Christilut | 1:054a50936ab6 | 638 | |
| Christilut | 1:054a50936ab6 | 639 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 640 | |
| Christilut | 1:054a50936ab6 | 641 | int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR); |
| Christilut | 1:054a50936ab6 | 642 | |
| Christilut | 1:054a50936ab6 | 643 | enRxAddr |= (1 << ( pipe - NRF24L01P_PIPE_P0 ) ); |
| Christilut | 1:054a50936ab6 | 644 | |
| Christilut | 1:054a50936ab6 | 645 | setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr); |
| Christilut | 1:054a50936ab6 | 646 | } |
| Christilut | 1:054a50936ab6 | 647 | |
| Christilut | 1:054a50936ab6 | 648 | /* |
| Christilut | 1:054a50936ab6 | 649 | * This version of setRxAddress is just a wrapper for the version that takes 'long long's, |
| Christilut | 1:054a50936ab6 | 650 | * in case the main code doesn't want to deal with long long's. |
| Christilut | 1:054a50936ab6 | 651 | */ |
| Christilut | 1:054a50936ab6 | 652 | void nRF24L01P::setRxAddress(unsigned long msb_address, unsigned long lsb_address, int width, int pipe) |
| Christilut | 1:054a50936ab6 | 653 | { |
| Christilut | 1:054a50936ab6 | 654 | |
| Christilut | 1:054a50936ab6 | 655 | unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 ); |
| Christilut | 1:054a50936ab6 | 656 | |
| Christilut | 1:054a50936ab6 | 657 | setRxAddress(address, width, pipe); |
| Christilut | 1:054a50936ab6 | 658 | |
| Christilut | 1:054a50936ab6 | 659 | } |
| Christilut | 1:054a50936ab6 | 660 | |
| Christilut | 1:054a50936ab6 | 661 | |
| Christilut | 1:054a50936ab6 | 662 | /* |
| Christilut | 1:054a50936ab6 | 663 | * This version of setTxAddress is just a wrapper for the version that takes 'long long's, |
| Christilut | 1:054a50936ab6 | 664 | * in case the main code doesn't want to deal with long long's. |
| Christilut | 1:054a50936ab6 | 665 | */ |
| Christilut | 1:054a50936ab6 | 666 | void nRF24L01P::setTxAddress(unsigned long msb_address, unsigned long lsb_address, int width) |
| Christilut | 1:054a50936ab6 | 667 | { |
| Christilut | 1:054a50936ab6 | 668 | |
| Christilut | 1:054a50936ab6 | 669 | unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 ); |
| Christilut | 1:054a50936ab6 | 670 | |
| Christilut | 1:054a50936ab6 | 671 | setTxAddress(address, width); |
| Christilut | 1:054a50936ab6 | 672 | |
| Christilut | 1:054a50936ab6 | 673 | } |
| Christilut | 1:054a50936ab6 | 674 | |
| Christilut | 1:054a50936ab6 | 675 | |
| Christilut | 1:054a50936ab6 | 676 | void nRF24L01P::setTxAddress(unsigned long long address, int width) |
| Christilut | 1:054a50936ab6 | 677 | { |
| Christilut | 1:054a50936ab6 | 678 | |
| Christilut | 1:054a50936ab6 | 679 | int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK; |
| Christilut | 1:054a50936ab6 | 680 | |
| Christilut | 1:054a50936ab6 | 681 | switch ( width ) { |
| Christilut | 1:054a50936ab6 | 682 | |
| Christilut | 1:054a50936ab6 | 683 | case 3: |
| Christilut | 1:054a50936ab6 | 684 | setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE; |
| Christilut | 1:054a50936ab6 | 685 | break; |
| Christilut | 1:054a50936ab6 | 686 | |
| Christilut | 1:054a50936ab6 | 687 | case 4: |
| Christilut | 1:054a50936ab6 | 688 | setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE; |
| Christilut | 1:054a50936ab6 | 689 | break; |
| Christilut | 1:054a50936ab6 | 690 | |
| Christilut | 1:054a50936ab6 | 691 | case 5: |
| Christilut | 1:054a50936ab6 | 692 | setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE; |
| Christilut | 1:054a50936ab6 | 693 | break; |
| Christilut | 1:054a50936ab6 | 694 | |
| Christilut | 1:054a50936ab6 | 695 | default: |
| Christilut | 1:054a50936ab6 | 696 | error( "nRF24L01P: Invalid setTxAddress width setting %d\r\n", width ); |
| Christilut | 1:054a50936ab6 | 697 | return; |
| Christilut | 1:054a50936ab6 | 698 | |
| Christilut | 1:054a50936ab6 | 699 | } |
| Christilut | 1:054a50936ab6 | 700 | |
| Christilut | 1:054a50936ab6 | 701 | setRegister(_NRF24L01P_REG_SETUP_AW, setupAw); |
| Christilut | 1:054a50936ab6 | 702 | |
| Christilut | 1:054a50936ab6 | 703 | int cn = (_NRF24L01P_SPI_CMD_WR_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK)); |
| Christilut | 1:054a50936ab6 | 704 | |
| Christilut | 1:054a50936ab6 | 705 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 706 | |
| Christilut | 1:054a50936ab6 | 707 | int status = spi_.write(cn); |
| Christilut | 1:054a50936ab6 | 708 | |
| Christilut | 1:054a50936ab6 | 709 | while ( width-- > 0 ) { |
| Christilut | 1:054a50936ab6 | 710 | |
| Christilut | 1:054a50936ab6 | 711 | // |
| Christilut | 1:054a50936ab6 | 712 | // LSByte first |
| Christilut | 1:054a50936ab6 | 713 | // |
| Christilut | 1:054a50936ab6 | 714 | spi_.write((int) (address & 0xFF)); |
| Christilut | 1:054a50936ab6 | 715 | address >>= 8; |
| Christilut | 1:054a50936ab6 | 716 | |
| Christilut | 1:054a50936ab6 | 717 | } |
| Christilut | 1:054a50936ab6 | 718 | |
| Christilut | 1:054a50936ab6 | 719 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 720 | |
| Christilut | 1:054a50936ab6 | 721 | } |
| Christilut | 1:054a50936ab6 | 722 | |
| Christilut | 1:054a50936ab6 | 723 | |
| Christilut | 1:054a50936ab6 | 724 | unsigned long long nRF24L01P::getRxAddress(int pipe) |
| Christilut | 1:054a50936ab6 | 725 | { |
| Christilut | 1:054a50936ab6 | 726 | |
| Christilut | 1:054a50936ab6 | 727 | if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) { |
| Christilut | 1:054a50936ab6 | 728 | |
| Christilut | 1:054a50936ab6 | 729 | error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe ); |
| Christilut | 1:054a50936ab6 | 730 | return 0; |
| Christilut | 1:054a50936ab6 | 731 | |
| Christilut | 1:054a50936ab6 | 732 | } |
| Christilut | 1:054a50936ab6 | 733 | |
| Christilut | 1:054a50936ab6 | 734 | int width; |
| Christilut | 1:054a50936ab6 | 735 | |
| Christilut | 1:054a50936ab6 | 736 | if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) { |
| Christilut | 1:054a50936ab6 | 737 | |
| Christilut | 1:054a50936ab6 | 738 | int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK; |
| Christilut | 1:054a50936ab6 | 739 | |
| Christilut | 1:054a50936ab6 | 740 | switch ( setupAw ) { |
| Christilut | 1:054a50936ab6 | 741 | |
| Christilut | 1:054a50936ab6 | 742 | case _NRF24L01P_SETUP_AW_AW_3BYTE: |
| Christilut | 1:054a50936ab6 | 743 | width = 3; |
| Christilut | 1:054a50936ab6 | 744 | break; |
| Christilut | 1:054a50936ab6 | 745 | |
| Christilut | 1:054a50936ab6 | 746 | case _NRF24L01P_SETUP_AW_AW_4BYTE: |
| Christilut | 1:054a50936ab6 | 747 | width = 4; |
| Christilut | 1:054a50936ab6 | 748 | break; |
| Christilut | 1:054a50936ab6 | 749 | |
| Christilut | 1:054a50936ab6 | 750 | case _NRF24L01P_SETUP_AW_AW_5BYTE: |
| Christilut | 1:054a50936ab6 | 751 | width = 5; |
| Christilut | 1:054a50936ab6 | 752 | break; |
| Christilut | 1:054a50936ab6 | 753 | |
| Christilut | 1:054a50936ab6 | 754 | default: |
| Christilut | 1:054a50936ab6 | 755 | error( "nRF24L01P: Unknown getRxAddress width value %d\r\n", setupAw ); |
| Christilut | 1:054a50936ab6 | 756 | return 0; |
| Christilut | 1:054a50936ab6 | 757 | |
| Christilut | 1:054a50936ab6 | 758 | } |
| Christilut | 1:054a50936ab6 | 759 | |
| Christilut | 1:054a50936ab6 | 760 | } else { |
| Christilut | 1:054a50936ab6 | 761 | |
| Christilut | 1:054a50936ab6 | 762 | width = 1; |
| Christilut | 1:054a50936ab6 | 763 | |
| Christilut | 1:054a50936ab6 | 764 | } |
| Christilut | 1:054a50936ab6 | 765 | |
| Christilut | 1:054a50936ab6 | 766 | int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 ); |
| Christilut | 1:054a50936ab6 | 767 | |
| Christilut | 1:054a50936ab6 | 768 | int cn = (_NRF24L01P_SPI_CMD_RD_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK)); |
| Christilut | 1:054a50936ab6 | 769 | |
| Christilut | 1:054a50936ab6 | 770 | unsigned long long address = 0; |
| Christilut | 1:054a50936ab6 | 771 | |
| Christilut | 1:054a50936ab6 | 772 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 773 | |
| Christilut | 1:054a50936ab6 | 774 | int status = spi_.write(cn); |
| Christilut | 1:054a50936ab6 | 775 | |
| Christilut | 1:054a50936ab6 | 776 | for ( int i=0; i<width; i++ ) { |
| Christilut | 1:054a50936ab6 | 777 | |
| Christilut | 1:054a50936ab6 | 778 | // |
| Christilut | 1:054a50936ab6 | 779 | // LSByte first |
| Christilut | 1:054a50936ab6 | 780 | // |
| Christilut | 1:054a50936ab6 | 781 | address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) ); |
| Christilut | 1:054a50936ab6 | 782 | |
| Christilut | 1:054a50936ab6 | 783 | } |
| Christilut | 1:054a50936ab6 | 784 | |
| Christilut | 1:054a50936ab6 | 785 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 786 | |
| Christilut | 1:054a50936ab6 | 787 | if ( !( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) ) { |
| Christilut | 1:054a50936ab6 | 788 | |
| Christilut | 1:054a50936ab6 | 789 | address |= ( getRxAddress(NRF24L01P_PIPE_P1) & ~((unsigned long long) 0xFF) ); |
| Christilut | 1:054a50936ab6 | 790 | |
| Christilut | 1:054a50936ab6 | 791 | } |
| Christilut | 1:054a50936ab6 | 792 | |
| Christilut | 1:054a50936ab6 | 793 | return address; |
| Christilut | 1:054a50936ab6 | 794 | |
| Christilut | 1:054a50936ab6 | 795 | } |
| Christilut | 1:054a50936ab6 | 796 | |
| Christilut | 1:054a50936ab6 | 797 | |
| Christilut | 1:054a50936ab6 | 798 | unsigned long long nRF24L01P::getTxAddress(void) |
| Christilut | 1:054a50936ab6 | 799 | { |
| Christilut | 1:054a50936ab6 | 800 | |
| Christilut | 1:054a50936ab6 | 801 | int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK; |
| Christilut | 1:054a50936ab6 | 802 | |
| Christilut | 1:054a50936ab6 | 803 | int width; |
| Christilut | 1:054a50936ab6 | 804 | |
| Christilut | 1:054a50936ab6 | 805 | switch ( setupAw ) { |
| Christilut | 1:054a50936ab6 | 806 | |
| Christilut | 1:054a50936ab6 | 807 | case _NRF24L01P_SETUP_AW_AW_3BYTE: |
| Christilut | 1:054a50936ab6 | 808 | width = 3; |
| Christilut | 1:054a50936ab6 | 809 | break; |
| Christilut | 1:054a50936ab6 | 810 | |
| Christilut | 1:054a50936ab6 | 811 | case _NRF24L01P_SETUP_AW_AW_4BYTE: |
| Christilut | 1:054a50936ab6 | 812 | width = 4; |
| Christilut | 1:054a50936ab6 | 813 | break; |
| Christilut | 1:054a50936ab6 | 814 | |
| Christilut | 1:054a50936ab6 | 815 | case _NRF24L01P_SETUP_AW_AW_5BYTE: |
| Christilut | 1:054a50936ab6 | 816 | width = 5; |
| Christilut | 1:054a50936ab6 | 817 | break; |
| Christilut | 1:054a50936ab6 | 818 | |
| Christilut | 1:054a50936ab6 | 819 | default: |
| Christilut | 1:054a50936ab6 | 820 | error( "nRF24L01P: Unknown getTxAddress width value %d\r\n", setupAw ); |
| Christilut | 1:054a50936ab6 | 821 | return 0; |
| Christilut | 1:054a50936ab6 | 822 | |
| Christilut | 1:054a50936ab6 | 823 | } |
| Christilut | 1:054a50936ab6 | 824 | |
| Christilut | 1:054a50936ab6 | 825 | int cn = (_NRF24L01P_SPI_CMD_RD_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK)); |
| Christilut | 1:054a50936ab6 | 826 | |
| Christilut | 1:054a50936ab6 | 827 | unsigned long long address = 0; |
| Christilut | 1:054a50936ab6 | 828 | |
| Christilut | 1:054a50936ab6 | 829 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 830 | |
| Christilut | 1:054a50936ab6 | 831 | int status = spi_.write(cn); |
| Christilut | 1:054a50936ab6 | 832 | |
| Christilut | 1:054a50936ab6 | 833 | for ( int i=0; i<width; i++ ) { |
| Christilut | 1:054a50936ab6 | 834 | |
| Christilut | 1:054a50936ab6 | 835 | // |
| Christilut | 1:054a50936ab6 | 836 | // LSByte first |
| Christilut | 1:054a50936ab6 | 837 | // |
| Christilut | 1:054a50936ab6 | 838 | address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) ); |
| Christilut | 1:054a50936ab6 | 839 | |
| Christilut | 1:054a50936ab6 | 840 | } |
| Christilut | 1:054a50936ab6 | 841 | |
| Christilut | 1:054a50936ab6 | 842 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 843 | |
| Christilut | 1:054a50936ab6 | 844 | return address; |
| Christilut | 1:054a50936ab6 | 845 | } |
| Christilut | 1:054a50936ab6 | 846 | |
| Christilut | 1:054a50936ab6 | 847 | |
| Christilut | 1:054a50936ab6 | 848 | bool nRF24L01P::readable(int pipe) |
| Christilut | 1:054a50936ab6 | 849 | { |
| Christilut | 1:054a50936ab6 | 850 | |
| Christilut | 1:054a50936ab6 | 851 | if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) { |
| Christilut | 1:054a50936ab6 | 852 | |
| Christilut | 1:054a50936ab6 | 853 | error( "nRF24L01P: Invalid readable pipe number %d\r\n", pipe ); |
| Christilut | 1:054a50936ab6 | 854 | return false; |
| Christilut | 1:054a50936ab6 | 855 | |
| Christilut | 1:054a50936ab6 | 856 | } |
| Christilut | 1:054a50936ab6 | 857 | |
| Christilut | 1:054a50936ab6 | 858 | int status = getStatusRegister(); |
| Christilut | 1:054a50936ab6 | 859 | |
| Christilut | 1:054a50936ab6 | 860 | return ( ( status & _NRF24L01P_STATUS_RX_DR ) && ( ( ( status & _NRF24L01P_STATUS_RX_P_NO ) >> 1 ) == ( pipe & 0x7 ) ) ); |
| Christilut | 1:054a50936ab6 | 861 | |
| Christilut | 1:054a50936ab6 | 862 | } |
| Christilut | 1:054a50936ab6 | 863 | |
| Christilut | 1:054a50936ab6 | 864 | |
| Christilut | 1:054a50936ab6 | 865 | int nRF24L01P::write(int pipe, char *data, int count) |
| Christilut | 1:054a50936ab6 | 866 | { |
| Christilut | 1:054a50936ab6 | 867 | |
| Christilut | 1:054a50936ab6 | 868 | // Note: the pipe number is ignored in a Transmit / write |
| Christilut | 1:054a50936ab6 | 869 | |
| Christilut | 1:054a50936ab6 | 870 | // |
| Christilut | 1:054a50936ab6 | 871 | // Save the CE state |
| Christilut | 1:054a50936ab6 | 872 | // |
| Christilut | 1:054a50936ab6 | 873 | int originalCe = ce_; |
| Christilut | 1:054a50936ab6 | 874 | disable(); |
| Christilut | 1:054a50936ab6 | 875 | |
| Christilut | 1:054a50936ab6 | 876 | if ( count <= 0 ) return 0; |
| Christilut | 1:054a50936ab6 | 877 | |
| Christilut | 1:054a50936ab6 | 878 | if ( count > _NRF24L01P_TX_FIFO_SIZE ) count = _NRF24L01P_TX_FIFO_SIZE; |
| Christilut | 1:054a50936ab6 | 879 | |
| Christilut | 1:054a50936ab6 | 880 | // Clear the Status bit |
| Christilut | 1:054a50936ab6 | 881 | setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS); |
| Christilut | 1:054a50936ab6 | 882 | |
| Christilut | 1:054a50936ab6 | 883 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 884 | |
| Christilut | 1:054a50936ab6 | 885 | int status = spi_.write(_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD); |
| Christilut | 1:054a50936ab6 | 886 | |
| Christilut | 1:054a50936ab6 | 887 | for ( int i = 0; i < count; i++ ) { |
| Christilut | 1:054a50936ab6 | 888 | |
| Christilut | 1:054a50936ab6 | 889 | spi_.write(*data++); |
| Christilut | 1:054a50936ab6 | 890 | |
| Christilut | 1:054a50936ab6 | 891 | } |
| Christilut | 1:054a50936ab6 | 892 | |
| Christilut | 1:054a50936ab6 | 893 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 894 | |
| Christilut | 1:054a50936ab6 | 895 | int originalMode = mode; |
| Christilut | 1:054a50936ab6 | 896 | setTransmitMode(); |
| Christilut | 1:054a50936ab6 | 897 | |
| Christilut | 1:054a50936ab6 | 898 | enable(); |
| Christilut | 1:054a50936ab6 | 899 | wait_us(_NRF24L01P_TIMING_Thce_us); |
| Christilut | 1:054a50936ab6 | 900 | disable(); |
| Christilut | 1:054a50936ab6 | 901 | |
| Christilut | 1:054a50936ab6 | 902 | while ( !( getStatusRegister() & _NRF24L01P_STATUS_TX_DS ) ) { |
| Christilut | 1:054a50936ab6 | 903 | |
| Christilut | 1:054a50936ab6 | 904 | // Wait for the transfer to complete |
| Christilut | 1:054a50936ab6 | 905 | |
| Christilut | 1:054a50936ab6 | 906 | } |
| Christilut | 1:054a50936ab6 | 907 | |
| Christilut | 1:054a50936ab6 | 908 | // Clear the Status bit |
| Christilut | 1:054a50936ab6 | 909 | setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS); |
| Christilut | 1:054a50936ab6 | 910 | |
| Christilut | 1:054a50936ab6 | 911 | if ( originalMode == _NRF24L01P_MODE_RX ) { |
| Christilut | 1:054a50936ab6 | 912 | |
| Christilut | 1:054a50936ab6 | 913 | setReceiveMode(); |
| Christilut | 1:054a50936ab6 | 914 | |
| Christilut | 1:054a50936ab6 | 915 | } |
| Christilut | 1:054a50936ab6 | 916 | |
| Christilut | 1:054a50936ab6 | 917 | ce_ = originalCe; |
| Christilut | 1:054a50936ab6 | 918 | wait_us( _NRF24L01P_TIMING_Tpece2csn_us ); |
| Christilut | 1:054a50936ab6 | 919 | |
| Christilut | 1:054a50936ab6 | 920 | return count; |
| Christilut | 1:054a50936ab6 | 921 | |
| Christilut | 1:054a50936ab6 | 922 | } |
| Christilut | 1:054a50936ab6 | 923 | |
| Christilut | 1:054a50936ab6 | 924 | |
| Christilut | 1:054a50936ab6 | 925 | int nRF24L01P::read(int pipe, char *data, int count) |
| Christilut | 1:054a50936ab6 | 926 | { |
| Christilut | 1:054a50936ab6 | 927 | |
| Christilut | 1:054a50936ab6 | 928 | if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) { |
| Christilut | 1:054a50936ab6 | 929 | |
| Christilut | 1:054a50936ab6 | 930 | error( "nRF24L01P: Invalid read pipe number %d\r\n", pipe ); |
| Christilut | 1:054a50936ab6 | 931 | return -1; |
| Christilut | 1:054a50936ab6 | 932 | |
| Christilut | 1:054a50936ab6 | 933 | } |
| Christilut | 1:054a50936ab6 | 934 | |
| Christilut | 1:054a50936ab6 | 935 | if ( count <= 0 ) return 0; |
| Christilut | 1:054a50936ab6 | 936 | |
| Christilut | 1:054a50936ab6 | 937 | if ( count > _NRF24L01P_RX_FIFO_SIZE ) count = _NRF24L01P_RX_FIFO_SIZE; |
| Christilut | 1:054a50936ab6 | 938 | |
| Christilut | 1:054a50936ab6 | 939 | if ( readable(pipe) ) { |
| Christilut | 1:054a50936ab6 | 940 | |
| Christilut | 1:054a50936ab6 | 941 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 942 | |
| Christilut | 1:054a50936ab6 | 943 | int status = spi_.write(_NRF24L01P_SPI_CMD_R_RX_PL_WID); |
| Christilut | 1:054a50936ab6 | 944 | |
| Christilut | 1:054a50936ab6 | 945 | int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP); |
| Christilut | 1:054a50936ab6 | 946 | |
| Christilut | 1:054a50936ab6 | 947 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 948 | |
| Christilut | 1:054a50936ab6 | 949 | if ( ( rxPayloadWidth < 0 ) || ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) { |
| Christilut | 1:054a50936ab6 | 950 | |
| Christilut | 1:054a50936ab6 | 951 | // Received payload error: need to flush the FIFO |
| Christilut | 1:054a50936ab6 | 952 | |
| Christilut | 1:054a50936ab6 | 953 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 954 | |
| Christilut | 1:054a50936ab6 | 955 | int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX); |
| Christilut | 1:054a50936ab6 | 956 | |
| Christilut | 1:054a50936ab6 | 957 | int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP); |
| Christilut | 1:054a50936ab6 | 958 | |
| Christilut | 1:054a50936ab6 | 959 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 960 | |
| Christilut | 1:054a50936ab6 | 961 | // |
| Christilut | 1:054a50936ab6 | 962 | // At this point, we should retry the reception, |
| Christilut | 1:054a50936ab6 | 963 | // but for now we'll just fall through... |
| Christilut | 1:054a50936ab6 | 964 | // |
| Christilut | 1:054a50936ab6 | 965 | |
| Christilut | 1:054a50936ab6 | 966 | } else { |
| Christilut | 1:054a50936ab6 | 967 | |
| Christilut | 1:054a50936ab6 | 968 | if ( rxPayloadWidth < count ) count = rxPayloadWidth; |
| Christilut | 1:054a50936ab6 | 969 | |
| Christilut | 1:054a50936ab6 | 970 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 971 | |
| Christilut | 1:054a50936ab6 | 972 | int status = spi_.write(_NRF24L01P_SPI_CMD_RD_RX_PAYLOAD); |
| Christilut | 1:054a50936ab6 | 973 | |
| Christilut | 1:054a50936ab6 | 974 | for ( int i = 0; i < count; i++ ) { |
| Christilut | 1:054a50936ab6 | 975 | |
| Christilut | 1:054a50936ab6 | 976 | *data++ = spi_.write(_NRF24L01P_SPI_CMD_NOP); |
| Christilut | 1:054a50936ab6 | 977 | |
| Christilut | 1:054a50936ab6 | 978 | } |
| Christilut | 1:054a50936ab6 | 979 | |
| Christilut | 1:054a50936ab6 | 980 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 981 | |
| Christilut | 1:054a50936ab6 | 982 | // Clear the Status bit |
| Christilut | 1:054a50936ab6 | 983 | setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_RX_DR); |
| Christilut | 1:054a50936ab6 | 984 | |
| Christilut | 1:054a50936ab6 | 985 | return count; |
| Christilut | 1:054a50936ab6 | 986 | |
| Christilut | 1:054a50936ab6 | 987 | } |
| Christilut | 1:054a50936ab6 | 988 | |
| Christilut | 1:054a50936ab6 | 989 | } else { |
| Christilut | 1:054a50936ab6 | 990 | |
| Christilut | 1:054a50936ab6 | 991 | // |
| Christilut | 1:054a50936ab6 | 992 | // What should we do if there is no 'readable' data? |
| Christilut | 1:054a50936ab6 | 993 | // We could wait for data to arrive, but for now, we'll |
| Christilut | 1:054a50936ab6 | 994 | // just return with no data. |
| Christilut | 1:054a50936ab6 | 995 | // |
| Christilut | 1:054a50936ab6 | 996 | return 0; |
| Christilut | 1:054a50936ab6 | 997 | |
| Christilut | 1:054a50936ab6 | 998 | } |
| Christilut | 1:054a50936ab6 | 999 | |
| Christilut | 1:054a50936ab6 | 1000 | // |
| Christilut | 1:054a50936ab6 | 1001 | // We get here because an error condition occured; |
| Christilut | 1:054a50936ab6 | 1002 | // We could wait for data to arrive, but for now, we'll |
| Christilut | 1:054a50936ab6 | 1003 | // just return with no data. |
| Christilut | 1:054a50936ab6 | 1004 | // |
| Christilut | 1:054a50936ab6 | 1005 | return -1; |
| Christilut | 1:054a50936ab6 | 1006 | |
| Christilut | 1:054a50936ab6 | 1007 | } |
| Christilut | 1:054a50936ab6 | 1008 | |
| Christilut | 1:054a50936ab6 | 1009 | void nRF24L01P::setRegister(int regAddress, int regData) |
| Christilut | 1:054a50936ab6 | 1010 | { |
| Christilut | 1:054a50936ab6 | 1011 | |
| Christilut | 1:054a50936ab6 | 1012 | // |
| Christilut | 1:054a50936ab6 | 1013 | // Save the CE state |
| Christilut | 1:054a50936ab6 | 1014 | // |
| Christilut | 1:054a50936ab6 | 1015 | int originalCe = ce_; |
| Christilut | 1:054a50936ab6 | 1016 | disable(); |
| Christilut | 1:054a50936ab6 | 1017 | |
| Christilut | 1:054a50936ab6 | 1018 | int cn = (_NRF24L01P_SPI_CMD_WR_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK)); |
| Christilut | 1:054a50936ab6 | 1019 | |
| Christilut | 1:054a50936ab6 | 1020 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 1021 | |
| Christilut | 1:054a50936ab6 | 1022 | int status = spi_.write(cn); |
| Christilut | 1:054a50936ab6 | 1023 | |
| Christilut | 1:054a50936ab6 | 1024 | spi_.write(regData & 0xFF); |
| Christilut | 1:054a50936ab6 | 1025 | |
| Christilut | 1:054a50936ab6 | 1026 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 1027 | |
| Christilut | 1:054a50936ab6 | 1028 | ce_ = originalCe; |
| Christilut | 1:054a50936ab6 | 1029 | wait_us( _NRF24L01P_TIMING_Tpece2csn_us ); |
| Christilut | 1:054a50936ab6 | 1030 | |
| Christilut | 1:054a50936ab6 | 1031 | } |
| Christilut | 1:054a50936ab6 | 1032 | |
| Christilut | 1:054a50936ab6 | 1033 | |
| Christilut | 1:054a50936ab6 | 1034 | int nRF24L01P::getRegister(int regAddress) |
| Christilut | 1:054a50936ab6 | 1035 | { |
| Christilut | 1:054a50936ab6 | 1036 | |
| Christilut | 1:054a50936ab6 | 1037 | int cn = (_NRF24L01P_SPI_CMD_RD_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK)); |
| Christilut | 1:054a50936ab6 | 1038 | |
| Christilut | 1:054a50936ab6 | 1039 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 1040 | |
| Christilut | 1:054a50936ab6 | 1041 | int status = spi_.write(cn); |
| Christilut | 1:054a50936ab6 | 1042 | |
| Christilut | 1:054a50936ab6 | 1043 | int dn = spi_.write(_NRF24L01P_SPI_CMD_NOP); |
| Christilut | 1:054a50936ab6 | 1044 | |
| Christilut | 1:054a50936ab6 | 1045 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 1046 | |
| Christilut | 1:054a50936ab6 | 1047 | return dn; |
| Christilut | 1:054a50936ab6 | 1048 | |
| Christilut | 1:054a50936ab6 | 1049 | } |
| Christilut | 1:054a50936ab6 | 1050 | |
| Christilut | 1:054a50936ab6 | 1051 | int nRF24L01P::getStatusRegister(void) |
| Christilut | 1:054a50936ab6 | 1052 | { |
| Christilut | 1:054a50936ab6 | 1053 | |
| Christilut | 1:054a50936ab6 | 1054 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 1055 | |
| Christilut | 1:054a50936ab6 | 1056 | int status = spi_.write(_NRF24L01P_SPI_CMD_NOP); |
| Christilut | 1:054a50936ab6 | 1057 | |
| Christilut | 1:054a50936ab6 | 1058 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 1059 | |
| Christilut | 1:054a50936ab6 | 1060 | return status; |
| Christilut | 1:054a50936ab6 | 1061 | |
| Christilut | 1:054a50936ab6 | 1062 | } |
| Christilut | 1:054a50936ab6 | 1063 | |
| Christilut | 1:054a50936ab6 | 1064 | int nRF24L01P::flushRxBuffer(void) |
| Christilut | 1:054a50936ab6 | 1065 | { |
| Christilut | 1:054a50936ab6 | 1066 | |
| Christilut | 1:054a50936ab6 | 1067 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 1068 | |
| Christilut | 1:054a50936ab6 | 1069 | int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX); |
| Christilut | 1:054a50936ab6 | 1070 | |
| Christilut | 1:054a50936ab6 | 1071 | int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP); |
| Christilut | 1:054a50936ab6 | 1072 | |
| Christilut | 1:054a50936ab6 | 1073 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 1074 | |
| Christilut | 1:054a50936ab6 | 1075 | return status; |
| Christilut | 1:054a50936ab6 | 1076 | |
| Christilut | 1:054a50936ab6 | 1077 | } |
| Christilut | 1:054a50936ab6 | 1078 | |
| Christilut | 1:054a50936ab6 | 1079 | int nRF24L01P::flushTxBuffer(void) |
| Christilut | 1:054a50936ab6 | 1080 | { |
| Christilut | 1:054a50936ab6 | 1081 | |
| Christilut | 1:054a50936ab6 | 1082 | nCS_ = 0; |
| Christilut | 1:054a50936ab6 | 1083 | |
| Christilut | 1:054a50936ab6 | 1084 | int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_TX); |
| Christilut | 1:054a50936ab6 | 1085 | |
| Christilut | 1:054a50936ab6 | 1086 | int txPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP); |
| Christilut | 1:054a50936ab6 | 1087 | |
| Christilut | 1:054a50936ab6 | 1088 | nCS_ = 1; |
| Christilut | 1:054a50936ab6 | 1089 | |
| Christilut | 1:054a50936ab6 | 1090 | return status; |
| Christilut | 1:054a50936ab6 | 1091 | } |