Robert Bolling / FXOS8700CQ

minor changes to support mobile life IoT project

Fork of FXOS8700CQ by Thomas Murphy

FXOS8700CQ.h@4:e2fe752b881e, 2014-06-03 (annotated)

Committer:
trm
Date:
Tue Jun 03 19:02:19 2014 +0000
Revision:
4:e2fe752b881e
Parent:
3:2ce85aa45d7d
Child:
5:fb4cef1399b8
Removed extraneous "#define"s.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
trm 0:cf6299acfe98 1 #ifndef FXOS8700CQ_H
trm 0:cf6299acfe98 2 #define FXOS8700CQ_H
trm 0:cf6299acfe98 3
trm 0:cf6299acfe98 4 #include "mbed.h" // Building this for the mbed platform
trm 0:cf6299acfe98 5
trm 0:cf6299acfe98 6 #define I2C_400K 400000
trm 0:cf6299acfe98 7
trm 0:cf6299acfe98 8 // FXOS8700CQ I2C address
trm 0:cf6299acfe98 9 #define FXOS8700CQ_SLAVE_ADDR0 (0x1E<<1) // with pins SA0=0, SA1=0
trm 0:cf6299acfe98 10 #define FXOS8700CQ_SLAVE_ADDR1 (0x1D<<1) // with pins SA0=1, SA1=0
trm 0:cf6299acfe98 11 #define FXOS8700CQ_SLAVE_ADDR2 (0x1C<<1) // with pins SA0=0, SA1=1
trm 0:cf6299acfe98 12 #define FXOS8700CQ_SLAVE_ADDR3 (0x1F<<1) // with pins SA0=1, SA1=1
trm 0:cf6299acfe98 13
trm 0:cf6299acfe98 14 // FXOS8700CQ internal register addresses
trm 0:cf6299acfe98 15 #define FXOS8700CQ_STATUS 0x00
trm 0:cf6299acfe98 16 #define FXOS8700CQ_OUT_X_MSB 0x01
trm 0:cf6299acfe98 17 #define FXOS8700CQ_WHOAMI 0x0D
trm 2:4c2f8a3549a9 18 #define FXOS8700CQ_M_OUT_X_MSB 0x33
trm 2:4c2f8a3549a9 19
trm 0:cf6299acfe98 20 #define FXOS8700CQ_XYZ_DATA_CFG 0x0E
trm 2:4c2f8a3549a9 21
trm 0:cf6299acfe98 22 #define FXOS8700CQ_CTRL_REG1 0x2A
trm 0:cf6299acfe98 23 #define FXOS8700CQ_CTRL_REG2 0x2B
trm 0:cf6299acfe98 24 #define FXOS8700CQ_CTRL_REG3 0x2C
trm 0:cf6299acfe98 25 #define FXOS8700CQ_CTRL_REG4 0x2D
trm 0:cf6299acfe98 26 #define FXOS8700CQ_CTRL_REG5 0x2E
trm 0:cf6299acfe98 27
trm 0:cf6299acfe98 28 #define FXOS8700CQ_M_CTRL_REG1 0x5B
trm 0:cf6299acfe98 29 #define FXOS8700CQ_M_CTRL_REG2 0x5C
trm 0:cf6299acfe98 30 #define FXOS8700CQ_M_CTRL_REG3 0x5D
trm 0:cf6299acfe98 31
trm 2:4c2f8a3549a9 32 // FXOS8700CQ configuration macros, per register
trm 2:4c2f8a3549a9 33
trm 2:4c2f8a3549a9 34 #define FXOS8700CQ_CTRL_REG1_ASLP_RATE2(x) (x << 6) // x is 2-bit
trm 2:4c2f8a3549a9 35 #define FXOS8700CQ_CTRL_REG1_DR3(x) (x << 3) // x is 3-bit
trm 2:4c2f8a3549a9 36 #define FXOS8700CQ_CTRL_REG1_LNOISE (1 << 2)
trm 2:4c2f8a3549a9 37 #define FXOS8700CQ_CTRL_REG1_F_READ (1 << 1)
trm 2:4c2f8a3549a9 38 #define FXOS8700CQ_CTRL_REG1_ACTIVE (1 << 0)
trm 2:4c2f8a3549a9 39
trm 2:4c2f8a3549a9 40 #define FXOS8700CQ_CTRL_REG2_ST (1 << 7)
trm 2:4c2f8a3549a9 41 #define FXOS8700CQ_CTRL_REG2_RST (1 << 6)
trm 2:4c2f8a3549a9 42 #define FXOS8700CQ_CTRL_REG2_SMODS2(x) (x << 3) // x is 2-bit
trm 2:4c2f8a3549a9 43 #define FXOS8700CQ_CTRL_REG2_SLPE (1 << 2)
trm 2:4c2f8a3549a9 44 #define FXOS8700CQ_CTRL_REG2_MODS2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 45
trm 2:4c2f8a3549a9 46 #define FXOS8700CQ_CTRL_REG3_FIFO_GATE (1 << 7)
trm 2:4c2f8a3549a9 47 #define FXOS8700CQ_CTRL_REG3_WAKE_TRANS (1 << 6)
trm 2:4c2f8a3549a9 48 #define FXOS8700CQ_CTRL_REG3_WAKE_LNDPRT (1 << 5)
trm 2:4c2f8a3549a9 49 #define FXOS8700CQ_CTRL_REG3_WAKE_PULSE (1 << 4)
trm 2:4c2f8a3549a9 50 #define FXOS8700CQ_CTRL_REG3_WAKE_FFMT (1 << 3)
trm 2:4c2f8a3549a9 51 #define FXOS8700CQ_CTRL_REG3_WAKE_A_VECM (1 << 2)
trm 2:4c2f8a3549a9 52 #define FXOS8700CQ_CTRL_REG3_IPOL (1 << 1)
trm 2:4c2f8a3549a9 53 #define FXOS8700CQ_CTRL_REG3_PP_OD (1 << 0)
trm 2:4c2f8a3549a9 54
trm 2:4c2f8a3549a9 55 #define FXOS8700CQ_CTRL_REG4_INT_EN_ASLP (1 << 7)
trm 2:4c2f8a3549a9 56 #define FXOS8700CQ_CTRL_REG4_INT_EN_FIFO (1 << 6)
trm 2:4c2f8a3549a9 57 #define FXOS8700CQ_CTRL_REG4_INT_EN_TRANS (1 << 5)
trm 2:4c2f8a3549a9 58 #define FXOS8700CQ_CTRL_REG4_INT_EN_LNDPRT (1 << 4)
trm 2:4c2f8a3549a9 59 #define FXOS8700CQ_CTRL_REG4_INT_EN_PULSE (1 << 3)
trm 2:4c2f8a3549a9 60 #define FXOS8700CQ_CTRL_REG4_INT_EN_FFMT (1 << 2)
trm 2:4c2f8a3549a9 61 #define FXOS8700CQ_CTRL_REG4_INT_EN_A_VECM (1 << 1)
trm 2:4c2f8a3549a9 62 #define FXOS8700CQ_CTRL_REG4_INT_EN_DRDY (1 << 0)
trm 2:4c2f8a3549a9 63
trm 2:4c2f8a3549a9 64 #define FXOS8700CQ_CTRL_REG5_INT_CFG_ASLP (1 << 7)
trm 2:4c2f8a3549a9 65 #define FXOS8700CQ_CTRL_REG5_INT_CFG_FIFO (1 << 6)
trm 2:4c2f8a3549a9 66 #define FXOS8700CQ_CTRL_REG5_INT_CFG_TRANS (1 << 5)
trm 2:4c2f8a3549a9 67 #define FXOS8700CQ_CTRL_REG5_INT_CFG_LNDPRT (1 << 4)
trm 2:4c2f8a3549a9 68 #define FXOS8700CQ_CTRL_REG5_INT_CFG_PULSE (1 << 3)
trm 2:4c2f8a3549a9 69 #define FXOS8700CQ_CTRL_REG5_INT_CFG_FFMT (1 << 2)
trm 2:4c2f8a3549a9 70 #define FXOS8700CQ_CTRL_REG5_INT_CFG_A_VECM (1 << 1)
trm 2:4c2f8a3549a9 71 #define FXOS8700CQ_CTRL_REG5_INT_CFG_DRDY (1 << 0)
trm 2:4c2f8a3549a9 72
trm 2:4c2f8a3549a9 73 #define FXOS8700CQ_XYZ_DATA_CFG_HPF_OUT (1 << 4)
trm 2:4c2f8a3549a9 74 #define FXOS8700CQ_XYZ_DATA_CFG_FS2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 75
trm 2:4c2f8a3549a9 76 #define FXOS8700CQ_M_CTRL_REG1_M_ACAL (1 << 7)
trm 2:4c2f8a3549a9 77 #define FXOS8700CQ_M_CTRL_REG1_M_RST (1 << 6)
trm 2:4c2f8a3549a9 78 #define FXOS8700CQ_M_CTRL_REG1_M_OST (1 << 5)
trm 2:4c2f8a3549a9 79 #define FXOS8700CQ_M_CTRL_REG1_MO_OS3(x) (x << 2) // x is 3-bit
trm 2:4c2f8a3549a9 80 #define FXOS8700CQ_M_CTRL_REG1_M_HMS2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 81
trm 2:4c2f8a3549a9 82 #define FXOS8700CQ_M_CTRL_REG2_HYB_AUTOINC_MODE (1 << 5)
trm 2:4c2f8a3549a9 83 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS (1 << 4)
trm 2:4c2f8a3549a9 84 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS_THS (1 << 3)
trm 2:4c2f8a3549a9 85 #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_RST (1 << 2)
trm 2:4c2f8a3549a9 86 #define FXOS8700CQ_M_CTRL_REG2_M_RST_CNT2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 87
trm 2:4c2f8a3549a9 88 #define FXOS8700CQ_M_CTRL_REG3_M_RAW (1 << 7)
trm 2:4c2f8a3549a9 89 #define FXOS8700CQ_M_CTRL_REG3_M_ASLP_OS3(x) (x << 4) // x is 3-bit
trm 2:4c2f8a3549a9 90 #define FXOS8700CQ_M_CTRL_REG3_M_THS_XYZ_UPDATE (1 << 3)
trm 2:4c2f8a3549a9 91 #define FXOS8700CQ_M_CTRL_REG3_M_ST_Z (1 << 2)
trm 2:4c2f8a3549a9 92 #define FXOS8700CQ_M_CTRL_REG3_M_ST_XY2(x) (x << 0) // x is 2-bit
trm 2:4c2f8a3549a9 93
trm 0:cf6299acfe98 94 // FXOS8700CQ WHOAMI production register value
trm 0:cf6299acfe98 95 #define FXOS8700CQ_WHOAMI_VAL 0xC7
trm 0:cf6299acfe98 96
trm 0:cf6299acfe98 97 // 6 channels of two bytes = 12 bytes; read from FXOS8700CQ_OUT_X_MSB
trm 0:cf6299acfe98 98 #define FXOS8700CQ_READ_LEN 12
trm 0:cf6299acfe98 99
trm 0:cf6299acfe98 100 // For processing the accelerometer data to right-justified 2's complement
trm 0:cf6299acfe98 101 #define UINT14_MAX 16383
trm 0:cf6299acfe98 102
trm 0:cf6299acfe98 103 // TODO: struct to hold the data out of the sensor
trm 0:cf6299acfe98 104 typedef struct {
trm 0:cf6299acfe98 105 int16_t x;
trm 0:cf6299acfe98 106 int16_t y;
trm 0:cf6299acfe98 107 int16_t z;
trm 0:cf6299acfe98 108 } SRAWDATA;
trm 0:cf6299acfe98 109
trm 1:3ec7e2676e48 110
trm 1:3ec7e2676e48 111 /**
trm 1:3ec7e2676e48 112 * A driver on top of mbed-I2C to operate the FXOS8700CQ accelerometer/magnetometer
trm 1:3ec7e2676e48 113 * on the FRDM-K64F.
trm 1:3ec7e2676e48 114 *
trm 3:2ce85aa45d7d 115 * Code has been completed, but likely not optimized and potentially buggy.
trm 1:3ec7e2676e48 116 */
trm 0:cf6299acfe98 117 class FXOS8700CQ
trm 0:cf6299acfe98 118 {
trm 0:cf6299acfe98 119 public:
trm 0:cf6299acfe98 120 /**
trm 0:cf6299acfe98 121 * FXOS8700CQ constructor
trm 0:cf6299acfe98 122 *
trm 0:cf6299acfe98 123 * @param sda SDA pin
trm 0:cf6299acfe98 124 * @param sdl SCL pin
trm 0:cf6299acfe98 125 * @param addr address of the I2C peripheral in (7-bit << 1) form
trm 0:cf6299acfe98 126 */
trm 0:cf6299acfe98 127 FXOS8700CQ(PinName sda, PinName scl, int addr);
trm 0:cf6299acfe98 128
trm 0:cf6299acfe98 129 /**
trm 0:cf6299acfe98 130 * FXOS8700CQ destructor
trm 0:cf6299acfe98 131 */
trm 2:4c2f8a3549a9 132 ~FXOS8700CQ(void);
trm 0:cf6299acfe98 133
trm 0:cf6299acfe98 134 void enable(void);
trm 0:cf6299acfe98 135 void disable(void);
trm 3:2ce85aa45d7d 136
trm 3:2ce85aa45d7d 137 /**
trm 3:2ce85aa45d7d 138 * @return the contents of device register FXOS8700CQ_WHOAMI 0x0D,
trm 3:2ce85aa45d7d 139 * should be FXOS8700CQ_WHOAMI_VAL 0xC7
trm 3:2ce85aa45d7d 140 */
trm 0:cf6299acfe98 141 uint8_t get_whoami(void);
trm 3:2ce85aa45d7d 142
trm 3:2ce85aa45d7d 143 /**
trm 3:2ce85aa45d7d 144 * @return the contents of device register FXOS8700CQ_STATUS 0x00
trm 3:2ce85aa45d7d 145 */
trm 0:cf6299acfe98 146 uint8_t status(void);
trm 3:2ce85aa45d7d 147
trm 1:3ec7e2676e48 148 /**
trm 1:3ec7e2676e48 149 * Data retrieval from the FXOS8700CQ
trm 1:3ec7e2676e48 150 *
trm 1:3ec7e2676e48 151 * @param accel_data destination XYZ accelerometer data struct
trm 1:3ec7e2676e48 152 * @param magn_data destination XYZ magnetometer data struct
trm 2:4c2f8a3549a9 153 * @return 0 on success, non-zero on failure
trm 1:3ec7e2676e48 154 */
trm 2:4c2f8a3549a9 155 uint8_t get_data(SRAWDATA *accel_data, SRAWDATA *magn_data);
trm 3:2ce85aa45d7d 156
trm 2:4c2f8a3549a9 157 /**
trm 2:4c2f8a3549a9 158 * Retrieve the full-range scale value of the accelerometer
trm 3:2ce85aa45d7d 159 *
trm 2:4c2f8a3549a9 160 * @return 2, 4, or 8, depending on part configuration; 0 on error
trm 2:4c2f8a3549a9 161 */
trm 2:4c2f8a3549a9 162 uint8_t get_accel_scale(void);
trm 0:cf6299acfe98 163
trm 0:cf6299acfe98 164
trm 0:cf6299acfe98 165
trm 0:cf6299acfe98 166 private:
trm 0:cf6299acfe98 167 I2C dev_i2c; // instance of the mbed I2C class
trm 0:cf6299acfe98 168 uint8_t dev_addr; // Device I2C address, in (7-bit << 1) form
trm 3:2ce85aa45d7d 169 bool enabled; // keep track of enable bit of device
trm 0:cf6299acfe98 170
trm 0:cf6299acfe98 171 // I2C helper methods
trm 0:cf6299acfe98 172 void read_regs(int reg_addr, uint8_t* data, int len);
trm 0:cf6299acfe98 173 void write_regs(uint8_t* data, int len);
trm 0:cf6299acfe98 174
trm 0:cf6299acfe98 175 };
trm 0:cf6299acfe98 176
trm 0:cf6299acfe98 177 #endif