DW1000Registers.h

00001 #ifndef __DWREG_H__
00002 #define __DWREG_H__
00003 
00004 // register addresses
00005 //      Mnemonic                    Address Bytes Description
00006 #define DW1000_DEV_ID               0x00 //     4 Device Identifier – includes device type and revision information
00007 #define DW1000_EUI                  0x01 //     8 Extended Unique Identifier
00008 #define DW1000_PANADR               0x03 //     4 PAN Identifier and Short Address
00009 #define DW1000_SYS_CFG              0x04 //     4 System Configuration bitmap
00010 #define DW1000_SYS_TIME             0x06 //     5 System Time Counter (40-bit)
00011 #define DW1000_TX_FCTRL             0x08 //     5 Transmit Frame Control
00012 #define DW1000_TX_BUFFER            0x09 //  1024 Transmit Data Buffer
00013 #define DW1000_DX_TIME              0x0A //     5 Delayed Send or Receive Time (40-bit)
00014 #define DW1000_RX_FWTO              0x0C //     2 Receive Frame Wait Timeout Period
00015 #define DW1000_SYS_CTRL             0x0D //     4 System Control Register
00016 #define DW1000_SYS_MASK             0x0E //     4 System Event Mask Register
00017 #define DW1000_SYS_STATUS           0x0F //     5 System Event Status Register
00018 #define DW1000_RX_FINFO             0x10 //     4 RX Frame Information                (in double buffer set)
00019 #define DW1000_RX_BUFFER            0x11 //  1024 Receive Data Buffer                 (in double buffer set)
00020 #define DW1000_RX_FQUAL             0x12 //     8 Rx Frame Quality information        (in double buffer set)
00021 #define DW1000_RX_TTCKI             0x13 //     4 Receiver Time Tracking Interval     (in double buffer set)
00022 #define DW1000_RX_TTCKO             0x14 //     5 Receiver Time Tracking Offset       (in double buffer set)
00023 #define DW1000_RX_TIME              0x15 //    14 Receive Message Time of Arrival     (in double buffer set)
00024 #define DW1000_TX_TIME              0x17 //    10 Transmit Message Time of Sending    (in double buffer set)
00025 #define DW1000_TX_ANTD              0x18 //     2 16-bit Delay from Transmit to Antenna
00026 #define DW1000_SYS_STATE            0x19 //     5 System State information
00027 #define DW1000_ACK_RESP_T           0x1A //     4 Acknowledgement Time and Response Time
00028 #define DW1000_RX_SNIFF             0x1D //     4 Pulsed Preamble Reception Configuration
00029 #define DW1000_TX_POWER             0x1E //     4 TX Power Control
00030 #define DW1000_CHAN_CTRL            0x1F //     4 Channel Control
00031 #define DW1000_USR_SFD              0x21 //    41 User-specified short/long TX/RX SFD sequences
00032 #define DW1000_AGC_CTRL             0x23 //    32 Automatic Gain Control configuration
00033 #define DW1000_EXT_SYNC             0x24 //    12 External synchronisation control.
00034 #define DW1000_ACC_MEM              0x25 //  4064 Read access to accumulator data
00035 #define DW1000_GPIO_CTRL            0x26 //    44 Peripheral register bus 1 access - GPIO control
00036 #define DW1000_DRX_CONF             0x27 //    44 Digital Receiver configuration
00037 #define DW1000_RF_CONF              0x28 //    58 Analog RF Configuration
00038 #define DW1000_TX_CAL               0x2A //    52 Transmitter calibration block
00039 #define DW1000_FS_CTRL              0x2B //    21 Frequency synthesiser control block
00040 #define DW1000_AON                  0x2C //    12 Always-On register set
00041 #define DW1000_OTP_IF               0x2D //    18 One Time Programmable Memory Interface
00042 #define DW1000_LDE_CTRL             0x2E //     - Leading edge detection control block
00043 #define DW1000_DIG_DIAG             0x2F //    41 Digital Diagnostics Interface
00044 #define DW1000_PMSC                 0x36 //    48 Power Management System Control Block
00045 
00046 // AGC_CTRL sub registers
00047 #define DWAGCCTRL_AGC_CTRL1         0x02
00048 #define DWAGCCTRL_AGC_TUNE1         0x04
00049 #define DWAGCCTRL_AGC_TUNE2         0x0C
00050 #define DWAGCCTRL_AGC_TUNE3         0x12
00051 
00052 // EXT_SYNC sub registers
00053 #define DWEXTSYNC_EC_CTRL           0x00
00054 #define DWEXTSYNC_EC_RXTC           0x04
00055 #define DWEXTSYNC_EC_GOLP           0x08
00056 
00057 // GPIO sub registers
00058 #define DWGPIO_GPIO_MODE           0x00
00059 #define DWGPIO_GPIO_DIR            0x08
00060 #define DWGPIO_GPIO_DOUT           0x0C
00061 #define DWGPIO_GPIO_IRQE           0x10
00062 #define DWGPIO_GPIO_ISEN           0x14
00063 #define DWGPIO_GPIO_IMODE          0x18
00064 #define DWGPIO_GPIO_IBES           0x1C
00065 #define DWGPIO_GPIO_ICLR           0x20
00066 #define DWGPIO_GPIO_IDBE           0x24
00067 #define DWGPIO_GPIO_RAW            0x28
00068 
00069 // DRX sub registers
00070 #define DWDRX_DRX_TUNE0B            0x02
00071 #define DWDRX_DRX_TUNE1A            0x04
00072 #define DWDRX_DRX_TUNE1B            0x06
00073 #define DWDRX_DRX_TUNE2             0x08
00074 #define DWDRX_DRX_SFDTOC            0x20
00075 #define DWDRX_DRX_PRETOC            0x24
00076 #define DWDRX_DRX_TUNE4H            0x26
00077 #define DWDRX_RXPAC_NOSAT           0x2c
00078 
00079 
00080 //RF conf sub registers
00081 #define DWRFCONF_RF_CONF            0x00
00082 #define DWRFCONF_RF_RXCTRLH         0x0B
00083 #define DWRFCONF_RF_TXCTRL          0x0C
00084 #define DWRFCONF_RF_STATUS          0x2C
00085 #define DWRFCONF_RF_LDOTUNE         0x30
00086 
00087 // TX cal sub registers
00088 #define DWTXCAL_TC_SARC             0x00
00089 #define DWTXCAL_TC_SARL             0x03
00090 #define DWTXCAL_TC_SARW             0x06
00091 #define DWTXCAL_TC_PGDELAY          0x0B
00092 #define DWTXCAL_TC_PGTEST           0x0C
00093 
00094 // Freq synth sub registers
00095 #define DWFSCTRL_FS_PLLCFG          0x07
00096 #define DWFSCTRL_FS_PLLTUNE         0x0B
00097 #define DWFSCTRL_FS_XTALT           0x0E
00098 
00099 // Always on sub registers
00100 #define DWAON_AON_WCFG              0x00
00101 #define DWAON_AON_CTRL              0x02
00102 #define DWAON_AON_RDAT              0x03
00103 #define DWAON_AON_ADDR              0x04
00104 #define DWAON_AON_CFG0              0x06
00105 #define DWAON_AON_CFG1              0x0A
00106 
00107 // OTP sub registers
00108 #define DWOTP_OTP_WDAT              0x00
00109 #define DWOTP_OTP_ADDR              0x04
00110 #define DWOTP_OTP_CTRL              0x06
00111 #define DWOTP_OTP_STAT              0x08
00112 #define DWOTP_OTP_RDAT              0x0A
00113 #define DWOTP_OTP_SRDAT             0x0E
00114 #define DWOTP_OTP_SF                0x12
00115 
00116 //LDE_IF sub registers
00117 #define DWLDE_LDE_THRESH            0x0000
00118 #define DWLDE_LDE_CFG1              0x0806
00119 #define DWLDE_LDE_PPINDX            0x1000
00120 #define DWLDE_LDE_PPAMPL            0x1002
00121 #define DWLDE_LDE_RXANTD            0x1804
00122 #define DWLDE_LDE_CFG2              0x1806
00123 #define DWLDE_LDE_REPC              0x2804
00124 
00125 // Dig Diag sub registers
00126 #define DWDIAG_EVC_CTRL             0x00
00127 #define DWDIAG_EVC_PHE              0x04
00128 #define DWDIAG_EVC_RSE              0x06
00129 #define DWDIAG_EVC_FCG              0x08
00130 #define DWDIAG_EVC_FCE              0x0A
00131 #define DWDIAG_EVC_FFR              0x0C
00132 #define DWDIAG_EVC_OVR              0x0E
00133 #define DWDIAG_EVC_STO              0x10
00134 #define DWDIAG_EVC_PTO              0x12
00135 #define DWDIAG_EVC_FWTO             0x14
00136 #define DWDIAG_EVC_TXFS             0x16
00137 #define DWDIAG_EVC_HPW              0x18
00138 #define DWDIAG_EVC_TPW              0x1A
00139 #define DWDIAG_DIAG_TMC             0x24
00140 
00141 // power control sub registers
00142 #define DWPMSC_PMSC_CTRL0           0x00
00143 #define DWPMSC_PMSC_CTRL1           0x04
00144 #define DWPMSC_PMSC_SNOZT           0x0C
00145 #define DWPMSC_PMSC_TXFSEQ          0x26
00146 #define DWPMSC_PMSC_LEDC            0x28
00147 
00148 
00149 #define DW1000_WRITE_FLAG           0x80 // First Bit of the address has to be 1 to indicate we want to write
00150 #define DW1000_SUBADDRESS_FLAG      0x40 // if we have a sub address second Bit has to be 1
00151 #define DW1000_2_SUBADDRESS_FLAG    0x80 // if we have a long sub adress (more than 7 Bit) we set this Bit in the first part
00152 
00153 #endif