Andy A / DW1000

DW1000 UWB driver based on work of Matthias Grob & Manuel Stalder - ETH Zürich - 2015

Dependencies:   BurstSPI

DW1000.h@6:2c77afdf7367, 2016-04-11 (annotated)

Committer:
AndyA
Date:
Mon Apr 11 14:45:44 2016 +0000
Revision:
6:2c77afdf7367
Parent:
5:68ffaa5962d1
Child:
7:b13881dbb09d
Improved comments.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AndyA 0:bddb8cd5e7df 1 // by Matthias Grob & Manuel Stalder - ETH Zürich - 2015
AndyA 0:bddb8cd5e7df 2
AndyA 0:bddb8cd5e7df 3 #ifndef DW1000_H
AndyA 0:bddb8cd5e7df 4 #define DW1000_H
AndyA 0:bddb8cd5e7df 5
AndyA 0:bddb8cd5e7df 6 #include "mbed.h"
AndyA 0:bddb8cd5e7df 7
AndyA 0:bddb8cd5e7df 8 // register addresses
AndyA 0:bddb8cd5e7df 9 // Mnemonic Address Bytes Description
AndyA 0:bddb8cd5e7df 10 #define DW1000_DEV_ID 0x00 // 4 Device Identifier – includes device type and revision information
AndyA 0:bddb8cd5e7df 11 #define DW1000_EUI 0x01 // 8 Extended Unique Identifier
AndyA 0:bddb8cd5e7df 12 #define DW1000_PANADR 0x03 // 4 PAN Identifier and Short Address
AndyA 0:bddb8cd5e7df 13 #define DW1000_SYS_CFG 0x04 // 4 System Configuration bitmap
AndyA 0:bddb8cd5e7df 14 #define DW1000_SYS_TIME 0x06 // 5 System Time Counter (40-bit)
AndyA 0:bddb8cd5e7df 15 #define DW1000_TX_FCTRL 0x08 // 5 Transmit Frame Control
AndyA 0:bddb8cd5e7df 16 #define DW1000_TX_BUFFER 0x09 // 1024 Transmit Data Buffer
AndyA 0:bddb8cd5e7df 17 #define DW1000_DX_TIME 0x0A // 5 Delayed Send or Receive Time (40-bit)
AndyA 0:bddb8cd5e7df 18 #define DW1000_RX_FWTO 0x0C // 2 Receive Frame Wait Timeout Period
AndyA 0:bddb8cd5e7df 19 #define DW1000_SYS_CTRL 0x0D // 4 System Control Register
AndyA 0:bddb8cd5e7df 20 #define DW1000_SYS_MASK 0x0E // 4 System Event Mask Register
AndyA 0:bddb8cd5e7df 21 #define DW1000_SYS_STATUS 0x0F // 5 System Event Status Register
AndyA 0:bddb8cd5e7df 22 #define DW1000_RX_FINFO 0x10 // 4 RX Frame Information (in double buffer set)
AndyA 0:bddb8cd5e7df 23 #define DW1000_RX_BUFFER 0x11 // 1024 Receive Data Buffer (in double buffer set)
AndyA 0:bddb8cd5e7df 24 #define DW1000_RX_FQUAL 0x12 // 8 Rx Frame Quality information (in double buffer set)
AndyA 0:bddb8cd5e7df 25 #define DW1000_RX_TTCKI 0x13 // 4 Receiver Time Tracking Interval (in double buffer set)
AndyA 0:bddb8cd5e7df 26 #define DW1000_RX_TTCKO 0x14 // 5 Receiver Time Tracking Offset (in double buffer set)
AndyA 0:bddb8cd5e7df 27 #define DW1000_RX_TIME 0x15 // 14 Receive Message Time of Arrival (in double buffer set)
AndyA 0:bddb8cd5e7df 28 #define DW1000_TX_TIME 0x17 // 10 Transmit Message Time of Sending (in double buffer set)
AndyA 0:bddb8cd5e7df 29 #define DW1000_TX_ANTD 0x18 // 2 16-bit Delay from Transmit to Antenna
AndyA 0:bddb8cd5e7df 30 #define DW1000_SYS_STATE 0x19 // 5 System State information
AndyA 0:bddb8cd5e7df 31 #define DW1000_ACK_RESP_T 0x1A // 4 Acknowledgement Time and Response Time
AndyA 0:bddb8cd5e7df 32 #define DW1000_RX_SNIFF 0x1D // 4 Pulsed Preamble Reception Configuration
AndyA 0:bddb8cd5e7df 33 #define DW1000_TX_POWER 0x1E // 4 TX Power Control
AndyA 0:bddb8cd5e7df 34 #define DW1000_CHAN_CTRL 0x1F // 4 Channel Control
AndyA 0:bddb8cd5e7df 35 #define DW1000_USR_SFD 0x21 // 41 User-specified short/long TX/RX SFD sequences
AndyA 0:bddb8cd5e7df 36 #define DW1000_AGC_CTRL 0x23 // 32 Automatic Gain Control configuration
AndyA 0:bddb8cd5e7df 37 #define DW1000_EXT_SYNC 0x24 // 12 External synchronisation control.
AndyA 0:bddb8cd5e7df 38 #define DW1000_ACC_MEM 0x25 // 4064 Read access to accumulator data
AndyA 0:bddb8cd5e7df 39 #define DW1000_GPIO_CTRL 0x26 // 44 Peripheral register bus 1 access - GPIO control
AndyA 0:bddb8cd5e7df 40 #define DW1000_DRX_CONF 0x27 // 44 Digital Receiver configuration
AndyA 0:bddb8cd5e7df 41 #define DW1000_RF_CONF 0x28 // 58 Analog RF Configuration
AndyA 0:bddb8cd5e7df 42 #define DW1000_TX_CAL 0x2A // 52 Transmitter calibration block
AndyA 0:bddb8cd5e7df 43 #define DW1000_FS_CTRL 0x2B // 21 Frequency synthesiser control block
AndyA 0:bddb8cd5e7df 44 #define DW1000_AON 0x2C // 12 Always-On register set
AndyA 0:bddb8cd5e7df 45 #define DW1000_OTP_IF 0x2D // 18 One Time Programmable Memory Interface
AndyA 0:bddb8cd5e7df 46 #define DW1000_LDE_CTRL 0x2E // - Leading edge detection control block
AndyA 0:bddb8cd5e7df 47 #define DW1000_DIG_DIAG 0x2F // 41 Digital Diagnostics Interface
AndyA 0:bddb8cd5e7df 48 #define DW1000_PMSC 0x36 // 48 Power Management System Control Block
AndyA 0:bddb8cd5e7df 49
AndyA 0:bddb8cd5e7df 50 // AGC_CTRL sub registers
AndyA 0:bddb8cd5e7df 51 #define DWAGCCTRL_AGC_CTRL1 0x02
AndyA 0:bddb8cd5e7df 52 #define DWAGCCTRL_AGC_TUNE1 0x04
AndyA 0:bddb8cd5e7df 53 #define DWAGCCTRL_AGC_TUNE2 0x0C
AndyA 0:bddb8cd5e7df 54 #define DWAGCCTRL_AGC_TUNE3 0x12
AndyA 0:bddb8cd5e7df 55
AndyA 0:bddb8cd5e7df 56 // EXT_SYNC sub registers
AndyA 0:bddb8cd5e7df 57 #define DWEXTSYNC_EC_CTRL 0x00
AndyA 0:bddb8cd5e7df 58 #define DWEXTSYNC_EC_RXTC 0x04
AndyA 0:bddb8cd5e7df 59 #define DWEXTSYNC_EC_GOLP 0x08
AndyA 0:bddb8cd5e7df 60
AndyA 0:bddb8cd5e7df 61 // GPIO sub registers
AndyA 0:bddb8cd5e7df 62 #define DWGPIO_GPIO_MODE 0x00
AndyA 0:bddb8cd5e7df 63 #define DWGPIO_GPIO_DIR 0x08
AndyA 0:bddb8cd5e7df 64 #define DWGPIO_GPIO_DOUT 0x0C
AndyA 0:bddb8cd5e7df 65 #define DWGPIO_GPIO_IRQE 0x10
AndyA 0:bddb8cd5e7df 66 #define DWGPIO_GPIO_ISEN 0x14
AndyA 0:bddb8cd5e7df 67 #define DWGPIO_GPIO_IMODE 0x18
AndyA 0:bddb8cd5e7df 68 #define DWGPIO_GPIO_IBES 0x1C
AndyA 0:bddb8cd5e7df 69 #define DWGPIO_GPIO_ICLR 0x20
AndyA 0:bddb8cd5e7df 70 #define DWGPIO_GPIO_IDBE 0x24
AndyA 0:bddb8cd5e7df 71 #define DWGPIO_GPIO_RAW 0x28
AndyA 0:bddb8cd5e7df 72
AndyA 0:bddb8cd5e7df 73 // DRX sub registers
AndyA 0:bddb8cd5e7df 74 #define DWDRX_DRX_TUNE0B 0x02
AndyA 0:bddb8cd5e7df 75 #define DWDRX_DRX_TUNE1A 0x04
AndyA 0:bddb8cd5e7df 76 #define DWDRX_DRX_TUNE1B 0x06
AndyA 0:bddb8cd5e7df 77 #define DWDRX_DRX_TUNE2 0x08
AndyA 0:bddb8cd5e7df 78 #define DWDRX_DRX_SFDTOC 0x20
AndyA 0:bddb8cd5e7df 79 #define DWDRX_DRX_PRETOC 0x24
AndyA 0:bddb8cd5e7df 80 #define DWDRX_DRX_TUNE4H 0x26
AndyA 0:bddb8cd5e7df 81
AndyA 0:bddb8cd5e7df 82 //RF conf sub registers
AndyA 0:bddb8cd5e7df 83 #define DWRFCONF_RF_CONF 0x00
AndyA 0:bddb8cd5e7df 84 #define DWRFCONF_RF_RXCTRLH 0x0B
AndyA 0:bddb8cd5e7df 85 #define DWRFCONF_RF_TXCTRL 0x0C
AndyA 0:bddb8cd5e7df 86 #define DWRFCONF_RF_STATUS 0x2C
AndyA 0:bddb8cd5e7df 87 #define DWRFCONF_RF_LDOTUNE 0x30
AndyA 0:bddb8cd5e7df 88
AndyA 0:bddb8cd5e7df 89 // TX cal sub registers
AndyA 0:bddb8cd5e7df 90 #define DWTXCAL_TC_SARC 0x00
AndyA 0:bddb8cd5e7df 91 #define DWTXCAL_TC_SARL 0x03
AndyA 0:bddb8cd5e7df 92 #define DWTXCAL_TC_SARW 0x06
AndyA 0:bddb8cd5e7df 93 #define DWTXCAL_TC_PGDELAY 0x0B
AndyA 0:bddb8cd5e7df 94 #define DWTXCAL_TC_PGTEST 0x0C
AndyA 0:bddb8cd5e7df 95
AndyA 0:bddb8cd5e7df 96 // Freq synth sub registers
AndyA 0:bddb8cd5e7df 97 #define DWFSCTRL_FS_PLLCFG 0x07
AndyA 0:bddb8cd5e7df 98 #define DWFSCTRL_FS_PLLTUNE 0x0B
AndyA 0:bddb8cd5e7df 99 #define DWFSCTRL_FS_XTALT 0x0E
AndyA 0:bddb8cd5e7df 100
AndyA 0:bddb8cd5e7df 101 // Always on sub registers
AndyA 0:bddb8cd5e7df 102 #define DWAON_AON_WCFG 0x00
AndyA 0:bddb8cd5e7df 103 #define DWAON_AON_CTRL 0x02
AndyA 0:bddb8cd5e7df 104 #define DWAON_AON_RDAT 0x03
AndyA 0:bddb8cd5e7df 105 #define DWAON_AON_ADDR 0x04
AndyA 0:bddb8cd5e7df 106 #define DWAON_AON_CFG0 0x06
AndyA 0:bddb8cd5e7df 107 #define DWAON_AON_CFG1 0x0A
AndyA 0:bddb8cd5e7df 108
AndyA 0:bddb8cd5e7df 109 // OTP sub registers
AndyA 0:bddb8cd5e7df 110 #define DWOTP_OTP_WDAT 0x00
AndyA 0:bddb8cd5e7df 111 #define DWOTP_OTP_ADDR 0x04
AndyA 0:bddb8cd5e7df 112 #define DWOTP_OTP_CTRL 0x06
AndyA 0:bddb8cd5e7df 113 #define DWOTP_OTP_STAT 0x08
AndyA 0:bddb8cd5e7df 114 #define DWOTP_OTP_RDAT 0x0A
AndyA 0:bddb8cd5e7df 115 #define DWOTP_OTP_SRDAT 0x0E
AndyA 0:bddb8cd5e7df 116 #define DWOTP_OTP_SF 0x12
AndyA 0:bddb8cd5e7df 117
AndyA 0:bddb8cd5e7df 118 //LDE_IF sub registers
AndyA 0:bddb8cd5e7df 119 #define DWLDE_LDE_THRESH 0x0000
AndyA 0:bddb8cd5e7df 120 #define DWLDE_LDE_CFG1 0x0806
AndyA 0:bddb8cd5e7df 121 #define DWLDE_LDE_PPINDX 0x1000
AndyA 0:bddb8cd5e7df 122 #define DWLDE_LDE_PPAMPL 0x1002
AndyA 0:bddb8cd5e7df 123 #define DWLDE_LDE_RXANTD 0x1804
AndyA 0:bddb8cd5e7df 124 #define DWLDE_LDE_CFG2 0x1806
AndyA 0:bddb8cd5e7df 125 #define DWLDE_LDE_REPC 0x2804
AndyA 0:bddb8cd5e7df 126
AndyA 0:bddb8cd5e7df 127 // Dig Diag sub registers
AndyA 0:bddb8cd5e7df 128 #define DWDIAG_EVC_CTRL 0x00
AndyA 0:bddb8cd5e7df 129 #define DWDIAG_EVC_PHE 0x04
AndyA 0:bddb8cd5e7df 130 #define DWDIAG_EVC_RSE 0x06
AndyA 0:bddb8cd5e7df 131 #define DWDIAG_EVC_FCG 0x08
AndyA 0:bddb8cd5e7df 132 #define DWDIAG_EVC_FCE 0x0A
AndyA 0:bddb8cd5e7df 133 #define DWDIAG_EVC_FFR 0x0C
AndyA 0:bddb8cd5e7df 134 #define DWDIAG_EVC_OVR 0x0E
AndyA 0:bddb8cd5e7df 135 #define DWDIAG_EVC_STO 0x10
AndyA 0:bddb8cd5e7df 136 #define DWDIAG_EVC_PTO 0x12
AndyA 0:bddb8cd5e7df 137 #define DWDIAG_EVC_FWTO 0x14
AndyA 0:bddb8cd5e7df 138 #define DWDIAG_EVC_TXFS 0x16
AndyA 0:bddb8cd5e7df 139 #define DWDIAG_EVC_HPW 0x18
AndyA 0:bddb8cd5e7df 140 #define DWDIAG_EVC_TPW 0x1A
AndyA 0:bddb8cd5e7df 141 #define DWDIAG_DIAG_TMC 0x24
AndyA 0:bddb8cd5e7df 142
AndyA 0:bddb8cd5e7df 143 // power control sub registers
AndyA 0:bddb8cd5e7df 144 #define DWPMSC_PMSC_CTRL0 0x00
AndyA 0:bddb8cd5e7df 145 #define DWPMSC_PMSC_CTRL1 0x04
AndyA 0:bddb8cd5e7df 146 #define DWPMSC_PMSC_SNOZT 0x0C
AndyA 0:bddb8cd5e7df 147 #define DWPMSC_PMSC_TXFSEQ 0x26
AndyA 0:bddb8cd5e7df 148 #define DWPMSC_PMSC_LEDC 0x28
AndyA 0:bddb8cd5e7df 149
AndyA 0:bddb8cd5e7df 150
AndyA 0:bddb8cd5e7df 151 #define DW1000_WRITE_FLAG 0x80 // First Bit of the address has to be 1 to indicate we want to write
AndyA 0:bddb8cd5e7df 152 #define DW1000_SUBADDRESS_FLAG 0x40 // if we have a sub address second Bit has to be 1
AndyA 0:bddb8cd5e7df 153 #define DW1000_2_SUBADDRESS_FLAG 0x80 // if we have a long sub adress (more than 7 Bit) we set this Bit in the first part
AndyA 0:bddb8cd5e7df 154
AndyA 3:1459d2aa6b97 155 /*
AndyA 3:1459d2aa6b97 156 From user manual 10.5
AndyA 3:1459d2aa6b97 157 Table 59:
AndyA 3:1459d2aa6b97 158 DW1000 supported UWB channels and recommended preamble codes
AndyA 3:1459d2aa6b97 159
AndyA 3:1459d2aa6b97 160 channel 16MHzPrf 64MHzPrf
AndyA 3:1459d2aa6b97 161 1 1,2 9, 10, 11, 12
AndyA 3:1459d2aa6b97 162 2 3, 4 9, 10, 11, 12
AndyA 3:1459d2aa6b97 163 3 5, 6 9, 10, 11, 12
AndyA 3:1459d2aa6b97 164 4 7, 8 17, 18, 19, 20
AndyA 3:1459d2aa6b97 165 5 3, 4 9, 10, 11, 12
AndyA 3:1459d2aa6b97 166 7 7, 8 17, 18, 19, 20
AndyA 3:1459d2aa6b97 167 */
AndyA 3:1459d2aa6b97 168
AndyA 3:1459d2aa6b97 169
AndyA 4:5f1025df5530 170 /** Class for holding DW1000 config options
AndyA 4:5f1025df5530 171 *
AndyA 4:5f1025df5530 172 */
AndyA 4:5f1025df5530 173 class DW1000Setup
AndyA 4:5f1025df5530 174 {
AndyA 4:5f1025df5530 175 public:
AndyA 4:5f1025df5530 176
AndyA 4:5f1025df5530 177 /// Constructor - default settings are close to hardware defaults.
AndyA 4:5f1025df5530 178 DW1000Setup() {
AndyA 4:5f1025df5530 179 channel = 5;
AndyA 4:5f1025df5530 180 prf =prf16MHz;
AndyA 4:5f1025df5530 181 dataRate = kbps850;
AndyA 4:5f1025df5530 182 sfd = standard;
AndyA 4:5f1025df5530 183 preamble = pre128;
AndyA 4:5f1025df5530 184 preambleCode = 3;
AndyA 4:5f1025df5530 185 enableSmartPower = true;
AndyA 4:5f1025df5530 186 }
AndyA 4:5f1025df5530 187
AndyA 4:5f1025df5530 188 /// enum for PRF options
AndyA 6:2c77afdf7367 189 enum prf_e {prf16MHz, ///< PRF rate of 16MHz. Lower power
AndyA 6:2c77afdf7367 190 prf64MHz ///< PRF rate of 64MHz. Higher power but more accurate timing.
AndyA 6:2c77afdf7367 191 };
AndyA 6:2c77afdf7367 192
AndyA 6:2c77afdf7367 193 /// enum for data rate options
AndyA 6:2c77afdf7367 194 enum dataRate_e {kbps110, ///< Data rate of 110kb/s (non-standard)
AndyA 6:2c77afdf7367 195 kbps850,///< Data rate of 850kb/s
AndyA 6:2c77afdf7367 196 kbps6800///< Data rate of 6.8Mb/s
AndyA 6:2c77afdf7367 197 };
AndyA 4:5f1025df5530 198
AndyA 6:2c77afdf7367 199 /// enum for SFD options
AndyA 6:2c77afdf7367 200 enum sfd_e {standard, ///< IEEE standard SFD
AndyA 6:2c77afdf7367 201 decaWave, ///< Decawave defined SFD
AndyA 6:2c77afdf7367 202 user ///< user defined SFD
AndyA 6:2c77afdf7367 203 };
AndyA 4:5f1025df5530 204
AndyA 6:2c77afdf7367 205 /// enum for preamble length options
AndyA 6:2c77afdf7367 206 enum preamble_e { pre64,///< Preamble is 64 symbols
AndyA 6:2c77afdf7367 207 pre128,///< Preamble is 128 symbols (non-standard)
AndyA 6:2c77afdf7367 208 pre256,///< Preamble is 256 symbols (non-standard)
AndyA 6:2c77afdf7367 209 pre512,///< Preamble is 512 symbols (non-standard)
AndyA 6:2c77afdf7367 210 pre1024,///< Preamble is 1024 symbols
AndyA 6:2c77afdf7367 211 pre1536,///< Preamble is 1536 symbols (non-standard)
AndyA 6:2c77afdf7367 212 pre2048, ///< Preamble is 2048 symbols (non-standard)
AndyA 6:2c77afdf7367 213 pre4096///< Preamble is 4096 symbols
AndyA 6:2c77afdf7367 214 };
AndyA 6:2c77afdf7367 215
AndyA 6:2c77afdf7367 216 /** Set the PRF
AndyA 6:2c77afdf7367 217 * @return true if a valid option
AndyA 6:2c77afdf7367 218 */
AndyA 4:5f1025df5530 219 bool setPRF(enum prf_e newSetting) {
AndyA 4:5f1025df5530 220 prf = newSetting;
AndyA 4:5f1025df5530 221 return true;
AndyA 4:5f1025df5530 222 };
AndyA 0:bddb8cd5e7df 223
AndyA 6:2c77afdf7367 224 /** Set the Channel
AndyA 6:2c77afdf7367 225 * @return true if a valid option
AndyA 6:2c77afdf7367 226 */
AndyA 4:5f1025df5530 227 bool setChannel(unsigned char newChannel) {
AndyA 4:5f1025df5530 228 if ((channel > 0) && ((channel <= 5) || (channel == 7))) {
AndyA 4:5f1025df5530 229 channel = newChannel;
AndyA 4:5f1025df5530 230 return true;
AndyA 4:5f1025df5530 231 }
AndyA 4:5f1025df5530 232 return false;
AndyA 4:5f1025df5530 233 };
AndyA 6:2c77afdf7367 234 /** Set the SFD
AndyA 6:2c77afdf7367 235 * @return true if a valid option
AndyA 6:2c77afdf7367 236 */
AndyA 4:5f1025df5530 237 bool setSfd(enum sfd_e newSetting) {
AndyA 4:5f1025df5530 238 sfd = newSetting;
AndyA 4:5f1025df5530 239 return true;
AndyA 4:5f1025df5530 240 };
AndyA 6:2c77afdf7367 241 /** Set the Preamble length
AndyA 6:2c77afdf7367 242 * @return true if a valid option
AndyA 6:2c77afdf7367 243 */
AndyA 4:5f1025df5530 244 bool setPreambleLength(enum preamble_e newSetting) {
AndyA 4:5f1025df5530 245 preamble = newSetting;
AndyA 4:5f1025df5530 246 return true;
AndyA 4:5f1025df5530 247 };
AndyA 6:2c77afdf7367 248 /** Set the Data rate
AndyA 6:2c77afdf7367 249 * @return true if a valid option
AndyA 6:2c77afdf7367 250 */
AndyA 4:5f1025df5530 251 bool setDataRate(enum dataRate_e newSetting) {
AndyA 4:5f1025df5530 252 dataRate = newSetting;
AndyA 4:5f1025df5530 253 return true;
AndyA 4:5f1025df5530 254 };
AndyA 6:2c77afdf7367 255 /** Set the Preamble code
AndyA 6:2c77afdf7367 256 * @return true if a valid option
AndyA 6:2c77afdf7367 257 *
AndyA 6:2c77afdf7367 258 * note - not all codes are valid for all channels. Set the channel first.
AndyA 6:2c77afdf7367 259 * TODO - enforce code restrictions
AndyA 6:2c77afdf7367 260 */
AndyA 4:5f1025df5530 261 bool setPreambleCode(unsigned char newCode) {
AndyA 4:5f1025df5530 262 if ((newCode > 0) && (newCode <= 24)) {
AndyA 4:5f1025df5530 263 preambleCode = newCode;
AndyA 4:5f1025df5530 264 return true;
AndyA 4:5f1025df5530 265 }
AndyA 4:5f1025df5530 266 return false;
AndyA 4:5f1025df5530 267 };
AndyA 6:2c77afdf7367 268 /** Set the smartpower state
AndyA 6:2c77afdf7367 269 * @return true if a valid option
AndyA 6:2c77afdf7367 270 *
AndyA 6:2c77afdf7367 271 * only takes effect at 6.8Mb/s
AndyA 6:2c77afdf7367 272 */
AndyA 4:5f1025df5530 273 bool setSmartPower(bool enable) {
AndyA 4:5f1025df5530 274 enableSmartPower = enable;
AndyA 4:5f1025df5530 275 return true;
AndyA 4:5f1025df5530 276 };
AndyA 4:5f1025df5530 277
AndyA 6:2c77afdf7367 278 /** Get the current channel
AndyA 6:2c77afdf7367 279 * @return the channel number
AndyA 6:2c77afdf7367 280 */
AndyA 4:5f1025df5530 281 unsigned char getChannel() {
AndyA 4:5f1025df5530 282 return channel;
AndyA 4:5f1025df5530 283 };
AndyA 6:2c77afdf7367 284 /** Get the current PRF
AndyA 6:2c77afdf7367 285 * @return the PRF
AndyA 6:2c77afdf7367 286 */
AndyA 4:5f1025df5530 287 enum prf_e getPRF() {
AndyA 4:5f1025df5530 288 return prf;
AndyA 4:5f1025df5530 289 };
AndyA 6:2c77afdf7367 290 /** Get the current data rate
AndyA 6:2c77afdf7367 291 * @return the data rate
AndyA 6:2c77afdf7367 292 */ enum dataRate_e getDataRate() {
AndyA 4:5f1025df5530 293 return dataRate;
AndyA 4:5f1025df5530 294 };
AndyA 6:2c77afdf7367 295
AndyA 6:2c77afdf7367 296 /** Get the current SFD mode
AndyA 6:2c77afdf7367 297 * @return the SFD
AndyA 6:2c77afdf7367 298 */ enum sfd_e getSfd() {
AndyA 6:2c77afdf7367 299 return sfd;
AndyA 6:2c77afdf7367 300 };
AndyA 6:2c77afdf7367 301 /** Get the current preamble length
AndyA 6:2c77afdf7367 302 * @return the preamble length
AndyA 6:2c77afdf7367 303 */
AndyA 6:2c77afdf7367 304 enum preamble_e getPreambleLength() {
AndyA 4:5f1025df5530 305 return preamble;
AndyA 4:5f1025df5530 306 };
AndyA 6:2c77afdf7367 307 /** Get the current preamble code
AndyA 6:2c77afdf7367 308 * @return the preamble code
AndyA 6:2c77afdf7367 309 */
AndyA 4:5f1025df5530 310 unsigned char getPreambleCode() {
AndyA 4:5f1025df5530 311 return preambleCode;
AndyA 4:5f1025df5530 312 };
AndyA 6:2c77afdf7367 313 /** Get the current smart power mode
AndyA 6:2c77afdf7367 314 * @return true if smartpower is on
AndyA 6:2c77afdf7367 315 */
AndyA 4:5f1025df5530 316 bool getSmartPower() {
AndyA 4:5f1025df5530 317 return enableSmartPower;
AndyA 4:5f1025df5530 318 };
AndyA 4:5f1025df5530 319
AndyA 4:5f1025df5530 320 private:
AndyA 4:5f1025df5530 321 unsigned char channel; // 1-5 , 7
AndyA 4:5f1025df5530 322 enum prf_e prf;
AndyA 4:5f1025df5530 323 enum dataRate_e dataRate;
AndyA 4:5f1025df5530 324 enum sfd_e sfd;
AndyA 4:5f1025df5530 325 enum preamble_e preamble;
AndyA 4:5f1025df5530 326 unsigned char preambleCode; // 1-24. See section 10.5 of user manual for details.
AndyA 4:5f1025df5530 327 bool enableSmartPower;
AndyA 4:5f1025df5530 328 };
AndyA 4:5f1025df5530 329
AndyA 4:5f1025df5530 330
AndyA 3:1459d2aa6b97 331 typedef enum {minPacketSize, tunedDefault, user110k} UWBMode;
AndyA 0:bddb8cd5e7df 332
AndyA 4:5f1025df5530 333 /** A DW1000 driver
AndyA 4:5f1025df5530 334 */
AndyA 0:bddb8cd5e7df 335 class DW1000
AndyA 0:bddb8cd5e7df 336 {
AndyA 0:bddb8cd5e7df 337 public:
AndyA 0:bddb8cd5e7df 338
AndyA 6:2c77afdf7367 339 /** Constructor.
AndyA 6:2c77afdf7367 340 *
AndyA 6:2c77afdf7367 341 * @param setup The radio mode to configure the unit to use.
AndyA 6:2c77afdf7367 342 *
AndyA 6:2c77afdf7367 343 * Valid setup values are defaultConfig, tunedDefault, user110k
AndyA 6:2c77afdf7367 344 */
AndyA 0:bddb8cd5e7df 345 DW1000(UWBMode setup, PinName MOSI, PinName MISO, PinName SCLK, PinName CS, PinName IRQ); // constructor, uses SPI class
AndyA 6:2c77afdf7367 346
AndyA 6:2c77afdf7367 347 /**
AndyA 6:2c77afdf7367 348 * Sets the callbacks on packet Rx and Tx
AndyA 6:2c77afdf7367 349 * @param callbackRX The function to call on packet Rx complete
AndyA 6:2c77afdf7367 350 * @param callbackTX The function to call on packet Tx complete
AndyA 6:2c77afdf7367 351 *
AndyA 6:2c77afdf7367 352 * set either or both to null to disable the appropriate interupt
AndyA 6:2c77afdf7367 353 */
AndyA 0:bddb8cd5e7df 354 void setCallbacks(void (*callbackRX)(void), void (*callbackTX)(void)); // setter for callback functions, automatically enables interrupt, if NULL is passed the coresponding interrupt gets disabled
AndyA 6:2c77afdf7367 355
AndyA 6:2c77afdf7367 356 /**
AndyA 6:2c77afdf7367 357 * c++ version of setCallbacks()
AndyA 6:2c77afdf7367 358 * @param tptr object for callbacks
AndyA 6:2c77afdf7367 359 * @param mptrRX method to call on packet Rx complete
AndyA 6:2c77afdf7367 360 * @param mptrTX method to call on packet Tx complete
AndyA 6:2c77afdf7367 361 *
AndyA 6:2c77afdf7367 362 */
AndyA 0:bddb8cd5e7df 363 template<typename T>
AndyA 0:bddb8cd5e7df 364 void setCallbacks(T* tptr, void (T::*mptrRX)(void), void (T::*mptrTX)(void)) { // overloaded setter to treat member function pointers of objects
AndyA 0:bddb8cd5e7df 365 callbackRX.attach(tptr, mptrRX); // possible client code: dw.setCallbacks(this, &A::callbackRX, &A::callbackTX);
AndyA 0:bddb8cd5e7df 366 callbackTX.attach(tptr, mptrTX); // concept seen in line 100 of http://developer.mbed.org/users/mbed_official/code/mbed/docs/4fc01daae5a5/InterruptIn_8h_source.html
AndyA 0:bddb8cd5e7df 367 setInterrupt(true,true);
AndyA 0:bddb8cd5e7df 368 }
AndyA 0:bddb8cd5e7df 369
AndyA 0:bddb8cd5e7df 370 // Device API
AndyA 6:2c77afdf7367 371 /** Read the device ID
AndyA 6:2c77afdf7367 372 * @return the device ID (0xDECA0130)
AndyA 6:2c77afdf7367 373 */
AndyA 0:bddb8cd5e7df 374 uint32_t getDeviceID(); // gets the Device ID which should be 0xDECA0130 (good for testing SPI!)
AndyA 6:2c77afdf7367 375
AndyA 6:2c77afdf7367 376 /** Read the Extended Unique ID
AndyA 6:2c77afdf7367 377 * @return The device EUI as stored in the system registers
AndyA 6:2c77afdf7367 378 */
AndyA 6:2c77afdf7367 379 uint64_t getEUI();
AndyA 6:2c77afdf7367 380
AndyA 6:2c77afdf7367 381 /** Set the Extended Unique ID
AndyA 6:2c77afdf7367 382 * @param EUI The EUID to use
AndyA 6:2c77afdf7367 383 *
AndyA 6:2c77afdf7367 384 * Note - ID is only valid until the next power cycle and overrides the value in the OTP memory.
AndyA 6:2c77afdf7367 385 * To set a value that is automatically loaded on startup set OTP memory addresses 0 and 1.
AndyA 6:2c77afdf7367 386 */
AndyA 0:bddb8cd5e7df 387 void setEUI(uint64_t EUI); // sets 64 bit Extended Unique Identifier according to IEEE standard
AndyA 6:2c77afdf7367 388
AndyA 6:2c77afdf7367 389 /** Read voltage input
AndyA 6:2c77afdf7367 390
AndyA 6:2c77afdf7367 391 @return the current device voltage
AndyA 6:2c77afdf7367 392
AndyA 6:2c77afdf7367 393 For accurate ranging the voltage of the device should be taken into account.
AndyA 6:2c77afdf7367 394 User manual give variation as ~5.35cm / V
AndyA 6:2c77afdf7367 395 */
AndyA 0:bddb8cd5e7df 396 float getVoltage(); // gets the current chip voltage measurement form the A/D converter
AndyA 6:2c77afdf7367 397
AndyA 6:2c77afdf7367 398 /** Read on board temperature sensor
AndyA 6:2c77afdf7367 399 @return The temperature in C
AndyA 6:2c77afdf7367 400
AndyA 6:2c77afdf7367 401 For accurate ranging the temperature of the device should be taken into account.
AndyA 6:2c77afdf7367 402 User manual give variation as ~2.15mm / C
AndyA 6:2c77afdf7367 403 */
AndyA 0:bddb8cd5e7df 404 float getTemperature(); // gets the current chip temperature measurement form the A/D converter
AndyA 6:2c77afdf7367 405
AndyA 6:2c77afdf7367 406 /** Get the status register
AndyA 6:2c77afdf7367 407 * @return The system status register
AndyA 6:2c77afdf7367 408 *
AndyA 6:2c77afdf7367 409 * See user manual section 7.2.17 for details
AndyA 6:2c77afdf7367 410 */
AndyA 0:bddb8cd5e7df 411 uint64_t getStatus(); // get the 40 bit device status
AndyA 6:2c77afdf7367 412
AndyA 6:2c77afdf7367 413 /** Get the last packet recieve time
AndyA 6:2c77afdf7367 414 * @return the internal time stamp for the last packet Rx
AndyA 6:2c77afdf7367 415 *
AndyA 6:2c77afdf7367 416 * Time is counted on a clock running at 499.2MHz * 128 (~15.65ps)
AndyA 6:2c77afdf7367 417 * This value is raw time minus user set Rx antenna delay.
AndyA 6:2c77afdf7367 418 */
AndyA 0:bddb8cd5e7df 419 uint64_t getRXTimestamp();
AndyA 6:2c77afdf7367 420
AndyA 6:2c77afdf7367 421 /** Get the last packet transmit time
AndyA 6:2c77afdf7367 422 * @return the internal time stamp for the last packet Tx
AndyA 6:2c77afdf7367 423 *
AndyA 6:2c77afdf7367 424 * Time is counted on a clock running at 499.2MHz * 128 (~15.65ps)
AndyA 6:2c77afdf7367 425 * This value is raw time plus user set Tx antenna delay to give time at the antenna.
AndyA 6:2c77afdf7367 426 */
AndyA 0:bddb8cd5e7df 427 uint64_t getTXTimestamp();
AndyA 0:bddb8cd5e7df 428
AndyA 6:2c77afdf7367 429 /** Send a packet
AndyA 6:2c77afdf7367 430 * @param message A buffer containing the data to send
AndyA 6:2c77afdf7367 431 * @param length The length of the data in bytes.
AndyA 6:2c77afdf7367 432 *
AndyA 6:2c77afdf7367 433 * The supplied packet is transmitted as soon as possible and the reciever re-enabled once transmission is complete.
AndyA 6:2c77afdf7367 434 * Maximum packet size is 125 bytes.
AndyA 6:2c77afdf7367 435 */
AndyA 0:bddb8cd5e7df 436 void sendFrame(uint8_t* message, uint16_t length); // send a raw frame (length in bytes)
AndyA 6:2c77afdf7367 437
AndyA 6:2c77afdf7367 438 /** Send a packet at a certain time
AndyA 6:2c77afdf7367 439 * @param message A buffer containing the data to send
AndyA 6:2c77afdf7367 440 * @param length The length of the data in bytes.
AndyA 6:2c77afdf7367 441 * @param TxTimestamp The timestamp to send the packet.
AndyA 6:2c77afdf7367 442 *
AndyA 6:2c77afdf7367 443 * The supplied packet is transmitted once the internal clock reaches the specified timestamp.
AndyA 6:2c77afdf7367 444 * Maximum packet size is 125 bytes.
AndyA 6:2c77afdf7367 445 * Rx is disabled as soon as this command is issued and re-enabled once transmission is complete.
AndyA 6:2c77afdf7367 446 * Note - 9 LSBs are ignored so timings are only accurate to ~8ns. For more accurate timing check the
AndyA 6:2c77afdf7367 447 * tx timestamp after transmission is complete.
AndyA 6:2c77afdf7367 448 */
AndyA 0:bddb8cd5e7df 449 void sendDelayedFrame(uint8_t* message, uint16_t length, uint64_t TxTimestamp);
AndyA 0:bddb8cd5e7df 450
AndyA 6:2c77afdf7367 451 /** Set up data for a transmit on sync
AndyA 6:2c77afdf7367 452 * @param message A buffer containing the data to send
AndyA 6:2c77afdf7367 453 * @param length The length of the data in bytes.
AndyA 6:2c77afdf7367 454 *
AndyA 6:2c77afdf7367 455 * Data is loaded into the transmit buffer but the transmission is not started.
AndyA 6:2c77afdf7367 456 * Maximum packet size is 125 bytes.
AndyA 6:2c77afdf7367 457 */
AndyA 0:bddb8cd5e7df 458 void setupSyncedFrame(uint8_t* message, uint16_t length);
AndyA 6:2c77afdf7367 459
AndyA 6:2c77afdf7367 460 /** Transmit on the next sync pulse
AndyA 6:2c77afdf7367 461 *
AndyA 6:2c77afdf7367 462 * On the next rising edge of the sync line the transmitter will be activated.
AndyA 6:2c77afdf7367 463 * The packet must have previously been set up using setupSyncedFrame()
AndyA 6:2c77afdf7367 464 *
AndyA 6:2c77afdf7367 465 * Rx is disabled until transmission is complete.
AndyA 6:2c77afdf7367 466 */
AndyA 0:bddb8cd5e7df 467 void armSyncedFrame();
AndyA 0:bddb8cd5e7df 468
AndyA 6:2c77afdf7367 469 /** Enable reciever
AndyA 6:2c77afdf7367 470 *
AndyA 6:2c77afdf7367 471 * This is automatically done after each Tx completes but can also be forced manually
AndyA 6:2c77afdf7367 472 */
AndyA 0:bddb8cd5e7df 473 void startRX(); // start listening for frames
AndyA 6:2c77afdf7367 474
AndyA 6:2c77afdf7367 475 /** Disable radio link
AndyA 6:2c77afdf7367 476 *
AndyA 6:2c77afdf7367 477 * Disables both the recieve and transmit systems.
AndyA 6:2c77afdf7367 478 * Any transmissions waiting for a delayed time or sync pulse will be canceled.
AndyA 6:2c77afdf7367 479 */
AndyA 0:bddb8cd5e7df 480 void stopTRX(); // disable tranceiver go back to idle mode
AndyA 0:bddb8cd5e7df 481
AndyA 6:2c77afdf7367 482 /** Set receive antenna delay
AndyA 6:2c77afdf7367 483 * @param ticks Delay in system clock cycles
AndyA 6:2c77afdf7367 484 */
AndyA 0:bddb8cd5e7df 485 void setRxDelay(uint16_t ticks);
AndyA 6:2c77afdf7367 486 /** Set transmit antenna delay
AndyA 6:2c77afdf7367 487 * @param ticks Delay in system clock cycles
AndyA 6:2c77afdf7367 488 */
AndyA 0:bddb8cd5e7df 489 void setTxDelay(uint16_t ticks);
AndyA 0:bddb8cd5e7df 490
AndyA 6:2c77afdf7367 491 /** Get last packet size
AndyA 6:2c77afdf7367 492 * @return The length in bytes of the last packet received
AndyA 6:2c77afdf7367 493 */
AndyA 0:bddb8cd5e7df 494 uint16_t getFramelength(); // to get the framelength of the received frame from the PHY header
AndyA 0:bddb8cd5e7df 495
AndyA 6:2c77afdf7367 496 /** Get last recieved packet
AndyA 6:2c77afdf7367 497 * @param buffer The location to put the received data
AndyA 6:2c77afdf7367 498 * @param length The number of bytes to read
AndyA 6:2c77afdf7367 499 */
AndyA 0:bddb8cd5e7df 500 void readRxBuffer( uint8_t *buffer, int length ) {
AndyA 0:bddb8cd5e7df 501 readRegister(DW1000_RX_BUFFER, 0, buffer, length);
AndyA 0:bddb8cd5e7df 502 }
AndyA 0:bddb8cd5e7df 503
AndyA 6:2c77afdf7367 504 /** Read a value from the OTP memory
AndyA 6:2c77afdf7367 505 * @param word_address The OTP memory address to read.
AndyA 6:2c77afdf7367 506 * @return The 32 bit value at that address.
AndyA 6:2c77afdf7367 507 *
AndyA 6:2c77afdf7367 508 * See Section 6.3.1 of the user manual for the memory map.
AndyA 6:2c77afdf7367 509 */
AndyA 1:dcbd071f38d5 510 uint32_t readOTP (uint16_t word_address);
AndyA 6:2c77afdf7367 511
AndyA 6:2c77afdf7367 512 /** Write a value to the OTP memory
AndyA 6:2c77afdf7367 513 * @param word_address The OTP memory address to read.
AndyA 6:2c77afdf7367 514 * @param data The value to write
AndyA 6:2c77afdf7367 515 * @return True if the write was sucessful.
AndyA 6:2c77afdf7367 516 *
AndyA 6:2c77afdf7367 517 * Writes the supplied data to the OTP memory and then reads it back to verify it was sucessfully programmed.
AndyA 6:2c77afdf7367 518 * Note - this is a one time operation for each memory address.
AndyA 6:2c77afdf7367 519 * See Section 6.3.1 of the user manual for the memory map.
AndyA 6:2c77afdf7367 520 * It is recommened that the device is reset or power cycled after programing.
AndyA 6:2c77afdf7367 521 */
AndyA 0:bddb8cd5e7df 522 bool writeOTP(uint16_t word_address,uint32_t data); // program a value in the OTP. It is recommended to reset afterwards.
AndyA 0:bddb8cd5e7df 523
AndyA 6:2c77afdf7367 524
AndyA 4:5f1025df5530 525 /** Get setup description
AndyA 4:5f1025df5530 526 *
AndyA 4:5f1025df5530 527 * @param buffer Data buffer to place description in
AndyA 4:5f1025df5530 528 * @param len Length of data buffer
AndyA 4:5f1025df5530 529 *
AndyA 4:5f1025df5530 530 * Places a text string describing the current setup into the suppled buffer.
AndyA 4:5f1025df5530 531 */
AndyA 4:5f1025df5530 532 void getSetup(char *buffer, int len);
AndyA 4:5f1025df5530 533
AndyA 0:bddb8cd5e7df 534 protected:
AndyA 6:2c77afdf7367 535 /** Reset the reciever logic
AndyA 6:2c77afdf7367 536 *
AndyA 6:2c77afdf7367 537 * This should be done after any receive errors
AndyA 6:2c77afdf7367 538 */
AndyA 0:bddb8cd5e7df 539 void resetRX(); // soft reset only the tranciever part of DW1000
AndyA 6:2c77afdf7367 540
AndyA 6:2c77afdf7367 541 /** Enable/Disable interrupts
AndyA 6:2c77afdf7367 542 * @param RX true to enable recieve interrupts
AndyA 6:2c77afdf7367 543 * @param TX true to enable transmit interrupts
AndyA 6:2c77afdf7367 544 *
AndyA 6:2c77afdf7367 545 * For c style callbacks simply set the callback to null to disable it.
AndyA 6:2c77afdf7367 546 * When using c++ style callbacks both are enabled as default, this allows a method to disabled one or both.
AndyA 6:2c77afdf7367 547 */
AndyA 0:bddb8cd5e7df 548 void setInterrupt(bool RX, bool TX); // set Interrupt for received a good frame (CRC ok) or transmission done
AndyA 0:bddb8cd5e7df 549
AndyA 3:1459d2aa6b97 550 /** Set Transmit gain
AndyA 3:1459d2aa6b97 551 *
AndyA 3:1459d2aa6b97 552 * @param normalPowercB Normal transmit gain to use.
AndyA 3:1459d2aa6b97 553 * @param boost500 Gain to use for 6.8Mb/s packets of under 500ms.
AndyA 3:1459d2aa6b97 554 * @param boost250 Gain to use for 6.8Mb/s packets of under 250ms.
AndyA 3:1459d2aa6b97 555 * @param boost125 Gain to use for 6.8Mb/s packets of under 125ms.
AndyA 3:1459d2aa6b97 556 *
AndyA 3:1459d2aa6b97 557 * All gains are in cB (dB * 10). Gains can be between 0 and 335 (33.5dB).
AndyA 3:1459d2aa6b97 558 * Boost gains are optional, if not specified boost gains are set to the power for the lower rate (e.g. boost125 is set to the boost250 level).
AndyA 3:1459d2aa6b97 559 */
AndyA 3:1459d2aa6b97 560 void setTxPower(uint16_t normalPowercB, uint16_t boost500 = 0, uint16_t boost250 = 0, uint16_t boost125 = 0);
AndyA 3:1459d2aa6b97 561
AndyA 0:bddb8cd5e7df 562
AndyA 0:bddb8cd5e7df 563 private:
AndyA 0:bddb8cd5e7df 564 void resetAll(); // soft reset the entire DW1000 (some registers stay as they were see User Manual)
AndyA 3:1459d2aa6b97 565
AndyA 3:1459d2aa6b97 566 void setupRadio();
AndyA 3:1459d2aa6b97 567
AndyA 4:5f1025df5530 568 // system register setup functions
AndyA 3:1459d2aa6b97 569 void setupAGC();
AndyA 3:1459d2aa6b97 570 void setupRxConfig();
AndyA 3:1459d2aa6b97 571 void setupLDE();
AndyA 3:1459d2aa6b97 572 void setupChannel();
AndyA 3:1459d2aa6b97 573 void setupTxFrameCtrl();
AndyA 3:1459d2aa6b97 574 void setupAnalogRF();
AndyA 3:1459d2aa6b97 575 void setupFreqSynth();
AndyA 3:1459d2aa6b97 576 void setupTxCalibration();
AndyA 3:1459d2aa6b97 577 void setupSystemConfig();
AndyA 0:bddb8cd5e7df 578 void loadLDE(); // load the leading edge detection algorithm to RAM, [IMPORTANT because receiving malfunction may occur] see User Manual LDELOAD on p22 & p158
AndyA 0:bddb8cd5e7df 579 void loadLDOTUNE(); // load the LDO tuning as set in the factory
AndyA 0:bddb8cd5e7df 580
AndyA 3:1459d2aa6b97 581 uint8_t powerToRegValue(uint16_t powercB);
AndyA 3:1459d2aa6b97 582
AndyA 4:5f1025df5530 583 DW1000Setup systemConfig;
AndyA 3:1459d2aa6b97 584
AndyA 0:bddb8cd5e7df 585
AndyA 0:bddb8cd5e7df 586
AndyA 0:bddb8cd5e7df 587 // Interrupt
AndyA 0:bddb8cd5e7df 588 InterruptIn irq; // Pin used to handle Events from DW1000 by an Interrupthandler
AndyA 0:bddb8cd5e7df 589 FunctionPointer callbackRX; // function pointer to callback which is called when successfull RX took place
AndyA 0:bddb8cd5e7df 590 FunctionPointer callbackTX; // function pointer to callback which is called when successfull TX took place
AndyA 0:bddb8cd5e7df 591 void ISR(); // interrupt handling method (also calls according callback methods)
AndyA 0:bddb8cd5e7df 592
AndyA 0:bddb8cd5e7df 593 // SPI Inteface
AndyA 0:bddb8cd5e7df 594 SPI spi; // SPI Bus
AndyA 0:bddb8cd5e7df 595 DigitalOut cs; // Slave selector for SPI-Bus (here explicitly needed to start and end SPI transactions also usable to wake up DW1000)
AndyA 0:bddb8cd5e7df 596
AndyA 0:bddb8cd5e7df 597 uint8_t readRegister8(uint8_t reg, uint16_t subaddress); // expressive methods to read or write the number of bits written in the name
AndyA 0:bddb8cd5e7df 598 uint16_t readRegister16(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 599 uint32_t readRegister32(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 600 uint64_t readRegister40(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 601 uint64_t readRegister64(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 602 void writeRegister8(uint8_t reg, uint16_t subaddress, uint8_t buffer);
AndyA 0:bddb8cd5e7df 603 void writeRegister16(uint8_t reg, uint16_t subaddress, uint16_t buffer);
AndyA 0:bddb8cd5e7df 604 void writeRegister32(uint8_t reg, uint16_t subaddress, uint32_t buffer);
AndyA 0:bddb8cd5e7df 605 void writeRegister40(uint8_t reg, uint16_t subaddress, uint64_t buffer);
AndyA 0:bddb8cd5e7df 606
AndyA 0:bddb8cd5e7df 607 void readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // reads the selected part of a slave register into the buffer memory
AndyA 0:bddb8cd5e7df 608 void writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // writes the buffer memory to the selected slave register
AndyA 0:bddb8cd5e7df 609 void setupTransaction(uint8_t reg, uint16_t subaddress, bool write); // sets up an SPI read or write transaction with correct register address and offset
AndyA 0:bddb8cd5e7df 610 void select(); // selects the only slave for a transaction
AndyA 0:bddb8cd5e7df 611 void deselect(); // deselects the only slave after transaction
AndyA 0:bddb8cd5e7df 612 };
AndyA 0:bddb8cd5e7df 613
AndyA 0:bddb8cd5e7df 614 #endif