Andy A / DW1000

DW1000 UWB driver based on work of Matthias Grob & Manuel Stalder - ETH Zürich - 2015

Dependencies:   BurstSPI

DW1000.h@16:2080adef6fa6, 2016-04-05 (annotated)

Committer:
AndyA
Date:
Tue Apr 05 13:43:54 2016 +0000
Revision:
16:2080adef6fa6
Parent:
1:dcbd071f38d5 
Added comments;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AndyA 0:bddb8cd5e7df 1 // by Matthias Grob & Manuel Stalder - ETH Zürich - 2015
AndyA 0:bddb8cd5e7df 2
AndyA 0:bddb8cd5e7df 3 #ifndef DW1000_H
AndyA 0:bddb8cd5e7df 4 #define DW1000_H
AndyA 0:bddb8cd5e7df 5
AndyA 0:bddb8cd5e7df 6 #include "mbed.h"
AndyA 0:bddb8cd5e7df 7
AndyA 0:bddb8cd5e7df 8 // register addresses
AndyA 0:bddb8cd5e7df 9 // Mnemonic Address Bytes Description
AndyA 0:bddb8cd5e7df 10 #define DW1000_DEV_ID 0x00 // 4 Device Identifier – includes device type and revision information
AndyA 0:bddb8cd5e7df 11 #define DW1000_EUI 0x01 // 8 Extended Unique Identifier
AndyA 0:bddb8cd5e7df 12 #define DW1000_PANADR 0x03 // 4 PAN Identifier and Short Address
AndyA 0:bddb8cd5e7df 13 #define DW1000_SYS_CFG 0x04 // 4 System Configuration bitmap
AndyA 0:bddb8cd5e7df 14 #define DW1000_SYS_TIME 0x06 // 5 System Time Counter (40-bit)
AndyA 0:bddb8cd5e7df 15 #define DW1000_TX_FCTRL 0x08 // 5 Transmit Frame Control
AndyA 0:bddb8cd5e7df 16 #define DW1000_TX_BUFFER 0x09 // 1024 Transmit Data Buffer
AndyA 0:bddb8cd5e7df 17 #define DW1000_DX_TIME 0x0A // 5 Delayed Send or Receive Time (40-bit)
AndyA 0:bddb8cd5e7df 18 #define DW1000_RX_FWTO 0x0C // 2 Receive Frame Wait Timeout Period
AndyA 0:bddb8cd5e7df 19 #define DW1000_SYS_CTRL 0x0D // 4 System Control Register
AndyA 0:bddb8cd5e7df 20 #define DW1000_SYS_MASK 0x0E // 4 System Event Mask Register
AndyA 0:bddb8cd5e7df 21 #define DW1000_SYS_STATUS 0x0F // 5 System Event Status Register
AndyA 0:bddb8cd5e7df 22 #define DW1000_RX_FINFO 0x10 // 4 RX Frame Information (in double buffer set)
AndyA 0:bddb8cd5e7df 23 #define DW1000_RX_BUFFER 0x11 // 1024 Receive Data Buffer (in double buffer set)
AndyA 0:bddb8cd5e7df 24 #define DW1000_RX_FQUAL 0x12 // 8 Rx Frame Quality information (in double buffer set)
AndyA 0:bddb8cd5e7df 25 #define DW1000_RX_TTCKI 0x13 // 4 Receiver Time Tracking Interval (in double buffer set)
AndyA 0:bddb8cd5e7df 26 #define DW1000_RX_TTCKO 0x14 // 5 Receiver Time Tracking Offset (in double buffer set)
AndyA 0:bddb8cd5e7df 27 #define DW1000_RX_TIME 0x15 // 14 Receive Message Time of Arrival (in double buffer set)
AndyA 0:bddb8cd5e7df 28 #define DW1000_TX_TIME 0x17 // 10 Transmit Message Time of Sending (in double buffer set)
AndyA 0:bddb8cd5e7df 29 #define DW1000_TX_ANTD 0x18 // 2 16-bit Delay from Transmit to Antenna
AndyA 0:bddb8cd5e7df 30 #define DW1000_SYS_STATE 0x19 // 5 System State information
AndyA 0:bddb8cd5e7df 31 #define DW1000_ACK_RESP_T 0x1A // 4 Acknowledgement Time and Response Time
AndyA 0:bddb8cd5e7df 32 #define DW1000_RX_SNIFF 0x1D // 4 Pulsed Preamble Reception Configuration
AndyA 0:bddb8cd5e7df 33 #define DW1000_TX_POWER 0x1E // 4 TX Power Control
AndyA 0:bddb8cd5e7df 34 #define DW1000_CHAN_CTRL 0x1F // 4 Channel Control
AndyA 0:bddb8cd5e7df 35 #define DW1000_USR_SFD 0x21 // 41 User-specified short/long TX/RX SFD sequences
AndyA 0:bddb8cd5e7df 36 #define DW1000_AGC_CTRL 0x23 // 32 Automatic Gain Control configuration
AndyA 0:bddb8cd5e7df 37 #define DW1000_EXT_SYNC 0x24 // 12 External synchronisation control.
AndyA 0:bddb8cd5e7df 38 #define DW1000_ACC_MEM 0x25 // 4064 Read access to accumulator data
AndyA 0:bddb8cd5e7df 39 #define DW1000_GPIO_CTRL 0x26 // 44 Peripheral register bus 1 access - GPIO control
AndyA 0:bddb8cd5e7df 40 #define DW1000_DRX_CONF 0x27 // 44 Digital Receiver configuration
AndyA 0:bddb8cd5e7df 41 #define DW1000_RF_CONF 0x28 // 58 Analog RF Configuration
AndyA 0:bddb8cd5e7df 42 #define DW1000_TX_CAL 0x2A // 52 Transmitter calibration block
AndyA 0:bddb8cd5e7df 43 #define DW1000_FS_CTRL 0x2B // 21 Frequency synthesiser control block
AndyA 0:bddb8cd5e7df 44 #define DW1000_AON 0x2C // 12 Always-On register set
AndyA 0:bddb8cd5e7df 45 #define DW1000_OTP_IF 0x2D // 18 One Time Programmable Memory Interface
AndyA 0:bddb8cd5e7df 46 #define DW1000_LDE_CTRL 0x2E // - Leading edge detection control block
AndyA 0:bddb8cd5e7df 47 #define DW1000_DIG_DIAG 0x2F // 41 Digital Diagnostics Interface
AndyA 0:bddb8cd5e7df 48 #define DW1000_PMSC 0x36 // 48 Power Management System Control Block
AndyA 0:bddb8cd5e7df 49
AndyA 0:bddb8cd5e7df 50 // AGC_CTRL sub registers
AndyA 0:bddb8cd5e7df 51 #define DWAGCCTRL_AGC_CTRL1 0x02
AndyA 0:bddb8cd5e7df 52 #define DWAGCCTRL_AGC_TUNE1 0x04
AndyA 0:bddb8cd5e7df 53 #define DWAGCCTRL_AGC_TUNE2 0x0C
AndyA 0:bddb8cd5e7df 54 #define DWAGCCTRL_AGC_TUNE3 0x12
AndyA 0:bddb8cd5e7df 55
AndyA 0:bddb8cd5e7df 56 // EXT_SYNC sub registers
AndyA 0:bddb8cd5e7df 57 #define DWEXTSYNC_EC_CTRL 0x00
AndyA 0:bddb8cd5e7df 58 #define DWEXTSYNC_EC_RXTC 0x04
AndyA 0:bddb8cd5e7df 59 #define DWEXTSYNC_EC_GOLP 0x08
AndyA 0:bddb8cd5e7df 60
AndyA 0:bddb8cd5e7df 61 // GPIO sub registers
AndyA 0:bddb8cd5e7df 62 #define DWGPIO_GPIO_MODE 0x00
AndyA 0:bddb8cd5e7df 63 #define DWGPIO_GPIO_DIR 0x08
AndyA 0:bddb8cd5e7df 64 #define DWGPIO_GPIO_DOUT 0x0C
AndyA 0:bddb8cd5e7df 65 #define DWGPIO_GPIO_IRQE 0x10
AndyA 0:bddb8cd5e7df 66 #define DWGPIO_GPIO_ISEN 0x14
AndyA 0:bddb8cd5e7df 67 #define DWGPIO_GPIO_IMODE 0x18
AndyA 0:bddb8cd5e7df 68 #define DWGPIO_GPIO_IBES 0x1C
AndyA 0:bddb8cd5e7df 69 #define DWGPIO_GPIO_ICLR 0x20
AndyA 0:bddb8cd5e7df 70 #define DWGPIO_GPIO_IDBE 0x24
AndyA 0:bddb8cd5e7df 71 #define DWGPIO_GPIO_RAW 0x28
AndyA 0:bddb8cd5e7df 72
AndyA 0:bddb8cd5e7df 73 // DRX sub registers
AndyA 0:bddb8cd5e7df 74 #define DWDRX_DRX_TUNE0B 0x02
AndyA 0:bddb8cd5e7df 75 #define DWDRX_DRX_TUNE1A 0x04
AndyA 0:bddb8cd5e7df 76 #define DWDRX_DRX_TUNE1B 0x06
AndyA 0:bddb8cd5e7df 77 #define DWDRX_DRX_TUNE2 0x08
AndyA 0:bddb8cd5e7df 78 #define DWDRX_DRX_SFDTOC 0x20
AndyA 0:bddb8cd5e7df 79 #define DWDRX_DRX_PRETOC 0x24
AndyA 0:bddb8cd5e7df 80 #define DWDRX_DRX_TUNE4H 0x26
AndyA 0:bddb8cd5e7df 81
AndyA 0:bddb8cd5e7df 82 //RF conf sub registers
AndyA 0:bddb8cd5e7df 83 #define DWRFCONF_RF_CONF 0x00
AndyA 0:bddb8cd5e7df 84 #define DWRFCONF_RF_RXCTRLH 0x0B
AndyA 0:bddb8cd5e7df 85 #define DWRFCONF_RF_TXCTRL 0x0C
AndyA 0:bddb8cd5e7df 86 #define DWRFCONF_RF_STATUS 0x2C
AndyA 0:bddb8cd5e7df 87 #define DWRFCONF_RF_LDOTUNE 0x30
AndyA 0:bddb8cd5e7df 88
AndyA 0:bddb8cd5e7df 89 // TX cal sub registers
AndyA 0:bddb8cd5e7df 90 #define DWTXCAL_TC_SARC 0x00
AndyA 0:bddb8cd5e7df 91 #define DWTXCAL_TC_SARL 0x03
AndyA 0:bddb8cd5e7df 92 #define DWTXCAL_TC_SARW 0x06
AndyA 0:bddb8cd5e7df 93 #define DWTXCAL_TC_PGDELAY 0x0B
AndyA 0:bddb8cd5e7df 94 #define DWTXCAL_TC_PGTEST 0x0C
AndyA 0:bddb8cd5e7df 95
AndyA 0:bddb8cd5e7df 96 // Freq synth sub registers
AndyA 0:bddb8cd5e7df 97 #define DWFSCTRL_FS_PLLCFG 0x07
AndyA 0:bddb8cd5e7df 98 #define DWFSCTRL_FS_PLLTUNE 0x0B
AndyA 0:bddb8cd5e7df 99 #define DWFSCTRL_FS_XTALT 0x0E
AndyA 0:bddb8cd5e7df 100
AndyA 0:bddb8cd5e7df 101 // Always on sub registers
AndyA 0:bddb8cd5e7df 102 #define DWAON_AON_WCFG 0x00
AndyA 0:bddb8cd5e7df 103 #define DWAON_AON_CTRL 0x02
AndyA 0:bddb8cd5e7df 104 #define DWAON_AON_RDAT 0x03
AndyA 0:bddb8cd5e7df 105 #define DWAON_AON_ADDR 0x04
AndyA 0:bddb8cd5e7df 106 #define DWAON_AON_CFG0 0x06
AndyA 0:bddb8cd5e7df 107 #define DWAON_AON_CFG1 0x0A
AndyA 0:bddb8cd5e7df 108
AndyA 0:bddb8cd5e7df 109 // OTP sub registers
AndyA 0:bddb8cd5e7df 110 #define DWOTP_OTP_WDAT 0x00
AndyA 0:bddb8cd5e7df 111 #define DWOTP_OTP_ADDR 0x04
AndyA 0:bddb8cd5e7df 112 #define DWOTP_OTP_CTRL 0x06
AndyA 0:bddb8cd5e7df 113 #define DWOTP_OTP_STAT 0x08
AndyA 0:bddb8cd5e7df 114 #define DWOTP_OTP_RDAT 0x0A
AndyA 0:bddb8cd5e7df 115 #define DWOTP_OTP_SRDAT 0x0E
AndyA 0:bddb8cd5e7df 116 #define DWOTP_OTP_SF 0x12
AndyA 0:bddb8cd5e7df 117
AndyA 0:bddb8cd5e7df 118 //LDE_IF sub registers
AndyA 0:bddb8cd5e7df 119 #define DWLDE_LDE_THRESH 0x0000
AndyA 0:bddb8cd5e7df 120 #define DWLDE_LDE_CFG1 0x0806
AndyA 0:bddb8cd5e7df 121 #define DWLDE_LDE_PPINDX 0x1000
AndyA 0:bddb8cd5e7df 122 #define DWLDE_LDE_PPAMPL 0x1002
AndyA 0:bddb8cd5e7df 123 #define DWLDE_LDE_RXANTD 0x1804
AndyA 0:bddb8cd5e7df 124 #define DWLDE_LDE_CFG2 0x1806
AndyA 0:bddb8cd5e7df 125 #define DWLDE_LDE_REPC 0x2804
AndyA 0:bddb8cd5e7df 126
AndyA 0:bddb8cd5e7df 127 // Dig Diag sub registers
AndyA 0:bddb8cd5e7df 128 #define DWDIAG_EVC_CTRL 0x00
AndyA 0:bddb8cd5e7df 129 #define DWDIAG_EVC_PHE 0x04
AndyA 0:bddb8cd5e7df 130 #define DWDIAG_EVC_RSE 0x06
AndyA 0:bddb8cd5e7df 131 #define DWDIAG_EVC_FCG 0x08
AndyA 0:bddb8cd5e7df 132 #define DWDIAG_EVC_FCE 0x0A
AndyA 0:bddb8cd5e7df 133 #define DWDIAG_EVC_FFR 0x0C
AndyA 0:bddb8cd5e7df 134 #define DWDIAG_EVC_OVR 0x0E
AndyA 0:bddb8cd5e7df 135 #define DWDIAG_EVC_STO 0x10
AndyA 0:bddb8cd5e7df 136 #define DWDIAG_EVC_PTO 0x12
AndyA 0:bddb8cd5e7df 137 #define DWDIAG_EVC_FWTO 0x14
AndyA 0:bddb8cd5e7df 138 #define DWDIAG_EVC_TXFS 0x16
AndyA 0:bddb8cd5e7df 139 #define DWDIAG_EVC_HPW 0x18
AndyA 0:bddb8cd5e7df 140 #define DWDIAG_EVC_TPW 0x1A
AndyA 0:bddb8cd5e7df 141 #define DWDIAG_DIAG_TMC 0x24
AndyA 0:bddb8cd5e7df 142
AndyA 0:bddb8cd5e7df 143 // power control sub registers
AndyA 0:bddb8cd5e7df 144 #define DWPMSC_PMSC_CTRL0 0x00
AndyA 0:bddb8cd5e7df 145 #define DWPMSC_PMSC_CTRL1 0x04
AndyA 0:bddb8cd5e7df 146 #define DWPMSC_PMSC_SNOZT 0x0C
AndyA 0:bddb8cd5e7df 147 #define DWPMSC_PMSC_TXFSEQ 0x26
AndyA 0:bddb8cd5e7df 148 #define DWPMSC_PMSC_LEDC 0x28
AndyA 0:bddb8cd5e7df 149
AndyA 0:bddb8cd5e7df 150
AndyA 0:bddb8cd5e7df 151 #define DW1000_WRITE_FLAG 0x80 // First Bit of the address has to be 1 to indicate we want to write
AndyA 0:bddb8cd5e7df 152 #define DW1000_SUBADDRESS_FLAG 0x40 // if we have a sub address second Bit has to be 1
AndyA 0:bddb8cd5e7df 153 #define DW1000_2_SUBADDRESS_FLAG 0x80 // if we have a long sub adress (more than 7 Bit) we set this Bit in the first part
AndyA 0:bddb8cd5e7df 154
AndyA 16:2080adef6fa6 155 /**
AndyA 16:2080adef6fa6 156 * The supported radio modes
AndyA 16:2080adef6fa6 157 * @param defaultConfig Leave everything as it's power up default
AndyA 16:2080adef6fa6 158 * @param tunedDefault The default plus the changes listed in V2.07 of the user manual as recomended changes to the default configuration
AndyA 16:2080adef6fa6 159 * @param user110k The lower data rate options used by Matthias Grob & Manuel Stalder in the origional version of the driver.
AndyA 16:2080adef6fa6 160 */
AndyA 0:bddb8cd5e7df 161 typedef enum {defaultConfig, tunedDefault, user110k} UWBMode;
AndyA 0:bddb8cd5e7df 162
AndyA 16:2080adef6fa6 163 /** A driver for the DW1000 UWB module
AndyA 16:2080adef6fa6 164 */
AndyA 0:bddb8cd5e7df 165 class DW1000
AndyA 0:bddb8cd5e7df 166 {
AndyA 0:bddb8cd5e7df 167 public:
AndyA 0:bddb8cd5e7df 168
AndyA 16:2080adef6fa6 169 /** Constructor.
AndyA 16:2080adef6fa6 170 *
AndyA 16:2080adef6fa6 171 * @param setup The radio mode to configure the unit to use.
AndyA 16:2080adef6fa6 172 *
AndyA 16:2080adef6fa6 173 */
AndyA 0:bddb8cd5e7df 174 DW1000(UWBMode setup, PinName MOSI, PinName MISO, PinName SCLK, PinName CS, PinName IRQ); // constructor, uses SPI class
AndyA 16:2080adef6fa6 175
AndyA 16:2080adef6fa6 176 /**
AndyA 16:2080adef6fa6 177 * Sets the callbacks on packet Rx and Tx
AndyA 16:2080adef6fa6 178 * @param callbackRX The function to call on packet Rx complete
AndyA 16:2080adef6fa6 179 * @param callbackTX The function to call on packet Tx complete
AndyA 16:2080adef6fa6 180 *
AndyA 16:2080adef6fa6 181 * set either or both to null to disable the appropriate interupt
AndyA 16:2080adef6fa6 182 */
AndyA 0:bddb8cd5e7df 183 void setCallbacks(void (*callbackRX)(void), void (*callbackTX)(void)); // setter for callback functions, automatically enables interrupt, if NULL is passed the coresponding interrupt gets disabled
AndyA 16:2080adef6fa6 184
AndyA 16:2080adef6fa6 185 /**
AndyA 16:2080adef6fa6 186 * c++ version of setCallbacks()
AndyA 16:2080adef6fa6 187 * @param tptr object for callbacks
AndyA 16:2080adef6fa6 188 * @param mptrRX method to call on packet Rx complete
AndyA 16:2080adef6fa6 189 * @param mptrTX method to call on packet Tx complete
AndyA 16:2080adef6fa6 190 *
AndyA 16:2080adef6fa6 191 */
AndyA 0:bddb8cd5e7df 192 template<typename T>
AndyA 0:bddb8cd5e7df 193 void setCallbacks(T* tptr, void (T::*mptrRX)(void), void (T::*mptrTX)(void)) { // overloaded setter to treat member function pointers of objects
AndyA 0:bddb8cd5e7df 194 callbackRX.attach(tptr, mptrRX); // possible client code: dw.setCallbacks(this, &A::callbackRX, &A::callbackTX);
AndyA 0:bddb8cd5e7df 195 callbackTX.attach(tptr, mptrTX); // concept seen in line 100 of http://developer.mbed.org/users/mbed_official/code/mbed/docs/4fc01daae5a5/InterruptIn_8h_source.html
AndyA 0:bddb8cd5e7df 196 setInterrupt(true,true);
AndyA 0:bddb8cd5e7df 197 }
AndyA 0:bddb8cd5e7df 198
AndyA 0:bddb8cd5e7df 199 // Device API
AndyA 16:2080adef6fa6 200 /** Read the device ID
AndyA 16:2080adef6fa6 201 * @return the device ID (0xDECA0130)
AndyA 16:2080adef6fa6 202 */
AndyA 0:bddb8cd5e7df 203 uint32_t getDeviceID(); // gets the Device ID which should be 0xDECA0130 (good for testing SPI!)
AndyA 16:2080adef6fa6 204
AndyA 16:2080adef6fa6 205 /** Read the Extended Unique ID
AndyA 16:2080adef6fa6 206 * @return The device EUI as stored in the system registers
AndyA 16:2080adef6fa6 207 */
AndyA 16:2080adef6fa6 208 uint64_t getEUI();
AndyA 16:2080adef6fa6 209
AndyA 16:2080adef6fa6 210 /** Set the Extended Unique ID
AndyA 16:2080adef6fa6 211 * @param EUI The EUID to use
AndyA 16:2080adef6fa6 212 *
AndyA 16:2080adef6fa6 213 * Note - ID is only valid until the next power cycle and overrides the value in the OTP memory.
AndyA 16:2080adef6fa6 214 * To set a value that is automatically loaded on startup set OTP memory addresses 0 and 1.
AndyA 16:2080adef6fa6 215 */
AndyA 0:bddb8cd5e7df 216 void setEUI(uint64_t EUI); // sets 64 bit Extended Unique Identifier according to IEEE standard
AndyA 16:2080adef6fa6 217
AndyA 16:2080adef6fa6 218 /** Read voltage input
AndyA 16:2080adef6fa6 219
AndyA 16:2080adef6fa6 220 @return the current device voltage
AndyA 16:2080adef6fa6 221
AndyA 16:2080adef6fa6 222 For accurate ranging the voltage of the device should be taken into account.
AndyA 16:2080adef6fa6 223 User manual give variation as ~5.35cm / V
AndyA 16:2080adef6fa6 224 */
AndyA 0:bddb8cd5e7df 225 float getVoltage(); // gets the current chip voltage measurement form the A/D converter
AndyA 16:2080adef6fa6 226
AndyA 16:2080adef6fa6 227 /** Read on board temperature sensor
AndyA 16:2080adef6fa6 228 @return The temperature in C
AndyA 16:2080adef6fa6 229
AndyA 16:2080adef6fa6 230 For accurate ranging the temperature of the device should be taken into account.
AndyA 16:2080adef6fa6 231 User manual give variation as ~2.15mm / C
AndyA 16:2080adef6fa6 232 */
AndyA 0:bddb8cd5e7df 233 float getTemperature(); // gets the current chip temperature measurement form the A/D converter
AndyA 16:2080adef6fa6 234
AndyA 16:2080adef6fa6 235 /** Get the status register
AndyA 16:2080adef6fa6 236 * @return The system status register
AndyA 16:2080adef6fa6 237 *
AndyA 16:2080adef6fa6 238 * See user manual section 7.2.17 for details
AndyA 16:2080adef6fa6 239 */
AndyA 0:bddb8cd5e7df 240 uint64_t getStatus(); // get the 40 bit device status
AndyA 16:2080adef6fa6 241
AndyA 16:2080adef6fa6 242 /** Get the last packet recieve time
AndyA 16:2080adef6fa6 243 * @return the internal time stamp for the last packet Rx
AndyA 16:2080adef6fa6 244 *
AndyA 16:2080adef6fa6 245 * Time is counted on a clock running at 499.2MHz * 128 (~15.65ps)
AndyA 16:2080adef6fa6 246 * This value is raw time minus user set Rx antenna delay.
AndyA 16:2080adef6fa6 247 */
AndyA 0:bddb8cd5e7df 248 uint64_t getRXTimestamp();
AndyA 16:2080adef6fa6 249
AndyA 16:2080adef6fa6 250 /** Get the last packet transmit time
AndyA 16:2080adef6fa6 251 * @return the internal time stamp for the last packet Tx
AndyA 16:2080adef6fa6 252 *
AndyA 16:2080adef6fa6 253 * Time is counted on a clock running at 499.2MHz * 128 (~15.65ps)
AndyA 16:2080adef6fa6 254 * This value is raw time plus user set Tx antenna delay to give time at the antenna.
AndyA 16:2080adef6fa6 255 */
AndyA 0:bddb8cd5e7df 256 uint64_t getTXTimestamp();
AndyA 0:bddb8cd5e7df 257
AndyA 16:2080adef6fa6 258 /** Send a packet
AndyA 16:2080adef6fa6 259 * @param message A buffer containing the data to send
AndyA 16:2080adef6fa6 260 * @param length The length of the data in bytes.
AndyA 16:2080adef6fa6 261 *
AndyA 16:2080adef6fa6 262 * The supplied packet is transmitted as soon as possible and the reciever re-enabled once transmission is complete.
AndyA 16:2080adef6fa6 263 * Maximum packet size is 125 bytes.
AndyA 16:2080adef6fa6 264 */
AndyA 0:bddb8cd5e7df 265 void sendFrame(uint8_t* message, uint16_t length); // send a raw frame (length in bytes)
AndyA 16:2080adef6fa6 266
AndyA 16:2080adef6fa6 267 /** Send a packet at a certain time
AndyA 16:2080adef6fa6 268 * @param message A buffer containing the data to send
AndyA 16:2080adef6fa6 269 * @param length The length of the data in bytes.
AndyA 16:2080adef6fa6 270 * @param TxTimestamp The timestamp to send the packet.
AndyA 16:2080adef6fa6 271 *
AndyA 16:2080adef6fa6 272 * The supplied packet is transmitted once the internal clock reaches the specified timestamp.
AndyA 16:2080adef6fa6 273 * Maximum packet size is 125 bytes.
AndyA 16:2080adef6fa6 274 * Rx is disabled as soon as this command is issued and re-enabled once transmission is complete.
AndyA 16:2080adef6fa6 275 * Note - 9 LSBs are ignored so timings are only accurate to ~8ns. For more accurate timing check the
AndyA 16:2080adef6fa6 276 * tx timestamp after transmission is complete.
AndyA 16:2080adef6fa6 277 */
AndyA 0:bddb8cd5e7df 278 void sendDelayedFrame(uint8_t* message, uint16_t length, uint64_t TxTimestamp);
AndyA 0:bddb8cd5e7df 279
AndyA 16:2080adef6fa6 280 /** Set up data for a transmit on sync
AndyA 16:2080adef6fa6 281 * @param message A buffer containing the data to send
AndyA 16:2080adef6fa6 282 * @param length The length of the data in bytes.
AndyA 16:2080adef6fa6 283 *
AndyA 16:2080adef6fa6 284 * Data is loaded into the transmit buffer but the transmission is not started.
AndyA 16:2080adef6fa6 285 * Maximum packet size is 125 bytes.
AndyA 16:2080adef6fa6 286 */
AndyA 0:bddb8cd5e7df 287 void setupSyncedFrame(uint8_t* message, uint16_t length);
AndyA 16:2080adef6fa6 288
AndyA 16:2080adef6fa6 289 /** Transmit on the next sync pulse
AndyA 16:2080adef6fa6 290 *
AndyA 16:2080adef6fa6 291 * On the next rising edge of the sync line the transmitter will be activated.
AndyA 16:2080adef6fa6 292 * The packet must have previously been set up using setupSyncedFrame()
AndyA 16:2080adef6fa6 293 *
AndyA 16:2080adef6fa6 294 * Rx is disabled until transmission is complete.
AndyA 16:2080adef6fa6 295 */
AndyA 0:bddb8cd5e7df 296 void armSyncedFrame();
AndyA 0:bddb8cd5e7df 297
AndyA 16:2080adef6fa6 298 /** Enable reciever
AndyA 16:2080adef6fa6 299 *
AndyA 16:2080adef6fa6 300 * This is automatically done after each Tx completes but can also be forced manually
AndyA 16:2080adef6fa6 301 */
AndyA 0:bddb8cd5e7df 302 void startRX(); // start listening for frames
AndyA 16:2080adef6fa6 303
AndyA 16:2080adef6fa6 304 /** Disable radio link
AndyA 16:2080adef6fa6 305 *
AndyA 16:2080adef6fa6 306 * Disables both the recieve and transmit systems.
AndyA 16:2080adef6fa6 307 * Any transmissions waiting for a delayed time or sync pulse will be canceled.
AndyA 16:2080adef6fa6 308 */
AndyA 0:bddb8cd5e7df 309 void stopTRX(); // disable tranceiver go back to idle mode
AndyA 0:bddb8cd5e7df 310
AndyA 16:2080adef6fa6 311 /** Set receive antenna delay
AndyA 16:2080adef6fa6 312 * @param ticks Delay in system clock cycles
AndyA 16:2080adef6fa6 313 */
AndyA 0:bddb8cd5e7df 314 void setRxDelay(uint16_t ticks);
AndyA 16:2080adef6fa6 315 /** Set transmit antenna delay
AndyA 16:2080adef6fa6 316 * @param ticks Delay in system clock cycles
AndyA 16:2080adef6fa6 317 */
AndyA 0:bddb8cd5e7df 318 void setTxDelay(uint16_t ticks);
AndyA 0:bddb8cd5e7df 319
AndyA 16:2080adef6fa6 320 /** Get last packet size
AndyA 16:2080adef6fa6 321 * @return The length in bytes of the last packet received
AndyA 16:2080adef6fa6 322 */
AndyA 0:bddb8cd5e7df 323 uint16_t getFramelength(); // to get the framelength of the received frame from the PHY header
AndyA 0:bddb8cd5e7df 324
AndyA 16:2080adef6fa6 325 /** Get last recieved packet
AndyA 16:2080adef6fa6 326 * @param buffer The location to put the received data
AndyA 16:2080adef6fa6 327 * @param length The number of bytes to read
AndyA 16:2080adef6fa6 328 */
AndyA 0:bddb8cd5e7df 329 void readRxBuffer( uint8_t *buffer, int length ) {
AndyA 0:bddb8cd5e7df 330 readRegister(DW1000_RX_BUFFER, 0, buffer, length);
AndyA 0:bddb8cd5e7df 331 }
AndyA 0:bddb8cd5e7df 332
AndyA 16:2080adef6fa6 333 /** Read a value from the OTP memory
AndyA 16:2080adef6fa6 334 * @param word_address The OTP memory address to read.
AndyA 16:2080adef6fa6 335 * @return The 32 bit value at that address.
AndyA 16:2080adef6fa6 336 *
AndyA 16:2080adef6fa6 337 * See Section 6.3.1 of the user manual for the memory map.
AndyA 16:2080adef6fa6 338 */
AndyA 1:dcbd071f38d5 339 uint32_t readOTP (uint16_t word_address);
AndyA 16:2080adef6fa6 340
AndyA 16:2080adef6fa6 341 /** Write a value to the OTP memory
AndyA 16:2080adef6fa6 342 * @param word_address The OTP memory address to read.
AndyA 16:2080adef6fa6 343 * @param data The value to write
AndyA 16:2080adef6fa6 344 * @return True if the write was sucessful.
AndyA 16:2080adef6fa6 345 *
AndyA 16:2080adef6fa6 346 * Writes the supplied data to the OTP memory and then reads it back to verify it was sucessfully programmed.
AndyA 16:2080adef6fa6 347 * Note - this is a one time operation for each memory address.
AndyA 16:2080adef6fa6 348 * See Section 6.3.1 of the user manual for the memory map.
AndyA 16:2080adef6fa6 349 * It is recommened that the device is reset or power cycled after programing.
AndyA 16:2080adef6fa6 350 */
AndyA 0:bddb8cd5e7df 351 bool writeOTP(uint16_t word_address,uint32_t data); // program a value in the OTP. It is recommended to reset afterwards.
AndyA 0:bddb8cd5e7df 352
AndyA 0:bddb8cd5e7df 353 protected:
AndyA 16:2080adef6fa6 354
AndyA 16:2080adef6fa6 355 /** Reset the reciever logic
AndyA 16:2080adef6fa6 356 *
AndyA 16:2080adef6fa6 357 * This should be done after any receive errors
AndyA 16:2080adef6fa6 358 */
AndyA 0:bddb8cd5e7df 359 void resetRX(); // soft reset only the tranciever part of DW1000
AndyA 16:2080adef6fa6 360
AndyA 16:2080adef6fa6 361 /** Enable/Disable interrupts
AndyA 16:2080adef6fa6 362 * @param RX true to enable recieve interrupts
AndyA 16:2080adef6fa6 363 * @param TX true to enable transmit interrupts
AndyA 16:2080adef6fa6 364 *
AndyA 16:2080adef6fa6 365 * For c style callbacks simply set the callback to null to disable it.
AndyA 16:2080adef6fa6 366 * When using c++ style callbacks both are enabled as default, this allows a method to disabled one or both.
AndyA 16:2080adef6fa6 367 */
AndyA 0:bddb8cd5e7df 368 void setInterrupt(bool RX, bool TX); // set Interrupt for received a good frame (CRC ok) or transmission done
AndyA 0:bddb8cd5e7df 369
AndyA 0:bddb8cd5e7df 370
AndyA 0:bddb8cd5e7df 371 private:
AndyA 0:bddb8cd5e7df 372 void resetAll(); // soft reset the entire DW1000 (some registers stay as they were see User Manual)
AndyA 0:bddb8cd5e7df 373 void loadLDE(); // load the leading edge detection algorithm to RAM, [IMPORTANT because receiving malfunction may occur] see User Manual LDELOAD on p22 & p158
AndyA 0:bddb8cd5e7df 374 void loadLDOTUNE(); // load the LDO tuning as set in the factory
AndyA 0:bddb8cd5e7df 375
AndyA 0:bddb8cd5e7df 376
AndyA 0:bddb8cd5e7df 377 // Interrupt
AndyA 0:bddb8cd5e7df 378 InterruptIn irq; // Pin used to handle Events from DW1000 by an Interrupthandler
AndyA 0:bddb8cd5e7df 379 FunctionPointer callbackRX; // function pointer to callback which is called when successfull RX took place
AndyA 0:bddb8cd5e7df 380 FunctionPointer callbackTX; // function pointer to callback which is called when successfull TX took place
AndyA 0:bddb8cd5e7df 381 void ISR(); // interrupt handling method (also calls according callback methods)
AndyA 0:bddb8cd5e7df 382
AndyA 0:bddb8cd5e7df 383 // SPI Inteface
AndyA 0:bddb8cd5e7df 384 SPI spi; // SPI Bus
AndyA 0:bddb8cd5e7df 385 DigitalOut cs; // Slave selector for SPI-Bus (here explicitly needed to start and end SPI transactions also usable to wake up DW1000)
AndyA 0:bddb8cd5e7df 386
AndyA 0:bddb8cd5e7df 387 uint8_t readRegister8(uint8_t reg, uint16_t subaddress); // expressive methods to read or write the number of bits written in the name
AndyA 0:bddb8cd5e7df 388 uint16_t readRegister16(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 389 uint32_t readRegister32(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 390 uint64_t readRegister40(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 391 uint64_t readRegister64(uint8_t reg, uint16_t subaddress);
AndyA 0:bddb8cd5e7df 392 void writeRegister8(uint8_t reg, uint16_t subaddress, uint8_t buffer);
AndyA 0:bddb8cd5e7df 393 void writeRegister16(uint8_t reg, uint16_t subaddress, uint16_t buffer);
AndyA 0:bddb8cd5e7df 394 void writeRegister32(uint8_t reg, uint16_t subaddress, uint32_t buffer);
AndyA 0:bddb8cd5e7df 395 void writeRegister40(uint8_t reg, uint16_t subaddress, uint64_t buffer);
AndyA 0:bddb8cd5e7df 396
AndyA 0:bddb8cd5e7df 397 void readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // reads the selected part of a slave register into the buffer memory
AndyA 0:bddb8cd5e7df 398 void writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // writes the buffer memory to the selected slave register
AndyA 0:bddb8cd5e7df 399 void setupTransaction(uint8_t reg, uint16_t subaddress, bool write); // sets up an SPI read or write transaction with correct register address and offset
AndyA 0:bddb8cd5e7df 400 void select(); // selects the only slave for a transaction
AndyA 0:bddb8cd5e7df 401 void deselect(); // deselects the only slave after transaction
AndyA 0:bddb8cd5e7df 402 };
AndyA 0:bddb8cd5e7df 403
AndyA 0:bddb8cd5e7df 404 #endif