DW1000 UWB driver based on work of Matthias Grob & Manuel Stalder - ETH Zürich - 2015
DW1000.cpp@3:1459d2aa6b97, 2016-04-07 (annotated)
- Committer:
- AndyA
- Date:
- Thu Apr 07 14:31:28 2016 +0000
- Revision:
- 3:1459d2aa6b97
- Parent:
- 1:dcbd071f38d5
- Child:
- 4:5f1025df5530
Simplified system config.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AndyA | 0:bddb8cd5e7df | 1 | #include "DW1000.h" |
AndyA | 0:bddb8cd5e7df | 2 | |
AndyA | 0:bddb8cd5e7df | 3 | #define SPIRATE_PLL (5*1000*1000) |
AndyA | 0:bddb8cd5e7df | 4 | #define SPIRATE_OSC (2*1000*1000) |
AndyA | 0:bddb8cd5e7df | 5 | |
AndyA | 0:bddb8cd5e7df | 6 | DW1000::DW1000(UWBMode setup, PinName MOSI, PinName MISO, PinName SCLK, PinName CS, PinName IRQ) : irq(IRQ), spi(MOSI, MISO, SCLK), cs(CS) |
AndyA | 0:bddb8cd5e7df | 7 | { |
AndyA | 0:bddb8cd5e7df | 8 | setCallbacks(NULL, NULL); |
AndyA | 0:bddb8cd5e7df | 9 | |
AndyA | 0:bddb8cd5e7df | 10 | deselect(); // Chip must be deselected first |
AndyA | 0:bddb8cd5e7df | 11 | spi.format(8,0); // Setup the spi for standard 8 bit data and SPI-Mode 0 (GPIO5, GPIO6 open circuit or ground on DW1000) |
AndyA | 0:bddb8cd5e7df | 12 | spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test) |
AndyA | 0:bddb8cd5e7df | 13 | |
AndyA | 0:bddb8cd5e7df | 14 | resetAll(); // we do a soft reset of the DW1000 everytime the driver starts |
AndyA | 0:bddb8cd5e7df | 15 | |
AndyA | 0:bddb8cd5e7df | 16 | switch (setup) { |
AndyA | 0:bddb8cd5e7df | 17 | case user110k: // values from Matthias Grob & Manuel Stalder - ETH Zürich - library |
AndyA | 0:bddb8cd5e7df | 18 | |
AndyA | 3:1459d2aa6b97 | 19 | systemConfig.channel = 5; |
AndyA | 3:1459d2aa6b97 | 20 | systemConfig.prf = prf16MHz; |
AndyA | 3:1459d2aa6b97 | 21 | systemConfig.dataRate = kbps110; |
AndyA | 3:1459d2aa6b97 | 22 | systemConfig.sfd = standard; |
AndyA | 3:1459d2aa6b97 | 23 | systemConfig.preamble = pre1024; |
AndyA | 3:1459d2aa6b97 | 24 | systemConfig.preambleCode = 3; |
AndyA | 3:1459d2aa6b97 | 25 | systemConfig.enableSmartPower = true; |
AndyA | 0:bddb8cd5e7df | 26 | |
AndyA | 3:1459d2aa6b97 | 27 | setupRadio(); |
AndyA | 0:bddb8cd5e7df | 28 | |
AndyA | 3:1459d2aa6b97 | 29 | setTxPower(230); // power = 23dB gain |
AndyA | 0:bddb8cd5e7df | 30 | |
AndyA | 3:1459d2aa6b97 | 31 | setRxDelay(1<<14); // set delays to 2^14 (1/4 of max) |
AndyA | 3:1459d2aa6b97 | 32 | setTxDelay(1<<14); |
AndyA | 0:bddb8cd5e7df | 33 | break; |
AndyA | 0:bddb8cd5e7df | 34 | |
AndyA | 0:bddb8cd5e7df | 35 | case tunedDefault: // User Manual "2.5.5 Default Configurations that should be modified" p. 22 |
AndyA | 3:1459d2aa6b97 | 36 | default: |
AndyA | 3:1459d2aa6b97 | 37 | |
AndyA | 3:1459d2aa6b97 | 38 | systemConfig.channel = 5; |
AndyA | 3:1459d2aa6b97 | 39 | systemConfig.prf = prf16MHz; |
AndyA | 3:1459d2aa6b97 | 40 | systemConfig.dataRate = kbps6800; |
AndyA | 3:1459d2aa6b97 | 41 | systemConfig.sfd = standard; |
AndyA | 3:1459d2aa6b97 | 42 | systemConfig.preamble = pre128; |
AndyA | 3:1459d2aa6b97 | 43 | systemConfig.preambleCode = 3; |
AndyA | 3:1459d2aa6b97 | 44 | systemConfig.enableSmartPower = false;; |
AndyA | 3:1459d2aa6b97 | 45 | |
AndyA | 3:1459d2aa6b97 | 46 | setupRadio(); |
AndyA | 0:bddb8cd5e7df | 47 | |
AndyA | 3:1459d2aa6b97 | 48 | setTxPower(230,260,290); // power = 23dB gain |
AndyA | 3:1459d2aa6b97 | 49 | setRxDelay(0); |
AndyA | 3:1459d2aa6b97 | 50 | setTxDelay(0); |
AndyA | 0:bddb8cd5e7df | 51 | |
AndyA | 3:1459d2aa6b97 | 52 | break; |
AndyA | 3:1459d2aa6b97 | 53 | case minPacketSize: |
AndyA | 3:1459d2aa6b97 | 54 | systemConfig.channel = 5; |
AndyA | 3:1459d2aa6b97 | 55 | systemConfig.prf = prf16MHz; |
AndyA | 3:1459d2aa6b97 | 56 | systemConfig.dataRate = kbps6800; |
AndyA | 3:1459d2aa6b97 | 57 | systemConfig.sfd = standard; |
AndyA | 3:1459d2aa6b97 | 58 | systemConfig.preamble = pre64; |
AndyA | 3:1459d2aa6b97 | 59 | systemConfig.preambleCode = 3; |
AndyA | 3:1459d2aa6b97 | 60 | systemConfig.enableSmartPower = true;; |
AndyA | 0:bddb8cd5e7df | 61 | |
AndyA | 3:1459d2aa6b97 | 62 | setupRadio(); |
AndyA | 3:1459d2aa6b97 | 63 | uint16_t txPower = 25*10; // 25dB gain. |
AndyA | 3:1459d2aa6b97 | 64 | // 3 packets per ms max. So can increase TX power of 250us packets by 10log(4/3) dB and 125us packets by 10log(8/3) dB |
AndyA | 3:1459d2aa6b97 | 65 | setTxPower(txPower,txPower,txPower+15,txPower+45); // power = 23dB gain |
AndyA | 0:bddb8cd5e7df | 66 | |
AndyA | 0:bddb8cd5e7df | 67 | setRxDelay(0); |
AndyA | 0:bddb8cd5e7df | 68 | setTxDelay(0); |
AndyA | 0:bddb8cd5e7df | 69 | |
AndyA | 0:bddb8cd5e7df | 70 | break; |
AndyA | 0:bddb8cd5e7df | 71 | } |
AndyA | 0:bddb8cd5e7df | 72 | |
AndyA | 0:bddb8cd5e7df | 73 | writeRegister8(DW1000_SYS_CFG, 3, 0x20); // enable auto reenabling receiver after error |
AndyA | 0:bddb8cd5e7df | 74 | |
AndyA | 0:bddb8cd5e7df | 75 | irq.rise(this, &DW1000::ISR); // attach interrupt handler to rising edge of interrupt pin from DW1000 |
AndyA | 0:bddb8cd5e7df | 76 | } |
AndyA | 0:bddb8cd5e7df | 77 | |
AndyA | 3:1459d2aa6b97 | 78 | void DW1000::setupRadio() |
AndyA | 3:1459d2aa6b97 | 79 | { |
AndyA | 3:1459d2aa6b97 | 80 | setupAGC(); |
AndyA | 3:1459d2aa6b97 | 81 | setupRxConfig(); |
AndyA | 3:1459d2aa6b97 | 82 | setupLDE(); |
AndyA | 3:1459d2aa6b97 | 83 | setupChannel(); |
AndyA | 3:1459d2aa6b97 | 84 | setupAnalogRF(); |
AndyA | 3:1459d2aa6b97 | 85 | setupFreqSynth(); |
AndyA | 3:1459d2aa6b97 | 86 | setupTxCalibration(); |
AndyA | 3:1459d2aa6b97 | 87 | setupTxFrameCtrl(); |
AndyA | 3:1459d2aa6b97 | 88 | setupSystemConfig(); |
AndyA | 3:1459d2aa6b97 | 89 | |
AndyA | 3:1459d2aa6b97 | 90 | } |
AndyA | 3:1459d2aa6b97 | 91 | |
AndyA | 3:1459d2aa6b97 | 92 | void DW1000::setupAGC() |
AndyA | 3:1459d2aa6b97 | 93 | { |
AndyA | 3:1459d2aa6b97 | 94 | |
AndyA | 3:1459d2aa6b97 | 95 | writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_CTRL1, 0x0001); |
AndyA | 3:1459d2aa6b97 | 96 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 97 | writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE1, 0x8870); |
AndyA | 3:1459d2aa6b97 | 98 | else |
AndyA | 3:1459d2aa6b97 | 99 | writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE1, 0x889B); |
AndyA | 3:1459d2aa6b97 | 100 | |
AndyA | 3:1459d2aa6b97 | 101 | writeRegister32(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE2, 0x2502A907); |
AndyA | 3:1459d2aa6b97 | 102 | writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE3, 0x0035); |
AndyA | 3:1459d2aa6b97 | 103 | } |
AndyA | 3:1459d2aa6b97 | 104 | |
AndyA | 3:1459d2aa6b97 | 105 | void DW1000::setupSystemConfig() |
AndyA | 3:1459d2aa6b97 | 106 | { |
AndyA | 3:1459d2aa6b97 | 107 | uint32_t valueToUse = 0; |
AndyA | 3:1459d2aa6b97 | 108 | valueToUse |= 1<<9; // IRQ output is active high (default) |
AndyA | 3:1459d2aa6b97 | 109 | valueToUse |= 1<<12; // Disable double buffered Rx (default) |
AndyA | 3:1459d2aa6b97 | 110 | |
AndyA | 3:1459d2aa6b97 | 111 | // valueToUse |= 3<<16; // enable long (>125bytes data) packets |
AndyA | 3:1459d2aa6b97 | 112 | |
AndyA | 3:1459d2aa6b97 | 113 | if (!systemConfig.enableSmartPower) |
AndyA | 3:1459d2aa6b97 | 114 | valueToUse |= 1<<18; // disable smart power |
AndyA | 3:1459d2aa6b97 | 115 | |
AndyA | 3:1459d2aa6b97 | 116 | if (systemConfig.dataRate == kbps110) |
AndyA | 3:1459d2aa6b97 | 117 | valueToUse |= 1<<22; |
AndyA | 3:1459d2aa6b97 | 118 | |
AndyA | 3:1459d2aa6b97 | 119 | writeRegister8(DW1000_SYS_CFG, 0, valueToUse); |
AndyA | 3:1459d2aa6b97 | 120 | } |
AndyA | 3:1459d2aa6b97 | 121 | |
AndyA | 3:1459d2aa6b97 | 122 | void DW1000::setupRxConfig() |
AndyA | 3:1459d2aa6b97 | 123 | { |
AndyA | 3:1459d2aa6b97 | 124 | |
AndyA | 3:1459d2aa6b97 | 125 | switch (systemConfig.dataRate) { |
AndyA | 3:1459d2aa6b97 | 126 | case kbps110: |
AndyA | 3:1459d2aa6b97 | 127 | if (systemConfig.sfd == standard) |
AndyA | 3:1459d2aa6b97 | 128 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x000A); |
AndyA | 3:1459d2aa6b97 | 129 | else |
AndyA | 3:1459d2aa6b97 | 130 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0016); |
AndyA | 3:1459d2aa6b97 | 131 | break; |
AndyA | 3:1459d2aa6b97 | 132 | case kbps850: |
AndyA | 3:1459d2aa6b97 | 133 | if (systemConfig.sfd == standard) |
AndyA | 3:1459d2aa6b97 | 134 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0001); |
AndyA | 3:1459d2aa6b97 | 135 | else |
AndyA | 3:1459d2aa6b97 | 136 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0006); |
AndyA | 3:1459d2aa6b97 | 137 | break; |
AndyA | 3:1459d2aa6b97 | 138 | case kbps6800: |
AndyA | 3:1459d2aa6b97 | 139 | default: |
AndyA | 3:1459d2aa6b97 | 140 | if (systemConfig.sfd == standard) |
AndyA | 3:1459d2aa6b97 | 141 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0001); |
AndyA | 3:1459d2aa6b97 | 142 | else |
AndyA | 3:1459d2aa6b97 | 143 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0002); |
AndyA | 3:1459d2aa6b97 | 144 | break; |
AndyA | 3:1459d2aa6b97 | 145 | } |
AndyA | 3:1459d2aa6b97 | 146 | |
AndyA | 3:1459d2aa6b97 | 147 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 148 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1A, 0x0087); //DRX_TUNE1a for 16MHz PRF |
AndyA | 3:1459d2aa6b97 | 149 | else |
AndyA | 3:1459d2aa6b97 | 150 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1A, 0x008D); |
AndyA | 3:1459d2aa6b97 | 151 | |
AndyA | 3:1459d2aa6b97 | 152 | switch (systemConfig.preamble) { |
AndyA | 3:1459d2aa6b97 | 153 | case pre1536: |
AndyA | 3:1459d2aa6b97 | 154 | case pre2048: |
AndyA | 3:1459d2aa6b97 | 155 | case pre4096: |
AndyA | 3:1459d2aa6b97 | 156 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0064); //DRX_TUNE1b for 110kbps & > 1024 symbols |
AndyA | 3:1459d2aa6b97 | 157 | break; |
AndyA | 3:1459d2aa6b97 | 158 | default: // 128 to 1024 |
AndyA | 3:1459d2aa6b97 | 159 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0020); //DRX_TUNE1b for 128- 1024 symbols |
AndyA | 3:1459d2aa6b97 | 160 | break; |
AndyA | 3:1459d2aa6b97 | 161 | case pre64: |
AndyA | 3:1459d2aa6b97 | 162 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0010); //DRX_TUNE1b for 64 symbols |
AndyA | 3:1459d2aa6b97 | 163 | break; |
AndyA | 3:1459d2aa6b97 | 164 | } |
AndyA | 3:1459d2aa6b97 | 165 | |
AndyA | 3:1459d2aa6b97 | 166 | switch (systemConfig.preamble) { |
AndyA | 3:1459d2aa6b97 | 167 | case pre64: |
AndyA | 3:1459d2aa6b97 | 168 | case pre128: // PAC = 8 |
AndyA | 3:1459d2aa6b97 | 169 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 170 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x311A002D); //DRX_TUNE2 PAC 8 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 171 | else |
AndyA | 3:1459d2aa6b97 | 172 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x313B006B); //DRX_TUNE2 PAC 8 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 173 | break; |
AndyA | 3:1459d2aa6b97 | 174 | case pre256: |
AndyA | 3:1459d2aa6b97 | 175 | case pre512: |
AndyA | 3:1459d2aa6b97 | 176 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 177 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x331A0052); //DRX_TUNE2 PAC 16 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 178 | else |
AndyA | 3:1459d2aa6b97 | 179 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x333B00BE); //DRX_TUNE2 PAC 16 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 180 | break; |
AndyA | 3:1459d2aa6b97 | 181 | case pre1024: |
AndyA | 3:1459d2aa6b97 | 182 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 183 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x351A009A); //DRX_TUNE2 PAC 32 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 184 | else |
AndyA | 3:1459d2aa6b97 | 185 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x353B015E); //DRX_TUNE2 PAC 32 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 186 | break; |
AndyA | 3:1459d2aa6b97 | 187 | case pre1536: |
AndyA | 3:1459d2aa6b97 | 188 | case pre2048: |
AndyA | 3:1459d2aa6b97 | 189 | case pre4096: |
AndyA | 3:1459d2aa6b97 | 190 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 191 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x371A011D); //DRX_TUNE2 PAC 64 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 192 | else |
AndyA | 3:1459d2aa6b97 | 193 | writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x373B0296); //DRX_TUNE2 PAC 64 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 194 | break; |
AndyA | 3:1459d2aa6b97 | 195 | } |
AndyA | 3:1459d2aa6b97 | 196 | |
AndyA | 3:1459d2aa6b97 | 197 | |
AndyA | 3:1459d2aa6b97 | 198 | if (systemConfig.preamble == pre64) |
AndyA | 3:1459d2aa6b97 | 199 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE4H, 0x0010); |
AndyA | 3:1459d2aa6b97 | 200 | else |
AndyA | 3:1459d2aa6b97 | 201 | writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE4H, 0x0028); |
AndyA | 3:1459d2aa6b97 | 202 | |
AndyA | 3:1459d2aa6b97 | 203 | } |
AndyA | 3:1459d2aa6b97 | 204 | |
AndyA | 3:1459d2aa6b97 | 205 | |
AndyA | 3:1459d2aa6b97 | 206 | void DW1000::setupLDE() |
AndyA | 3:1459d2aa6b97 | 207 | { |
AndyA | 3:1459d2aa6b97 | 208 | |
AndyA | 3:1459d2aa6b97 | 209 | writeRegister8 (DW1000_LDE_CTRL, DWLDE_LDE_CFG1, 0x13 | 0x03<<5); //NTM = 13 (12 may be better in some situations. PMULT = 3 |
AndyA | 3:1459d2aa6b97 | 210 | |
AndyA | 3:1459d2aa6b97 | 211 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 212 | writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_CFG2, 0x1607); //LDE_CFG2 for 16MHz PRF |
AndyA | 3:1459d2aa6b97 | 213 | else |
AndyA | 3:1459d2aa6b97 | 214 | writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_CFG2, 0x0607); //LDE_CFG2 for 64MHz PRF |
AndyA | 3:1459d2aa6b97 | 215 | |
AndyA | 3:1459d2aa6b97 | 216 | uint16_t replicaCoeff; |
AndyA | 3:1459d2aa6b97 | 217 | switch (systemConfig.preambleCode) { |
AndyA | 3:1459d2aa6b97 | 218 | default: |
AndyA | 3:1459d2aa6b97 | 219 | case 1: |
AndyA | 3:1459d2aa6b97 | 220 | case 2: |
AndyA | 3:1459d2aa6b97 | 221 | replicaCoeff = 0x5998; |
AndyA | 3:1459d2aa6b97 | 222 | break; |
AndyA | 3:1459d2aa6b97 | 223 | case 3: |
AndyA | 3:1459d2aa6b97 | 224 | replicaCoeff = 0x51EA; |
AndyA | 3:1459d2aa6b97 | 225 | break; |
AndyA | 3:1459d2aa6b97 | 226 | case 4: |
AndyA | 3:1459d2aa6b97 | 227 | replicaCoeff = 0x428E; |
AndyA | 3:1459d2aa6b97 | 228 | break; |
AndyA | 3:1459d2aa6b97 | 229 | case 5: |
AndyA | 3:1459d2aa6b97 | 230 | replicaCoeff = 0x451E; |
AndyA | 3:1459d2aa6b97 | 231 | break; |
AndyA | 3:1459d2aa6b97 | 232 | case 6: |
AndyA | 3:1459d2aa6b97 | 233 | replicaCoeff = 0x2E14; |
AndyA | 3:1459d2aa6b97 | 234 | break; |
AndyA | 3:1459d2aa6b97 | 235 | case 7: |
AndyA | 3:1459d2aa6b97 | 236 | replicaCoeff = 0x8000; |
AndyA | 3:1459d2aa6b97 | 237 | break; |
AndyA | 3:1459d2aa6b97 | 238 | case 8: |
AndyA | 3:1459d2aa6b97 | 239 | replicaCoeff = 0x51EA; |
AndyA | 3:1459d2aa6b97 | 240 | break; |
AndyA | 3:1459d2aa6b97 | 241 | case 9: |
AndyA | 3:1459d2aa6b97 | 242 | replicaCoeff = 0x28F4; |
AndyA | 3:1459d2aa6b97 | 243 | break; |
AndyA | 3:1459d2aa6b97 | 244 | case 10: |
AndyA | 3:1459d2aa6b97 | 245 | replicaCoeff = 0x3332; |
AndyA | 3:1459d2aa6b97 | 246 | break; |
AndyA | 3:1459d2aa6b97 | 247 | case 11: |
AndyA | 3:1459d2aa6b97 | 248 | replicaCoeff = 0x3AE0; |
AndyA | 3:1459d2aa6b97 | 249 | break; |
AndyA | 3:1459d2aa6b97 | 250 | case 12: |
AndyA | 3:1459d2aa6b97 | 251 | replicaCoeff = 0x3D70; |
AndyA | 3:1459d2aa6b97 | 252 | break; |
AndyA | 3:1459d2aa6b97 | 253 | case 13: |
AndyA | 3:1459d2aa6b97 | 254 | replicaCoeff = 0x3AE0; |
AndyA | 3:1459d2aa6b97 | 255 | break; |
AndyA | 3:1459d2aa6b97 | 256 | case 14: |
AndyA | 3:1459d2aa6b97 | 257 | replicaCoeff = 0x35C2; |
AndyA | 3:1459d2aa6b97 | 258 | break; |
AndyA | 3:1459d2aa6b97 | 259 | case 15: |
AndyA | 3:1459d2aa6b97 | 260 | replicaCoeff = 0x2B84; |
AndyA | 3:1459d2aa6b97 | 261 | break; |
AndyA | 3:1459d2aa6b97 | 262 | case 16: |
AndyA | 3:1459d2aa6b97 | 263 | replicaCoeff = 0x35C2; |
AndyA | 3:1459d2aa6b97 | 264 | break; |
AndyA | 3:1459d2aa6b97 | 265 | case 17: |
AndyA | 3:1459d2aa6b97 | 266 | replicaCoeff = 0x3332; |
AndyA | 3:1459d2aa6b97 | 267 | break; |
AndyA | 3:1459d2aa6b97 | 268 | case 18: |
AndyA | 3:1459d2aa6b97 | 269 | replicaCoeff = 0x35C2; |
AndyA | 3:1459d2aa6b97 | 270 | break; |
AndyA | 3:1459d2aa6b97 | 271 | case 19: |
AndyA | 3:1459d2aa6b97 | 272 | replicaCoeff = 0x35C2; |
AndyA | 3:1459d2aa6b97 | 273 | break; |
AndyA | 3:1459d2aa6b97 | 274 | case 20: |
AndyA | 3:1459d2aa6b97 | 275 | replicaCoeff = 0x47AE; |
AndyA | 3:1459d2aa6b97 | 276 | break; |
AndyA | 3:1459d2aa6b97 | 277 | case 21: |
AndyA | 3:1459d2aa6b97 | 278 | replicaCoeff = 0x3AE0; |
AndyA | 3:1459d2aa6b97 | 279 | break; |
AndyA | 3:1459d2aa6b97 | 280 | case 22: |
AndyA | 3:1459d2aa6b97 | 281 | replicaCoeff = 0x3850; |
AndyA | 3:1459d2aa6b97 | 282 | break; |
AndyA | 3:1459d2aa6b97 | 283 | case 23: |
AndyA | 3:1459d2aa6b97 | 284 | replicaCoeff = 0x30A2; |
AndyA | 3:1459d2aa6b97 | 285 | break; |
AndyA | 3:1459d2aa6b97 | 286 | case 24: |
AndyA | 3:1459d2aa6b97 | 287 | replicaCoeff = 0x3850; |
AndyA | 3:1459d2aa6b97 | 288 | break; |
AndyA | 3:1459d2aa6b97 | 289 | } |
AndyA | 3:1459d2aa6b97 | 290 | |
AndyA | 3:1459d2aa6b97 | 291 | if (systemConfig.dataRate == kbps110) |
AndyA | 3:1459d2aa6b97 | 292 | replicaCoeff = replicaCoeff>>3; |
AndyA | 3:1459d2aa6b97 | 293 | |
AndyA | 3:1459d2aa6b97 | 294 | writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_REPC, replicaCoeff); |
AndyA | 3:1459d2aa6b97 | 295 | |
AndyA | 3:1459d2aa6b97 | 296 | loadLDE(); |
AndyA | 3:1459d2aa6b97 | 297 | } |
AndyA | 3:1459d2aa6b97 | 298 | |
AndyA | 3:1459d2aa6b97 | 299 | void DW1000::setupChannel() |
AndyA | 3:1459d2aa6b97 | 300 | { |
AndyA | 3:1459d2aa6b97 | 301 | uint16_t registerValue = 0; |
AndyA | 3:1459d2aa6b97 | 302 | |
AndyA | 3:1459d2aa6b97 | 303 | registerValue = systemConfig.channel; // set Tx channel |
AndyA | 3:1459d2aa6b97 | 304 | registerValue |= systemConfig.channel<<4; // set Rx channel |
AndyA | 3:1459d2aa6b97 | 305 | |
AndyA | 3:1459d2aa6b97 | 306 | if ( systemConfig.prf == prf16MHz) // set PRF (2 bit value 01 or 10) |
AndyA | 3:1459d2aa6b97 | 307 | registerValue |= 0x01 << 18; |
AndyA | 3:1459d2aa6b97 | 308 | else |
AndyA | 3:1459d2aa6b97 | 309 | registerValue |= 0x02 << 18; |
AndyA | 3:1459d2aa6b97 | 310 | |
AndyA | 3:1459d2aa6b97 | 311 | if (systemConfig.sfd == nonStandard) { |
AndyA | 3:1459d2aa6b97 | 312 | registerValue |= 0x01 << 17; // enable DW own SFD |
AndyA | 3:1459d2aa6b97 | 313 | // registerValue |= 0x01 << 20; // enable user set SFD Tx |
AndyA | 3:1459d2aa6b97 | 314 | // registerValue |= 0x01 << 21; // enable user set SFD Rx |
AndyA | 3:1459d2aa6b97 | 315 | } |
AndyA | 3:1459d2aa6b97 | 316 | |
AndyA | 3:1459d2aa6b97 | 317 | registerValue |= systemConfig.preambleCode << 22; // set Tx preamble code |
AndyA | 3:1459d2aa6b97 | 318 | registerValue |= systemConfig.preambleCode << 27; // set Rx preamble code |
AndyA | 3:1459d2aa6b97 | 319 | |
AndyA | 3:1459d2aa6b97 | 320 | writeRegister16(DW1000_CHAN_CTRL, 0, registerValue); |
AndyA | 3:1459d2aa6b97 | 321 | } |
AndyA | 3:1459d2aa6b97 | 322 | |
AndyA | 3:1459d2aa6b97 | 323 | |
AndyA | 3:1459d2aa6b97 | 324 | uint8_t DW1000::powerToRegValue(uint16_t powercB) |
AndyA | 3:1459d2aa6b97 | 325 | { |
AndyA | 3:1459d2aa6b97 | 326 | |
AndyA | 3:1459d2aa6b97 | 327 | // course power control - 0 = 18dB, 6 = 0dB in 3dB steps. |
AndyA | 3:1459d2aa6b97 | 328 | uint8_t course = powercB / 30; |
AndyA | 3:1459d2aa6b97 | 329 | |
AndyA | 3:1459d2aa6b97 | 330 | if(course > 6) |
AndyA | 3:1459d2aa6b97 | 331 | course = 6; |
AndyA | 3:1459d2aa6b97 | 332 | |
AndyA | 3:1459d2aa6b97 | 333 | // remaining power |
AndyA | 3:1459d2aa6b97 | 334 | powercB -= course * 30; |
AndyA | 3:1459d2aa6b97 | 335 | |
AndyA | 3:1459d2aa6b97 | 336 | // value in reg is inverse. |
AndyA | 3:1459d2aa6b97 | 337 | course = 6-course; |
AndyA | 3:1459d2aa6b97 | 338 | |
AndyA | 3:1459d2aa6b97 | 339 | // fine control in steps of 0.5dB |
AndyA | 3:1459d2aa6b97 | 340 | uint8_t fine = powercB / 5; |
AndyA | 3:1459d2aa6b97 | 341 | if (fine > 31) |
AndyA | 3:1459d2aa6b97 | 342 | fine = 31; |
AndyA | 3:1459d2aa6b97 | 343 | |
AndyA | 3:1459d2aa6b97 | 344 | |
AndyA | 3:1459d2aa6b97 | 345 | return (course << 5) | fine; |
AndyA | 3:1459d2aa6b97 | 346 | |
AndyA | 3:1459d2aa6b97 | 347 | } |
AndyA | 3:1459d2aa6b97 | 348 | |
AndyA | 3:1459d2aa6b97 | 349 | // transmit power: 0 to 33.5 dB gain in steps of 0.5. Inputs are in 10ths of a dB (0 to 335) |
AndyA | 3:1459d2aa6b97 | 350 | void DW1000::setTxPower(uint16_t normalPowercB, uint16_t boost500, uint16_t boost250, uint16_t boost125) |
AndyA | 3:1459d2aa6b97 | 351 | { |
AndyA | 3:1459d2aa6b97 | 352 | if(normalPowercB > 335) |
AndyA | 3:1459d2aa6b97 | 353 | normalPowercB = 335; |
AndyA | 3:1459d2aa6b97 | 354 | |
AndyA | 3:1459d2aa6b97 | 355 | if (boost500 < normalPowercB) |
AndyA | 3:1459d2aa6b97 | 356 | boost500 = normalPowercB; |
AndyA | 3:1459d2aa6b97 | 357 | if(boost500 > 335) |
AndyA | 3:1459d2aa6b97 | 358 | boost500 = 335; |
AndyA | 3:1459d2aa6b97 | 359 | |
AndyA | 3:1459d2aa6b97 | 360 | if (boost250 < boost500) |
AndyA | 3:1459d2aa6b97 | 361 | boost250 = boost500; |
AndyA | 3:1459d2aa6b97 | 362 | if(boost250 > 335) |
AndyA | 3:1459d2aa6b97 | 363 | boost250 = 335; |
AndyA | 3:1459d2aa6b97 | 364 | |
AndyA | 3:1459d2aa6b97 | 365 | if (boost125 < boost250) |
AndyA | 3:1459d2aa6b97 | 366 | boost125 = boost250; |
AndyA | 3:1459d2aa6b97 | 367 | if(boost125 > 335) |
AndyA | 3:1459d2aa6b97 | 368 | boost125 = 335; |
AndyA | 3:1459d2aa6b97 | 369 | |
AndyA | 3:1459d2aa6b97 | 370 | uint32_t powerReg = powerToRegValue(normalPowercB); |
AndyA | 3:1459d2aa6b97 | 371 | powerReg |= powerToRegValue(boost500) << 8; |
AndyA | 3:1459d2aa6b97 | 372 | powerReg |= powerToRegValue(boost250) << 16; |
AndyA | 3:1459d2aa6b97 | 373 | powerReg |= powerToRegValue(boost125) << 24; |
AndyA | 3:1459d2aa6b97 | 374 | } |
AndyA | 3:1459d2aa6b97 | 375 | |
AndyA | 3:1459d2aa6b97 | 376 | void DW1000::setupAnalogRF() |
AndyA | 3:1459d2aa6b97 | 377 | { |
AndyA | 3:1459d2aa6b97 | 378 | switch (systemConfig.channel) { |
AndyA | 3:1459d2aa6b97 | 379 | case 1: |
AndyA | 3:1459d2aa6b97 | 380 | writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00005C40); |
AndyA | 3:1459d2aa6b97 | 381 | break; |
AndyA | 3:1459d2aa6b97 | 382 | case 2: |
AndyA | 3:1459d2aa6b97 | 383 | writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00045CA0); |
AndyA | 3:1459d2aa6b97 | 384 | break; |
AndyA | 3:1459d2aa6b97 | 385 | case 3: |
AndyA | 3:1459d2aa6b97 | 386 | writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00086CC0); |
AndyA | 3:1459d2aa6b97 | 387 | break; |
AndyA | 3:1459d2aa6b97 | 388 | case 4: |
AndyA | 3:1459d2aa6b97 | 389 | writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00045C80); |
AndyA | 3:1459d2aa6b97 | 390 | break; |
AndyA | 3:1459d2aa6b97 | 391 | case 5: |
AndyA | 3:1459d2aa6b97 | 392 | default: |
AndyA | 3:1459d2aa6b97 | 393 | writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x001E3FE0); |
AndyA | 3:1459d2aa6b97 | 394 | break; |
AndyA | 3:1459d2aa6b97 | 395 | case 7: |
AndyA | 3:1459d2aa6b97 | 396 | writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x001E7DE0); |
AndyA | 3:1459d2aa6b97 | 397 | break; |
AndyA | 3:1459d2aa6b97 | 398 | } |
AndyA | 3:1459d2aa6b97 | 399 | |
AndyA | 3:1459d2aa6b97 | 400 | switch (systemConfig.channel) { |
AndyA | 3:1459d2aa6b97 | 401 | case 1: |
AndyA | 3:1459d2aa6b97 | 402 | case 2: |
AndyA | 3:1459d2aa6b97 | 403 | case 3: |
AndyA | 3:1459d2aa6b97 | 404 | case 5: |
AndyA | 3:1459d2aa6b97 | 405 | default: |
AndyA | 3:1459d2aa6b97 | 406 | writeRegister8(DW1000_RF_CONF, DWRFCONF_RF_RXCTRLH, 0xD8); |
AndyA | 3:1459d2aa6b97 | 407 | break; |
AndyA | 3:1459d2aa6b97 | 408 | case 4: |
AndyA | 3:1459d2aa6b97 | 409 | case 7: |
AndyA | 3:1459d2aa6b97 | 410 | writeRegister8(DW1000_RF_CONF, DWRFCONF_RF_RXCTRLH, 0xBC); |
AndyA | 3:1459d2aa6b97 | 411 | break; |
AndyA | 3:1459d2aa6b97 | 412 | } |
AndyA | 3:1459d2aa6b97 | 413 | |
AndyA | 3:1459d2aa6b97 | 414 | loadLDOTUNE(); |
AndyA | 3:1459d2aa6b97 | 415 | |
AndyA | 3:1459d2aa6b97 | 416 | } |
AndyA | 3:1459d2aa6b97 | 417 | |
AndyA | 3:1459d2aa6b97 | 418 | void DW1000::setupTxCalibration() |
AndyA | 3:1459d2aa6b97 | 419 | { |
AndyA | 3:1459d2aa6b97 | 420 | switch (systemConfig.channel) { |
AndyA | 3:1459d2aa6b97 | 421 | case 1: |
AndyA | 3:1459d2aa6b97 | 422 | writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC9); |
AndyA | 3:1459d2aa6b97 | 423 | break; |
AndyA | 3:1459d2aa6b97 | 424 | case 2: |
AndyA | 3:1459d2aa6b97 | 425 | writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC2); |
AndyA | 3:1459d2aa6b97 | 426 | break; |
AndyA | 3:1459d2aa6b97 | 427 | case 3: |
AndyA | 3:1459d2aa6b97 | 428 | writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC5); |
AndyA | 3:1459d2aa6b97 | 429 | break; |
AndyA | 3:1459d2aa6b97 | 430 | case 4: |
AndyA | 3:1459d2aa6b97 | 431 | writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0x95); |
AndyA | 3:1459d2aa6b97 | 432 | break; |
AndyA | 3:1459d2aa6b97 | 433 | case 5: |
AndyA | 3:1459d2aa6b97 | 434 | default: |
AndyA | 3:1459d2aa6b97 | 435 | writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC0); |
AndyA | 3:1459d2aa6b97 | 436 | break; |
AndyA | 3:1459d2aa6b97 | 437 | case 7: |
AndyA | 3:1459d2aa6b97 | 438 | writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0x93); |
AndyA | 3:1459d2aa6b97 | 439 | break; |
AndyA | 3:1459d2aa6b97 | 440 | } |
AndyA | 3:1459d2aa6b97 | 441 | } |
AndyA | 3:1459d2aa6b97 | 442 | |
AndyA | 3:1459d2aa6b97 | 443 | void DW1000::setupFreqSynth() |
AndyA | 3:1459d2aa6b97 | 444 | { |
AndyA | 3:1459d2aa6b97 | 445 | |
AndyA | 3:1459d2aa6b97 | 446 | switch (systemConfig.channel) { |
AndyA | 3:1459d2aa6b97 | 447 | case 1: |
AndyA | 3:1459d2aa6b97 | 448 | writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x09000407); //FS_PLLCFG for channel 1 |
AndyA | 3:1459d2aa6b97 | 449 | writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0x1E); |
AndyA | 3:1459d2aa6b97 | 450 | break; |
AndyA | 3:1459d2aa6b97 | 451 | case 2: |
AndyA | 3:1459d2aa6b97 | 452 | case 4: |
AndyA | 3:1459d2aa6b97 | 453 | writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x08400508); //FS_PLLCFG for channel 2,4 |
AndyA | 3:1459d2aa6b97 | 454 | writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0x26); |
AndyA | 3:1459d2aa6b97 | 455 | break; |
AndyA | 3:1459d2aa6b97 | 456 | case 3: |
AndyA | 3:1459d2aa6b97 | 457 | writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x08401009); //FS_PLLCFG for channel 3 |
AndyA | 3:1459d2aa6b97 | 458 | writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0x5E); |
AndyA | 3:1459d2aa6b97 | 459 | break; |
AndyA | 3:1459d2aa6b97 | 460 | case 5: |
AndyA | 3:1459d2aa6b97 | 461 | case 7: |
AndyA | 3:1459d2aa6b97 | 462 | default: |
AndyA | 3:1459d2aa6b97 | 463 | writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x0800041D); //FS_PLLCFG for channel 5,7 |
AndyA | 3:1459d2aa6b97 | 464 | writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0xBE); //FS_PLLTUNE for channel 5 |
AndyA | 3:1459d2aa6b97 | 465 | break; |
AndyA | 3:1459d2aa6b97 | 466 | } |
AndyA | 3:1459d2aa6b97 | 467 | } |
AndyA | 3:1459d2aa6b97 | 468 | |
AndyA | 3:1459d2aa6b97 | 469 | void DW1000::setupTxFrameCtrl() |
AndyA | 3:1459d2aa6b97 | 470 | { |
AndyA | 3:1459d2aa6b97 | 471 | uint16_t frameCtrlValue = 0; |
AndyA | 3:1459d2aa6b97 | 472 | switch (systemConfig.dataRate) { |
AndyA | 3:1459d2aa6b97 | 473 | case kbps110: |
AndyA | 3:1459d2aa6b97 | 474 | break; |
AndyA | 3:1459d2aa6b97 | 475 | case kbps850: |
AndyA | 3:1459d2aa6b97 | 476 | frameCtrlValue |= 0x01<<13; |
AndyA | 3:1459d2aa6b97 | 477 | break; |
AndyA | 3:1459d2aa6b97 | 478 | case kbps6800: |
AndyA | 3:1459d2aa6b97 | 479 | default: |
AndyA | 3:1459d2aa6b97 | 480 | frameCtrlValue |= 0x02<<13; |
AndyA | 3:1459d2aa6b97 | 481 | break; |
AndyA | 3:1459d2aa6b97 | 482 | } |
AndyA | 3:1459d2aa6b97 | 483 | frameCtrlValue |= 0x01<<15; |
AndyA | 3:1459d2aa6b97 | 484 | |
AndyA | 3:1459d2aa6b97 | 485 | if (systemConfig.prf == prf16MHz) |
AndyA | 3:1459d2aa6b97 | 486 | frameCtrlValue |= 0x01<<16; |
AndyA | 3:1459d2aa6b97 | 487 | else |
AndyA | 3:1459d2aa6b97 | 488 | frameCtrlValue |= 0x02<<16; |
AndyA | 3:1459d2aa6b97 | 489 | |
AndyA | 3:1459d2aa6b97 | 490 | switch (systemConfig.preamble) { |
AndyA | 3:1459d2aa6b97 | 491 | case pre64: |
AndyA | 3:1459d2aa6b97 | 492 | frameCtrlValue |= 0x01<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 493 | frameCtrlValue |= 0x00<<20; // PE |
AndyA | 3:1459d2aa6b97 | 494 | break; |
AndyA | 3:1459d2aa6b97 | 495 | case pre128: |
AndyA | 3:1459d2aa6b97 | 496 | default: |
AndyA | 3:1459d2aa6b97 | 497 | frameCtrlValue |= 0x01<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 498 | frameCtrlValue |= 0x01<<20; // PE |
AndyA | 3:1459d2aa6b97 | 499 | break; |
AndyA | 3:1459d2aa6b97 | 500 | case pre256: |
AndyA | 3:1459d2aa6b97 | 501 | frameCtrlValue |= 0x01<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 502 | frameCtrlValue |= 0x02<<20; // PE |
AndyA | 3:1459d2aa6b97 | 503 | break; |
AndyA | 3:1459d2aa6b97 | 504 | case pre512: |
AndyA | 3:1459d2aa6b97 | 505 | frameCtrlValue |= 0x01<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 506 | frameCtrlValue |= 0x03<<20; // PE |
AndyA | 3:1459d2aa6b97 | 507 | break; |
AndyA | 3:1459d2aa6b97 | 508 | case pre1024: |
AndyA | 3:1459d2aa6b97 | 509 | frameCtrlValue |= 0x02<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 510 | frameCtrlValue |= 0x00<<20; // PE |
AndyA | 3:1459d2aa6b97 | 511 | break; |
AndyA | 3:1459d2aa6b97 | 512 | case pre1536: |
AndyA | 3:1459d2aa6b97 | 513 | frameCtrlValue |= 0x02<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 514 | frameCtrlValue |= 0x01<<20; // PE |
AndyA | 3:1459d2aa6b97 | 515 | break; |
AndyA | 3:1459d2aa6b97 | 516 | case pre2048: |
AndyA | 3:1459d2aa6b97 | 517 | frameCtrlValue |= 0x02<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 518 | frameCtrlValue |= 0x02<<20; // PE |
AndyA | 3:1459d2aa6b97 | 519 | break; |
AndyA | 3:1459d2aa6b97 | 520 | case pre4096: |
AndyA | 3:1459d2aa6b97 | 521 | frameCtrlValue |= 0x03<<18; // TXPSR |
AndyA | 3:1459d2aa6b97 | 522 | frameCtrlValue |= 0x00<<20; // PE |
AndyA | 3:1459d2aa6b97 | 523 | break; |
AndyA | 3:1459d2aa6b97 | 524 | } |
AndyA | 3:1459d2aa6b97 | 525 | } |
AndyA | 3:1459d2aa6b97 | 526 | |
AndyA | 0:bddb8cd5e7df | 527 | void DW1000::setRxDelay(uint16_t ticks) |
AndyA | 0:bddb8cd5e7df | 528 | { |
AndyA | 0:bddb8cd5e7df | 529 | writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_RXANTD, ticks); |
AndyA | 0:bddb8cd5e7df | 530 | } |
AndyA | 0:bddb8cd5e7df | 531 | void DW1000::setTxDelay(uint16_t ticks) |
AndyA | 0:bddb8cd5e7df | 532 | { |
AndyA | 0:bddb8cd5e7df | 533 | writeRegister16(DW1000_TX_ANTD, 0, ticks); |
AndyA | 0:bddb8cd5e7df | 534 | } |
AndyA | 0:bddb8cd5e7df | 535 | |
AndyA | 0:bddb8cd5e7df | 536 | void DW1000::setCallbacks(void (*callbackRX)(void), void (*callbackTX)(void)) |
AndyA | 0:bddb8cd5e7df | 537 | { |
AndyA | 0:bddb8cd5e7df | 538 | bool RX = false; |
AndyA | 0:bddb8cd5e7df | 539 | bool TX = false; |
AndyA | 0:bddb8cd5e7df | 540 | if (callbackRX) { |
AndyA | 0:bddb8cd5e7df | 541 | DW1000::callbackRX.attach(callbackRX); |
AndyA | 0:bddb8cd5e7df | 542 | RX = true; |
AndyA | 0:bddb8cd5e7df | 543 | } |
AndyA | 0:bddb8cd5e7df | 544 | if (callbackTX) { |
AndyA | 0:bddb8cd5e7df | 545 | DW1000::callbackTX.attach(callbackTX); |
AndyA | 0:bddb8cd5e7df | 546 | TX = true; |
AndyA | 0:bddb8cd5e7df | 547 | } |
AndyA | 0:bddb8cd5e7df | 548 | setInterrupt(RX,TX); |
AndyA | 0:bddb8cd5e7df | 549 | } |
AndyA | 0:bddb8cd5e7df | 550 | |
AndyA | 0:bddb8cd5e7df | 551 | uint32_t DW1000::getDeviceID() |
AndyA | 0:bddb8cd5e7df | 552 | { |
AndyA | 0:bddb8cd5e7df | 553 | uint32_t result; |
AndyA | 0:bddb8cd5e7df | 554 | readRegister(DW1000_DEV_ID, 0, (uint8_t*)&result, 4); |
AndyA | 0:bddb8cd5e7df | 555 | return result; |
AndyA | 0:bddb8cd5e7df | 556 | } |
AndyA | 0:bddb8cd5e7df | 557 | |
AndyA | 0:bddb8cd5e7df | 558 | uint64_t DW1000::getEUI() |
AndyA | 0:bddb8cd5e7df | 559 | { |
AndyA | 0:bddb8cd5e7df | 560 | uint64_t result; |
AndyA | 0:bddb8cd5e7df | 561 | readRegister(DW1000_EUI, 0, (uint8_t*)&result, 8); |
AndyA | 0:bddb8cd5e7df | 562 | return result; |
AndyA | 0:bddb8cd5e7df | 563 | } |
AndyA | 0:bddb8cd5e7df | 564 | |
AndyA | 0:bddb8cd5e7df | 565 | void DW1000::setEUI(uint64_t EUI) |
AndyA | 0:bddb8cd5e7df | 566 | { |
AndyA | 0:bddb8cd5e7df | 567 | writeRegister(DW1000_EUI, 0, (uint8_t*)&EUI, 8); |
AndyA | 0:bddb8cd5e7df | 568 | } |
AndyA | 0:bddb8cd5e7df | 569 | |
AndyA | 0:bddb8cd5e7df | 570 | |
AndyA | 0:bddb8cd5e7df | 571 | float DW1000::getVoltage() |
AndyA | 0:bddb8cd5e7df | 572 | { |
AndyA | 0:bddb8cd5e7df | 573 | uint8_t data; |
AndyA | 0:bddb8cd5e7df | 574 | |
AndyA | 0:bddb8cd5e7df | 575 | writeRegister8(DW1000_RF_CONF, 0x11, 0x80); |
AndyA | 0:bddb8cd5e7df | 576 | writeRegister8(DW1000_RF_CONF, 0x12, 0x0A); |
AndyA | 0:bddb8cd5e7df | 577 | writeRegister8(DW1000_RF_CONF, 0x12, 0x0F); |
AndyA | 0:bddb8cd5e7df | 578 | writeRegister8(DW1000_TX_CAL, 0x00, 0x01); |
AndyA | 0:bddb8cd5e7df | 579 | writeRegister8(DW1000_TX_CAL, 0x00, 0x00); |
AndyA | 0:bddb8cd5e7df | 580 | data = readRegister8(DW1000_TX_CAL, 0x03); // get the 8-Bit reading for Voltage |
AndyA | 1:dcbd071f38d5 | 581 | float Voltage = (float)(data - (readOTP(0x08)&0x00ff)) *0.00578 + 3.3; |
AndyA | 0:bddb8cd5e7df | 582 | return Voltage; |
AndyA | 0:bddb8cd5e7df | 583 | } |
AndyA | 0:bddb8cd5e7df | 584 | |
AndyA | 0:bddb8cd5e7df | 585 | float DW1000::getTemperature() |
AndyA | 0:bddb8cd5e7df | 586 | { |
AndyA | 0:bddb8cd5e7df | 587 | uint8_t data; |
AndyA | 0:bddb8cd5e7df | 588 | |
AndyA | 0:bddb8cd5e7df | 589 | writeRegister8(DW1000_RF_CONF, 0x11, 0x80); |
AndyA | 0:bddb8cd5e7df | 590 | writeRegister8(DW1000_RF_CONF, 0x12, 0x0A); |
AndyA | 0:bddb8cd5e7df | 591 | writeRegister8(DW1000_RF_CONF, 0x12, 0x0F); |
AndyA | 0:bddb8cd5e7df | 592 | writeRegister8(DW1000_TX_CAL, 0x00, 0x01); |
AndyA | 0:bddb8cd5e7df | 593 | writeRegister8(DW1000_TX_CAL, 0x00, 0x00); |
AndyA | 0:bddb8cd5e7df | 594 | data = readRegister16(DW1000_TX_CAL, 0x04); // get the 8-Bit reading for Temperature |
AndyA | 1:dcbd071f38d5 | 595 | float temperature = (float)(data - (readOTP(0x09) & 0x00ff))*0.9 + 23; |
AndyA | 0:bddb8cd5e7df | 596 | return temperature; |
AndyA | 0:bddb8cd5e7df | 597 | } |
AndyA | 0:bddb8cd5e7df | 598 | |
AndyA | 0:bddb8cd5e7df | 599 | |
AndyA | 0:bddb8cd5e7df | 600 | uint64_t DW1000::getStatus() |
AndyA | 0:bddb8cd5e7df | 601 | { |
AndyA | 0:bddb8cd5e7df | 602 | return readRegister40(DW1000_SYS_STATUS, 0); |
AndyA | 0:bddb8cd5e7df | 603 | } |
AndyA | 0:bddb8cd5e7df | 604 | |
AndyA | 0:bddb8cd5e7df | 605 | uint64_t DW1000::getRXTimestamp() |
AndyA | 0:bddb8cd5e7df | 606 | { |
AndyA | 0:bddb8cd5e7df | 607 | return readRegister40(DW1000_RX_TIME, 0); |
AndyA | 0:bddb8cd5e7df | 608 | } |
AndyA | 0:bddb8cd5e7df | 609 | |
AndyA | 0:bddb8cd5e7df | 610 | uint64_t DW1000::getTXTimestamp() |
AndyA | 0:bddb8cd5e7df | 611 | { |
AndyA | 0:bddb8cd5e7df | 612 | return readRegister40(DW1000_TX_TIME, 0); |
AndyA | 0:bddb8cd5e7df | 613 | } |
AndyA | 0:bddb8cd5e7df | 614 | |
AndyA | 0:bddb8cd5e7df | 615 | void DW1000::sendString(char* message) |
AndyA | 0:bddb8cd5e7df | 616 | { |
AndyA | 0:bddb8cd5e7df | 617 | sendFrame((uint8_t*)message, strlen(message)+1); |
AndyA | 0:bddb8cd5e7df | 618 | } |
AndyA | 0:bddb8cd5e7df | 619 | |
AndyA | 0:bddb8cd5e7df | 620 | void DW1000::receiveString(char* message) |
AndyA | 0:bddb8cd5e7df | 621 | { |
AndyA | 0:bddb8cd5e7df | 622 | readRegister(DW1000_RX_BUFFER, 0, (uint8_t*)message, getFramelength()); // get data from buffer |
AndyA | 0:bddb8cd5e7df | 623 | } |
AndyA | 0:bddb8cd5e7df | 624 | |
AndyA | 0:bddb8cd5e7df | 625 | void DW1000::sendFrame(uint8_t* message, uint16_t length) |
AndyA | 0:bddb8cd5e7df | 626 | { |
AndyA | 0:bddb8cd5e7df | 627 | //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor] |
AndyA | 0:bddb8cd5e7df | 628 | if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames |
AndyA | 0:bddb8cd5e7df | 629 | uint8_t len_7bit = length; |
AndyA | 0:bddb8cd5e7df | 630 | writeRegister(DW1000_TX_BUFFER, 0, message, len_7bit); // fill buffer |
AndyA | 0:bddb8cd5e7df | 631 | |
AndyA | 3:1459d2aa6b97 | 632 | /* support for frames over 127 bytes |
AndyA | 3:1459d2aa6b97 | 633 | uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame |
AndyA | 3:1459d2aa6b97 | 634 | length += 2; // including 2 CRC Bytes |
AndyA | 3:1459d2aa6b97 | 635 | length = ((backup & 0xFC) << 8) | (length & 0x03FF); |
AndyA | 3:1459d2aa6b97 | 636 | writeRegister16(DW1000_TX_FCTRL, 0, length); |
AndyA | 3:1459d2aa6b97 | 637 | */ |
AndyA | 0:bddb8cd5e7df | 638 | len_7bit += 2; // including 2 CRC Bytes |
AndyA | 0:bddb8cd5e7df | 639 | writeRegister8(DW1000_TX_FCTRL, 0, len_7bit); |
AndyA | 0:bddb8cd5e7df | 640 | |
AndyA | 0:bddb8cd5e7df | 641 | stopTRX(); // stop receiving |
AndyA | 0:bddb8cd5e7df | 642 | writeRegister8(DW1000_SYS_CTRL, 0, 0x02 | 0x80); // trigger sending process by setting the TXSTRT bit |
AndyA | 0:bddb8cd5e7df | 643 | // startRX(); // enable receiver again |
AndyA | 0:bddb8cd5e7df | 644 | } |
AndyA | 0:bddb8cd5e7df | 645 | |
AndyA | 3:1459d2aa6b97 | 646 | void DW1000::setupSyncedFrame(uint8_t* message, uint16_t length) |
AndyA | 3:1459d2aa6b97 | 647 | { |
AndyA | 0:bddb8cd5e7df | 648 | //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor] |
AndyA | 0:bddb8cd5e7df | 649 | if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames |
AndyA | 0:bddb8cd5e7df | 650 | writeRegister(DW1000_TX_BUFFER, 0, message, length); // fill buffer |
AndyA | 0:bddb8cd5e7df | 651 | |
AndyA | 0:bddb8cd5e7df | 652 | uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame |
AndyA | 0:bddb8cd5e7df | 653 | length += 2; // including 2 CRC Bytes |
AndyA | 0:bddb8cd5e7df | 654 | length = ((backup & 0xFC) << 8) | (length & 0x03FF); |
AndyA | 0:bddb8cd5e7df | 655 | writeRegister16(DW1000_TX_FCTRL, 0, length); |
AndyA | 0:bddb8cd5e7df | 656 | } |
AndyA | 0:bddb8cd5e7df | 657 | |
AndyA | 3:1459d2aa6b97 | 658 | void DW1000::armSyncedFrame() |
AndyA | 3:1459d2aa6b97 | 659 | { |
AndyA | 0:bddb8cd5e7df | 660 | stopTRX(); // stop receiving |
AndyA | 0:bddb8cd5e7df | 661 | writeRegister16(DW1000_EXT_SYNC, DWEXTSYNC_EC_CTRL, 33<<3 | 0x01); // Sync register = TX start with a wait of 33 (recomended, value must fulfill wait % 4 = 1) |
AndyA | 3:1459d2aa6b97 | 662 | } |
AndyA | 0:bddb8cd5e7df | 663 | |
AndyA | 0:bddb8cd5e7df | 664 | void DW1000::sendDelayedFrame(uint8_t* message, uint16_t length, uint64_t TxTimestamp) |
AndyA | 0:bddb8cd5e7df | 665 | { |
AndyA | 0:bddb8cd5e7df | 666 | //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor] |
AndyA | 0:bddb8cd5e7df | 667 | if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames |
AndyA | 0:bddb8cd5e7df | 668 | writeRegister(DW1000_TX_BUFFER, 0, message, length); // fill buffer |
AndyA | 0:bddb8cd5e7df | 669 | |
AndyA | 0:bddb8cd5e7df | 670 | uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame |
AndyA | 0:bddb8cd5e7df | 671 | length += 2; // including 2 CRC Bytes |
AndyA | 0:bddb8cd5e7df | 672 | length = ((backup & 0xFC) << 8) | (length & 0x03FF); |
AndyA | 0:bddb8cd5e7df | 673 | writeRegister16(DW1000_TX_FCTRL, 0, length); |
AndyA | 0:bddb8cd5e7df | 674 | |
AndyA | 0:bddb8cd5e7df | 675 | writeRegister40(DW1000_DX_TIME, 0, TxTimestamp); //write the timestamp on which to send the message |
AndyA | 0:bddb8cd5e7df | 676 | |
AndyA | 0:bddb8cd5e7df | 677 | stopTRX(); // stop receiving |
AndyA | 0:bddb8cd5e7df | 678 | writeRegister8(DW1000_SYS_CTRL, 0, 0x02 | 0x04 | 0x80); // trigger sending process by setting the TXSTRT and TXDLYS bit. Set Wait4resp to automatically enter RX mode after tx. |
AndyA | 0:bddb8cd5e7df | 679 | } |
AndyA | 0:bddb8cd5e7df | 680 | |
AndyA | 0:bddb8cd5e7df | 681 | void DW1000::startRX() |
AndyA | 0:bddb8cd5e7df | 682 | { |
AndyA | 0:bddb8cd5e7df | 683 | writeRegister8(DW1000_SYS_CTRL, 0x01, 0x01); // start listening for preamble by setting the RXENAB bit |
AndyA | 0:bddb8cd5e7df | 684 | } |
AndyA | 0:bddb8cd5e7df | 685 | |
AndyA | 0:bddb8cd5e7df | 686 | void DW1000::stopTRX() |
AndyA | 0:bddb8cd5e7df | 687 | { |
AndyA | 0:bddb8cd5e7df | 688 | writeRegister8(DW1000_SYS_CTRL, 0, 0x40); // disable tranceiver go back to idle mode |
AndyA | 0:bddb8cd5e7df | 689 | } |
AndyA | 0:bddb8cd5e7df | 690 | |
AndyA | 0:bddb8cd5e7df | 691 | // PRIVATE Methods ------------------------------------------------------------------------------------ |
AndyA | 0:bddb8cd5e7df | 692 | void DW1000::loadLDE() // initialise LDE algorithm LDELOAD User Manual p22 |
AndyA | 0:bddb8cd5e7df | 693 | { |
AndyA | 0:bddb8cd5e7df | 694 | spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test) |
AndyA | 0:bddb8cd5e7df | 695 | |
AndyA | 0:bddb8cd5e7df | 696 | writeRegister16(DW1000_PMSC, 0, 0x0301); // set clock to XTAL so OTP is reliable |
AndyA | 0:bddb8cd5e7df | 697 | writeRegister16(DW1000_OTP_IF, DWOTP_OTP_CTRL, 0x8000); // set LDELOAD bit in OTP |
AndyA | 0:bddb8cd5e7df | 698 | wait_us(150); |
AndyA | 0:bddb8cd5e7df | 699 | writeRegister16(DW1000_PMSC, 0, 0x0200); // recover to PLL clock |
AndyA | 0:bddb8cd5e7df | 700 | |
AndyA | 0:bddb8cd5e7df | 701 | wait_ms(1); |
AndyA | 0:bddb8cd5e7df | 702 | |
AndyA | 0:bddb8cd5e7df | 703 | spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test) |
AndyA | 0:bddb8cd5e7df | 704 | |
AndyA | 0:bddb8cd5e7df | 705 | } |
AndyA | 0:bddb8cd5e7df | 706 | |
AndyA | 0:bddb8cd5e7df | 707 | void DW1000::loadLDOTUNE() |
AndyA | 0:bddb8cd5e7df | 708 | { |
AndyA | 1:dcbd071f38d5 | 709 | uint64_t LDOTuningValue = readOTP(0x0004); |
AndyA | 1:dcbd071f38d5 | 710 | if (LDOTuningValue != 0) { |
AndyA | 1:dcbd071f38d5 | 711 | LDOTuningValue = LDOTuningValue | ((uint64_t)(readOTP(0x0005) & 0x00ff) << 32); |
AndyA | 0:bddb8cd5e7df | 712 | writeRegister40(DW1000_RF_CONF,DWRFCONF_RF_LDOTUNE,LDOTuningValue); |
AndyA | 1:dcbd071f38d5 | 713 | } |
AndyA | 0:bddb8cd5e7df | 714 | } |
AndyA | 0:bddb8cd5e7df | 715 | |
AndyA | 0:bddb8cd5e7df | 716 | void DW1000::resetRX() |
AndyA | 0:bddb8cd5e7df | 717 | { |
AndyA | 0:bddb8cd5e7df | 718 | writeRegister8(DW1000_PMSC, 3, 0xE0); // set RX reset |
AndyA | 0:bddb8cd5e7df | 719 | writeRegister8(DW1000_PMSC, 3, 0xF0); // clear RX reset |
AndyA | 0:bddb8cd5e7df | 720 | } |
AndyA | 0:bddb8cd5e7df | 721 | |
AndyA | 0:bddb8cd5e7df | 722 | void DW1000::resetAll() |
AndyA | 0:bddb8cd5e7df | 723 | { |
AndyA | 0:bddb8cd5e7df | 724 | spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test) |
AndyA | 0:bddb8cd5e7df | 725 | |
AndyA | 0:bddb8cd5e7df | 726 | writeRegister8(DW1000_PMSC, 0, 0x01); // set clock to XTAL |
AndyA | 0:bddb8cd5e7df | 727 | writeRegister8(DW1000_PMSC, 3, 0x00); // set All reset |
AndyA | 0:bddb8cd5e7df | 728 | wait_us(10); // wait for PLL to lock |
AndyA | 0:bddb8cd5e7df | 729 | writeRegister8(DW1000_PMSC, 3, 0xF0); // clear All reset |
AndyA | 0:bddb8cd5e7df | 730 | |
AndyA | 0:bddb8cd5e7df | 731 | wait_ms(1); |
AndyA | 0:bddb8cd5e7df | 732 | |
AndyA | 0:bddb8cd5e7df | 733 | spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test) |
AndyA | 0:bddb8cd5e7df | 734 | } |
AndyA | 0:bddb8cd5e7df | 735 | |
AndyA | 0:bddb8cd5e7df | 736 | /// After writes have been completed reset the device. |
AndyA | 1:dcbd071f38d5 | 737 | bool DW1000::writeOTP(uint16_t word_address,uint32_t data) |
AndyA | 0:bddb8cd5e7df | 738 | { |
AndyA | 0:bddb8cd5e7df | 739 | spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test) |
AndyA | 0:bddb8cd5e7df | 740 | |
AndyA | 0:bddb8cd5e7df | 741 | writeRegister8(DW1000_PMSC, 0, 0x01); // set clock to XTAL |
AndyA | 0:bddb8cd5e7df | 742 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x03); // |
AndyA | 0:bddb8cd5e7df | 743 | writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x9220); // |
AndyA | 0:bddb8cd5e7df | 744 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); // |
AndyA | 0:bddb8cd5e7df | 745 | wait_ms(1); |
AndyA | 0:bddb8cd5e7df | 746 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x02); // |
AndyA | 0:bddb8cd5e7df | 747 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x88); // |
AndyA | 0:bddb8cd5e7df | 748 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x80); // |
AndyA | 0:bddb8cd5e7df | 749 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // |
AndyA | 0:bddb8cd5e7df | 750 | |
AndyA | 0:bddb8cd5e7df | 751 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x05); // |
AndyA | 0:bddb8cd5e7df | 752 | writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x000E); // |
AndyA | 0:bddb8cd5e7df | 753 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); // |
AndyA | 0:bddb8cd5e7df | 754 | wait_ms(1); |
AndyA | 0:bddb8cd5e7df | 755 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x04); // |
AndyA | 0:bddb8cd5e7df | 756 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x88); // |
AndyA | 0:bddb8cd5e7df | 757 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x80); // |
AndyA | 0:bddb8cd5e7df | 758 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // |
AndyA | 0:bddb8cd5e7df | 759 | |
AndyA | 0:bddb8cd5e7df | 760 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x01); // |
AndyA | 0:bddb8cd5e7df | 761 | writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x1024); // |
AndyA | 0:bddb8cd5e7df | 762 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); // |
AndyA | 0:bddb8cd5e7df | 763 | wait_ms(1); |
AndyA | 0:bddb8cd5e7df | 764 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x00); // |
AndyA | 0:bddb8cd5e7df | 765 | |
AndyA | 0:bddb8cd5e7df | 766 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // |
AndyA | 0:bddb8cd5e7df | 767 | writeRegister32(DW1000_OTP_IF,DWOTP_OTP_WDAT,data); // |
AndyA | 1:dcbd071f38d5 | 768 | writeRegister16(DW1000_OTP_IF,DWOTP_OTP_ADDR,word_address); // |
AndyA | 0:bddb8cd5e7df | 769 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x40); // |
AndyA | 0:bddb8cd5e7df | 770 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // |
AndyA | 0:bddb8cd5e7df | 771 | wait_ms(1); |
AndyA | 0:bddb8cd5e7df | 772 | |
AndyA | 0:bddb8cd5e7df | 773 | for (int i=0; i<10; i++) { |
AndyA | 1:dcbd071f38d5 | 774 | if (readOTP(word_address) == data) |
AndyA | 0:bddb8cd5e7df | 775 | return true; |
AndyA | 0:bddb8cd5e7df | 776 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x40); // retry |
AndyA | 0:bddb8cd5e7df | 777 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); |
AndyA | 0:bddb8cd5e7df | 778 | wait_ms(1); |
AndyA | 0:bddb8cd5e7df | 779 | } |
AndyA | 0:bddb8cd5e7df | 780 | return false; |
AndyA | 0:bddb8cd5e7df | 781 | } |
AndyA | 0:bddb8cd5e7df | 782 | |
AndyA | 0:bddb8cd5e7df | 783 | |
AndyA | 1:dcbd071f38d5 | 784 | uint32_t DW1000::readOTP(uint16_t word_address) |
AndyA | 0:bddb8cd5e7df | 785 | { |
AndyA | 1:dcbd071f38d5 | 786 | writeRegister16(DW1000_OTP_IF,DWOTP_OTP_ADDR,word_address); // write address |
AndyA | 0:bddb8cd5e7df | 787 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x03); // read address load |
AndyA | 0:bddb8cd5e7df | 788 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x01); // read |
AndyA | 0:bddb8cd5e7df | 789 | uint32_t data = readRegister32(DW1000_OTP_IF,DWOTP_OTP_RDAT); |
AndyA | 0:bddb8cd5e7df | 790 | writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // OTP idle |
AndyA | 0:bddb8cd5e7df | 791 | return data; |
AndyA | 0:bddb8cd5e7df | 792 | } |
AndyA | 0:bddb8cd5e7df | 793 | |
AndyA | 0:bddb8cd5e7df | 794 | void DW1000::setInterrupt(bool RX, bool TX) |
AndyA | 0:bddb8cd5e7df | 795 | { |
AndyA | 0:bddb8cd5e7df | 796 | writeRegister16(DW1000_SYS_MASK, 0, RX*0x4000 | TX*0x0080); // RX good frame 0x4000, TX done 0x0080 |
AndyA | 0:bddb8cd5e7df | 797 | } |
AndyA | 0:bddb8cd5e7df | 798 | |
AndyA | 0:bddb8cd5e7df | 799 | void DW1000::ISR() |
AndyA | 0:bddb8cd5e7df | 800 | { |
AndyA | 0:bddb8cd5e7df | 801 | uint64_t status = getStatus(); |
AndyA | 0:bddb8cd5e7df | 802 | if (status & 0x4000) { // a frame was received |
AndyA | 0:bddb8cd5e7df | 803 | callbackRX.call(); |
AndyA | 0:bddb8cd5e7df | 804 | writeRegister16(DW1000_SYS_STATUS, 0, 0x6F00); // clearing of receiving status bits |
AndyA | 0:bddb8cd5e7df | 805 | } |
AndyA | 0:bddb8cd5e7df | 806 | if (status & 0x80) { // sending complete |
AndyA | 0:bddb8cd5e7df | 807 | callbackTX.call(); |
AndyA | 0:bddb8cd5e7df | 808 | writeRegister8(DW1000_SYS_STATUS, 0, 0xF8); // clearing of sending status bits |
AndyA | 0:bddb8cd5e7df | 809 | } |
AndyA | 0:bddb8cd5e7df | 810 | } |
AndyA | 0:bddb8cd5e7df | 811 | |
AndyA | 0:bddb8cd5e7df | 812 | uint16_t DW1000::getFramelength() |
AndyA | 0:bddb8cd5e7df | 813 | { |
AndyA | 0:bddb8cd5e7df | 814 | uint16_t framelength = readRegister16(DW1000_RX_FINFO, 0); // get framelength |
AndyA | 0:bddb8cd5e7df | 815 | framelength = (framelength & 0x03FF) - 2; // take only the right bits and subtract the 2 CRC Bytes |
AndyA | 0:bddb8cd5e7df | 816 | return framelength; |
AndyA | 0:bddb8cd5e7df | 817 | } |
AndyA | 0:bddb8cd5e7df | 818 | |
AndyA | 0:bddb8cd5e7df | 819 | // SPI Interface ------------------------------------------------------------------------------------ |
AndyA | 0:bddb8cd5e7df | 820 | uint8_t DW1000::readRegister8(uint8_t reg, uint16_t subaddress) |
AndyA | 0:bddb8cd5e7df | 821 | { |
AndyA | 0:bddb8cd5e7df | 822 | uint8_t result; |
AndyA | 0:bddb8cd5e7df | 823 | readRegister(reg, subaddress, &result, 1); |
AndyA | 0:bddb8cd5e7df | 824 | return result; |
AndyA | 0:bddb8cd5e7df | 825 | } |
AndyA | 0:bddb8cd5e7df | 826 | |
AndyA | 0:bddb8cd5e7df | 827 | uint16_t DW1000::readRegister16(uint8_t reg, uint16_t subaddress) |
AndyA | 0:bddb8cd5e7df | 828 | { |
AndyA | 0:bddb8cd5e7df | 829 | uint16_t result; |
AndyA | 0:bddb8cd5e7df | 830 | readRegister(reg, subaddress, (uint8_t*)&result, 2); |
AndyA | 0:bddb8cd5e7df | 831 | return result; |
AndyA | 0:bddb8cd5e7df | 832 | } |
AndyA | 0:bddb8cd5e7df | 833 | |
AndyA | 0:bddb8cd5e7df | 834 | uint32_t DW1000::readRegister32(uint8_t reg, uint16_t subaddress) |
AndyA | 0:bddb8cd5e7df | 835 | { |
AndyA | 0:bddb8cd5e7df | 836 | uint32_t result; |
AndyA | 0:bddb8cd5e7df | 837 | readRegister(reg, subaddress, (uint8_t*)&result, 4); |
AndyA | 0:bddb8cd5e7df | 838 | return result; |
AndyA | 0:bddb8cd5e7df | 839 | } |
AndyA | 0:bddb8cd5e7df | 840 | |
AndyA | 0:bddb8cd5e7df | 841 | |
AndyA | 0:bddb8cd5e7df | 842 | uint64_t DW1000::readRegister40(uint8_t reg, uint16_t subaddress) |
AndyA | 0:bddb8cd5e7df | 843 | { |
AndyA | 0:bddb8cd5e7df | 844 | uint64_t result = 0; |
AndyA | 0:bddb8cd5e7df | 845 | readRegister(reg, subaddress, (uint8_t*)&result, 5); |
AndyA | 0:bddb8cd5e7df | 846 | return result; |
AndyA | 0:bddb8cd5e7df | 847 | } |
AndyA | 0:bddb8cd5e7df | 848 | uint64_t DW1000::readRegister64(uint8_t reg, uint16_t subaddress) |
AndyA | 0:bddb8cd5e7df | 849 | { |
AndyA | 0:bddb8cd5e7df | 850 | uint64_t result; |
AndyA | 0:bddb8cd5e7df | 851 | readRegister(reg, subaddress, (uint8_t*)&result, 8); |
AndyA | 0:bddb8cd5e7df | 852 | return result; |
AndyA | 0:bddb8cd5e7df | 853 | } |
AndyA | 0:bddb8cd5e7df | 854 | |
AndyA | 0:bddb8cd5e7df | 855 | void DW1000::writeRegister8(uint8_t reg, uint16_t subaddress, uint8_t buffer) |
AndyA | 0:bddb8cd5e7df | 856 | { |
AndyA | 0:bddb8cd5e7df | 857 | writeRegister(reg, subaddress, &buffer, 1); |
AndyA | 0:bddb8cd5e7df | 858 | } |
AndyA | 0:bddb8cd5e7df | 859 | |
AndyA | 0:bddb8cd5e7df | 860 | void DW1000::writeRegister16(uint8_t reg, uint16_t subaddress, uint16_t buffer) |
AndyA | 0:bddb8cd5e7df | 861 | { |
AndyA | 0:bddb8cd5e7df | 862 | writeRegister(reg, subaddress, (uint8_t*)&buffer, 2); |
AndyA | 0:bddb8cd5e7df | 863 | } |
AndyA | 0:bddb8cd5e7df | 864 | |
AndyA | 0:bddb8cd5e7df | 865 | void DW1000::writeRegister32(uint8_t reg, uint16_t subaddress, uint32_t buffer) |
AndyA | 0:bddb8cd5e7df | 866 | { |
AndyA | 0:bddb8cd5e7df | 867 | writeRegister(reg, subaddress, (uint8_t*)&buffer, 4); |
AndyA | 0:bddb8cd5e7df | 868 | } |
AndyA | 0:bddb8cd5e7df | 869 | |
AndyA | 0:bddb8cd5e7df | 870 | void DW1000::writeRegister40(uint8_t reg, uint16_t subaddress, uint64_t buffer) |
AndyA | 0:bddb8cd5e7df | 871 | { |
AndyA | 0:bddb8cd5e7df | 872 | writeRegister(reg, subaddress, (uint8_t*)&buffer, 5); |
AndyA | 0:bddb8cd5e7df | 873 | } |
AndyA | 0:bddb8cd5e7df | 874 | |
AndyA | 0:bddb8cd5e7df | 875 | void DW1000::readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length) |
AndyA | 0:bddb8cd5e7df | 876 | { |
AndyA | 0:bddb8cd5e7df | 877 | setupTransaction(reg, subaddress, false); |
AndyA | 0:bddb8cd5e7df | 878 | for(int i=0; i<length; i++) // get data |
AndyA | 0:bddb8cd5e7df | 879 | buffer[i] = spi.write(0x00); |
AndyA | 0:bddb8cd5e7df | 880 | deselect(); |
AndyA | 0:bddb8cd5e7df | 881 | } |
AndyA | 0:bddb8cd5e7df | 882 | |
AndyA | 0:bddb8cd5e7df | 883 | void DW1000::writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length) |
AndyA | 0:bddb8cd5e7df | 884 | { |
AndyA | 0:bddb8cd5e7df | 885 | setupTransaction(reg, subaddress, true); |
AndyA | 0:bddb8cd5e7df | 886 | for(int i=0; i<length; i++) // put data |
AndyA | 0:bddb8cd5e7df | 887 | spi.write(buffer[i]); |
AndyA | 0:bddb8cd5e7df | 888 | deselect(); |
AndyA | 0:bddb8cd5e7df | 889 | } |
AndyA | 0:bddb8cd5e7df | 890 | |
AndyA | 0:bddb8cd5e7df | 891 | void DW1000::setupTransaction(uint8_t reg, uint16_t subaddress, bool write) |
AndyA | 0:bddb8cd5e7df | 892 | { |
AndyA | 0:bddb8cd5e7df | 893 | reg |= (write * DW1000_WRITE_FLAG); // set read/write flag |
AndyA | 0:bddb8cd5e7df | 894 | select(); |
AndyA | 0:bddb8cd5e7df | 895 | if (subaddress > 0) { // there's a subadress, we need to set flag and send second header byte |
AndyA | 0:bddb8cd5e7df | 896 | spi.write(reg | DW1000_SUBADDRESS_FLAG); |
AndyA | 0:bddb8cd5e7df | 897 | if (subaddress > 0x7F) { // sub address too long, we need to set flag and send third header byte |
AndyA | 0:bddb8cd5e7df | 898 | spi.write((uint8_t)(subaddress & 0x7F) | DW1000_2_SUBADDRESS_FLAG); // and |
AndyA | 0:bddb8cd5e7df | 899 | spi.write((uint8_t)(subaddress >> 7)); |
AndyA | 0:bddb8cd5e7df | 900 | } else { |
AndyA | 0:bddb8cd5e7df | 901 | spi.write((uint8_t)subaddress); |
AndyA | 0:bddb8cd5e7df | 902 | } |
AndyA | 0:bddb8cd5e7df | 903 | } else { |
AndyA | 0:bddb8cd5e7df | 904 | spi.write(reg); // say which register address we want to access |
AndyA | 0:bddb8cd5e7df | 905 | } |
AndyA | 0:bddb8cd5e7df | 906 | } |
AndyA | 0:bddb8cd5e7df | 907 | |
AndyA | 0:bddb8cd5e7df | 908 | void DW1000::select() // always called to start an SPI transmission |
AndyA | 0:bddb8cd5e7df | 909 | { |
AndyA | 0:bddb8cd5e7df | 910 | irq.disable_irq(); // disable interrupts from DW1000 during SPI becaus this leads to crashes! TODO: if you have other interrupt handlers attached on the micro controller, they could also interfere. |
AndyA | 0:bddb8cd5e7df | 911 | cs = 0; // set Cable Select pin low to start transmission |
AndyA | 0:bddb8cd5e7df | 912 | } |
AndyA | 0:bddb8cd5e7df | 913 | |
AndyA | 0:bddb8cd5e7df | 914 | void DW1000::deselect() // always called to end an SPI transmission |
AndyA | 0:bddb8cd5e7df | 915 | { |
AndyA | 0:bddb8cd5e7df | 916 | cs = 1; // set Cable Select pin high to stop transmission |
AndyA | 0:bddb8cd5e7df | 917 | irq.enable_irq(); // reenable the interrupt handler |
AndyA | 0:bddb8cd5e7df | 918 | } |