Andy A / DW1000

DW1000 UWB driver based on work of Matthias Grob & Manuel Stalder - ETH Zürich - 2015

Dependencies:   BurstSPI

DW1000Registers.h@8:0b408e77b701, 2016-04-18 (annotated)

Committer:
AndyA
Date:
Mon Apr 18 16:58:27 2016 +0000
Revision:
8:0b408e77b701
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
AndyA 8:0b408e77b701 1 #ifndef __DWREG_H__
AndyA 8:0b408e77b701 2 #define __DWREG_H__
AndyA 8:0b408e77b701 3
AndyA 8:0b408e77b701 4 // register addresses
AndyA 8:0b408e77b701 5 // Mnemonic Address Bytes Description
AndyA 8:0b408e77b701 6 #define DW1000_DEV_ID 0x00 // 4 Device Identifier – includes device type and revision information
AndyA 8:0b408e77b701 7 #define DW1000_EUI 0x01 // 8 Extended Unique Identifier
AndyA 8:0b408e77b701 8 #define DW1000_PANADR 0x03 // 4 PAN Identifier and Short Address
AndyA 8:0b408e77b701 9 #define DW1000_SYS_CFG 0x04 // 4 System Configuration bitmap
AndyA 8:0b408e77b701 10 #define DW1000_SYS_TIME 0x06 // 5 System Time Counter (40-bit)
AndyA 8:0b408e77b701 11 #define DW1000_TX_FCTRL 0x08 // 5 Transmit Frame Control
AndyA 8:0b408e77b701 12 #define DW1000_TX_BUFFER 0x09 // 1024 Transmit Data Buffer
AndyA 8:0b408e77b701 13 #define DW1000_DX_TIME 0x0A // 5 Delayed Send or Receive Time (40-bit)
AndyA 8:0b408e77b701 14 #define DW1000_RX_FWTO 0x0C // 2 Receive Frame Wait Timeout Period
AndyA 8:0b408e77b701 15 #define DW1000_SYS_CTRL 0x0D // 4 System Control Register
AndyA 8:0b408e77b701 16 #define DW1000_SYS_MASK 0x0E // 4 System Event Mask Register
AndyA 8:0b408e77b701 17 #define DW1000_SYS_STATUS 0x0F // 5 System Event Status Register
AndyA 8:0b408e77b701 18 #define DW1000_RX_FINFO 0x10 // 4 RX Frame Information (in double buffer set)
AndyA 8:0b408e77b701 19 #define DW1000_RX_BUFFER 0x11 // 1024 Receive Data Buffer (in double buffer set)
AndyA 8:0b408e77b701 20 #define DW1000_RX_FQUAL 0x12 // 8 Rx Frame Quality information (in double buffer set)
AndyA 8:0b408e77b701 21 #define DW1000_RX_TTCKI 0x13 // 4 Receiver Time Tracking Interval (in double buffer set)
AndyA 8:0b408e77b701 22 #define DW1000_RX_TTCKO 0x14 // 5 Receiver Time Tracking Offset (in double buffer set)
AndyA 8:0b408e77b701 23 #define DW1000_RX_TIME 0x15 // 14 Receive Message Time of Arrival (in double buffer set)
AndyA 8:0b408e77b701 24 #define DW1000_TX_TIME 0x17 // 10 Transmit Message Time of Sending (in double buffer set)
AndyA 8:0b408e77b701 25 #define DW1000_TX_ANTD 0x18 // 2 16-bit Delay from Transmit to Antenna
AndyA 8:0b408e77b701 26 #define DW1000_SYS_STATE 0x19 // 5 System State information
AndyA 8:0b408e77b701 27 #define DW1000_ACK_RESP_T 0x1A // 4 Acknowledgement Time and Response Time
AndyA 8:0b408e77b701 28 #define DW1000_RX_SNIFF 0x1D // 4 Pulsed Preamble Reception Configuration
AndyA 8:0b408e77b701 29 #define DW1000_TX_POWER 0x1E // 4 TX Power Control
AndyA 8:0b408e77b701 30 #define DW1000_CHAN_CTRL 0x1F // 4 Channel Control
AndyA 8:0b408e77b701 31 #define DW1000_USR_SFD 0x21 // 41 User-specified short/long TX/RX SFD sequences
AndyA 8:0b408e77b701 32 #define DW1000_AGC_CTRL 0x23 // 32 Automatic Gain Control configuration
AndyA 8:0b408e77b701 33 #define DW1000_EXT_SYNC 0x24 // 12 External synchronisation control.
AndyA 8:0b408e77b701 34 #define DW1000_ACC_MEM 0x25 // 4064 Read access to accumulator data
AndyA 8:0b408e77b701 35 #define DW1000_GPIO_CTRL 0x26 // 44 Peripheral register bus 1 access - GPIO control
AndyA 8:0b408e77b701 36 #define DW1000_DRX_CONF 0x27 // 44 Digital Receiver configuration
AndyA 8:0b408e77b701 37 #define DW1000_RF_CONF 0x28 // 58 Analog RF Configuration
AndyA 8:0b408e77b701 38 #define DW1000_TX_CAL 0x2A // 52 Transmitter calibration block
AndyA 8:0b408e77b701 39 #define DW1000_FS_CTRL 0x2B // 21 Frequency synthesiser control block
AndyA 8:0b408e77b701 40 #define DW1000_AON 0x2C // 12 Always-On register set
AndyA 8:0b408e77b701 41 #define DW1000_OTP_IF 0x2D // 18 One Time Programmable Memory Interface
AndyA 8:0b408e77b701 42 #define DW1000_LDE_CTRL 0x2E // - Leading edge detection control block
AndyA 8:0b408e77b701 43 #define DW1000_DIG_DIAG 0x2F // 41 Digital Diagnostics Interface
AndyA 8:0b408e77b701 44 #define DW1000_PMSC 0x36 // 48 Power Management System Control Block
AndyA 8:0b408e77b701 45
AndyA 8:0b408e77b701 46 // AGC_CTRL sub registers
AndyA 8:0b408e77b701 47 #define DWAGCCTRL_AGC_CTRL1 0x02
AndyA 8:0b408e77b701 48 #define DWAGCCTRL_AGC_TUNE1 0x04
AndyA 8:0b408e77b701 49 #define DWAGCCTRL_AGC_TUNE2 0x0C
AndyA 8:0b408e77b701 50 #define DWAGCCTRL_AGC_TUNE3 0x12
AndyA 8:0b408e77b701 51
AndyA 8:0b408e77b701 52 // EXT_SYNC sub registers
AndyA 8:0b408e77b701 53 #define DWEXTSYNC_EC_CTRL 0x00
AndyA 8:0b408e77b701 54 #define DWEXTSYNC_EC_RXTC 0x04
AndyA 8:0b408e77b701 55 #define DWEXTSYNC_EC_GOLP 0x08
AndyA 8:0b408e77b701 56
AndyA 8:0b408e77b701 57 // GPIO sub registers
AndyA 8:0b408e77b701 58 #define DWGPIO_GPIO_MODE 0x00
AndyA 8:0b408e77b701 59 #define DWGPIO_GPIO_DIR 0x08
AndyA 8:0b408e77b701 60 #define DWGPIO_GPIO_DOUT 0x0C
AndyA 8:0b408e77b701 61 #define DWGPIO_GPIO_IRQE 0x10
AndyA 8:0b408e77b701 62 #define DWGPIO_GPIO_ISEN 0x14
AndyA 8:0b408e77b701 63 #define DWGPIO_GPIO_IMODE 0x18
AndyA 8:0b408e77b701 64 #define DWGPIO_GPIO_IBES 0x1C
AndyA 8:0b408e77b701 65 #define DWGPIO_GPIO_ICLR 0x20
AndyA 8:0b408e77b701 66 #define DWGPIO_GPIO_IDBE 0x24
AndyA 8:0b408e77b701 67 #define DWGPIO_GPIO_RAW 0x28
AndyA 8:0b408e77b701 68
AndyA 8:0b408e77b701 69 // DRX sub registers
AndyA 8:0b408e77b701 70 #define DWDRX_DRX_TUNE0B 0x02
AndyA 8:0b408e77b701 71 #define DWDRX_DRX_TUNE1A 0x04
AndyA 8:0b408e77b701 72 #define DWDRX_DRX_TUNE1B 0x06
AndyA 8:0b408e77b701 73 #define DWDRX_DRX_TUNE2 0x08
AndyA 8:0b408e77b701 74 #define DWDRX_DRX_SFDTOC 0x20
AndyA 8:0b408e77b701 75 #define DWDRX_DRX_PRETOC 0x24
AndyA 8:0b408e77b701 76 #define DWDRX_DRX_TUNE4H 0x26
AndyA 8:0b408e77b701 77 #define DWDRX_RXPAC_NOSAT 0x2c
AndyA 8:0b408e77b701 78
AndyA 8:0b408e77b701 79
AndyA 8:0b408e77b701 80 //RF conf sub registers
AndyA 8:0b408e77b701 81 #define DWRFCONF_RF_CONF 0x00
AndyA 8:0b408e77b701 82 #define DWRFCONF_RF_RXCTRLH 0x0B
AndyA 8:0b408e77b701 83 #define DWRFCONF_RF_TXCTRL 0x0C
AndyA 8:0b408e77b701 84 #define DWRFCONF_RF_STATUS 0x2C
AndyA 8:0b408e77b701 85 #define DWRFCONF_RF_LDOTUNE 0x30
AndyA 8:0b408e77b701 86
AndyA 8:0b408e77b701 87 // TX cal sub registers
AndyA 8:0b408e77b701 88 #define DWTXCAL_TC_SARC 0x00
AndyA 8:0b408e77b701 89 #define DWTXCAL_TC_SARL 0x03
AndyA 8:0b408e77b701 90 #define DWTXCAL_TC_SARW 0x06
AndyA 8:0b408e77b701 91 #define DWTXCAL_TC_PGDELAY 0x0B
AndyA 8:0b408e77b701 92 #define DWTXCAL_TC_PGTEST 0x0C
AndyA 8:0b408e77b701 93
AndyA 8:0b408e77b701 94 // Freq synth sub registers
AndyA 8:0b408e77b701 95 #define DWFSCTRL_FS_PLLCFG 0x07
AndyA 8:0b408e77b701 96 #define DWFSCTRL_FS_PLLTUNE 0x0B
AndyA 8:0b408e77b701 97 #define DWFSCTRL_FS_XTALT 0x0E
AndyA 8:0b408e77b701 98
AndyA 8:0b408e77b701 99 // Always on sub registers
AndyA 8:0b408e77b701 100 #define DWAON_AON_WCFG 0x00
AndyA 8:0b408e77b701 101 #define DWAON_AON_CTRL 0x02
AndyA 8:0b408e77b701 102 #define DWAON_AON_RDAT 0x03
AndyA 8:0b408e77b701 103 #define DWAON_AON_ADDR 0x04
AndyA 8:0b408e77b701 104 #define DWAON_AON_CFG0 0x06
AndyA 8:0b408e77b701 105 #define DWAON_AON_CFG1 0x0A
AndyA 8:0b408e77b701 106
AndyA 8:0b408e77b701 107 // OTP sub registers
AndyA 8:0b408e77b701 108 #define DWOTP_OTP_WDAT 0x00
AndyA 8:0b408e77b701 109 #define DWOTP_OTP_ADDR 0x04
AndyA 8:0b408e77b701 110 #define DWOTP_OTP_CTRL 0x06
AndyA 8:0b408e77b701 111 #define DWOTP_OTP_STAT 0x08
AndyA 8:0b408e77b701 112 #define DWOTP_OTP_RDAT 0x0A
AndyA 8:0b408e77b701 113 #define DWOTP_OTP_SRDAT 0x0E
AndyA 8:0b408e77b701 114 #define DWOTP_OTP_SF 0x12
AndyA 8:0b408e77b701 115
AndyA 8:0b408e77b701 116 //LDE_IF sub registers
AndyA 8:0b408e77b701 117 #define DWLDE_LDE_THRESH 0x0000
AndyA 8:0b408e77b701 118 #define DWLDE_LDE_CFG1 0x0806
AndyA 8:0b408e77b701 119 #define DWLDE_LDE_PPINDX 0x1000
AndyA 8:0b408e77b701 120 #define DWLDE_LDE_PPAMPL 0x1002
AndyA 8:0b408e77b701 121 #define DWLDE_LDE_RXANTD 0x1804
AndyA 8:0b408e77b701 122 #define DWLDE_LDE_CFG2 0x1806
AndyA 8:0b408e77b701 123 #define DWLDE_LDE_REPC 0x2804
AndyA 8:0b408e77b701 124
AndyA 8:0b408e77b701 125 // Dig Diag sub registers
AndyA 8:0b408e77b701 126 #define DWDIAG_EVC_CTRL 0x00
AndyA 8:0b408e77b701 127 #define DWDIAG_EVC_PHE 0x04
AndyA 8:0b408e77b701 128 #define DWDIAG_EVC_RSE 0x06
AndyA 8:0b408e77b701 129 #define DWDIAG_EVC_FCG 0x08
AndyA 8:0b408e77b701 130 #define DWDIAG_EVC_FCE 0x0A
AndyA 8:0b408e77b701 131 #define DWDIAG_EVC_FFR 0x0C
AndyA 8:0b408e77b701 132 #define DWDIAG_EVC_OVR 0x0E
AndyA 8:0b408e77b701 133 #define DWDIAG_EVC_STO 0x10
AndyA 8:0b408e77b701 134 #define DWDIAG_EVC_PTO 0x12
AndyA 8:0b408e77b701 135 #define DWDIAG_EVC_FWTO 0x14
AndyA 8:0b408e77b701 136 #define DWDIAG_EVC_TXFS 0x16
AndyA 8:0b408e77b701 137 #define DWDIAG_EVC_HPW 0x18
AndyA 8:0b408e77b701 138 #define DWDIAG_EVC_TPW 0x1A
AndyA 8:0b408e77b701 139 #define DWDIAG_DIAG_TMC 0x24
AndyA 8:0b408e77b701 140
AndyA 8:0b408e77b701 141 // power control sub registers
AndyA 8:0b408e77b701 142 #define DWPMSC_PMSC_CTRL0 0x00
AndyA 8:0b408e77b701 143 #define DWPMSC_PMSC_CTRL1 0x04
AndyA 8:0b408e77b701 144 #define DWPMSC_PMSC_SNOZT 0x0C
AndyA 8:0b408e77b701 145 #define DWPMSC_PMSC_TXFSEQ 0x26
AndyA 8:0b408e77b701 146 #define DWPMSC_PMSC_LEDC 0x28
AndyA 8:0b408e77b701 147
AndyA 8:0b408e77b701 148
AndyA 8:0b408e77b701 149 #define DW1000_WRITE_FLAG 0x80 // First Bit of the address has to be 1 to indicate we want to write
AndyA 8:0b408e77b701 150 #define DW1000_SUBADDRESS_FLAG 0x40 // if we have a sub address second Bit has to be 1
AndyA 8:0b408e77b701 151 #define DW1000_2_SUBADDRESS_FLAG 0x80 // if we have a long sub adress (more than 7 Bit) we set this Bit in the first part
AndyA 8:0b408e77b701 152
AndyA 8:0b408e77b701 153 #endif