Andy A / DW1000

DW1000 UWB driver based on work of Matthias Grob & Manuel Stalder - ETH Zürich - 2015

Dependencies:   BurstSPI

DW1000.cpp@15:6faab70a5b19, 2017-11-08 (annotated)

Committer:
AndyA
Date:
Wed Nov 08 10:43:03 2017 +0000
Revision:
15:6faab70a5b19
Parent:
14:02f0912e4ce4
Child:
17:1fb08dfef237
Added clock tuning controls

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AndyA 0:bddb8cd5e7df 1 #include "DW1000.h"
AndyA 15:6faab70a5b19 2 #include "main.h"
AndyA 7:b13881dbb09d 3 #define SPIRATE_PLL (10*1000*1000)
AndyA 15:6faab70a5b19 4 #define SPIRATE_OSC (1*1000*1000)
AndyA 0:bddb8cd5e7df 5
AndyA 9:326bf149c8bc 6 DW1000::DW1000(PinName MOSI, PinName MISO, PinName SCLK, PinName CS, PinName IRQ) : irq(IRQ), spi(MOSI, MISO, SCLK), cs(CS)
AndyA 0:bddb8cd5e7df 7 {
AndyA 0:bddb8cd5e7df 8 setCallbacks(NULL, NULL);
AndyA 9:326bf149c8bc 9 DW1000Setup newSetup(DW1000Setup::tunedDefault);
AndyA 8:0b408e77b701 10 systemConfig.applyConfig(&newSetup);
AndyA 0:bddb8cd5e7df 11
AndyA 0:bddb8cd5e7df 12 deselect(); // Chip must be deselected first
AndyA 0:bddb8cd5e7df 13 spi.format(8,0); // Setup the spi for standard 8 bit data and SPI-Mode 0 (GPIO5, GPIO6 open circuit or ground on DW1000)
AndyA 0:bddb8cd5e7df 14 spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test)
AndyA 0:bddb8cd5e7df 15
AndyA 9:326bf149c8bc 16 setupRadio();
AndyA 0:bddb8cd5e7df 17
AndyA 9:326bf149c8bc 18 setRxDelay(0);
AndyA 9:326bf149c8bc 19 setTxDelay(0);
AndyA 0:bddb8cd5e7df 20 }
AndyA 0:bddb8cd5e7df 21
AndyA 4:5f1025df5530 22
AndyA 15:6faab70a5b19 23 void DW1000::setSPISpeed(uint32_t speed) {
AndyA 15:6faab70a5b19 24 spi.frequency(speed);
AndyA 15:6faab70a5b19 25 }
AndyA 15:6faab70a5b19 26
AndyA 15:6faab70a5b19 27
AndyA 15:6faab70a5b19 28 void DW1000::enterRFTestMode() {
AndyA 15:6faab70a5b19 29 writeRegister32(DW1000_RF_CONF,0,0x0009A000);
AndyA 15:6faab70a5b19 30 wait_ms(1);
AndyA 15:6faab70a5b19 31 writeRegister16(DW1000_PMSC,DWPMSC_PMSC_CTRL1,0x0000);
AndyA 15:6faab70a5b19 32 wait_ms(1);
AndyA 15:6faab70a5b19 33 writeRegister32(DW1000_TX_POWER,0,0x1f1f1f1f);
AndyA 15:6faab70a5b19 34 wait_ms(1);
AndyA 15:6faab70a5b19 35 uint32_t config = rangingSystem.readRegister32(DW1000_SYS_CFG,0);
AndyA 15:6faab70a5b19 36 config |= 1<<18;
AndyA 15:6faab70a5b19 37 writeRegister32(DW1000_SYS_CFG,0,config);
AndyA 15:6faab70a5b19 38 wait_ms(1);
AndyA 15:6faab70a5b19 39 writeRegister16(DW1000_PMSC,DWPMSC_PMSC_CTRL0,0x0222);
AndyA 15:6faab70a5b19 40 wait_ms(1);
AndyA 15:6faab70a5b19 41 writeRegister32(DW1000_PMSC,DWPMSC_PMSC_TXFSEQ,0x00000000);
AndyA 15:6faab70a5b19 42 wait_ms(1);
AndyA 15:6faab70a5b19 43 writeRegister32(DW1000_RF_CONF,0,0x005fff00);
AndyA 15:6faab70a5b19 44 wait_ms(1);
AndyA 15:6faab70a5b19 45 writeRegister8(DW1000_TX_CAL,DWTXCAL_TC_PGTEST,0x13);
AndyA 15:6faab70a5b19 46 }
AndyA 15:6faab70a5b19 47
AndyA 15:6faab70a5b19 48
AndyA 9:326bf149c8bc 49 DW1000Setup* DW1000::getSetup()
AndyA 9:326bf149c8bc 50 {
AndyA 8:0b408e77b701 51 return &systemConfig;
AndyA 9:326bf149c8bc 52 }
AndyA 9:326bf149c8bc 53
AndyA 9:326bf149c8bc 54 bool DW1000::applySetup(DW1000Setup *setup)
AndyA 9:326bf149c8bc 55 {
AndyA 9:326bf149c8bc 56
AndyA 9:326bf149c8bc 57 if (setup->check()) {
AndyA 9:326bf149c8bc 58 systemConfig.applyConfig(setup);
AndyA 9:326bf149c8bc 59 setupRadio();
AndyA 9:326bf149c8bc 60 spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test)
AndyA 9:326bf149c8bc 61 return true;
AndyA 4:5f1025df5530 62 }
AndyA 9:326bf149c8bc 63 return false;
AndyA 9:326bf149c8bc 64 }
AndyA 4:5f1025df5530 65
AndyA 3:1459d2aa6b97 66 void DW1000::setupRadio()
AndyA 3:1459d2aa6b97 67 {
AndyA 9:326bf149c8bc 68 irq.rise(NULL); // attach interrupt handler to rising edge of interrupt pin from DW1000
AndyA 9:326bf149c8bc 69
AndyA 9:326bf149c8bc 70 stopTRX();
AndyA 9:326bf149c8bc 71 resetAll(); // we do a soft reset of the DW1000 to get to a known state. Without this we lose comms.
AndyA 3:1459d2aa6b97 72 setupAGC();
AndyA 3:1459d2aa6b97 73 setupRxConfig();
AndyA 3:1459d2aa6b97 74 setupLDE();
AndyA 3:1459d2aa6b97 75 setupChannel();
AndyA 3:1459d2aa6b97 76 setupAnalogRF();
AndyA 3:1459d2aa6b97 77 setupFreqSynth();
AndyA 3:1459d2aa6b97 78 setupTxCalibration();
AndyA 3:1459d2aa6b97 79 setupTxFrameCtrl();
AndyA 3:1459d2aa6b97 80 setupSystemConfig();
AndyA 9:326bf149c8bc 81 setupGPIO();
AndyA 9:326bf149c8bc 82 setupPower();
AndyA 3:1459d2aa6b97 83
AndyA 9:326bf149c8bc 84 irq.rise(this, &DW1000::ISR); // attach interrupt handler to rising edge of interrupt pin from DW1000
AndyA 9:326bf149c8bc 85 }
AndyA 9:326bf149c8bc 86
AndyA 9:326bf149c8bc 87
AndyA 9:326bf149c8bc 88 void DW1000::setupGPIO()
AndyA 9:326bf149c8bc 89 {
AndyA 9:326bf149c8bc 90 // not done in a loop because bits 7 and 8 are the inverse, a value of 01 indicates GPIO
AndyA 9:326bf149c8bc 91 uint32_t value = 0;
AndyA 9:326bf149c8bc 92 uint32_t pinMask = systemConfig.getGPIO();
AndyA 9:326bf149c8bc 93 if (pinMask & (0x01<<0))
AndyA 9:326bf149c8bc 94 value |= 1<<6;
AndyA 9:326bf149c8bc 95
AndyA 9:326bf149c8bc 96 if (pinMask & (0x01<<1))
AndyA 9:326bf149c8bc 97 value |= 1<<8;
AndyA 9:326bf149c8bc 98
AndyA 9:326bf149c8bc 99 if (pinMask & (0x01<<2))
AndyA 9:326bf149c8bc 100 value |= 1<<10;
AndyA 9:326bf149c8bc 101
AndyA 9:326bf149c8bc 102 if (pinMask & (0x01<<3))
AndyA 9:326bf149c8bc 103 value |= 1<<12;
AndyA 9:326bf149c8bc 104
AndyA 9:326bf149c8bc 105 if (pinMask & (0x01<<4))
AndyA 9:326bf149c8bc 106 value |= 1<<14;
AndyA 9:326bf149c8bc 107
AndyA 9:326bf149c8bc 108 if (pinMask & (0x01<<5))
AndyA 9:326bf149c8bc 109 value |= 1<<16;
AndyA 9:326bf149c8bc 110
AndyA 9:326bf149c8bc 111 if (pinMask & (0x01<<6))
AndyA 9:326bf149c8bc 112 value |= 1<<18;
AndyA 9:326bf149c8bc 113
AndyA 9:326bf149c8bc 114 if (!(pinMask & (0x01<<7)))
AndyA 9:326bf149c8bc 115 value |= 1<<20;
AndyA 9:326bf149c8bc 116
AndyA 9:326bf149c8bc 117 if (!(pinMask & (0x01<<8)))
AndyA 9:326bf149c8bc 118 value |= 1<<22;
AndyA 9:326bf149c8bc 119
AndyA 9:326bf149c8bc 120 writeRegister32(DW1000_GPIO_CTRL, 0, value); // set time to 400ms, enable blink and flash all LEDs
AndyA 9:326bf149c8bc 121
AndyA 9:326bf149c8bc 122 if (pinMask & 0x000f) { // some LEDs are active
AndyA 9:326bf149c8bc 123 writeRegister32(DW1000_PMSC,DWPMSC_PMSC_CTRL0,readRegister32(DW1000_PMSC,DWPMSC_PMSC_CTRL0) | 1<<23 | 1<<18);
AndyA 9:326bf149c8bc 124 writeRegister32(DW1000_PMSC, DWPMSC_PMSC_LEDC, 0x00000120); // set time to 400ms, enable blink and flash all LEDs
AndyA 9:326bf149c8bc 125 }
AndyA 3:1459d2aa6b97 126 }
AndyA 3:1459d2aa6b97 127
AndyA 3:1459d2aa6b97 128 void DW1000::setupAGC()
AndyA 3:1459d2aa6b97 129 {
AndyA 3:1459d2aa6b97 130
AndyA 3:1459d2aa6b97 131 writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_CTRL1, 0x0001);
AndyA 4:5f1025df5530 132 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 133 writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE1, 0x8870);
AndyA 3:1459d2aa6b97 134 else
AndyA 3:1459d2aa6b97 135 writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE1, 0x889B);
AndyA 3:1459d2aa6b97 136
AndyA 3:1459d2aa6b97 137 writeRegister32(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE2, 0x2502A907);
AndyA 3:1459d2aa6b97 138 writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE3, 0x0035);
AndyA 3:1459d2aa6b97 139 }
AndyA 3:1459d2aa6b97 140
AndyA 3:1459d2aa6b97 141 void DW1000::setupSystemConfig()
AndyA 3:1459d2aa6b97 142 {
AndyA 3:1459d2aa6b97 143 uint32_t valueToUse = 0;
AndyA 3:1459d2aa6b97 144 valueToUse |= 1<<9; // IRQ output is active high (default)
AndyA 3:1459d2aa6b97 145 valueToUse |= 1<<12; // Disable double buffered Rx (default)
AndyA 3:1459d2aa6b97 146
AndyA 3:1459d2aa6b97 147 // valueToUse |= 3<<16; // enable long (>125bytes data) packets
AndyA 3:1459d2aa6b97 148
AndyA 4:5f1025df5530 149 if (!systemConfig.getSmartPower())
AndyA 3:1459d2aa6b97 150 valueToUse |= 1<<18; // disable smart power
AndyA 3:1459d2aa6b97 151
AndyA 4:5f1025df5530 152 if (systemConfig.getDataRate() == DW1000Setup::kbps110)
AndyA 3:1459d2aa6b97 153 valueToUse |= 1<<22;
AndyA 3:1459d2aa6b97 154
AndyA 4:5f1025df5530 155 valueToUse |= 1<<29;// enable auto reenabling receiver after error
AndyA 4:5f1025df5530 156
AndyA 4:5f1025df5530 157 writeRegister32(DW1000_SYS_CFG, 0, valueToUse);
AndyA 3:1459d2aa6b97 158 }
AndyA 3:1459d2aa6b97 159
AndyA 3:1459d2aa6b97 160 void DW1000::setupRxConfig()
AndyA 3:1459d2aa6b97 161 {
AndyA 3:1459d2aa6b97 162
AndyA 4:5f1025df5530 163 switch (systemConfig.getDataRate()) {
AndyA 4:5f1025df5530 164 case DW1000Setup::kbps110:
AndyA 4:5f1025df5530 165 if (systemConfig.getSfd() == DW1000Setup::standard)
AndyA 3:1459d2aa6b97 166 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x000A);
AndyA 3:1459d2aa6b97 167 else
AndyA 3:1459d2aa6b97 168 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0016);
AndyA 3:1459d2aa6b97 169 break;
AndyA 4:5f1025df5530 170 case DW1000Setup::kbps850:
AndyA 4:5f1025df5530 171 if (systemConfig.getSfd() == DW1000Setup::standard)
AndyA 3:1459d2aa6b97 172 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0001);
AndyA 3:1459d2aa6b97 173 else
AndyA 3:1459d2aa6b97 174 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0006);
AndyA 3:1459d2aa6b97 175 break;
AndyA 4:5f1025df5530 176 case DW1000Setup::kbps6800:
AndyA 3:1459d2aa6b97 177 default:
AndyA 4:5f1025df5530 178 if (systemConfig.getSfd() == DW1000Setup::standard)
AndyA 3:1459d2aa6b97 179 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0001);
AndyA 3:1459d2aa6b97 180 else
AndyA 3:1459d2aa6b97 181 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0002);
AndyA 3:1459d2aa6b97 182 break;
AndyA 3:1459d2aa6b97 183 }
AndyA 3:1459d2aa6b97 184
AndyA 4:5f1025df5530 185 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 186 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1A, 0x0087); //DRX_TUNE1a for 16MHz PRF
AndyA 3:1459d2aa6b97 187 else
AndyA 3:1459d2aa6b97 188 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1A, 0x008D);
AndyA 3:1459d2aa6b97 189
AndyA 4:5f1025df5530 190 switch (systemConfig.getPreambleLength()) {
AndyA 4:5f1025df5530 191 case DW1000Setup::pre1536:
AndyA 4:5f1025df5530 192 case DW1000Setup::pre2048:
AndyA 4:5f1025df5530 193 case DW1000Setup::pre4096:
AndyA 3:1459d2aa6b97 194 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0064); //DRX_TUNE1b for 110kbps & > 1024 symbols
AndyA 3:1459d2aa6b97 195 break;
AndyA 3:1459d2aa6b97 196 default: // 128 to 1024
AndyA 3:1459d2aa6b97 197 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0020); //DRX_TUNE1b for 128- 1024 symbols
AndyA 3:1459d2aa6b97 198 break;
AndyA 4:5f1025df5530 199 case DW1000Setup::pre64:
AndyA 3:1459d2aa6b97 200 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0010); //DRX_TUNE1b for 64 symbols
AndyA 3:1459d2aa6b97 201 break;
AndyA 3:1459d2aa6b97 202 }
AndyA 3:1459d2aa6b97 203
AndyA 4:5f1025df5530 204 switch (systemConfig.getPreambleLength()) {
AndyA 4:5f1025df5530 205 case DW1000Setup::pre64:
AndyA 4:5f1025df5530 206 case DW1000Setup::pre128: // PAC = 8
AndyA 4:5f1025df5530 207 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 208 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x311A002D); //DRX_TUNE2 PAC 8 for 64MHz PRF
AndyA 3:1459d2aa6b97 209 else
AndyA 3:1459d2aa6b97 210 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x313B006B); //DRX_TUNE2 PAC 8 for 64MHz PRF
AndyA 3:1459d2aa6b97 211 break;
AndyA 4:5f1025df5530 212 case DW1000Setup::pre256:
AndyA 4:5f1025df5530 213 case DW1000Setup::pre512: // PAC = 16
AndyA 4:5f1025df5530 214 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 215 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x331A0052); //DRX_TUNE2 PAC 16 for 64MHz PRF
AndyA 3:1459d2aa6b97 216 else
AndyA 3:1459d2aa6b97 217 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x333B00BE); //DRX_TUNE2 PAC 16 for 64MHz PRF
AndyA 3:1459d2aa6b97 218 break;
AndyA 4:5f1025df5530 219 case DW1000Setup::pre1024: // PAC = 32
AndyA 4:5f1025df5530 220 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 221 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x351A009A); //DRX_TUNE2 PAC 32 for 64MHz PRF
AndyA 3:1459d2aa6b97 222 else
AndyA 3:1459d2aa6b97 223 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x353B015E); //DRX_TUNE2 PAC 32 for 64MHz PRF
AndyA 3:1459d2aa6b97 224 break;
AndyA 4:5f1025df5530 225 case DW1000Setup::pre1536:
AndyA 4:5f1025df5530 226 case DW1000Setup::pre2048:
AndyA 4:5f1025df5530 227 case DW1000Setup::pre4096: // PAC = 64
AndyA 4:5f1025df5530 228 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 229 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x371A011D); //DRX_TUNE2 PAC 64 for 64MHz PRF
AndyA 3:1459d2aa6b97 230 else
AndyA 3:1459d2aa6b97 231 writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x373B0296); //DRX_TUNE2 PAC 64 for 64MHz PRF
AndyA 0:bddb8cd5e7df 232 break;
AndyA 0:bddb8cd5e7df 233 }
AndyA 0:bddb8cd5e7df 234
AndyA 3:1459d2aa6b97 235
AndyA 4:5f1025df5530 236 if (systemConfig.getPreambleLength() == DW1000Setup::pre64)
AndyA 3:1459d2aa6b97 237 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE4H, 0x0010);
AndyA 3:1459d2aa6b97 238 else
AndyA 3:1459d2aa6b97 239 writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE4H, 0x0028);
AndyA 3:1459d2aa6b97 240
AndyA 3:1459d2aa6b97 241 }
AndyA 3:1459d2aa6b97 242
AndyA 3:1459d2aa6b97 243
AndyA 3:1459d2aa6b97 244 void DW1000::setupLDE()
AndyA 3:1459d2aa6b97 245 {
AndyA 3:1459d2aa6b97 246
AndyA 3:1459d2aa6b97 247 writeRegister8 (DW1000_LDE_CTRL, DWLDE_LDE_CFG1, 0x13 | 0x03<<5); //NTM = 13 (12 may be better in some situations. PMULT = 3
AndyA 3:1459d2aa6b97 248
AndyA 4:5f1025df5530 249 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 250 writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_CFG2, 0x1607); //LDE_CFG2 for 16MHz PRF
AndyA 3:1459d2aa6b97 251 else
AndyA 3:1459d2aa6b97 252 writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_CFG2, 0x0607); //LDE_CFG2 for 64MHz PRF
AndyA 3:1459d2aa6b97 253
AndyA 3:1459d2aa6b97 254 uint16_t replicaCoeff;
AndyA 4:5f1025df5530 255 switch (systemConfig.getPreambleCode()) {
AndyA 3:1459d2aa6b97 256 default:
AndyA 3:1459d2aa6b97 257 case 1:
AndyA 3:1459d2aa6b97 258 case 2:
AndyA 3:1459d2aa6b97 259 replicaCoeff = 0x5998;
AndyA 3:1459d2aa6b97 260 break;
AndyA 3:1459d2aa6b97 261 case 3:
AndyA 3:1459d2aa6b97 262 replicaCoeff = 0x51EA;
AndyA 3:1459d2aa6b97 263 break;
AndyA 3:1459d2aa6b97 264 case 4:
AndyA 3:1459d2aa6b97 265 replicaCoeff = 0x428E;
AndyA 3:1459d2aa6b97 266 break;
AndyA 3:1459d2aa6b97 267 case 5:
AndyA 3:1459d2aa6b97 268 replicaCoeff = 0x451E;
AndyA 3:1459d2aa6b97 269 break;
AndyA 3:1459d2aa6b97 270 case 6:
AndyA 3:1459d2aa6b97 271 replicaCoeff = 0x2E14;
AndyA 3:1459d2aa6b97 272 break;
AndyA 3:1459d2aa6b97 273 case 7:
AndyA 3:1459d2aa6b97 274 replicaCoeff = 0x8000;
AndyA 3:1459d2aa6b97 275 break;
AndyA 3:1459d2aa6b97 276 case 8:
AndyA 3:1459d2aa6b97 277 replicaCoeff = 0x51EA;
AndyA 3:1459d2aa6b97 278 break;
AndyA 3:1459d2aa6b97 279 case 9:
AndyA 3:1459d2aa6b97 280 replicaCoeff = 0x28F4;
AndyA 3:1459d2aa6b97 281 break;
AndyA 3:1459d2aa6b97 282 case 10:
AndyA 3:1459d2aa6b97 283 replicaCoeff = 0x3332;
AndyA 3:1459d2aa6b97 284 break;
AndyA 3:1459d2aa6b97 285 case 11:
AndyA 3:1459d2aa6b97 286 replicaCoeff = 0x3AE0;
AndyA 3:1459d2aa6b97 287 break;
AndyA 3:1459d2aa6b97 288 case 12:
AndyA 3:1459d2aa6b97 289 replicaCoeff = 0x3D70;
AndyA 3:1459d2aa6b97 290 break;
AndyA 3:1459d2aa6b97 291 case 13:
AndyA 3:1459d2aa6b97 292 replicaCoeff = 0x3AE0;
AndyA 3:1459d2aa6b97 293 break;
AndyA 3:1459d2aa6b97 294 case 14:
AndyA 3:1459d2aa6b97 295 replicaCoeff = 0x35C2;
AndyA 3:1459d2aa6b97 296 break;
AndyA 3:1459d2aa6b97 297 case 15:
AndyA 3:1459d2aa6b97 298 replicaCoeff = 0x2B84;
AndyA 3:1459d2aa6b97 299 break;
AndyA 3:1459d2aa6b97 300 case 16:
AndyA 3:1459d2aa6b97 301 replicaCoeff = 0x35C2;
AndyA 3:1459d2aa6b97 302 break;
AndyA 3:1459d2aa6b97 303 case 17:
AndyA 3:1459d2aa6b97 304 replicaCoeff = 0x3332;
AndyA 3:1459d2aa6b97 305 break;
AndyA 3:1459d2aa6b97 306 case 18:
AndyA 3:1459d2aa6b97 307 replicaCoeff = 0x35C2;
AndyA 3:1459d2aa6b97 308 break;
AndyA 3:1459d2aa6b97 309 case 19:
AndyA 3:1459d2aa6b97 310 replicaCoeff = 0x35C2;
AndyA 3:1459d2aa6b97 311 break;
AndyA 3:1459d2aa6b97 312 case 20:
AndyA 3:1459d2aa6b97 313 replicaCoeff = 0x47AE;
AndyA 3:1459d2aa6b97 314 break;
AndyA 3:1459d2aa6b97 315 case 21:
AndyA 3:1459d2aa6b97 316 replicaCoeff = 0x3AE0;
AndyA 3:1459d2aa6b97 317 break;
AndyA 3:1459d2aa6b97 318 case 22:
AndyA 3:1459d2aa6b97 319 replicaCoeff = 0x3850;
AndyA 3:1459d2aa6b97 320 break;
AndyA 3:1459d2aa6b97 321 case 23:
AndyA 3:1459d2aa6b97 322 replicaCoeff = 0x30A2;
AndyA 3:1459d2aa6b97 323 break;
AndyA 3:1459d2aa6b97 324 case 24:
AndyA 3:1459d2aa6b97 325 replicaCoeff = 0x3850;
AndyA 3:1459d2aa6b97 326 break;
AndyA 3:1459d2aa6b97 327 }
AndyA 3:1459d2aa6b97 328
AndyA 4:5f1025df5530 329 if (systemConfig.getDataRate() == DW1000Setup::kbps110)
AndyA 3:1459d2aa6b97 330 replicaCoeff = replicaCoeff>>3;
AndyA 3:1459d2aa6b97 331
AndyA 3:1459d2aa6b97 332 writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_REPC, replicaCoeff);
AndyA 3:1459d2aa6b97 333
AndyA 3:1459d2aa6b97 334 loadLDE();
AndyA 3:1459d2aa6b97 335 }
AndyA 3:1459d2aa6b97 336
AndyA 3:1459d2aa6b97 337 void DW1000::setupChannel()
AndyA 3:1459d2aa6b97 338 {
AndyA 4:5f1025df5530 339 uint32_t registerValue = 0;
AndyA 3:1459d2aa6b97 340
AndyA 4:5f1025df5530 341 registerValue = systemConfig.getChannel(); // set Tx channel
AndyA 4:5f1025df5530 342 registerValue |= systemConfig.getChannel()<<4; // set Rx channel
AndyA 3:1459d2aa6b97 343
AndyA 4:5f1025df5530 344 if (systemConfig.getPRF() == DW1000Setup::prf16MHz) // set PRF (2 bit value 01 or 10)
AndyA 3:1459d2aa6b97 345 registerValue |= 0x01 << 18;
AndyA 3:1459d2aa6b97 346 else
AndyA 3:1459d2aa6b97 347 registerValue |= 0x02 << 18;
AndyA 3:1459d2aa6b97 348
AndyA 8:0b408e77b701 349 if (systemConfig.getSfd() == DW1000Setup::decaWave)
AndyA 3:1459d2aa6b97 350 registerValue |= 0x01 << 17; // enable DW own SFD
AndyA 4:5f1025df5530 351
AndyA 8:0b408e77b701 352 if (systemConfig.getSfd() == DW1000Setup::user) {
AndyA 4:5f1025df5530 353 registerValue |= 0x01 << 20; // enable user set SFD Tx
AndyA 4:5f1025df5530 354 registerValue |= 0x01 << 21; // enable user set SFD Rx
AndyA 3:1459d2aa6b97 355 }
AndyA 3:1459d2aa6b97 356
AndyA 4:5f1025df5530 357 registerValue |= systemConfig.getPreambleCode() << 22; // set Tx preamble code
AndyA 4:5f1025df5530 358 registerValue |= systemConfig.getPreambleCode() << 27; // set Rx preamble code
AndyA 3:1459d2aa6b97 359
AndyA 4:5f1025df5530 360 writeRegister32(DW1000_CHAN_CTRL, 0, registerValue);
AndyA 3:1459d2aa6b97 361 }
AndyA 3:1459d2aa6b97 362
AndyA 15:6faab70a5b19 363 uint8_t DW1000::readXTALTune() {
AndyA 15:6faab70a5b19 364 return readRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_XTALT);
AndyA 15:6faab70a5b19 365 }
AndyA 15:6faab70a5b19 366
AndyA 15:6faab70a5b19 367 void DW1000::setXTALTune(uint8_t value) {
AndyA 15:6faab70a5b19 368 value &= 0x1f; // mask reserved bits
AndyA 15:6faab70a5b19 369 value |= 0x60; // set reserved bits
AndyA 15:6faab70a5b19 370 writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_XTALT,value);
AndyA 15:6faab70a5b19 371 }
AndyA 3:1459d2aa6b97 372
AndyA 9:326bf149c8bc 373 uint8_t DW1000::powerToRegValue(float powerdB)
AndyA 3:1459d2aa6b97 374 {
AndyA 3:1459d2aa6b97 375 // course power control - 0 = 18dB, 6 = 0dB in 3dB steps.
AndyA 9:326bf149c8bc 376 uint8_t course = powerdB / 3;
AndyA 3:1459d2aa6b97 377
AndyA 3:1459d2aa6b97 378 if(course > 6)
AndyA 3:1459d2aa6b97 379 course = 6;
AndyA 3:1459d2aa6b97 380
AndyA 3:1459d2aa6b97 381 // remaining power
AndyA 9:326bf149c8bc 382 powerdB -= course * 3;
AndyA 3:1459d2aa6b97 383
AndyA 3:1459d2aa6b97 384 // value in reg is inverse.
AndyA 3:1459d2aa6b97 385 course = 6-course;
AndyA 3:1459d2aa6b97 386
AndyA 3:1459d2aa6b97 387 // fine control in steps of 0.5dB
AndyA 9:326bf149c8bc 388 uint8_t fine = powerdB / 0.5f;
AndyA 3:1459d2aa6b97 389 if (fine > 31)
AndyA 3:1459d2aa6b97 390 fine = 31;
AndyA 3:1459d2aa6b97 391
AndyA 9:326bf149c8bc 392 return (course << 5) | fine;
AndyA 9:326bf149c8bc 393 }
AndyA 3:1459d2aa6b97 394
AndyA 9:326bf149c8bc 395
AndyA 9:326bf149c8bc 396 float DW1000::regToPowerValue(uint8_t powerVal)
AndyA 9:326bf149c8bc 397 {
AndyA 9:326bf149c8bc 398
AndyA 9:326bf149c8bc 399 int course = powerVal >> 5;
AndyA 9:326bf149c8bc 400 if (course==7) // off
AndyA 9:326bf149c8bc 401 return 0;
AndyA 9:326bf149c8bc 402
AndyA 9:326bf149c8bc 403 course = (6-course)*3;
AndyA 9:326bf149c8bc 404
AndyA 9:326bf149c8bc 405 int fine = (powerVal & 0x1f);
AndyA 3:1459d2aa6b97 406
AndyA 9:326bf149c8bc 407 return course + fine/2.0f;
AndyA 9:326bf149c8bc 408 }
AndyA 9:326bf149c8bc 409
AndyA 9:326bf149c8bc 410
AndyA 9:326bf149c8bc 411 void DW1000::setupPower()
AndyA 9:326bf149c8bc 412 {
AndyA 9:326bf149c8bc 413 const float *powerPtr = systemConfig.getTxPowers();
AndyA 9:326bf149c8bc 414
AndyA 9:326bf149c8bc 415 uint32_t powerReg = powerToRegValue(*powerPtr);
AndyA 9:326bf149c8bc 416 powerReg |= powerToRegValue(*(powerPtr+1)) << 8;
AndyA 9:326bf149c8bc 417 powerReg |= powerToRegValue(*(powerPtr+2)) << 16;
AndyA 9:326bf149c8bc 418 powerReg |= powerToRegValue(*(powerPtr+3)) << 24;
AndyA 9:326bf149c8bc 419 writeRegister32(DW1000_TX_POWER,0,powerReg);
AndyA 3:1459d2aa6b97 420 }
AndyA 3:1459d2aa6b97 421
AndyA 3:1459d2aa6b97 422 // transmit power: 0 to 33.5 dB gain in steps of 0.5. Inputs are in 10ths of a dB (0 to 335)
AndyA 9:326bf149c8bc 423 void DW1000::setTxPower(float normalPowerdB, float boost500, float boost250, float boost125)
AndyA 3:1459d2aa6b97 424 {
AndyA 15:6faab70a5b19 425
AndyA 9:326bf149c8bc 426 if(normalPowerdB > 33.5)
AndyA 9:326bf149c8bc 427 normalPowerdB = 33.5;
AndyA 4:5f1025df5530 428
AndyA 9:326bf149c8bc 429 if (boost500 < normalPowerdB)
AndyA 9:326bf149c8bc 430 boost500 = normalPowerdB;
AndyA 9:326bf149c8bc 431 if(boost500 > 33.5)
AndyA 9:326bf149c8bc 432 boost500 = 33.5;
AndyA 0:bddb8cd5e7df 433
AndyA 3:1459d2aa6b97 434 if (boost250 < boost500)
AndyA 3:1459d2aa6b97 435 boost250 = boost500;
AndyA 9:326bf149c8bc 436 if(boost250 > 33.5)
AndyA 9:326bf149c8bc 437 boost250 = 33.5;
AndyA 3:1459d2aa6b97 438
AndyA 3:1459d2aa6b97 439 if (boost125 < boost250)
AndyA 3:1459d2aa6b97 440 boost125 = boost250;
AndyA 9:326bf149c8bc 441 if(boost125 > 33.5)
AndyA 9:326bf149c8bc 442 boost125 = 33.5;
AndyA 3:1459d2aa6b97 443
AndyA 4:5f1025df5530 444 if (systemConfig.getSmartPower() == false) {
AndyA 9:326bf149c8bc 445 boost500 = normalPowerdB;
AndyA 9:326bf149c8bc 446 boost250 = normalPowerdB;
AndyA 9:326bf149c8bc 447 boost125 = normalPowerdB;
AndyA 4:5f1025df5530 448 }
AndyA 4:5f1025df5530 449
AndyA 9:326bf149c8bc 450 uint32_t powerReg = powerToRegValue(normalPowerdB);
AndyA 3:1459d2aa6b97 451 powerReg |= powerToRegValue(boost500) << 8;
AndyA 3:1459d2aa6b97 452 powerReg |= powerToRegValue(boost250) << 16;
AndyA 3:1459d2aa6b97 453 powerReg |= powerToRegValue(boost125) << 24;
AndyA 9:326bf149c8bc 454 writeRegister32(DW1000_TX_POWER,0,powerReg);
AndyA 15:6faab70a5b19 455
AndyA 9:326bf149c8bc 456 systemConfig.setSmartTxPower(normalPowerdB,boost500,boost250,boost125); // update the systemConfig
AndyA 9:326bf149c8bc 457 }
AndyA 9:326bf149c8bc 458
AndyA 9:326bf149c8bc 459 uint32_t DW1000::getTxPower(float *power,float *boost500, float *boost250, float*boost125)
AndyA 9:326bf149c8bc 460 {
AndyA 8:0b408e77b701 461
AndyA 9:326bf149c8bc 462 uint32_t value = readRegister32(DW1000_TX_POWER,0);
AndyA 9:326bf149c8bc 463 if (power)
AndyA 9:326bf149c8bc 464 *power = regToPowerValue(value&0x000000ff);
AndyA 9:326bf149c8bc 465 if (boost500)
AndyA 9:326bf149c8bc 466 *boost500 = regToPowerValue((value&0x0000ff00)>>8);
AndyA 9:326bf149c8bc 467 if (boost250)
AndyA 9:326bf149c8bc 468 *boost250 = regToPowerValue((value&0x00ff0000)>>16);
AndyA 9:326bf149c8bc 469 if (boost125)
AndyA 9:326bf149c8bc 470 *boost125 = regToPowerValue((value&0xff000000)>>24);
AndyA 9:326bf149c8bc 471 return value;
AndyA 3:1459d2aa6b97 472 }
AndyA 3:1459d2aa6b97 473
AndyA 3:1459d2aa6b97 474 void DW1000::setupAnalogRF()
AndyA 3:1459d2aa6b97 475 {
AndyA 4:5f1025df5530 476 switch (systemConfig.getChannel()) {
AndyA 3:1459d2aa6b97 477 case 1:
AndyA 3:1459d2aa6b97 478 writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00005C40);
AndyA 3:1459d2aa6b97 479 break;
AndyA 3:1459d2aa6b97 480 case 2:
AndyA 3:1459d2aa6b97 481 writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00045CA0);
AndyA 3:1459d2aa6b97 482 break;
AndyA 3:1459d2aa6b97 483 case 3:
AndyA 3:1459d2aa6b97 484 writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00086CC0);
AndyA 3:1459d2aa6b97 485 break;
AndyA 3:1459d2aa6b97 486 case 4:
AndyA 3:1459d2aa6b97 487 writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x00045C80);
AndyA 3:1459d2aa6b97 488 break;
AndyA 3:1459d2aa6b97 489 case 5:
AndyA 3:1459d2aa6b97 490 default:
AndyA 3:1459d2aa6b97 491 writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x001E3FE0);
AndyA 3:1459d2aa6b97 492 break;
AndyA 3:1459d2aa6b97 493 case 7:
AndyA 3:1459d2aa6b97 494 writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x001E7DE0);
AndyA 3:1459d2aa6b97 495 break;
AndyA 3:1459d2aa6b97 496 }
AndyA 3:1459d2aa6b97 497
AndyA 4:5f1025df5530 498 switch (systemConfig.getChannel()) {
AndyA 3:1459d2aa6b97 499 case 1:
AndyA 3:1459d2aa6b97 500 case 2:
AndyA 3:1459d2aa6b97 501 case 3:
AndyA 3:1459d2aa6b97 502 case 5:
AndyA 3:1459d2aa6b97 503 default:
AndyA 3:1459d2aa6b97 504 writeRegister8(DW1000_RF_CONF, DWRFCONF_RF_RXCTRLH, 0xD8);
AndyA 3:1459d2aa6b97 505 break;
AndyA 3:1459d2aa6b97 506 case 4:
AndyA 3:1459d2aa6b97 507 case 7:
AndyA 3:1459d2aa6b97 508 writeRegister8(DW1000_RF_CONF, DWRFCONF_RF_RXCTRLH, 0xBC);
AndyA 3:1459d2aa6b97 509 break;
AndyA 3:1459d2aa6b97 510 }
AndyA 3:1459d2aa6b97 511
AndyA 3:1459d2aa6b97 512 loadLDOTUNE();
AndyA 3:1459d2aa6b97 513
AndyA 3:1459d2aa6b97 514 }
AndyA 3:1459d2aa6b97 515
AndyA 3:1459d2aa6b97 516 void DW1000::setupTxCalibration()
AndyA 3:1459d2aa6b97 517 {
AndyA 4:5f1025df5530 518 switch (systemConfig.getChannel()) {
AndyA 3:1459d2aa6b97 519 case 1:
AndyA 3:1459d2aa6b97 520 writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC9);
AndyA 3:1459d2aa6b97 521 break;
AndyA 3:1459d2aa6b97 522 case 2:
AndyA 3:1459d2aa6b97 523 writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC2);
AndyA 3:1459d2aa6b97 524 break;
AndyA 3:1459d2aa6b97 525 case 3:
AndyA 3:1459d2aa6b97 526 writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC5);
AndyA 3:1459d2aa6b97 527 break;
AndyA 3:1459d2aa6b97 528 case 4:
AndyA 3:1459d2aa6b97 529 writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0x95);
AndyA 3:1459d2aa6b97 530 break;
AndyA 3:1459d2aa6b97 531 case 5:
AndyA 3:1459d2aa6b97 532 default:
AndyA 3:1459d2aa6b97 533 writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC0);
AndyA 3:1459d2aa6b97 534 break;
AndyA 3:1459d2aa6b97 535 case 7:
AndyA 3:1459d2aa6b97 536 writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0x93);
AndyA 3:1459d2aa6b97 537 break;
AndyA 3:1459d2aa6b97 538 }
AndyA 3:1459d2aa6b97 539 }
AndyA 3:1459d2aa6b97 540
AndyA 3:1459d2aa6b97 541 void DW1000::setupFreqSynth()
AndyA 3:1459d2aa6b97 542 {
AndyA 3:1459d2aa6b97 543
AndyA 4:5f1025df5530 544 switch (systemConfig.getChannel()) {
AndyA 3:1459d2aa6b97 545 case 1:
AndyA 3:1459d2aa6b97 546 writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x09000407); //FS_PLLCFG for channel 1
AndyA 3:1459d2aa6b97 547 writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0x1E);
AndyA 3:1459d2aa6b97 548 break;
AndyA 3:1459d2aa6b97 549 case 2:
AndyA 3:1459d2aa6b97 550 case 4:
AndyA 3:1459d2aa6b97 551 writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x08400508); //FS_PLLCFG for channel 2,4
AndyA 3:1459d2aa6b97 552 writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0x26);
AndyA 3:1459d2aa6b97 553 break;
AndyA 3:1459d2aa6b97 554 case 3:
AndyA 3:1459d2aa6b97 555 writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x08401009); //FS_PLLCFG for channel 3
AndyA 3:1459d2aa6b97 556 writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0x5E);
AndyA 3:1459d2aa6b97 557 break;
AndyA 3:1459d2aa6b97 558 case 5:
AndyA 3:1459d2aa6b97 559 case 7:
AndyA 3:1459d2aa6b97 560 default:
AndyA 3:1459d2aa6b97 561 writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x0800041D); //FS_PLLCFG for channel 5,7
AndyA 3:1459d2aa6b97 562 writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0xBE); //FS_PLLTUNE for channel 5
AndyA 3:1459d2aa6b97 563 break;
AndyA 3:1459d2aa6b97 564 }
AndyA 3:1459d2aa6b97 565 }
AndyA 3:1459d2aa6b97 566
AndyA 3:1459d2aa6b97 567 void DW1000::setupTxFrameCtrl()
AndyA 3:1459d2aa6b97 568 {
AndyA 4:5f1025df5530 569 uint32_t frameCtrlValue = 0;
AndyA 4:5f1025df5530 570 switch (systemConfig.getDataRate()) {
AndyA 4:5f1025df5530 571 case DW1000Setup::kbps110:
AndyA 3:1459d2aa6b97 572 break;
AndyA 4:5f1025df5530 573 case DW1000Setup::kbps850:
AndyA 3:1459d2aa6b97 574 frameCtrlValue |= 0x01<<13;
AndyA 3:1459d2aa6b97 575 break;
AndyA 4:5f1025df5530 576 case DW1000Setup::kbps6800:
AndyA 3:1459d2aa6b97 577 default:
AndyA 3:1459d2aa6b97 578 frameCtrlValue |= 0x02<<13;
AndyA 3:1459d2aa6b97 579 break;
AndyA 3:1459d2aa6b97 580 }
AndyA 3:1459d2aa6b97 581 frameCtrlValue |= 0x01<<15;
AndyA 3:1459d2aa6b97 582
AndyA 4:5f1025df5530 583 if (systemConfig.getPRF() == DW1000Setup::prf16MHz)
AndyA 3:1459d2aa6b97 584 frameCtrlValue |= 0x01<<16;
AndyA 3:1459d2aa6b97 585 else
AndyA 3:1459d2aa6b97 586 frameCtrlValue |= 0x02<<16;
AndyA 3:1459d2aa6b97 587
AndyA 4:5f1025df5530 588 switch (systemConfig.getPreambleLength()) {
AndyA 4:5f1025df5530 589 case DW1000Setup::pre64:
AndyA 3:1459d2aa6b97 590 frameCtrlValue |= 0x01<<18; // TXPSR
AndyA 3:1459d2aa6b97 591 frameCtrlValue |= 0x00<<20; // PE
AndyA 3:1459d2aa6b97 592 break;
AndyA 4:5f1025df5530 593 case DW1000Setup::pre128:
AndyA 3:1459d2aa6b97 594 default:
AndyA 3:1459d2aa6b97 595 frameCtrlValue |= 0x01<<18; // TXPSR
AndyA 3:1459d2aa6b97 596 frameCtrlValue |= 0x01<<20; // PE
AndyA 3:1459d2aa6b97 597 break;
AndyA 4:5f1025df5530 598 case DW1000Setup::pre256:
AndyA 3:1459d2aa6b97 599 frameCtrlValue |= 0x01<<18; // TXPSR
AndyA 3:1459d2aa6b97 600 frameCtrlValue |= 0x02<<20; // PE
AndyA 3:1459d2aa6b97 601 break;
AndyA 4:5f1025df5530 602 case DW1000Setup::pre512:
AndyA 3:1459d2aa6b97 603 frameCtrlValue |= 0x01<<18; // TXPSR
AndyA 3:1459d2aa6b97 604 frameCtrlValue |= 0x03<<20; // PE
AndyA 3:1459d2aa6b97 605 break;
AndyA 4:5f1025df5530 606 case DW1000Setup::pre1024:
AndyA 3:1459d2aa6b97 607 frameCtrlValue |= 0x02<<18; // TXPSR
AndyA 3:1459d2aa6b97 608 frameCtrlValue |= 0x00<<20; // PE
AndyA 3:1459d2aa6b97 609 break;
AndyA 4:5f1025df5530 610 case DW1000Setup::pre1536:
AndyA 3:1459d2aa6b97 611 frameCtrlValue |= 0x02<<18; // TXPSR
AndyA 3:1459d2aa6b97 612 frameCtrlValue |= 0x01<<20; // PE
AndyA 3:1459d2aa6b97 613 break;
AndyA 4:5f1025df5530 614 case DW1000Setup::pre2048:
AndyA 3:1459d2aa6b97 615 frameCtrlValue |= 0x02<<18; // TXPSR
AndyA 3:1459d2aa6b97 616 frameCtrlValue |= 0x02<<20; // PE
AndyA 3:1459d2aa6b97 617 break;
AndyA 4:5f1025df5530 618 case DW1000Setup::pre4096:
AndyA 3:1459d2aa6b97 619 frameCtrlValue |= 0x03<<18; // TXPSR
AndyA 3:1459d2aa6b97 620 frameCtrlValue |= 0x00<<20; // PE
AndyA 3:1459d2aa6b97 621 break;
AndyA 3:1459d2aa6b97 622 }
AndyA 4:5f1025df5530 623 writeRegister32(DW1000_TX_FCTRL,0,frameCtrlValue);
AndyA 0:bddb8cd5e7df 624 }
AndyA 0:bddb8cd5e7df 625
AndyA 10:f1e3c04080d6 626 void DW1000::getFullQualityMetrics(uint16_t *std_noise, uint16_t *fp_amp1, uint16_t *fp_amp2, uint16_t *fp_amp3,
AndyA 15:6faab70a5b19 627 uint16_t *cir_pwr, uint16_t *preAmbleAcc, uint16_t *preAmbleAcc_NoSat)
AndyA 10:f1e3c04080d6 628 {
AndyA 10:f1e3c04080d6 629 *fp_amp1 = readRegister16(DW1000_RX_TIME,7);
AndyA 10:f1e3c04080d6 630 *std_noise = readRegister16(DW1000_RX_FQUAL,0);
AndyA 10:f1e3c04080d6 631 *fp_amp2 = readRegister16(DW1000_RX_FQUAL,2);
AndyA 10:f1e3c04080d6 632 *fp_amp3 = readRegister16(DW1000_RX_FQUAL,4);
AndyA 10:f1e3c04080d6 633 *cir_pwr = readRegister16(DW1000_RX_FQUAL,6);
AndyA 10:f1e3c04080d6 634 *preAmbleAcc = readRegister16(DW1000_RX_FINFO,4) >> 4;
AndyA 10:f1e3c04080d6 635 *preAmbleAcc_NoSat = readRegister16(DW1000_DRX_CONF,DWDRX_RXPAC_NOSAT);
AndyA 10:f1e3c04080d6 636 }
AndyA 9:326bf149c8bc 637
AndyA 15:6faab70a5b19 638 void DW1000::getFullLEDMetrics(uint16_t *led_thresh, uint16_t *led_ppindx, uint16_t *led_ppampl)
AndyA 15:6faab70a5b19 639 {
AndyA 13:8718966cd81e 640 *led_thresh = readRegister16(DW1000_LDE_CTRL,DWLDE_LDE_THRESH);
AndyA 13:8718966cd81e 641 *led_ppindx = readRegister16(DW1000_LDE_CTRL,DWLDE_LDE_PPINDX);
AndyA 15:6faab70a5b19 642 *led_ppampl = readRegister16(DW1000_LDE_CTRL,DWLDE_LDE_PPAMPL);
AndyA 15:6faab70a5b19 643 }
AndyA 13:8718966cd81e 644
AndyA 13:8718966cd81e 645
AndyA 9:326bf149c8bc 646 #define SQR(x) ((float)(x) * (float)(x))
AndyA 9:326bf149c8bc 647
AndyA 9:326bf149c8bc 648 void DW1000::getRxSignalPower(float *direct, float *total)
AndyA 9:326bf149c8bc 649 {
AndyA 9:326bf149c8bc 650 uint16_t firstPathAmp1 = readRegister16(DW1000_RX_TIME,7);
AndyA 9:326bf149c8bc 651 uint16_t firstPathAmp2 = readRegister16(DW1000_RX_FQUAL,2);
AndyA 9:326bf149c8bc 652 uint16_t firstPathAmp3 = readRegister16(DW1000_RX_FQUAL,4);
AndyA 9:326bf149c8bc 653 uint16_t preambleAcc = readRegister16(DW1000_RX_FINFO,4) >> 4;
AndyA 9:326bf149c8bc 654 uint16_t preambleAccNoSat = readRegister16(DW1000_DRX_CONF,DWDRX_RXPAC_NOSAT);
AndyA 9:326bf149c8bc 655 uint16_t channelImpulse = readRegister16(DW1000_RX_FQUAL,6);
AndyA 9:326bf149c8bc 656
AndyA 9:326bf149c8bc 657 if (preambleAcc == preambleAccNoSat) {
AndyA 9:326bf149c8bc 658 if (systemConfig.getSfd() == DW1000Setup::standard) {
AndyA 9:326bf149c8bc 659 if (systemConfig.getDataRate() == DW1000Setup::kbps110)
AndyA 9:326bf149c8bc 660 preambleAcc += -64;
AndyA 9:326bf149c8bc 661 else
AndyA 9:326bf149c8bc 662 preambleAcc += -5;
AndyA 9:326bf149c8bc 663 } else {
AndyA 9:326bf149c8bc 664 if (systemConfig.getDataRate() == DW1000Setup::kbps110)
AndyA 9:326bf149c8bc 665 preambleAcc += -82;
AndyA 9:326bf149c8bc 666 else
AndyA 9:326bf149c8bc 667 preambleAcc += -10;
AndyA 9:326bf149c8bc 668 }
AndyA 9:326bf149c8bc 669 }
AndyA 9:326bf149c8bc 670
AndyA 9:326bf149c8bc 671
AndyA 9:326bf149c8bc 672 float directPower = 10*log10( (SQR(firstPathAmp1) + SQR(firstPathAmp2) + SQR(firstPathAmp3))/SQR(preambleAcc));
AndyA 9:326bf149c8bc 673
AndyA 9:326bf149c8bc 674 float rxSignalPower = 10*log10( ((float)channelImpulse * (1<<17))/SQR(preambleAcc) );
AndyA 9:326bf149c8bc 675
AndyA 9:326bf149c8bc 676 if (systemConfig.getPRF() == DW1000Setup::prf16MHz) {
AndyA 9:326bf149c8bc 677 directPower -= 113.77;
AndyA 9:326bf149c8bc 678 rxSignalPower -= 113.77;
AndyA 9:326bf149c8bc 679 } else {
AndyA 9:326bf149c8bc 680 directPower -= 121.74;
AndyA 9:326bf149c8bc 681 rxSignalPower -= 121.74;
AndyA 9:326bf149c8bc 682 }
AndyA 9:326bf149c8bc 683
AndyA 9:326bf149c8bc 684 *direct = directPower;
AndyA 9:326bf149c8bc 685 *total = rxSignalPower;
AndyA 9:326bf149c8bc 686
AndyA 9:326bf149c8bc 687 }
AndyA 9:326bf149c8bc 688
AndyA 9:326bf149c8bc 689
AndyA 10:f1e3c04080d6 690 #undef SQR
AndyA 10:f1e3c04080d6 691
AndyA 10:f1e3c04080d6 692 void DW1000::getFirstPath(uint16_t *fp_amp2,uint16_t *fp_amp3)
AndyA 9:326bf149c8bc 693 {
AndyA 10:f1e3c04080d6 694 *fp_amp2 = readRegister16(DW1000_RX_FQUAL,2);
AndyA 10:f1e3c04080d6 695 *fp_amp3 = readRegister16(DW1000_RX_FQUAL,4);
AndyA 10:f1e3c04080d6 696 }
AndyA 9:326bf149c8bc 697
AndyA 9:326bf149c8bc 698
AndyA 9:326bf149c8bc 699
AndyA 0:bddb8cd5e7df 700 void DW1000::setRxDelay(uint16_t ticks)
AndyA 0:bddb8cd5e7df 701 {
AndyA 0:bddb8cd5e7df 702 writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_RXANTD, ticks);
AndyA 0:bddb8cd5e7df 703 }
AndyA 0:bddb8cd5e7df 704 void DW1000::setTxDelay(uint16_t ticks)
AndyA 0:bddb8cd5e7df 705 {
AndyA 0:bddb8cd5e7df 706 writeRegister16(DW1000_TX_ANTD, 0, ticks);
AndyA 0:bddb8cd5e7df 707 }
AndyA 0:bddb8cd5e7df 708
AndyA 0:bddb8cd5e7df 709 void DW1000::setCallbacks(void (*callbackRX)(void), void (*callbackTX)(void))
AndyA 0:bddb8cd5e7df 710 {
AndyA 0:bddb8cd5e7df 711 bool RX = false;
AndyA 0:bddb8cd5e7df 712 bool TX = false;
AndyA 0:bddb8cd5e7df 713 if (callbackRX) {
AndyA 0:bddb8cd5e7df 714 DW1000::callbackRX.attach(callbackRX);
AndyA 0:bddb8cd5e7df 715 RX = true;
AndyA 0:bddb8cd5e7df 716 }
AndyA 0:bddb8cd5e7df 717 if (callbackTX) {
AndyA 0:bddb8cd5e7df 718 DW1000::callbackTX.attach(callbackTX);
AndyA 0:bddb8cd5e7df 719 TX = true;
AndyA 0:bddb8cd5e7df 720 }
AndyA 0:bddb8cd5e7df 721 setInterrupt(RX,TX);
AndyA 0:bddb8cd5e7df 722 }
AndyA 0:bddb8cd5e7df 723
AndyA 0:bddb8cd5e7df 724 uint32_t DW1000::getDeviceID()
AndyA 0:bddb8cd5e7df 725 {
AndyA 0:bddb8cd5e7df 726 uint32_t result;
AndyA 0:bddb8cd5e7df 727 readRegister(DW1000_DEV_ID, 0, (uint8_t*)&result, 4);
AndyA 0:bddb8cd5e7df 728 return result;
AndyA 0:bddb8cd5e7df 729 }
AndyA 0:bddb8cd5e7df 730
AndyA 0:bddb8cd5e7df 731 uint64_t DW1000::getEUI()
AndyA 0:bddb8cd5e7df 732 {
AndyA 0:bddb8cd5e7df 733 uint64_t result;
AndyA 0:bddb8cd5e7df 734 readRegister(DW1000_EUI, 0, (uint8_t*)&result, 8);
AndyA 0:bddb8cd5e7df 735 return result;
AndyA 0:bddb8cd5e7df 736 }
AndyA 0:bddb8cd5e7df 737
AndyA 0:bddb8cd5e7df 738 void DW1000::setEUI(uint64_t EUI)
AndyA 0:bddb8cd5e7df 739 {
AndyA 0:bddb8cd5e7df 740 writeRegister(DW1000_EUI, 0, (uint8_t*)&EUI, 8);
AndyA 0:bddb8cd5e7df 741 }
AndyA 0:bddb8cd5e7df 742
AndyA 0:bddb8cd5e7df 743
AndyA 0:bddb8cd5e7df 744 float DW1000::getVoltage()
AndyA 0:bddb8cd5e7df 745 {
AndyA 0:bddb8cd5e7df 746 uint8_t data;
AndyA 0:bddb8cd5e7df 747
AndyA 0:bddb8cd5e7df 748 writeRegister8(DW1000_RF_CONF, 0x11, 0x80);
AndyA 0:bddb8cd5e7df 749 writeRegister8(DW1000_RF_CONF, 0x12, 0x0A);
AndyA 0:bddb8cd5e7df 750 writeRegister8(DW1000_RF_CONF, 0x12, 0x0F);
AndyA 0:bddb8cd5e7df 751 writeRegister8(DW1000_TX_CAL, 0x00, 0x01);
AndyA 0:bddb8cd5e7df 752 writeRegister8(DW1000_TX_CAL, 0x00, 0x00);
AndyA 0:bddb8cd5e7df 753 data = readRegister8(DW1000_TX_CAL, 0x03); // get the 8-Bit reading for Voltage
AndyA 1:dcbd071f38d5 754 float Voltage = (float)(data - (readOTP(0x08)&0x00ff)) *0.00578 + 3.3;
AndyA 0:bddb8cd5e7df 755 return Voltage;
AndyA 0:bddb8cd5e7df 756 }
AndyA 0:bddb8cd5e7df 757
AndyA 0:bddb8cd5e7df 758 float DW1000::getTemperature()
AndyA 0:bddb8cd5e7df 759 {
AndyA 0:bddb8cd5e7df 760 uint8_t data;
AndyA 0:bddb8cd5e7df 761
AndyA 0:bddb8cd5e7df 762 writeRegister8(DW1000_RF_CONF, 0x11, 0x80);
AndyA 0:bddb8cd5e7df 763 writeRegister8(DW1000_RF_CONF, 0x12, 0x0A);
AndyA 0:bddb8cd5e7df 764 writeRegister8(DW1000_RF_CONF, 0x12, 0x0F);
AndyA 0:bddb8cd5e7df 765 writeRegister8(DW1000_TX_CAL, 0x00, 0x01);
AndyA 0:bddb8cd5e7df 766 writeRegister8(DW1000_TX_CAL, 0x00, 0x00);
AndyA 0:bddb8cd5e7df 767 data = readRegister16(DW1000_TX_CAL, 0x04); // get the 8-Bit reading for Temperature
AndyA 1:dcbd071f38d5 768 float temperature = (float)(data - (readOTP(0x09) & 0x00ff))*0.9 + 23;
AndyA 0:bddb8cd5e7df 769 return temperature;
AndyA 0:bddb8cd5e7df 770 }
AndyA 0:bddb8cd5e7df 771
AndyA 0:bddb8cd5e7df 772
AndyA 0:bddb8cd5e7df 773 uint64_t DW1000::getStatus()
AndyA 0:bddb8cd5e7df 774 {
AndyA 0:bddb8cd5e7df 775 return readRegister40(DW1000_SYS_STATUS, 0);
AndyA 0:bddb8cd5e7df 776 }
AndyA 0:bddb8cd5e7df 777
AndyA 0:bddb8cd5e7df 778 uint64_t DW1000::getRXTimestamp()
AndyA 0:bddb8cd5e7df 779 {
AndyA 0:bddb8cd5e7df 780 return readRegister40(DW1000_RX_TIME, 0);
AndyA 0:bddb8cd5e7df 781 }
AndyA 0:bddb8cd5e7df 782
AndyA 0:bddb8cd5e7df 783 uint64_t DW1000::getTXTimestamp()
AndyA 0:bddb8cd5e7df 784 {
AndyA 0:bddb8cd5e7df 785 return readRegister40(DW1000_TX_TIME, 0);
AndyA 0:bddb8cd5e7df 786 }
AndyA 0:bddb8cd5e7df 787
AndyA 0:bddb8cd5e7df 788
AndyA 0:bddb8cd5e7df 789 void DW1000::sendFrame(uint8_t* message, uint16_t length)
AndyA 0:bddb8cd5e7df 790 {
AndyA 0:bddb8cd5e7df 791 //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor]
AndyA 0:bddb8cd5e7df 792 if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames
AndyA 0:bddb8cd5e7df 793 uint8_t len_7bit = length;
AndyA 0:bddb8cd5e7df 794 writeRegister(DW1000_TX_BUFFER, 0, message, len_7bit); // fill buffer
AndyA 0:bddb8cd5e7df 795
AndyA 3:1459d2aa6b97 796 /* support for frames over 127 bytes
AndyA 3:1459d2aa6b97 797 uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame
AndyA 3:1459d2aa6b97 798 length += 2; // including 2 CRC Bytes
AndyA 3:1459d2aa6b97 799 length = ((backup & 0xFC) << 8) | (length & 0x03FF);
AndyA 3:1459d2aa6b97 800 writeRegister16(DW1000_TX_FCTRL, 0, length);
AndyA 3:1459d2aa6b97 801 */
AndyA 0:bddb8cd5e7df 802 len_7bit += 2; // including 2 CRC Bytes
AndyA 0:bddb8cd5e7df 803 writeRegister8(DW1000_TX_FCTRL, 0, len_7bit);
AndyA 0:bddb8cd5e7df 804
AndyA 0:bddb8cd5e7df 805 stopTRX(); // stop receiving
AndyA 0:bddb8cd5e7df 806 writeRegister8(DW1000_SYS_CTRL, 0, 0x02 | 0x80); // trigger sending process by setting the TXSTRT bit
AndyA 0:bddb8cd5e7df 807 // startRX(); // enable receiver again
AndyA 0:bddb8cd5e7df 808 }
AndyA 0:bddb8cd5e7df 809
AndyA 3:1459d2aa6b97 810 void DW1000::setupSyncedFrame(uint8_t* message, uint16_t length)
AndyA 3:1459d2aa6b97 811 {
AndyA 0:bddb8cd5e7df 812 //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor]
AndyA 0:bddb8cd5e7df 813 if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames
AndyA 0:bddb8cd5e7df 814 writeRegister(DW1000_TX_BUFFER, 0, message, length); // fill buffer
AndyA 0:bddb8cd5e7df 815
AndyA 0:bddb8cd5e7df 816 uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame
AndyA 0:bddb8cd5e7df 817 length += 2; // including 2 CRC Bytes
AndyA 0:bddb8cd5e7df 818 length = ((backup & 0xFC) << 8) | (length & 0x03FF);
AndyA 0:bddb8cd5e7df 819 writeRegister16(DW1000_TX_FCTRL, 0, length);
AndyA 0:bddb8cd5e7df 820 }
AndyA 0:bddb8cd5e7df 821
AndyA 3:1459d2aa6b97 822 void DW1000::armSyncedFrame()
AndyA 3:1459d2aa6b97 823 {
AndyA 0:bddb8cd5e7df 824 stopTRX(); // stop receiving
AndyA 0:bddb8cd5e7df 825 writeRegister16(DW1000_EXT_SYNC, DWEXTSYNC_EC_CTRL, 33<<3 | 0x01); // Sync register = TX start with a wait of 33 (recomended, value must fulfill wait % 4 = 1)
AndyA 3:1459d2aa6b97 826 }
AndyA 0:bddb8cd5e7df 827
AndyA 0:bddb8cd5e7df 828 void DW1000::sendDelayedFrame(uint8_t* message, uint16_t length, uint64_t TxTimestamp)
AndyA 0:bddb8cd5e7df 829 {
AndyA 0:bddb8cd5e7df 830 //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor]
AndyA 0:bddb8cd5e7df 831 if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames
AndyA 0:bddb8cd5e7df 832 writeRegister(DW1000_TX_BUFFER, 0, message, length); // fill buffer
AndyA 0:bddb8cd5e7df 833
AndyA 0:bddb8cd5e7df 834 uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame
AndyA 0:bddb8cd5e7df 835 length += 2; // including 2 CRC Bytes
AndyA 0:bddb8cd5e7df 836 length = ((backup & 0xFC) << 8) | (length & 0x03FF);
AndyA 0:bddb8cd5e7df 837 writeRegister16(DW1000_TX_FCTRL, 0, length);
AndyA 0:bddb8cd5e7df 838
AndyA 0:bddb8cd5e7df 839 writeRegister40(DW1000_DX_TIME, 0, TxTimestamp); //write the timestamp on which to send the message
AndyA 0:bddb8cd5e7df 840
AndyA 0:bddb8cd5e7df 841 stopTRX(); // stop receiving
AndyA 0:bddb8cd5e7df 842 writeRegister8(DW1000_SYS_CTRL, 0, 0x02 | 0x04 | 0x80); // trigger sending process by setting the TXSTRT and TXDLYS bit. Set Wait4resp to automatically enter RX mode after tx.
AndyA 0:bddb8cd5e7df 843 }
AndyA 0:bddb8cd5e7df 844
AndyA 0:bddb8cd5e7df 845 void DW1000::startRX()
AndyA 0:bddb8cd5e7df 846 {
AndyA 0:bddb8cd5e7df 847 writeRegister8(DW1000_SYS_CTRL, 0x01, 0x01); // start listening for preamble by setting the RXENAB bit
AndyA 0:bddb8cd5e7df 848 }
AndyA 0:bddb8cd5e7df 849
AndyA 0:bddb8cd5e7df 850 void DW1000::stopTRX()
AndyA 0:bddb8cd5e7df 851 {
AndyA 0:bddb8cd5e7df 852 writeRegister8(DW1000_SYS_CTRL, 0, 0x40); // disable tranceiver go back to idle mode
AndyA 0:bddb8cd5e7df 853 }
AndyA 0:bddb8cd5e7df 854
AndyA 0:bddb8cd5e7df 855 // PRIVATE Methods ------------------------------------------------------------------------------------
AndyA 0:bddb8cd5e7df 856 void DW1000::loadLDE() // initialise LDE algorithm LDELOAD User Manual p22
AndyA 0:bddb8cd5e7df 857 {
AndyA 0:bddb8cd5e7df 858 spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test)
AndyA 0:bddb8cd5e7df 859
AndyA 0:bddb8cd5e7df 860 writeRegister16(DW1000_PMSC, 0, 0x0301); // set clock to XTAL so OTP is reliable
AndyA 0:bddb8cd5e7df 861 writeRegister16(DW1000_OTP_IF, DWOTP_OTP_CTRL, 0x8000); // set LDELOAD bit in OTP
AndyA 0:bddb8cd5e7df 862 wait_us(150);
AndyA 0:bddb8cd5e7df 863 writeRegister16(DW1000_PMSC, 0, 0x0200); // recover to PLL clock
AndyA 0:bddb8cd5e7df 864
AndyA 0:bddb8cd5e7df 865 wait_ms(1);
AndyA 0:bddb8cd5e7df 866
AndyA 0:bddb8cd5e7df 867 spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test)
AndyA 0:bddb8cd5e7df 868
AndyA 0:bddb8cd5e7df 869 }
AndyA 0:bddb8cd5e7df 870
AndyA 0:bddb8cd5e7df 871 void DW1000::loadLDOTUNE()
AndyA 0:bddb8cd5e7df 872 {
AndyA 1:dcbd071f38d5 873 uint64_t LDOTuningValue = readOTP(0x0004);
AndyA 1:dcbd071f38d5 874 if (LDOTuningValue != 0) {
AndyA 1:dcbd071f38d5 875 LDOTuningValue = LDOTuningValue | ((uint64_t)(readOTP(0x0005) & 0x00ff) << 32);
AndyA 0:bddb8cd5e7df 876 writeRegister40(DW1000_RF_CONF,DWRFCONF_RF_LDOTUNE,LDOTuningValue);
AndyA 1:dcbd071f38d5 877 }
AndyA 0:bddb8cd5e7df 878 }
AndyA 0:bddb8cd5e7df 879
AndyA 0:bddb8cd5e7df 880 void DW1000::resetRX()
AndyA 0:bddb8cd5e7df 881 {
AndyA 0:bddb8cd5e7df 882 writeRegister8(DW1000_PMSC, 3, 0xE0); // set RX reset
AndyA 0:bddb8cd5e7df 883 writeRegister8(DW1000_PMSC, 3, 0xF0); // clear RX reset
AndyA 0:bddb8cd5e7df 884 }
AndyA 0:bddb8cd5e7df 885
AndyA 0:bddb8cd5e7df 886 void DW1000::resetAll()
AndyA 0:bddb8cd5e7df 887 {
AndyA 0:bddb8cd5e7df 888 spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test)
AndyA 0:bddb8cd5e7df 889
AndyA 0:bddb8cd5e7df 890 writeRegister8(DW1000_PMSC, 0, 0x01); // set clock to XTAL
AndyA 0:bddb8cd5e7df 891 writeRegister8(DW1000_PMSC, 3, 0x00); // set All reset
AndyA 0:bddb8cd5e7df 892 wait_us(10); // wait for PLL to lock
AndyA 0:bddb8cd5e7df 893 writeRegister8(DW1000_PMSC, 3, 0xF0); // clear All reset
AndyA 0:bddb8cd5e7df 894
AndyA 0:bddb8cd5e7df 895 wait_ms(1);
AndyA 0:bddb8cd5e7df 896
AndyA 0:bddb8cd5e7df 897 spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test)
AndyA 0:bddb8cd5e7df 898 }
AndyA 0:bddb8cd5e7df 899
AndyA 0:bddb8cd5e7df 900 /// After writes have been completed reset the device.
AndyA 1:dcbd071f38d5 901 bool DW1000::writeOTP(uint16_t word_address,uint32_t data)
AndyA 0:bddb8cd5e7df 902 {
AndyA 0:bddb8cd5e7df 903 spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test)
AndyA 0:bddb8cd5e7df 904
AndyA 0:bddb8cd5e7df 905 writeRegister8(DW1000_PMSC, 0, 0x01); // set clock to XTAL
AndyA 0:bddb8cd5e7df 906 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x03); //
AndyA 0:bddb8cd5e7df 907 writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x9220); //
AndyA 0:bddb8cd5e7df 908 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); //
AndyA 0:bddb8cd5e7df 909 wait_ms(1);
AndyA 0:bddb8cd5e7df 910 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x02); //
AndyA 0:bddb8cd5e7df 911 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x88); //
AndyA 0:bddb8cd5e7df 912 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x80); //
AndyA 0:bddb8cd5e7df 913 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
AndyA 0:bddb8cd5e7df 914
AndyA 0:bddb8cd5e7df 915 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x05); //
AndyA 0:bddb8cd5e7df 916 writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x000E); //
AndyA 0:bddb8cd5e7df 917 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); //
AndyA 0:bddb8cd5e7df 918 wait_ms(1);
AndyA 0:bddb8cd5e7df 919 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x04); //
AndyA 0:bddb8cd5e7df 920 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x88); //
AndyA 0:bddb8cd5e7df 921 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x80); //
AndyA 0:bddb8cd5e7df 922 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
AndyA 0:bddb8cd5e7df 923
AndyA 0:bddb8cd5e7df 924 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x01); //
AndyA 0:bddb8cd5e7df 925 writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x1024); //
AndyA 0:bddb8cd5e7df 926 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); //
AndyA 0:bddb8cd5e7df 927 wait_ms(1);
AndyA 0:bddb8cd5e7df 928 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x00); //
AndyA 0:bddb8cd5e7df 929
AndyA 0:bddb8cd5e7df 930 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
AndyA 0:bddb8cd5e7df 931 writeRegister32(DW1000_OTP_IF,DWOTP_OTP_WDAT,data); //
AndyA 1:dcbd071f38d5 932 writeRegister16(DW1000_OTP_IF,DWOTP_OTP_ADDR,word_address); //
AndyA 0:bddb8cd5e7df 933 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x40); //
AndyA 0:bddb8cd5e7df 934 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
AndyA 0:bddb8cd5e7df 935 wait_ms(1);
AndyA 0:bddb8cd5e7df 936
AndyA 0:bddb8cd5e7df 937 for (int i=0; i<10; i++) {
AndyA 1:dcbd071f38d5 938 if (readOTP(word_address) == data)
AndyA 0:bddb8cd5e7df 939 return true;
AndyA 0:bddb8cd5e7df 940 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x40); // retry
AndyA 0:bddb8cd5e7df 941 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00);
AndyA 0:bddb8cd5e7df 942 wait_ms(1);
AndyA 0:bddb8cd5e7df 943 }
AndyA 0:bddb8cd5e7df 944 return false;
AndyA 0:bddb8cd5e7df 945 }
AndyA 0:bddb8cd5e7df 946
AndyA 0:bddb8cd5e7df 947
AndyA 1:dcbd071f38d5 948 uint32_t DW1000::readOTP(uint16_t word_address)
AndyA 0:bddb8cd5e7df 949 {
AndyA 1:dcbd071f38d5 950 writeRegister16(DW1000_OTP_IF,DWOTP_OTP_ADDR,word_address); // write address
AndyA 0:bddb8cd5e7df 951 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x03); // read address load
AndyA 0:bddb8cd5e7df 952 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x01); // read
AndyA 0:bddb8cd5e7df 953 uint32_t data = readRegister32(DW1000_OTP_IF,DWOTP_OTP_RDAT);
AndyA 0:bddb8cd5e7df 954 writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // OTP idle
AndyA 0:bddb8cd5e7df 955 return data;
AndyA 0:bddb8cd5e7df 956 }
AndyA 0:bddb8cd5e7df 957
AndyA 0:bddb8cd5e7df 958 void DW1000::setInterrupt(bool RX, bool TX)
AndyA 0:bddb8cd5e7df 959 {
AndyA 0:bddb8cd5e7df 960 writeRegister16(DW1000_SYS_MASK, 0, RX*0x4000 | TX*0x0080); // RX good frame 0x4000, TX done 0x0080
AndyA 15:6faab70a5b19 961 // writeRegister32(DW1000_SYS_MASK, 0, 0x377fff0); // RX good frame 0x4000, TX done 0x0080
AndyA 0:bddb8cd5e7df 962 }
AndyA 0:bddb8cd5e7df 963
AndyA 0:bddb8cd5e7df 964 void DW1000::ISR()
AndyA 0:bddb8cd5e7df 965 {
AndyA 15:6faab70a5b19 966 // led1 = !led1;
AndyA 0:bddb8cd5e7df 967 uint64_t status = getStatus();
AndyA 0:bddb8cd5e7df 968 if (status & 0x4000) { // a frame was received
AndyA 0:bddb8cd5e7df 969 callbackRX.call();
AndyA 0:bddb8cd5e7df 970 writeRegister16(DW1000_SYS_STATUS, 0, 0x6F00); // clearing of receiving status bits
AndyA 0:bddb8cd5e7df 971 }
AndyA 0:bddb8cd5e7df 972 if (status & 0x80) { // sending complete
AndyA 0:bddb8cd5e7df 973 callbackTX.call();
AndyA 0:bddb8cd5e7df 974 writeRegister8(DW1000_SYS_STATUS, 0, 0xF8); // clearing of sending status bits
AndyA 0:bddb8cd5e7df 975 }
AndyA 0:bddb8cd5e7df 976 }
AndyA 0:bddb8cd5e7df 977
AndyA 0:bddb8cd5e7df 978 uint16_t DW1000::getFramelength()
AndyA 0:bddb8cd5e7df 979 {
AndyA 0:bddb8cd5e7df 980 uint16_t framelength = readRegister16(DW1000_RX_FINFO, 0); // get framelength
AndyA 0:bddb8cd5e7df 981 framelength = (framelength & 0x03FF) - 2; // take only the right bits and subtract the 2 CRC Bytes
AndyA 0:bddb8cd5e7df 982 return framelength;
AndyA 0:bddb8cd5e7df 983 }
AndyA 0:bddb8cd5e7df 984
AndyA 0:bddb8cd5e7df 985 // SPI Interface ------------------------------------------------------------------------------------
AndyA 0:bddb8cd5e7df 986 uint8_t DW1000::readRegister8(uint8_t reg, uint16_t subaddress)
AndyA 0:bddb8cd5e7df 987 {
AndyA 0:bddb8cd5e7df 988 uint8_t result;
AndyA 0:bddb8cd5e7df 989 readRegister(reg, subaddress, &result, 1);
AndyA 0:bddb8cd5e7df 990 return result;
AndyA 0:bddb8cd5e7df 991 }
AndyA 0:bddb8cd5e7df 992
AndyA 0:bddb8cd5e7df 993 uint16_t DW1000::readRegister16(uint8_t reg, uint16_t subaddress)
AndyA 0:bddb8cd5e7df 994 {
AndyA 0:bddb8cd5e7df 995 uint16_t result;
AndyA 0:bddb8cd5e7df 996 readRegister(reg, subaddress, (uint8_t*)&result, 2);
AndyA 0:bddb8cd5e7df 997 return result;
AndyA 0:bddb8cd5e7df 998 }
AndyA 0:bddb8cd5e7df 999
AndyA 0:bddb8cd5e7df 1000 uint32_t DW1000::readRegister32(uint8_t reg, uint16_t subaddress)
AndyA 0:bddb8cd5e7df 1001 {
AndyA 0:bddb8cd5e7df 1002 uint32_t result;
AndyA 0:bddb8cd5e7df 1003 readRegister(reg, subaddress, (uint8_t*)&result, 4);
AndyA 0:bddb8cd5e7df 1004 return result;
AndyA 0:bddb8cd5e7df 1005 }
AndyA 0:bddb8cd5e7df 1006
AndyA 0:bddb8cd5e7df 1007
AndyA 0:bddb8cd5e7df 1008 uint64_t DW1000::readRegister40(uint8_t reg, uint16_t subaddress)
AndyA 0:bddb8cd5e7df 1009 {
AndyA 0:bddb8cd5e7df 1010 uint64_t result = 0;
AndyA 0:bddb8cd5e7df 1011 readRegister(reg, subaddress, (uint8_t*)&result, 5);
AndyA 0:bddb8cd5e7df 1012 return result;
AndyA 0:bddb8cd5e7df 1013 }
AndyA 0:bddb8cd5e7df 1014 uint64_t DW1000::readRegister64(uint8_t reg, uint16_t subaddress)
AndyA 0:bddb8cd5e7df 1015 {
AndyA 0:bddb8cd5e7df 1016 uint64_t result;
AndyA 0:bddb8cd5e7df 1017 readRegister(reg, subaddress, (uint8_t*)&result, 8);
AndyA 0:bddb8cd5e7df 1018 return result;
AndyA 0:bddb8cd5e7df 1019 }
AndyA 0:bddb8cd5e7df 1020
AndyA 0:bddb8cd5e7df 1021 void DW1000::writeRegister8(uint8_t reg, uint16_t subaddress, uint8_t buffer)
AndyA 0:bddb8cd5e7df 1022 {
AndyA 0:bddb8cd5e7df 1023 writeRegister(reg, subaddress, &buffer, 1);
AndyA 0:bddb8cd5e7df 1024 }
AndyA 0:bddb8cd5e7df 1025
AndyA 0:bddb8cd5e7df 1026 void DW1000::writeRegister16(uint8_t reg, uint16_t subaddress, uint16_t buffer)
AndyA 0:bddb8cd5e7df 1027 {
AndyA 0:bddb8cd5e7df 1028 writeRegister(reg, subaddress, (uint8_t*)&buffer, 2);
AndyA 0:bddb8cd5e7df 1029 }
AndyA 0:bddb8cd5e7df 1030
AndyA 0:bddb8cd5e7df 1031 void DW1000::writeRegister32(uint8_t reg, uint16_t subaddress, uint32_t buffer)
AndyA 0:bddb8cd5e7df 1032 {
AndyA 0:bddb8cd5e7df 1033 writeRegister(reg, subaddress, (uint8_t*)&buffer, 4);
AndyA 0:bddb8cd5e7df 1034 }
AndyA 0:bddb8cd5e7df 1035
AndyA 0:bddb8cd5e7df 1036 void DW1000::writeRegister40(uint8_t reg, uint16_t subaddress, uint64_t buffer)
AndyA 0:bddb8cd5e7df 1037 {
AndyA 0:bddb8cd5e7df 1038 writeRegister(reg, subaddress, (uint8_t*)&buffer, 5);
AndyA 0:bddb8cd5e7df 1039 }
AndyA 0:bddb8cd5e7df 1040
AndyA 0:bddb8cd5e7df 1041 void DW1000::readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length)
AndyA 0:bddb8cd5e7df 1042 {
AndyA 0:bddb8cd5e7df 1043 setupTransaction(reg, subaddress, false);
AndyA 0:bddb8cd5e7df 1044 for(int i=0; i<length; i++) // get data
AndyA 0:bddb8cd5e7df 1045 buffer[i] = spi.write(0x00);
AndyA 0:bddb8cd5e7df 1046 deselect();
AndyA 0:bddb8cd5e7df 1047 }
AndyA 0:bddb8cd5e7df 1048
AndyA 0:bddb8cd5e7df 1049 void DW1000::writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length)
AndyA 0:bddb8cd5e7df 1050 {
AndyA 0:bddb8cd5e7df 1051 setupTransaction(reg, subaddress, true);
AndyA 0:bddb8cd5e7df 1052 for(int i=0; i<length; i++) // put data
AndyA 0:bddb8cd5e7df 1053 spi.write(buffer[i]);
AndyA 0:bddb8cd5e7df 1054 deselect();
AndyA 0:bddb8cd5e7df 1055 }
AndyA 0:bddb8cd5e7df 1056
AndyA 0:bddb8cd5e7df 1057 void DW1000::setupTransaction(uint8_t reg, uint16_t subaddress, bool write)
AndyA 0:bddb8cd5e7df 1058 {
AndyA 0:bddb8cd5e7df 1059 reg |= (write * DW1000_WRITE_FLAG); // set read/write flag
AndyA 0:bddb8cd5e7df 1060 select();
AndyA 0:bddb8cd5e7df 1061 if (subaddress > 0) { // there's a subadress, we need to set flag and send second header byte
AndyA 0:bddb8cd5e7df 1062 spi.write(reg | DW1000_SUBADDRESS_FLAG);
AndyA 0:bddb8cd5e7df 1063 if (subaddress > 0x7F) { // sub address too long, we need to set flag and send third header byte
AndyA 0:bddb8cd5e7df 1064 spi.write((uint8_t)(subaddress & 0x7F) | DW1000_2_SUBADDRESS_FLAG); // and
AndyA 0:bddb8cd5e7df 1065 spi.write((uint8_t)(subaddress >> 7));
AndyA 0:bddb8cd5e7df 1066 } else {
AndyA 0:bddb8cd5e7df 1067 spi.write((uint8_t)subaddress);
AndyA 0:bddb8cd5e7df 1068 }
AndyA 0:bddb8cd5e7df 1069 } else {
AndyA 0:bddb8cd5e7df 1070 spi.write(reg); // say which register address we want to access
AndyA 0:bddb8cd5e7df 1071 }
AndyA 0:bddb8cd5e7df 1072 }
AndyA 0:bddb8cd5e7df 1073
AndyA 0:bddb8cd5e7df 1074 void DW1000::select() // always called to start an SPI transmission
AndyA 0:bddb8cd5e7df 1075 {
AndyA 0:bddb8cd5e7df 1076 irq.disable_irq(); // disable interrupts from DW1000 during SPI becaus this leads to crashes! TODO: if you have other interrupt handlers attached on the micro controller, they could also interfere.
AndyA 0:bddb8cd5e7df 1077 cs = 0; // set Cable Select pin low to start transmission
AndyA 0:bddb8cd5e7df 1078 }
AndyA 0:bddb8cd5e7df 1079
AndyA 0:bddb8cd5e7df 1080 void DW1000::deselect() // always called to end an SPI transmission
AndyA 0:bddb8cd5e7df 1081 {
AndyA 0:bddb8cd5e7df 1082 cs = 1; // set Cable Select pin high to stop transmission
AndyA 0:bddb8cd5e7df 1083 irq.enable_irq(); // reenable the interrupt handler
AndyA 0:bddb8cd5e7df 1084 }
AndyA 15:6faab70a5b19 1085
AndyA 15:6faab70a5b19 1086 void DW1000::getRxClockInfo(int32_t *offset, uint8_t* phase, uint8_t* delta)
AndyA 15:6faab70a5b19 1087 {
AndyA 15:6faab70a5b19 1088 uint64_t data = readRegister40(DW1000_RX_TTCKO,0);
AndyA 15:6faab70a5b19 1089 *phase = (data >> 32)&0x07f;
AndyA 15:6faab70a5b19 1090 *delta = data >> 24 & 0x0ff;
AndyA 15:6faab70a5b19 1091 int32_t RXTofs = data &0x07ffff;
AndyA 15:6faab70a5b19 1092 if (RXTofs & 0x040000)
AndyA 15:6faab70a5b19 1093 RXTofs |= 0xfff80000;
AndyA 15:6faab70a5b19 1094 *offset = RXTofs;
AndyA 15:6faab70a5b19 1095
AndyA 15:6faab70a5b19 1096 // uint32_t RXTTCKI = 0x01FC0000;
AndyA 15:6faab70a5b19 1097 // if (getSetup()->getPRF() == DW1000Setup::prf16MHz)
AndyA 15:6faab70a5b19 1098 // RXTTCKI = 0x01F00000;
AndyA 15:6faab70a5b19 1099
AndyA 15:6faab70a5b19 1100 // double clockOffset = (1000000.0 * RXTofs) / RXTTCKI;
AndyA 15:6faab70a5b19 1101 // printf("Clock offset %.4f ppm, re-sample delay %d, phase adjustment %d\n",clockOffset,RSMPDel,RCPhase);
AndyA 15:6faab70a5b19 1102
AndyA 15:6faab70a5b19 1103 }