Andy A
DW1000 UWB driver based on work of Matthias Grob & Manuel Stalder - ETH Zürich - 2015
Diff: DW1000.cpp
- Revision:
- 0:bddb8cd5e7df
- Child:
- 1:dcbd071f38d5
- Child:
- 2:ebbb05cbc417
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/DW1000.cpp Tue Apr 05 10:51:00 2016 +0000
@@ -0,0 +1,497 @@
+#include "DW1000.h"
+
+#define SPIRATE_PLL (5*1000*1000)
+#define SPIRATE_OSC (2*1000*1000)
+
+DW1000::DW1000(UWBMode setup, PinName MOSI, PinName MISO, PinName SCLK, PinName CS, PinName IRQ) : irq(IRQ), spi(MOSI, MISO, SCLK), cs(CS)
+{
+ setCallbacks(NULL, NULL);
+
+ deselect(); // Chip must be deselected first
+ spi.format(8,0); // Setup the spi for standard 8 bit data and SPI-Mode 0 (GPIO5, GPIO6 open circuit or ground on DW1000)
+ spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test)
+
+ resetAll(); // we do a soft reset of the DW1000 everytime the driver starts
+
+ switch (setup) {
+ case user110k: // values from Matthias Grob & Manuel Stalder - ETH Zürich - library
+ //Those values are for the 110kbps mode (5, 16MHz, 1024 Symbols) and are quite complete
+ writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE1, 0x8870); //AGC_TUNE1 for 16MHz PRF
+ writeRegister32(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE2, 0x2502A907); //AGC_TUNE2 (Universal)
+ writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE3, 0x0055); //AGC_TUNE3 (Universal)
+
+ writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x000A); //DRX_TUNE0b for 110kbps
+ writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1A, 0x0087); //DRX_TUNE1a for 16MHz PRF
+ writeRegister16(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0064); //DRX_TUNE1b for 110kbps & > 1024 symbols
+ writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x351A009A); //PAC size for 1024 symbols preamble & 16MHz PRF
+ //writeRegister32(DW1000_DRX_CONF, 0x08, 0x371A011D); //PAC size for 2048 symbols preamble
+
+ writeRegister8 (DW1000_LDE_CTRL, DWLDE_LDE_CFG1, 0xD); //LDE_CFG1
+ writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_CFG2, 0x1607); //LDE_CFG2 for 16MHz PRF
+
+ writeRegister32(DW1000_TX_POWER, 0, 0x28282828); //Power for channel 5
+
+ writeRegister8(DW1000_RF_CONF, DWRFCONF_RF_RXCTRLH, 0xD8); //RF_RXCTRLH for channel 5
+ writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x001E3FE0); //RF_TXCTRL for channel 5
+
+ writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC0); //TC_PGDELAY for channel 5
+
+ writeRegister32 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLCFG, 0x0800041D); //FS_PLLCFG for channel 5
+ writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0xBE); // changed from 0xA6 //FS_PLLTUNE for channel 5
+
+ loadLDE(); // important everytime DW1000 initialises/awakes otherwise the LDE algorithm must be turned off or there's receiving malfunction see User Manual LDELOAD on p22 & p158
+
+ // 110kbps CAUTION: a lot of other registers have to be set for an optimized operation on 110kbps
+ writeRegister16(DW1000_TX_FCTRL, 1, 0x0800 | 0x0100 | 0x0080); // use 1024 symbols preamble (0x0800) (previously 2048 - 0x2800), 16MHz pulse repetition frequency (0x0100), 110kbps bit rate (0x0080) see p.69 of DW1000 User Manual
+ writeRegister8(DW1000_SYS_CFG, 2, 0x44); // enable special receiving option for 110kbps (disable smartTxPower)!! (0x44) see p.64 of DW1000 User Manual [DO NOT enable 1024 byte frames (0x03) becuase it generates disturbance of ranging don't know why...]
+
+ writeRegister16(DW1000_TX_ANTD, 0, 16384); // set TX and RX Antenna delay to neutral because we calibrate afterwards
+ writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_RXANTD, 16384); // = 2^14 a quarter of the range of the 16-Bit register which corresponds to zero calibration in a round trip (TX1+RX2+TX2+RX1)
+ break;
+
+ case tunedDefault: // User Manual "2.5.5 Default Configurations that should be modified" p. 22
+ //Those values are for the standard mode (6.8Mbps, 5, 16Mhz, 32 Symbols) and are (may be?) INCOMPLETE!
+ writeRegister16(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE1, 0x8870);
+ writeRegister32(DW1000_AGC_CTRL, DWAGCCTRL_AGC_TUNE2, 0x2502A907);
+ writeRegister32(DW1000_DRX_CONF, DWDRX_DRX_TUNE2, 0x311A002D);
+ writeRegister8(DW1000_DRX_CONF, DWDRX_DRX_TUNE0B, 0x0001);
+ writeRegister8(DW1000_DRX_CONF, DWDRX_DRX_TUNE1A, 0x0087);
+ writeRegister8(DW1000_DRX_CONF, DWDRX_DRX_TUNE1B, 0x0020);
+ writeRegister8 (DW1000_LDE_CTRL, DWLDE_LDE_CFG1, 0xD);
+ writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_CFG2, 0x1607);
+ writeRegister32(DW1000_TX_POWER, 0, 0x0E082848);
+// writeRegister32(DW1000_TX_POWER, 0, 0x75757575);
+ writeRegister32(DW1000_RF_CONF, DWRFCONF_RF_TXCTRL, 0x001E3FE0);
+ writeRegister8 (DW1000_TX_CAL, DWTXCAL_TC_PGDELAY, 0xC0);
+ writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_PLLTUNE, 0xBE);
+
+ loadLDE(); // important everytime DW1000 initialises/awakes otherwise the LDE algorithm must be turned off or there's receiving malfunction see User Manual LDELOAD on p22 & p158
+
+ writeRegister32(DW1000_GPIO_CTRL,DWGPIO_GPIO_MODE,0x00001400);
+ writeRegister16(DW1000_PMSC,DWPMSC_PMSC_LEDC,0x0120);
+
+// writeRegister8(DW1000_SYS_CFG, 3, 0x20); // enable auto RX reenable
+
+ setRxDelay(0);
+ setTxDelay(0);
+
+ break;
+ case defaultConfig:
+ default:
+ loadLDE(); // important everytime DW1000 initialises/awakes otherwise the LDE algorithm must be turned off or there's receiving malfunction see User Manual LDELOAD on p22 & p158
+ break;
+ }
+
+ writeRegister8(DW1000_SYS_CFG, 3, 0x20); // enable auto reenabling receiver after error
+
+ irq.rise(this, &DW1000::ISR); // attach interrupt handler to rising edge of interrupt pin from DW1000
+}
+
+void DW1000::setRxDelay(uint16_t ticks)
+{
+ writeRegister16(DW1000_LDE_CTRL, DWLDE_LDE_RXANTD, ticks);
+}
+void DW1000::setTxDelay(uint16_t ticks)
+{
+ writeRegister16(DW1000_TX_ANTD, 0, ticks);
+}
+
+void DW1000::setCallbacks(void (*callbackRX)(void), void (*callbackTX)(void))
+{
+ bool RX = false;
+ bool TX = false;
+ if (callbackRX) {
+ DW1000::callbackRX.attach(callbackRX);
+ RX = true;
+ }
+ if (callbackTX) {
+ DW1000::callbackTX.attach(callbackTX);
+ TX = true;
+ }
+ setInterrupt(RX,TX);
+}
+
+uint32_t DW1000::getDeviceID()
+{
+ uint32_t result;
+ readRegister(DW1000_DEV_ID, 0, (uint8_t*)&result, 4);
+ return result;
+}
+
+uint64_t DW1000::getEUI()
+{
+ uint64_t result;
+ readRegister(DW1000_EUI, 0, (uint8_t*)&result, 8);
+ return result;
+}
+
+void DW1000::setEUI(uint64_t EUI)
+{
+ writeRegister(DW1000_EUI, 0, (uint8_t*)&EUI, 8);
+}
+
+
+float DW1000::getVoltage()
+{
+ uint8_t data;
+
+ writeRegister8(DW1000_RF_CONF, 0x11, 0x80);
+ writeRegister8(DW1000_RF_CONF, 0x12, 0x0A);
+ writeRegister8(DW1000_RF_CONF, 0x12, 0x0F);
+ writeRegister8(DW1000_TX_CAL, 0x00, 0x01);
+ writeRegister8(DW1000_TX_CAL, 0x00, 0x00);
+ data = readRegister8(DW1000_TX_CAL, 0x03); // get the 8-Bit reading for Voltage
+ float Voltage = (float)(data - readOTP8(0x08)) *0.00578 + 3.3;
+ return Voltage;
+}
+
+float DW1000::getTemperature()
+{
+ uint8_t data;
+
+ writeRegister8(DW1000_RF_CONF, 0x11, 0x80);
+ writeRegister8(DW1000_RF_CONF, 0x12, 0x0A);
+ writeRegister8(DW1000_RF_CONF, 0x12, 0x0F);
+ writeRegister8(DW1000_TX_CAL, 0x00, 0x01);
+ writeRegister8(DW1000_TX_CAL, 0x00, 0x00);
+ data = readRegister16(DW1000_TX_CAL, 0x04); // get the 8-Bit reading for Temperature
+ float temperature = (float)(data - readOTP8(0x09))*0.9 + 23;
+ return temperature;
+}
+
+
+uint64_t DW1000::getStatus()
+{
+ return readRegister40(DW1000_SYS_STATUS, 0);
+}
+
+uint64_t DW1000::getRXTimestamp()
+{
+ return readRegister40(DW1000_RX_TIME, 0);
+}
+
+uint64_t DW1000::getTXTimestamp()
+{
+ return readRegister40(DW1000_TX_TIME, 0);
+}
+
+void DW1000::sendString(char* message)
+{
+ sendFrame((uint8_t*)message, strlen(message)+1);
+}
+
+void DW1000::receiveString(char* message)
+{
+ readRegister(DW1000_RX_BUFFER, 0, (uint8_t*)message, getFramelength()); // get data from buffer
+}
+
+void DW1000::sendFrame(uint8_t* message, uint16_t length)
+{
+ //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor]
+ if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames
+ uint8_t len_7bit = length;
+ writeRegister(DW1000_TX_BUFFER, 0, message, len_7bit); // fill buffer
+
+/* support for frames over 127 bytes
+ uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame
+ length += 2; // including 2 CRC Bytes
+ length = ((backup & 0xFC) << 8) | (length & 0x03FF);
+ writeRegister16(DW1000_TX_FCTRL, 0, length);
+*/
+ len_7bit += 2; // including 2 CRC Bytes
+ writeRegister8(DW1000_TX_FCTRL, 0, len_7bit);
+
+ stopTRX(); // stop receiving
+ writeRegister8(DW1000_SYS_CTRL, 0, 0x02 | 0x80); // trigger sending process by setting the TXSTRT bit
+// startRX(); // enable receiver again
+}
+
+void DW1000::setupSyncedFrame(uint8_t* message, uint16_t length) {
+ //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor]
+ if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames
+ writeRegister(DW1000_TX_BUFFER, 0, message, length); // fill buffer
+
+ uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame
+ length += 2; // including 2 CRC Bytes
+ length = ((backup & 0xFC) << 8) | (length & 0x03FF);
+ writeRegister16(DW1000_TX_FCTRL, 0, length);
+}
+
+void DW1000::armSyncedFrame() {
+ stopTRX(); // stop receiving
+ writeRegister16(DW1000_EXT_SYNC, DWEXTSYNC_EC_CTRL, 33<<3 | 0x01); // Sync register = TX start with a wait of 33 (recomended, value must fulfill wait % 4 = 1)
+ }
+
+void DW1000::sendDelayedFrame(uint8_t* message, uint16_t length, uint64_t TxTimestamp)
+{
+ //if (length >= 1021) length = 1021; // check for maximim length a frame can have with 1024 Byte frames [not used, see constructor]
+ if (length >= 125) length = 125; // check for maximim length a frame can have with 127 Byte frames
+ writeRegister(DW1000_TX_BUFFER, 0, message, length); // fill buffer
+
+ uint8_t backup = readRegister8(DW1000_TX_FCTRL, 1); // put length of frame
+ length += 2; // including 2 CRC Bytes
+ length = ((backup & 0xFC) << 8) | (length & 0x03FF);
+ writeRegister16(DW1000_TX_FCTRL, 0, length);
+
+ writeRegister40(DW1000_DX_TIME, 0, TxTimestamp); //write the timestamp on which to send the message
+
+ stopTRX(); // stop receiving
+ writeRegister8(DW1000_SYS_CTRL, 0, 0x02 | 0x04 | 0x80); // trigger sending process by setting the TXSTRT and TXDLYS bit. Set Wait4resp to automatically enter RX mode after tx.
+}
+
+void DW1000::startRX()
+{
+ writeRegister8(DW1000_SYS_CTRL, 0x01, 0x01); // start listening for preamble by setting the RXENAB bit
+}
+
+void DW1000::stopTRX()
+{
+ writeRegister8(DW1000_SYS_CTRL, 0, 0x40); // disable tranceiver go back to idle mode
+}
+
+// PRIVATE Methods ------------------------------------------------------------------------------------
+void DW1000::loadLDE() // initialise LDE algorithm LDELOAD User Manual p22
+{
+ spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test)
+
+ writeRegister16(DW1000_PMSC, 0, 0x0301); // set clock to XTAL so OTP is reliable
+ writeRegister16(DW1000_OTP_IF, DWOTP_OTP_CTRL, 0x8000); // set LDELOAD bit in OTP
+ wait_us(150);
+ writeRegister16(DW1000_PMSC, 0, 0x0200); // recover to PLL clock
+
+ wait_ms(1);
+
+ spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test)
+
+}
+
+void DW1000::loadLDOTUNE()
+{
+ uint64_t LDOTuningValue = readOTP40(0x0004);
+ if (LDOTuningValue != 0)
+ writeRegister40(DW1000_RF_CONF,DWRFCONF_RF_LDOTUNE,LDOTuningValue);
+
+}
+
+void DW1000::resetRX()
+{
+ writeRegister8(DW1000_PMSC, 3, 0xE0); // set RX reset
+ writeRegister8(DW1000_PMSC, 3, 0xF0); // clear RX reset
+}
+
+void DW1000::resetAll()
+{
+ spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test)
+
+ writeRegister8(DW1000_PMSC, 0, 0x01); // set clock to XTAL
+ writeRegister8(DW1000_PMSC, 3, 0x00); // set All reset
+ wait_us(10); // wait for PLL to lock
+ writeRegister8(DW1000_PMSC, 3, 0xF0); // clear All reset
+
+ wait_ms(1);
+
+ spi.frequency(SPIRATE_PLL); // with a 1MHz clock rate (worked up to 49MHz in our Test)
+}
+
+/// After writes have been completed reset the device.
+bool DW1000::writeOTP(uint16_t address,uint32_t data)
+{
+ spi.frequency(SPIRATE_OSC); // with a 1MHz clock rate (worked up to 49MHz in our Test)
+
+ writeRegister8(DW1000_PMSC, 0, 0x01); // set clock to XTAL
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x03); //
+ writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x9220); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); //
+ wait_ms(1);
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x02); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x88); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x80); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
+
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x05); //
+ writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x000E); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); //
+ wait_ms(1);
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x04); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x88); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x80); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
+
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x01); //
+ writeRegister16(DW1000_OTP_IF,DWOTP_OTP_WDAT,0x1024); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x08); //
+ wait_ms(1);
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL+1,0x00); //
+
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
+ writeRegister32(DW1000_OTP_IF,DWOTP_OTP_WDAT,data); //
+ writeRegister16(DW1000_OTP_IF,DWOTP_OTP_ADDR,address); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x40); //
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); //
+ wait_ms(1);
+
+ for (int i=0; i<10; i++) {
+ if (readOTP32(address) == data)
+ return true;
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x40); // retry
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00);
+ wait_ms(1);
+ }
+ return false;
+}
+
+uint32_t DW1000::readOTP (uint16_t word_address, uint8_t size) {
+ if (size == 1)
+ return readOTP8(word_address);
+ else if (size == 2)
+ return readOTP16(word_address);
+ else
+ return readOTP32(word_address);
+ }
+
+
+uint32_t DW1000::readOTP32(uint16_t address)
+{
+ writeRegister16(DW1000_OTP_IF,DWOTP_OTP_ADDR,address); // write address
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x03); // read address load
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x01); // read
+ uint32_t data = readRegister32(DW1000_OTP_IF,DWOTP_OTP_RDAT);
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // OTP idle
+ return data;
+}
+
+uint8_t DW1000::readOTP8(uint16_t address)
+{
+ writeRegister16(DW1000_OTP_IF,DWOTP_OTP_ADDR,address); // write address
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x03); // read address load
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x01); // read
+ uint8_t data = readRegister8(DW1000_OTP_IF,DWOTP_OTP_RDAT);
+ writeRegister8(DW1000_OTP_IF,DWOTP_OTP_CTRL,0x00); // OTP idle
+ return data;
+}
+
+void DW1000::setInterrupt(bool RX, bool TX)
+{
+ writeRegister16(DW1000_SYS_MASK, 0, RX*0x4000 | TX*0x0080); // RX good frame 0x4000, TX done 0x0080
+}
+
+void DW1000::ISR()
+{
+ uint64_t status = getStatus();
+ if (status & 0x4000) { // a frame was received
+ callbackRX.call();
+ writeRegister16(DW1000_SYS_STATUS, 0, 0x6F00); // clearing of receiving status bits
+ }
+ if (status & 0x80) { // sending complete
+ callbackTX.call();
+ writeRegister8(DW1000_SYS_STATUS, 0, 0xF8); // clearing of sending status bits
+ }
+}
+
+uint16_t DW1000::getFramelength()
+{
+ uint16_t framelength = readRegister16(DW1000_RX_FINFO, 0); // get framelength
+ framelength = (framelength & 0x03FF) - 2; // take only the right bits and subtract the 2 CRC Bytes
+ return framelength;
+}
+
+// SPI Interface ------------------------------------------------------------------------------------
+uint8_t DW1000::readRegister8(uint8_t reg, uint16_t subaddress)
+{
+ uint8_t result;
+ readRegister(reg, subaddress, &result, 1);
+ return result;
+}
+
+uint16_t DW1000::readRegister16(uint8_t reg, uint16_t subaddress)
+{
+ uint16_t result;
+ readRegister(reg, subaddress, (uint8_t*)&result, 2);
+ return result;
+}
+
+uint32_t DW1000::readRegister32(uint8_t reg, uint16_t subaddress)
+{
+ uint32_t result;
+ readRegister(reg, subaddress, (uint8_t*)&result, 4);
+ return result;
+}
+
+
+uint64_t DW1000::readRegister40(uint8_t reg, uint16_t subaddress)
+{
+ uint64_t result = 0;
+ readRegister(reg, subaddress, (uint8_t*)&result, 5);
+ return result;
+}
+uint64_t DW1000::readRegister64(uint8_t reg, uint16_t subaddress)
+{
+ uint64_t result;
+ readRegister(reg, subaddress, (uint8_t*)&result, 8);
+ return result;
+}
+
+void DW1000::writeRegister8(uint8_t reg, uint16_t subaddress, uint8_t buffer)
+{
+ writeRegister(reg, subaddress, &buffer, 1);
+}
+
+void DW1000::writeRegister16(uint8_t reg, uint16_t subaddress, uint16_t buffer)
+{
+ writeRegister(reg, subaddress, (uint8_t*)&buffer, 2);
+}
+
+void DW1000::writeRegister32(uint8_t reg, uint16_t subaddress, uint32_t buffer)
+{
+ writeRegister(reg, subaddress, (uint8_t*)&buffer, 4);
+}
+
+void DW1000::writeRegister40(uint8_t reg, uint16_t subaddress, uint64_t buffer)
+{
+ writeRegister(reg, subaddress, (uint8_t*)&buffer, 5);
+}
+
+void DW1000::readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length)
+{
+ setupTransaction(reg, subaddress, false);
+ for(int i=0; i<length; i++) // get data
+ buffer[i] = spi.write(0x00);
+ deselect();
+}
+
+void DW1000::writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length)
+{
+ setupTransaction(reg, subaddress, true);
+ for(int i=0; i<length; i++) // put data
+ spi.write(buffer[i]);
+ deselect();
+}
+
+void DW1000::setupTransaction(uint8_t reg, uint16_t subaddress, bool write)
+{
+ reg |= (write * DW1000_WRITE_FLAG); // set read/write flag
+ select();
+ if (subaddress > 0) { // there's a subadress, we need to set flag and send second header byte
+ spi.write(reg | DW1000_SUBADDRESS_FLAG);
+ if (subaddress > 0x7F) { // sub address too long, we need to set flag and send third header byte
+ spi.write((uint8_t)(subaddress & 0x7F) | DW1000_2_SUBADDRESS_FLAG); // and
+ spi.write((uint8_t)(subaddress >> 7));
+ } else {
+ spi.write((uint8_t)subaddress);
+ }
+ } else {
+ spi.write(reg); // say which register address we want to access
+ }
+}
+
+void DW1000::select() // always called to start an SPI transmission
+{
+ irq.disable_irq(); // disable interrupts from DW1000 during SPI becaus this leads to crashes! TODO: if you have other interrupt handlers attached on the micro controller, they could also interfere.
+ cs = 0; // set Cable Select pin low to start transmission
+}
+
+void DW1000::deselect() // always called to end an SPI transmission
+{
+ cs = 1; // set Cable Select pin high to stop transmission
+ irq.enable_irq(); // reenable the interrupt handler
+}