DW1000 UWB driver based on work of Matthias Grob & Manuel Stalder - ETH Zürich - 2015
DW1000.h@4:5f1025df5530, 2016-04-07 (annotated)
- Committer:
- AndyA
- Date:
- Thu Apr 07 16:25:31 2016 +0000
- Revision:
- 4:5f1025df5530
- Parent:
- 3:1459d2aa6b97
- Child:
- 5:68ffaa5962d1
Moved config to it's own class
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AndyA | 0:bddb8cd5e7df | 1 | // by Matthias Grob & Manuel Stalder - ETH Zürich - 2015 |
AndyA | 0:bddb8cd5e7df | 2 | |
AndyA | 0:bddb8cd5e7df | 3 | #ifndef DW1000_H |
AndyA | 0:bddb8cd5e7df | 4 | #define DW1000_H |
AndyA | 0:bddb8cd5e7df | 5 | |
AndyA | 0:bddb8cd5e7df | 6 | #include "mbed.h" |
AndyA | 0:bddb8cd5e7df | 7 | |
AndyA | 0:bddb8cd5e7df | 8 | // register addresses |
AndyA | 0:bddb8cd5e7df | 9 | // Mnemonic Address Bytes Description |
AndyA | 0:bddb8cd5e7df | 10 | #define DW1000_DEV_ID 0x00 // 4 Device Identifier – includes device type and revision information |
AndyA | 0:bddb8cd5e7df | 11 | #define DW1000_EUI 0x01 // 8 Extended Unique Identifier |
AndyA | 0:bddb8cd5e7df | 12 | #define DW1000_PANADR 0x03 // 4 PAN Identifier and Short Address |
AndyA | 0:bddb8cd5e7df | 13 | #define DW1000_SYS_CFG 0x04 // 4 System Configuration bitmap |
AndyA | 0:bddb8cd5e7df | 14 | #define DW1000_SYS_TIME 0x06 // 5 System Time Counter (40-bit) |
AndyA | 0:bddb8cd5e7df | 15 | #define DW1000_TX_FCTRL 0x08 // 5 Transmit Frame Control |
AndyA | 0:bddb8cd5e7df | 16 | #define DW1000_TX_BUFFER 0x09 // 1024 Transmit Data Buffer |
AndyA | 0:bddb8cd5e7df | 17 | #define DW1000_DX_TIME 0x0A // 5 Delayed Send or Receive Time (40-bit) |
AndyA | 0:bddb8cd5e7df | 18 | #define DW1000_RX_FWTO 0x0C // 2 Receive Frame Wait Timeout Period |
AndyA | 0:bddb8cd5e7df | 19 | #define DW1000_SYS_CTRL 0x0D // 4 System Control Register |
AndyA | 0:bddb8cd5e7df | 20 | #define DW1000_SYS_MASK 0x0E // 4 System Event Mask Register |
AndyA | 0:bddb8cd5e7df | 21 | #define DW1000_SYS_STATUS 0x0F // 5 System Event Status Register |
AndyA | 0:bddb8cd5e7df | 22 | #define DW1000_RX_FINFO 0x10 // 4 RX Frame Information (in double buffer set) |
AndyA | 0:bddb8cd5e7df | 23 | #define DW1000_RX_BUFFER 0x11 // 1024 Receive Data Buffer (in double buffer set) |
AndyA | 0:bddb8cd5e7df | 24 | #define DW1000_RX_FQUAL 0x12 // 8 Rx Frame Quality information (in double buffer set) |
AndyA | 0:bddb8cd5e7df | 25 | #define DW1000_RX_TTCKI 0x13 // 4 Receiver Time Tracking Interval (in double buffer set) |
AndyA | 0:bddb8cd5e7df | 26 | #define DW1000_RX_TTCKO 0x14 // 5 Receiver Time Tracking Offset (in double buffer set) |
AndyA | 0:bddb8cd5e7df | 27 | #define DW1000_RX_TIME 0x15 // 14 Receive Message Time of Arrival (in double buffer set) |
AndyA | 0:bddb8cd5e7df | 28 | #define DW1000_TX_TIME 0x17 // 10 Transmit Message Time of Sending (in double buffer set) |
AndyA | 0:bddb8cd5e7df | 29 | #define DW1000_TX_ANTD 0x18 // 2 16-bit Delay from Transmit to Antenna |
AndyA | 0:bddb8cd5e7df | 30 | #define DW1000_SYS_STATE 0x19 // 5 System State information |
AndyA | 0:bddb8cd5e7df | 31 | #define DW1000_ACK_RESP_T 0x1A // 4 Acknowledgement Time and Response Time |
AndyA | 0:bddb8cd5e7df | 32 | #define DW1000_RX_SNIFF 0x1D // 4 Pulsed Preamble Reception Configuration |
AndyA | 0:bddb8cd5e7df | 33 | #define DW1000_TX_POWER 0x1E // 4 TX Power Control |
AndyA | 0:bddb8cd5e7df | 34 | #define DW1000_CHAN_CTRL 0x1F // 4 Channel Control |
AndyA | 0:bddb8cd5e7df | 35 | #define DW1000_USR_SFD 0x21 // 41 User-specified short/long TX/RX SFD sequences |
AndyA | 0:bddb8cd5e7df | 36 | #define DW1000_AGC_CTRL 0x23 // 32 Automatic Gain Control configuration |
AndyA | 0:bddb8cd5e7df | 37 | #define DW1000_EXT_SYNC 0x24 // 12 External synchronisation control. |
AndyA | 0:bddb8cd5e7df | 38 | #define DW1000_ACC_MEM 0x25 // 4064 Read access to accumulator data |
AndyA | 0:bddb8cd5e7df | 39 | #define DW1000_GPIO_CTRL 0x26 // 44 Peripheral register bus 1 access - GPIO control |
AndyA | 0:bddb8cd5e7df | 40 | #define DW1000_DRX_CONF 0x27 // 44 Digital Receiver configuration |
AndyA | 0:bddb8cd5e7df | 41 | #define DW1000_RF_CONF 0x28 // 58 Analog RF Configuration |
AndyA | 0:bddb8cd5e7df | 42 | #define DW1000_TX_CAL 0x2A // 52 Transmitter calibration block |
AndyA | 0:bddb8cd5e7df | 43 | #define DW1000_FS_CTRL 0x2B // 21 Frequency synthesiser control block |
AndyA | 0:bddb8cd5e7df | 44 | #define DW1000_AON 0x2C // 12 Always-On register set |
AndyA | 0:bddb8cd5e7df | 45 | #define DW1000_OTP_IF 0x2D // 18 One Time Programmable Memory Interface |
AndyA | 0:bddb8cd5e7df | 46 | #define DW1000_LDE_CTRL 0x2E // - Leading edge detection control block |
AndyA | 0:bddb8cd5e7df | 47 | #define DW1000_DIG_DIAG 0x2F // 41 Digital Diagnostics Interface |
AndyA | 0:bddb8cd5e7df | 48 | #define DW1000_PMSC 0x36 // 48 Power Management System Control Block |
AndyA | 0:bddb8cd5e7df | 49 | |
AndyA | 0:bddb8cd5e7df | 50 | // AGC_CTRL sub registers |
AndyA | 0:bddb8cd5e7df | 51 | #define DWAGCCTRL_AGC_CTRL1 0x02 |
AndyA | 0:bddb8cd5e7df | 52 | #define DWAGCCTRL_AGC_TUNE1 0x04 |
AndyA | 0:bddb8cd5e7df | 53 | #define DWAGCCTRL_AGC_TUNE2 0x0C |
AndyA | 0:bddb8cd5e7df | 54 | #define DWAGCCTRL_AGC_TUNE3 0x12 |
AndyA | 0:bddb8cd5e7df | 55 | |
AndyA | 0:bddb8cd5e7df | 56 | // EXT_SYNC sub registers |
AndyA | 0:bddb8cd5e7df | 57 | #define DWEXTSYNC_EC_CTRL 0x00 |
AndyA | 0:bddb8cd5e7df | 58 | #define DWEXTSYNC_EC_RXTC 0x04 |
AndyA | 0:bddb8cd5e7df | 59 | #define DWEXTSYNC_EC_GOLP 0x08 |
AndyA | 0:bddb8cd5e7df | 60 | |
AndyA | 0:bddb8cd5e7df | 61 | // GPIO sub registers |
AndyA | 0:bddb8cd5e7df | 62 | #define DWGPIO_GPIO_MODE 0x00 |
AndyA | 0:bddb8cd5e7df | 63 | #define DWGPIO_GPIO_DIR 0x08 |
AndyA | 0:bddb8cd5e7df | 64 | #define DWGPIO_GPIO_DOUT 0x0C |
AndyA | 0:bddb8cd5e7df | 65 | #define DWGPIO_GPIO_IRQE 0x10 |
AndyA | 0:bddb8cd5e7df | 66 | #define DWGPIO_GPIO_ISEN 0x14 |
AndyA | 0:bddb8cd5e7df | 67 | #define DWGPIO_GPIO_IMODE 0x18 |
AndyA | 0:bddb8cd5e7df | 68 | #define DWGPIO_GPIO_IBES 0x1C |
AndyA | 0:bddb8cd5e7df | 69 | #define DWGPIO_GPIO_ICLR 0x20 |
AndyA | 0:bddb8cd5e7df | 70 | #define DWGPIO_GPIO_IDBE 0x24 |
AndyA | 0:bddb8cd5e7df | 71 | #define DWGPIO_GPIO_RAW 0x28 |
AndyA | 0:bddb8cd5e7df | 72 | |
AndyA | 0:bddb8cd5e7df | 73 | // DRX sub registers |
AndyA | 0:bddb8cd5e7df | 74 | #define DWDRX_DRX_TUNE0B 0x02 |
AndyA | 0:bddb8cd5e7df | 75 | #define DWDRX_DRX_TUNE1A 0x04 |
AndyA | 0:bddb8cd5e7df | 76 | #define DWDRX_DRX_TUNE1B 0x06 |
AndyA | 0:bddb8cd5e7df | 77 | #define DWDRX_DRX_TUNE2 0x08 |
AndyA | 0:bddb8cd5e7df | 78 | #define DWDRX_DRX_SFDTOC 0x20 |
AndyA | 0:bddb8cd5e7df | 79 | #define DWDRX_DRX_PRETOC 0x24 |
AndyA | 0:bddb8cd5e7df | 80 | #define DWDRX_DRX_TUNE4H 0x26 |
AndyA | 0:bddb8cd5e7df | 81 | |
AndyA | 0:bddb8cd5e7df | 82 | //RF conf sub registers |
AndyA | 0:bddb8cd5e7df | 83 | #define DWRFCONF_RF_CONF 0x00 |
AndyA | 0:bddb8cd5e7df | 84 | #define DWRFCONF_RF_RXCTRLH 0x0B |
AndyA | 0:bddb8cd5e7df | 85 | #define DWRFCONF_RF_TXCTRL 0x0C |
AndyA | 0:bddb8cd5e7df | 86 | #define DWRFCONF_RF_STATUS 0x2C |
AndyA | 0:bddb8cd5e7df | 87 | #define DWRFCONF_RF_LDOTUNE 0x30 |
AndyA | 0:bddb8cd5e7df | 88 | |
AndyA | 0:bddb8cd5e7df | 89 | // TX cal sub registers |
AndyA | 0:bddb8cd5e7df | 90 | #define DWTXCAL_TC_SARC 0x00 |
AndyA | 0:bddb8cd5e7df | 91 | #define DWTXCAL_TC_SARL 0x03 |
AndyA | 0:bddb8cd5e7df | 92 | #define DWTXCAL_TC_SARW 0x06 |
AndyA | 0:bddb8cd5e7df | 93 | #define DWTXCAL_TC_PGDELAY 0x0B |
AndyA | 0:bddb8cd5e7df | 94 | #define DWTXCAL_TC_PGTEST 0x0C |
AndyA | 0:bddb8cd5e7df | 95 | |
AndyA | 0:bddb8cd5e7df | 96 | // Freq synth sub registers |
AndyA | 0:bddb8cd5e7df | 97 | #define DWFSCTRL_FS_PLLCFG 0x07 |
AndyA | 0:bddb8cd5e7df | 98 | #define DWFSCTRL_FS_PLLTUNE 0x0B |
AndyA | 0:bddb8cd5e7df | 99 | #define DWFSCTRL_FS_XTALT 0x0E |
AndyA | 0:bddb8cd5e7df | 100 | |
AndyA | 0:bddb8cd5e7df | 101 | // Always on sub registers |
AndyA | 0:bddb8cd5e7df | 102 | #define DWAON_AON_WCFG 0x00 |
AndyA | 0:bddb8cd5e7df | 103 | #define DWAON_AON_CTRL 0x02 |
AndyA | 0:bddb8cd5e7df | 104 | #define DWAON_AON_RDAT 0x03 |
AndyA | 0:bddb8cd5e7df | 105 | #define DWAON_AON_ADDR 0x04 |
AndyA | 0:bddb8cd5e7df | 106 | #define DWAON_AON_CFG0 0x06 |
AndyA | 0:bddb8cd5e7df | 107 | #define DWAON_AON_CFG1 0x0A |
AndyA | 0:bddb8cd5e7df | 108 | |
AndyA | 0:bddb8cd5e7df | 109 | // OTP sub registers |
AndyA | 0:bddb8cd5e7df | 110 | #define DWOTP_OTP_WDAT 0x00 |
AndyA | 0:bddb8cd5e7df | 111 | #define DWOTP_OTP_ADDR 0x04 |
AndyA | 0:bddb8cd5e7df | 112 | #define DWOTP_OTP_CTRL 0x06 |
AndyA | 0:bddb8cd5e7df | 113 | #define DWOTP_OTP_STAT 0x08 |
AndyA | 0:bddb8cd5e7df | 114 | #define DWOTP_OTP_RDAT 0x0A |
AndyA | 0:bddb8cd5e7df | 115 | #define DWOTP_OTP_SRDAT 0x0E |
AndyA | 0:bddb8cd5e7df | 116 | #define DWOTP_OTP_SF 0x12 |
AndyA | 0:bddb8cd5e7df | 117 | |
AndyA | 0:bddb8cd5e7df | 118 | //LDE_IF sub registers |
AndyA | 0:bddb8cd5e7df | 119 | #define DWLDE_LDE_THRESH 0x0000 |
AndyA | 0:bddb8cd5e7df | 120 | #define DWLDE_LDE_CFG1 0x0806 |
AndyA | 0:bddb8cd5e7df | 121 | #define DWLDE_LDE_PPINDX 0x1000 |
AndyA | 0:bddb8cd5e7df | 122 | #define DWLDE_LDE_PPAMPL 0x1002 |
AndyA | 0:bddb8cd5e7df | 123 | #define DWLDE_LDE_RXANTD 0x1804 |
AndyA | 0:bddb8cd5e7df | 124 | #define DWLDE_LDE_CFG2 0x1806 |
AndyA | 0:bddb8cd5e7df | 125 | #define DWLDE_LDE_REPC 0x2804 |
AndyA | 0:bddb8cd5e7df | 126 | |
AndyA | 0:bddb8cd5e7df | 127 | // Dig Diag sub registers |
AndyA | 0:bddb8cd5e7df | 128 | #define DWDIAG_EVC_CTRL 0x00 |
AndyA | 0:bddb8cd5e7df | 129 | #define DWDIAG_EVC_PHE 0x04 |
AndyA | 0:bddb8cd5e7df | 130 | #define DWDIAG_EVC_RSE 0x06 |
AndyA | 0:bddb8cd5e7df | 131 | #define DWDIAG_EVC_FCG 0x08 |
AndyA | 0:bddb8cd5e7df | 132 | #define DWDIAG_EVC_FCE 0x0A |
AndyA | 0:bddb8cd5e7df | 133 | #define DWDIAG_EVC_FFR 0x0C |
AndyA | 0:bddb8cd5e7df | 134 | #define DWDIAG_EVC_OVR 0x0E |
AndyA | 0:bddb8cd5e7df | 135 | #define DWDIAG_EVC_STO 0x10 |
AndyA | 0:bddb8cd5e7df | 136 | #define DWDIAG_EVC_PTO 0x12 |
AndyA | 0:bddb8cd5e7df | 137 | #define DWDIAG_EVC_FWTO 0x14 |
AndyA | 0:bddb8cd5e7df | 138 | #define DWDIAG_EVC_TXFS 0x16 |
AndyA | 0:bddb8cd5e7df | 139 | #define DWDIAG_EVC_HPW 0x18 |
AndyA | 0:bddb8cd5e7df | 140 | #define DWDIAG_EVC_TPW 0x1A |
AndyA | 0:bddb8cd5e7df | 141 | #define DWDIAG_DIAG_TMC 0x24 |
AndyA | 0:bddb8cd5e7df | 142 | |
AndyA | 0:bddb8cd5e7df | 143 | // power control sub registers |
AndyA | 0:bddb8cd5e7df | 144 | #define DWPMSC_PMSC_CTRL0 0x00 |
AndyA | 0:bddb8cd5e7df | 145 | #define DWPMSC_PMSC_CTRL1 0x04 |
AndyA | 0:bddb8cd5e7df | 146 | #define DWPMSC_PMSC_SNOZT 0x0C |
AndyA | 0:bddb8cd5e7df | 147 | #define DWPMSC_PMSC_TXFSEQ 0x26 |
AndyA | 0:bddb8cd5e7df | 148 | #define DWPMSC_PMSC_LEDC 0x28 |
AndyA | 0:bddb8cd5e7df | 149 | |
AndyA | 0:bddb8cd5e7df | 150 | |
AndyA | 0:bddb8cd5e7df | 151 | #define DW1000_WRITE_FLAG 0x80 // First Bit of the address has to be 1 to indicate we want to write |
AndyA | 0:bddb8cd5e7df | 152 | #define DW1000_SUBADDRESS_FLAG 0x40 // if we have a sub address second Bit has to be 1 |
AndyA | 0:bddb8cd5e7df | 153 | #define DW1000_2_SUBADDRESS_FLAG 0x80 // if we have a long sub adress (more than 7 Bit) we set this Bit in the first part |
AndyA | 0:bddb8cd5e7df | 154 | |
AndyA | 3:1459d2aa6b97 | 155 | /* |
AndyA | 3:1459d2aa6b97 | 156 | From user manual 10.5 |
AndyA | 3:1459d2aa6b97 | 157 | Table 59: |
AndyA | 3:1459d2aa6b97 | 158 | DW1000 supported UWB channels and recommended preamble codes |
AndyA | 3:1459d2aa6b97 | 159 | |
AndyA | 3:1459d2aa6b97 | 160 | channel 16MHzPrf 64MHzPrf |
AndyA | 3:1459d2aa6b97 | 161 | 1 1,2 9, 10, 11, 12 |
AndyA | 3:1459d2aa6b97 | 162 | 2 3, 4 9, 10, 11, 12 |
AndyA | 3:1459d2aa6b97 | 163 | 3 5, 6 9, 10, 11, 12 |
AndyA | 3:1459d2aa6b97 | 164 | 4 7, 8 17, 18, 19, 20 |
AndyA | 3:1459d2aa6b97 | 165 | 5 3, 4 9, 10, 11, 12 |
AndyA | 3:1459d2aa6b97 | 166 | 7 7, 8 17, 18, 19, 20 |
AndyA | 3:1459d2aa6b97 | 167 | */ |
AndyA | 3:1459d2aa6b97 | 168 | |
AndyA | 3:1459d2aa6b97 | 169 | |
AndyA | 4:5f1025df5530 | 170 | /** Class for holding DW1000 config options |
AndyA | 4:5f1025df5530 | 171 | * |
AndyA | 4:5f1025df5530 | 172 | */ |
AndyA | 4:5f1025df5530 | 173 | class DW1000Setup |
AndyA | 4:5f1025df5530 | 174 | { |
AndyA | 4:5f1025df5530 | 175 | public: |
AndyA | 4:5f1025df5530 | 176 | |
AndyA | 4:5f1025df5530 | 177 | /// Constructor - default settings are close to hardware defaults. |
AndyA | 4:5f1025df5530 | 178 | DW1000Setup() { |
AndyA | 4:5f1025df5530 | 179 | channel = 5; |
AndyA | 4:5f1025df5530 | 180 | prf =prf16MHz; |
AndyA | 4:5f1025df5530 | 181 | dataRate = kbps850; |
AndyA | 4:5f1025df5530 | 182 | sfd = standard; |
AndyA | 4:5f1025df5530 | 183 | preamble = pre128; |
AndyA | 4:5f1025df5530 | 184 | preambleCode = 3; |
AndyA | 4:5f1025df5530 | 185 | enableSmartPower = true; |
AndyA | 4:5f1025df5530 | 186 | } |
AndyA | 4:5f1025df5530 | 187 | |
AndyA | 4:5f1025df5530 | 188 | /// enum for PRF options |
AndyA | 4:5f1025df5530 | 189 | enum prf_e {prf16MHz,prf64MHz}; |
AndyA | 4:5f1025df5530 | 190 | |
AndyA | 4:5f1025df5530 | 191 | /// enum for data rate options |
AndyA | 4:5f1025df5530 | 192 | enum dataRate_e {kbps110,kbps850,kbps6800}; |
AndyA | 4:5f1025df5530 | 193 | |
AndyA | 4:5f1025df5530 | 194 | /// enum for SFD options |
AndyA | 4:5f1025df5530 | 195 | enum sfd_e {standard, decaWave, user}; |
AndyA | 4:5f1025df5530 | 196 | |
AndyA | 4:5f1025df5530 | 197 | /// enum for preamble length options |
AndyA | 4:5f1025df5530 | 198 | enum preamble_e { pre64, pre128, pre256, pre512, pre1024, pre1536, pre2048, pre4096}; |
AndyA | 4:5f1025df5530 | 199 | |
AndyA | 4:5f1025df5530 | 200 | /** Set the PRF |
AndyA | 4:5f1025df5530 | 201 | * @return true if a valid option |
AndyA | 4:5f1025df5530 | 202 | */ |
AndyA | 4:5f1025df5530 | 203 | bool setPRF(enum prf_e newSetting) { |
AndyA | 4:5f1025df5530 | 204 | prf = newSetting; |
AndyA | 4:5f1025df5530 | 205 | return true; |
AndyA | 4:5f1025df5530 | 206 | }; |
AndyA | 4:5f1025df5530 | 207 | |
AndyA | 4:5f1025df5530 | 208 | /** Set the Channel |
AndyA | 4:5f1025df5530 | 209 | * @return true if a valid option |
AndyA | 4:5f1025df5530 | 210 | */ |
AndyA | 4:5f1025df5530 | 211 | bool setChannel(unsigned char newChannel) { |
AndyA | 4:5f1025df5530 | 212 | if ((channel > 0) && ((channel <= 5) || (channel == 7))) { |
AndyA | 4:5f1025df5530 | 213 | channel = newChannel; |
AndyA | 4:5f1025df5530 | 214 | return true; |
AndyA | 4:5f1025df5530 | 215 | } |
AndyA | 4:5f1025df5530 | 216 | return false; |
AndyA | 4:5f1025df5530 | 217 | }; |
AndyA | 4:5f1025df5530 | 218 | /** Set the SFD |
AndyA | 4:5f1025df5530 | 219 | * @return true if a valid option |
AndyA | 4:5f1025df5530 | 220 | */ |
AndyA | 4:5f1025df5530 | 221 | bool setSfd(enum sfd_e newSetting) { |
AndyA | 4:5f1025df5530 | 222 | sfd = newSetting; |
AndyA | 4:5f1025df5530 | 223 | return true; |
AndyA | 4:5f1025df5530 | 224 | }; |
AndyA | 4:5f1025df5530 | 225 | /** Set the Preamble length |
AndyA | 4:5f1025df5530 | 226 | * @return true if a valid option |
AndyA | 4:5f1025df5530 | 227 | */ |
AndyA | 4:5f1025df5530 | 228 | bool setPreambleLength(enum preamble_e newSetting) { |
AndyA | 4:5f1025df5530 | 229 | preamble = newSetting; |
AndyA | 4:5f1025df5530 | 230 | return true; |
AndyA | 4:5f1025df5530 | 231 | }; |
AndyA | 4:5f1025df5530 | 232 | /** Set the Data rate |
AndyA | 4:5f1025df5530 | 233 | * @return true if a valid option |
AndyA | 4:5f1025df5530 | 234 | */ |
AndyA | 4:5f1025df5530 | 235 | bool setDataRate(enum dataRate_e newSetting) { |
AndyA | 4:5f1025df5530 | 236 | dataRate = newSetting; |
AndyA | 4:5f1025df5530 | 237 | return true; |
AndyA | 4:5f1025df5530 | 238 | }; |
AndyA | 4:5f1025df5530 | 239 | /** Set the Preamble code |
AndyA | 4:5f1025df5530 | 240 | * @return true if a valid option |
AndyA | 4:5f1025df5530 | 241 | * |
AndyA | 4:5f1025df5530 | 242 | * note - not all codes are valid for all channels. Set the channel first. |
AndyA | 4:5f1025df5530 | 243 | * TODO - enforce code restrictions |
AndyA | 4:5f1025df5530 | 244 | */ |
AndyA | 4:5f1025df5530 | 245 | bool setPreambleCode(unsigned char newCode) { |
AndyA | 4:5f1025df5530 | 246 | if ((newCode > 0) && (newCode <= 24)) { |
AndyA | 4:5f1025df5530 | 247 | preambleCode = newCode; |
AndyA | 4:5f1025df5530 | 248 | return true; |
AndyA | 4:5f1025df5530 | 249 | } |
AndyA | 4:5f1025df5530 | 250 | return false; |
AndyA | 4:5f1025df5530 | 251 | }; |
AndyA | 4:5f1025df5530 | 252 | /** Set the smartpower state |
AndyA | 4:5f1025df5530 | 253 | * @return true if a valid option |
AndyA | 4:5f1025df5530 | 254 | * |
AndyA | 4:5f1025df5530 | 255 | * only takes effect at 6.8Mb/s |
AndyA | 4:5f1025df5530 | 256 | */ |
AndyA | 4:5f1025df5530 | 257 | bool setSmartPower(bool enable) { |
AndyA | 4:5f1025df5530 | 258 | enableSmartPower = enable; |
AndyA | 4:5f1025df5530 | 259 | return true; |
AndyA | 4:5f1025df5530 | 260 | }; |
AndyA | 4:5f1025df5530 | 261 | |
AndyA | 4:5f1025df5530 | 262 | /** Get the current channel |
AndyA | 4:5f1025df5530 | 263 | * @return the channel number |
AndyA | 4:5f1025df5530 | 264 | */ |
AndyA | 4:5f1025df5530 | 265 | unsigned char getChannel() { |
AndyA | 4:5f1025df5530 | 266 | return channel; |
AndyA | 4:5f1025df5530 | 267 | }; |
AndyA | 4:5f1025df5530 | 268 | enum prf_e getPRF() { |
AndyA | 4:5f1025df5530 | 269 | return prf; |
AndyA | 4:5f1025df5530 | 270 | }; |
AndyA | 4:5f1025df5530 | 271 | enum dataRate_e getDataRate() { |
AndyA | 4:5f1025df5530 | 272 | return dataRate; |
AndyA | 4:5f1025df5530 | 273 | }; |
AndyA | 4:5f1025df5530 | 274 | |
AndyA | 4:5f1025df5530 | 275 | enum sfd_e getSfd() {return sfd;}; |
AndyA | 4:5f1025df5530 | 276 | enum preamble_e getPreambleLength() { |
AndyA | 4:5f1025df5530 | 277 | return preamble; |
AndyA | 4:5f1025df5530 | 278 | }; |
AndyA | 4:5f1025df5530 | 279 | unsigned char getPreambleCode() { |
AndyA | 4:5f1025df5530 | 280 | return preambleCode; |
AndyA | 4:5f1025df5530 | 281 | }; |
AndyA | 4:5f1025df5530 | 282 | bool getSmartPower() { |
AndyA | 4:5f1025df5530 | 283 | return enableSmartPower; |
AndyA | 4:5f1025df5530 | 284 | }; |
AndyA | 4:5f1025df5530 | 285 | |
AndyA | 4:5f1025df5530 | 286 | private: |
AndyA | 4:5f1025df5530 | 287 | unsigned char channel; // 1-5 , 7 |
AndyA | 4:5f1025df5530 | 288 | enum prf_e prf; |
AndyA | 4:5f1025df5530 | 289 | enum dataRate_e dataRate; |
AndyA | 4:5f1025df5530 | 290 | enum sfd_e sfd; |
AndyA | 4:5f1025df5530 | 291 | enum preamble_e preamble; |
AndyA | 4:5f1025df5530 | 292 | unsigned char preambleCode; // 1-24. See section 10.5 of user manual for details. |
AndyA | 4:5f1025df5530 | 293 | bool enableSmartPower; |
AndyA | 4:5f1025df5530 | 294 | }; |
AndyA | 4:5f1025df5530 | 295 | |
AndyA | 4:5f1025df5530 | 296 | |
AndyA | 3:1459d2aa6b97 | 297 | typedef enum {minPacketSize, tunedDefault, user110k} UWBMode; |
AndyA | 0:bddb8cd5e7df | 298 | |
AndyA | 4:5f1025df5530 | 299 | /** A DW1000 driver |
AndyA | 4:5f1025df5530 | 300 | */ |
AndyA | 0:bddb8cd5e7df | 301 | class DW1000 |
AndyA | 0:bddb8cd5e7df | 302 | { |
AndyA | 0:bddb8cd5e7df | 303 | public: |
AndyA | 0:bddb8cd5e7df | 304 | |
AndyA | 0:bddb8cd5e7df | 305 | DW1000(UWBMode setup, PinName MOSI, PinName MISO, PinName SCLK, PinName CS, PinName IRQ); // constructor, uses SPI class |
AndyA | 0:bddb8cd5e7df | 306 | void setCallbacks(void (*callbackRX)(void), void (*callbackTX)(void)); // setter for callback functions, automatically enables interrupt, if NULL is passed the coresponding interrupt gets disabled |
AndyA | 0:bddb8cd5e7df | 307 | template<typename T> |
AndyA | 0:bddb8cd5e7df | 308 | void setCallbacks(T* tptr, void (T::*mptrRX)(void), void (T::*mptrTX)(void)) { // overloaded setter to treat member function pointers of objects |
AndyA | 0:bddb8cd5e7df | 309 | callbackRX.attach(tptr, mptrRX); // possible client code: dw.setCallbacks(this, &A::callbackRX, &A::callbackTX); |
AndyA | 0:bddb8cd5e7df | 310 | callbackTX.attach(tptr, mptrTX); // concept seen in line 100 of http://developer.mbed.org/users/mbed_official/code/mbed/docs/4fc01daae5a5/InterruptIn_8h_source.html |
AndyA | 0:bddb8cd5e7df | 311 | setInterrupt(true,true); |
AndyA | 0:bddb8cd5e7df | 312 | } |
AndyA | 0:bddb8cd5e7df | 313 | |
AndyA | 0:bddb8cd5e7df | 314 | // Device API |
AndyA | 0:bddb8cd5e7df | 315 | uint32_t getDeviceID(); // gets the Device ID which should be 0xDECA0130 (good for testing SPI!) |
AndyA | 0:bddb8cd5e7df | 316 | uint64_t getEUI(); // gets 64 bit Extended Unique Identifier according to IEEE standard |
AndyA | 0:bddb8cd5e7df | 317 | void setEUI(uint64_t EUI); // sets 64 bit Extended Unique Identifier according to IEEE standard |
AndyA | 0:bddb8cd5e7df | 318 | float getVoltage(); // gets the current chip voltage measurement form the A/D converter |
AndyA | 0:bddb8cd5e7df | 319 | float getTemperature(); // gets the current chip temperature measurement form the A/D converter |
AndyA | 0:bddb8cd5e7df | 320 | uint64_t getStatus(); // get the 40 bit device status |
AndyA | 0:bddb8cd5e7df | 321 | uint64_t getRXTimestamp(); |
AndyA | 0:bddb8cd5e7df | 322 | uint64_t getTXTimestamp(); |
AndyA | 0:bddb8cd5e7df | 323 | |
AndyA | 0:bddb8cd5e7df | 324 | void sendString(char* message); // to send String with arbitrary length |
AndyA | 0:bddb8cd5e7df | 325 | void receiveString(char* message); // to receive char string (length of the buffer must be 1021 to be safe) |
AndyA | 0:bddb8cd5e7df | 326 | void sendFrame(uint8_t* message, uint16_t length); // send a raw frame (length in bytes) |
AndyA | 0:bddb8cd5e7df | 327 | void sendDelayedFrame(uint8_t* message, uint16_t length, uint64_t TxTimestamp); |
AndyA | 0:bddb8cd5e7df | 328 | |
AndyA | 0:bddb8cd5e7df | 329 | void setupSyncedFrame(uint8_t* message, uint16_t length); |
AndyA | 0:bddb8cd5e7df | 330 | void armSyncedFrame(); |
AndyA | 0:bddb8cd5e7df | 331 | |
AndyA | 0:bddb8cd5e7df | 332 | void startRX(); // start listening for frames |
AndyA | 0:bddb8cd5e7df | 333 | void stopTRX(); // disable tranceiver go back to idle mode |
AndyA | 0:bddb8cd5e7df | 334 | |
AndyA | 0:bddb8cd5e7df | 335 | void setRxDelay(uint16_t ticks); |
AndyA | 0:bddb8cd5e7df | 336 | void setTxDelay(uint16_t ticks); |
AndyA | 0:bddb8cd5e7df | 337 | |
AndyA | 0:bddb8cd5e7df | 338 | uint16_t getFramelength(); // to get the framelength of the received frame from the PHY header |
AndyA | 0:bddb8cd5e7df | 339 | |
AndyA | 0:bddb8cd5e7df | 340 | void readRxBuffer( uint8_t *buffer, int length ) { |
AndyA | 0:bddb8cd5e7df | 341 | readRegister(DW1000_RX_BUFFER, 0, buffer, length); |
AndyA | 0:bddb8cd5e7df | 342 | } |
AndyA | 0:bddb8cd5e7df | 343 | |
AndyA | 1:dcbd071f38d5 | 344 | uint32_t readOTP (uint16_t word_address); |
AndyA | 0:bddb8cd5e7df | 345 | bool writeOTP(uint16_t word_address,uint32_t data); // program a value in the OTP. It is recommended to reset afterwards. |
AndyA | 0:bddb8cd5e7df | 346 | |
AndyA | 4:5f1025df5530 | 347 | /** Get setup description |
AndyA | 4:5f1025df5530 | 348 | * |
AndyA | 4:5f1025df5530 | 349 | * @param buffer Data buffer to place description in |
AndyA | 4:5f1025df5530 | 350 | * @param len Length of data buffer |
AndyA | 4:5f1025df5530 | 351 | * |
AndyA | 4:5f1025df5530 | 352 | * Places a text string describing the current setup into the suppled buffer. |
AndyA | 4:5f1025df5530 | 353 | */ |
AndyA | 4:5f1025df5530 | 354 | void getSetup(char *buffer, int len); |
AndyA | 4:5f1025df5530 | 355 | |
AndyA | 0:bddb8cd5e7df | 356 | protected: |
AndyA | 0:bddb8cd5e7df | 357 | void resetRX(); // soft reset only the tranciever part of DW1000 |
AndyA | 0:bddb8cd5e7df | 358 | void setInterrupt(bool RX, bool TX); // set Interrupt for received a good frame (CRC ok) or transmission done |
AndyA | 0:bddb8cd5e7df | 359 | |
AndyA | 3:1459d2aa6b97 | 360 | /** Set Transmit gain |
AndyA | 3:1459d2aa6b97 | 361 | * |
AndyA | 3:1459d2aa6b97 | 362 | * @param normalPowercB Normal transmit gain to use. |
AndyA | 3:1459d2aa6b97 | 363 | * @param boost500 Gain to use for 6.8Mb/s packets of under 500ms. |
AndyA | 3:1459d2aa6b97 | 364 | * @param boost250 Gain to use for 6.8Mb/s packets of under 250ms. |
AndyA | 3:1459d2aa6b97 | 365 | * @param boost125 Gain to use for 6.8Mb/s packets of under 125ms. |
AndyA | 3:1459d2aa6b97 | 366 | * |
AndyA | 3:1459d2aa6b97 | 367 | * All gains are in cB (dB * 10). Gains can be between 0 and 335 (33.5dB). |
AndyA | 3:1459d2aa6b97 | 368 | * Boost gains are optional, if not specified boost gains are set to the power for the lower rate (e.g. boost125 is set to the boost250 level). |
AndyA | 3:1459d2aa6b97 | 369 | */ |
AndyA | 3:1459d2aa6b97 | 370 | void setTxPower(uint16_t normalPowercB, uint16_t boost500 = 0, uint16_t boost250 = 0, uint16_t boost125 = 0); |
AndyA | 3:1459d2aa6b97 | 371 | |
AndyA | 0:bddb8cd5e7df | 372 | |
AndyA | 0:bddb8cd5e7df | 373 | private: |
AndyA | 0:bddb8cd5e7df | 374 | void resetAll(); // soft reset the entire DW1000 (some registers stay as they were see User Manual) |
AndyA | 3:1459d2aa6b97 | 375 | |
AndyA | 3:1459d2aa6b97 | 376 | void setupRadio(); |
AndyA | 3:1459d2aa6b97 | 377 | |
AndyA | 4:5f1025df5530 | 378 | // system register setup functions |
AndyA | 3:1459d2aa6b97 | 379 | void setupAGC(); |
AndyA | 3:1459d2aa6b97 | 380 | void setupRxConfig(); |
AndyA | 3:1459d2aa6b97 | 381 | void setupLDE(); |
AndyA | 3:1459d2aa6b97 | 382 | void setupChannel(); |
AndyA | 3:1459d2aa6b97 | 383 | void setupTxFrameCtrl(); |
AndyA | 3:1459d2aa6b97 | 384 | void setupAnalogRF(); |
AndyA | 3:1459d2aa6b97 | 385 | void setupFreqSynth(); |
AndyA | 3:1459d2aa6b97 | 386 | void setupTxCalibration(); |
AndyA | 3:1459d2aa6b97 | 387 | void setupSystemConfig(); |
AndyA | 0:bddb8cd5e7df | 388 | void loadLDE(); // load the leading edge detection algorithm to RAM, [IMPORTANT because receiving malfunction may occur] see User Manual LDELOAD on p22 & p158 |
AndyA | 0:bddb8cd5e7df | 389 | void loadLDOTUNE(); // load the LDO tuning as set in the factory |
AndyA | 4:5f1025df5530 | 390 | |
AndyA | 3:1459d2aa6b97 | 391 | uint8_t powerToRegValue(uint16_t powercB); |
AndyA | 3:1459d2aa6b97 | 392 | |
AndyA | 4:5f1025df5530 | 393 | DW1000Setup systemConfig; |
AndyA | 3:1459d2aa6b97 | 394 | |
AndyA | 0:bddb8cd5e7df | 395 | |
AndyA | 0:bddb8cd5e7df | 396 | |
AndyA | 0:bddb8cd5e7df | 397 | // Interrupt |
AndyA | 0:bddb8cd5e7df | 398 | InterruptIn irq; // Pin used to handle Events from DW1000 by an Interrupthandler |
AndyA | 0:bddb8cd5e7df | 399 | FunctionPointer callbackRX; // function pointer to callback which is called when successfull RX took place |
AndyA | 0:bddb8cd5e7df | 400 | FunctionPointer callbackTX; // function pointer to callback which is called when successfull TX took place |
AndyA | 0:bddb8cd5e7df | 401 | void ISR(); // interrupt handling method (also calls according callback methods) |
AndyA | 0:bddb8cd5e7df | 402 | |
AndyA | 0:bddb8cd5e7df | 403 | // SPI Inteface |
AndyA | 0:bddb8cd5e7df | 404 | SPI spi; // SPI Bus |
AndyA | 0:bddb8cd5e7df | 405 | DigitalOut cs; // Slave selector for SPI-Bus (here explicitly needed to start and end SPI transactions also usable to wake up DW1000) |
AndyA | 0:bddb8cd5e7df | 406 | |
AndyA | 0:bddb8cd5e7df | 407 | uint8_t readRegister8(uint8_t reg, uint16_t subaddress); // expressive methods to read or write the number of bits written in the name |
AndyA | 0:bddb8cd5e7df | 408 | uint16_t readRegister16(uint8_t reg, uint16_t subaddress); |
AndyA | 0:bddb8cd5e7df | 409 | uint32_t readRegister32(uint8_t reg, uint16_t subaddress); |
AndyA | 0:bddb8cd5e7df | 410 | uint64_t readRegister40(uint8_t reg, uint16_t subaddress); |
AndyA | 0:bddb8cd5e7df | 411 | uint64_t readRegister64(uint8_t reg, uint16_t subaddress); |
AndyA | 0:bddb8cd5e7df | 412 | void writeRegister8(uint8_t reg, uint16_t subaddress, uint8_t buffer); |
AndyA | 0:bddb8cd5e7df | 413 | void writeRegister16(uint8_t reg, uint16_t subaddress, uint16_t buffer); |
AndyA | 0:bddb8cd5e7df | 414 | void writeRegister32(uint8_t reg, uint16_t subaddress, uint32_t buffer); |
AndyA | 0:bddb8cd5e7df | 415 | void writeRegister40(uint8_t reg, uint16_t subaddress, uint64_t buffer); |
AndyA | 0:bddb8cd5e7df | 416 | |
AndyA | 0:bddb8cd5e7df | 417 | void readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // reads the selected part of a slave register into the buffer memory |
AndyA | 0:bddb8cd5e7df | 418 | void writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // writes the buffer memory to the selected slave register |
AndyA | 0:bddb8cd5e7df | 419 | void setupTransaction(uint8_t reg, uint16_t subaddress, bool write); // sets up an SPI read or write transaction with correct register address and offset |
AndyA | 0:bddb8cd5e7df | 420 | void select(); // selects the only slave for a transaction |
AndyA | 0:bddb8cd5e7df | 421 | void deselect(); // deselects the only slave after transaction |
AndyA | 0:bddb8cd5e7df | 422 | }; |
AndyA | 0:bddb8cd5e7df | 423 | |
AndyA | 0:bddb8cd5e7df | 424 | #endif |