A library to interface with the LSM9DS1 IMU using SPI
LSM9DS1_SPI_Registers.h@0:dc98084cf6be, 2017-10-18 (annotated)
- Committer:
- Anaesthetix
- Date:
- Wed Oct 18 09:22:00 2017 +0000
- Revision:
- 0:dc98084cf6be
LSM9DS1 spi library
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Anaesthetix | 0:dc98084cf6be | 1 | /****************************************************************************** |
Anaesthetix | 0:dc98084cf6be | 2 | LSM9DS1_Registers.h |
Anaesthetix | 0:dc98084cf6be | 3 | SFE_LSM9DS1 Library - LSM9DS1 Register Map |
Anaesthetix | 0:dc98084cf6be | 4 | Jim Lindblom @ SparkFun Electronics |
Anaesthetix | 0:dc98084cf6be | 5 | Original Creation Date: April 21, 2015 |
Anaesthetix | 0:dc98084cf6be | 6 | https://github.com/sparkfun/LSM9DS1_Breakout |
Anaesthetix | 0:dc98084cf6be | 7 | |
Anaesthetix | 0:dc98084cf6be | 8 | This file defines all registers internal to the gyro/accel and magnetometer |
Anaesthetix | 0:dc98084cf6be | 9 | devices in the LSM9DS1. |
Anaesthetix | 0:dc98084cf6be | 10 | |
Anaesthetix | 0:dc98084cf6be | 11 | Development environment specifics: |
Anaesthetix | 0:dc98084cf6be | 12 | IDE: Arduino 1.6.0 |
Anaesthetix | 0:dc98084cf6be | 13 | Hardware Platform: Arduino Uno |
Anaesthetix | 0:dc98084cf6be | 14 | LSM9DS1 Breakout Version: 1.0 |
Anaesthetix | 0:dc98084cf6be | 15 | |
Anaesthetix | 0:dc98084cf6be | 16 | This code is beerware; if you see me (or any other SparkFun employee) at the |
Anaesthetix | 0:dc98084cf6be | 17 | local, and you've found our code helpful, please buy us a round! |
Anaesthetix | 0:dc98084cf6be | 18 | |
Anaesthetix | 0:dc98084cf6be | 19 | Distributed as-is; no warranty is given. |
Anaesthetix | 0:dc98084cf6be | 20 | ******************************************************************************/ |
Anaesthetix | 0:dc98084cf6be | 21 | |
Anaesthetix | 0:dc98084cf6be | 22 | #ifndef __LSM9DS1_Registers_H__ |
Anaesthetix | 0:dc98084cf6be | 23 | #define __LSM9DS1_Registers_H__ |
Anaesthetix | 0:dc98084cf6be | 24 | |
Anaesthetix | 0:dc98084cf6be | 25 | ///////////////////////////////////////// |
Anaesthetix | 0:dc98084cf6be | 26 | // LSM9DS1 Accel/Gyro (XL/G) Registers // |
Anaesthetix | 0:dc98084cf6be | 27 | ///////////////////////////////////////// |
Anaesthetix | 0:dc98084cf6be | 28 | #define ACT_THS 0x04 |
Anaesthetix | 0:dc98084cf6be | 29 | #define ACT_DUR 0x05 |
Anaesthetix | 0:dc98084cf6be | 30 | #define INT_GEN_CFG_XL 0x06 |
Anaesthetix | 0:dc98084cf6be | 31 | #define INT_GEN_THS_X_XL 0x07 |
Anaesthetix | 0:dc98084cf6be | 32 | #define INT_GEN_THS_Y_XL 0x08 |
Anaesthetix | 0:dc98084cf6be | 33 | #define INT_GEN_THS_Z_XL 0x09 |
Anaesthetix | 0:dc98084cf6be | 34 | #define INT_GEN_DUR_XL 0x0A |
Anaesthetix | 0:dc98084cf6be | 35 | #define REFERENCE_G 0x0B |
Anaesthetix | 0:dc98084cf6be | 36 | #define INT1_CTRL 0x0C |
Anaesthetix | 0:dc98084cf6be | 37 | #define INT2_CTRL 0x0D |
Anaesthetix | 0:dc98084cf6be | 38 | #define WHO_AM_I_XG 0x0F |
Anaesthetix | 0:dc98084cf6be | 39 | #define CTRL_REG1_G 0x10 |
Anaesthetix | 0:dc98084cf6be | 40 | #define CTRL_REG2_G 0x11 |
Anaesthetix | 0:dc98084cf6be | 41 | #define CTRL_REG3_G 0x12 |
Anaesthetix | 0:dc98084cf6be | 42 | #define ORIENT_CFG_G 0x13 |
Anaesthetix | 0:dc98084cf6be | 43 | #define INT_GEN_SRC_G 0x14 |
Anaesthetix | 0:dc98084cf6be | 44 | #define OUT_TEMP_L 0x15 |
Anaesthetix | 0:dc98084cf6be | 45 | #define OUT_TEMP_H 0x16 |
Anaesthetix | 0:dc98084cf6be | 46 | #define STATUS_REG_0 0x17 |
Anaesthetix | 0:dc98084cf6be | 47 | #define OUT_X_L_G 0x18 |
Anaesthetix | 0:dc98084cf6be | 48 | #define OUT_X_H_G 0x19 |
Anaesthetix | 0:dc98084cf6be | 49 | #define OUT_Y_L_G 0x1A |
Anaesthetix | 0:dc98084cf6be | 50 | #define OUT_Y_H_G 0x1B |
Anaesthetix | 0:dc98084cf6be | 51 | #define OUT_Z_L_G 0x1C |
Anaesthetix | 0:dc98084cf6be | 52 | #define OUT_Z_H_G 0x1D |
Anaesthetix | 0:dc98084cf6be | 53 | #define CTRL_REG4 0x1E |
Anaesthetix | 0:dc98084cf6be | 54 | #define CTRL_REG5_XL 0x1F |
Anaesthetix | 0:dc98084cf6be | 55 | #define CTRL_REG6_XL 0x20 |
Anaesthetix | 0:dc98084cf6be | 56 | #define CTRL_REG7_XL 0x21 |
Anaesthetix | 0:dc98084cf6be | 57 | #define CTRL_REG8 0x22 |
Anaesthetix | 0:dc98084cf6be | 58 | #define CTRL_REG9 0x23 |
Anaesthetix | 0:dc98084cf6be | 59 | #define CTRL_REG10 0x24 |
Anaesthetix | 0:dc98084cf6be | 60 | #define INT_GEN_SRC_XL 0x26 |
Anaesthetix | 0:dc98084cf6be | 61 | #define STATUS_REG_1 0x27 |
Anaesthetix | 0:dc98084cf6be | 62 | #define OUT_X_L_XL 0x28 |
Anaesthetix | 0:dc98084cf6be | 63 | #define OUT_X_H_XL 0x29 |
Anaesthetix | 0:dc98084cf6be | 64 | #define OUT_Y_L_XL 0x2A |
Anaesthetix | 0:dc98084cf6be | 65 | #define OUT_Y_H_XL 0x2B |
Anaesthetix | 0:dc98084cf6be | 66 | #define OUT_Z_L_XL 0x2C |
Anaesthetix | 0:dc98084cf6be | 67 | #define OUT_Z_H_XL 0x2D |
Anaesthetix | 0:dc98084cf6be | 68 | #define FIFO_CTRL 0x2E |
Anaesthetix | 0:dc98084cf6be | 69 | #define FIFO_SRC 0x2F |
Anaesthetix | 0:dc98084cf6be | 70 | #define INT_GEN_CFG_G 0x30 |
Anaesthetix | 0:dc98084cf6be | 71 | #define INT_GEN_THS_XH_G 0x31 |
Anaesthetix | 0:dc98084cf6be | 72 | #define INT_GEN_THS_XL_G 0x32 |
Anaesthetix | 0:dc98084cf6be | 73 | #define INT_GEN_THS_YH_G 0x33 |
Anaesthetix | 0:dc98084cf6be | 74 | #define INT_GEN_THS_YL_G 0x34 |
Anaesthetix | 0:dc98084cf6be | 75 | #define INT_GEN_THS_ZH_G 0x35 |
Anaesthetix | 0:dc98084cf6be | 76 | #define INT_GEN_THS_ZL_G 0x36 |
Anaesthetix | 0:dc98084cf6be | 77 | #define INT_GEN_DUR_G 0x37 |
Anaesthetix | 0:dc98084cf6be | 78 | |
Anaesthetix | 0:dc98084cf6be | 79 | /////////////////////////////// |
Anaesthetix | 0:dc98084cf6be | 80 | // LSM9DS1 Magneto Registers // |
Anaesthetix | 0:dc98084cf6be | 81 | /////////////////////////////// |
Anaesthetix | 0:dc98084cf6be | 82 | #define OFFSET_X_REG_L_M 0x05 |
Anaesthetix | 0:dc98084cf6be | 83 | #define OFFSET_X_REG_H_M 0x06 |
Anaesthetix | 0:dc98084cf6be | 84 | #define OFFSET_Y_REG_L_M 0x07 |
Anaesthetix | 0:dc98084cf6be | 85 | #define OFFSET_Y_REG_H_M 0x08 |
Anaesthetix | 0:dc98084cf6be | 86 | #define OFFSET_Z_REG_L_M 0x09 |
Anaesthetix | 0:dc98084cf6be | 87 | #define OFFSET_Z_REG_H_M 0x0A |
Anaesthetix | 0:dc98084cf6be | 88 | #define WHO_AM_I_M 0x0F |
Anaesthetix | 0:dc98084cf6be | 89 | #define CTRL_REG1_M 0x20 |
Anaesthetix | 0:dc98084cf6be | 90 | #define CTRL_REG2_M 0x21 |
Anaesthetix | 0:dc98084cf6be | 91 | #define CTRL_REG3_M 0x22 |
Anaesthetix | 0:dc98084cf6be | 92 | #define CTRL_REG4_M 0x23 |
Anaesthetix | 0:dc98084cf6be | 93 | #define CTRL_REG5_M 0x24 |
Anaesthetix | 0:dc98084cf6be | 94 | #define STATUS_REG_M 0x27 |
Anaesthetix | 0:dc98084cf6be | 95 | #define OUT_X_L_M 0x28 |
Anaesthetix | 0:dc98084cf6be | 96 | #define OUT_X_H_M 0x29 |
Anaesthetix | 0:dc98084cf6be | 97 | #define OUT_Y_L_M 0x2A |
Anaesthetix | 0:dc98084cf6be | 98 | #define OUT_Y_H_M 0x2B |
Anaesthetix | 0:dc98084cf6be | 99 | #define OUT_Z_L_M 0x2C |
Anaesthetix | 0:dc98084cf6be | 100 | #define OUT_Z_H_M 0x2D |
Anaesthetix | 0:dc98084cf6be | 101 | #define INT_CFG_M 0x30 |
Anaesthetix | 0:dc98084cf6be | 102 | #define INT_SRC_M 0x30 |
Anaesthetix | 0:dc98084cf6be | 103 | #define INT_THS_L_M 0x32 |
Anaesthetix | 0:dc98084cf6be | 104 | #define INT_THS_H_M 0x33 |
Anaesthetix | 0:dc98084cf6be | 105 | |
Anaesthetix | 0:dc98084cf6be | 106 | //////////////////////////////// |
Anaesthetix | 0:dc98084cf6be | 107 | // LSM9DS1 WHO_AM_I Responses // |
Anaesthetix | 0:dc98084cf6be | 108 | //////////////////////////////// |
Anaesthetix | 0:dc98084cf6be | 109 | #define WHO_AM_I_AG_RSP 0x68 |
Anaesthetix | 0:dc98084cf6be | 110 | #define WHO_AM_I_M_RSP 0x3D |
Anaesthetix | 0:dc98084cf6be | 111 | |
Anaesthetix | 0:dc98084cf6be | 112 | #endif |
Anaesthetix | 0:dc98084cf6be | 113 |