Provides an API software interface to TIMER2 to control upto four stepper motors.
inc/IOmacros.h@0:7393c52297ee, 2011-05-02 (annotated)
- Committer:
- AjK
- Date:
- Mon May 02 10:02:18 2011 +0000
- Revision:
- 0:7393c52297ee
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AjK | 0:7393c52297ee | 1 | /**************************************************************************** |
AjK | 0:7393c52297ee | 2 | * Product: LIB17 Open Source Library |
AjK | 0:7393c52297ee | 3 | * |
AjK | 0:7393c52297ee | 4 | * Steller Technologies Limited |
AjK | 0:7393c52297ee | 5 | * ---------------------------- |
AjK | 0:7393c52297ee | 6 | * |
AjK | 0:7393c52297ee | 7 | * Copyright (C) 2002-2011 Steller Technologies Limited. All rights reserved. |
AjK | 0:7393c52297ee | 8 | * |
AjK | 0:7393c52297ee | 9 | * This software may be distributed and modified under the terms of the GNU |
AjK | 0:7393c52297ee | 10 | * General Public License version 2 (GPL) as published by the Free Software |
AjK | 0:7393c52297ee | 11 | * Foundation and appearing in the file GPL.TXT included in the packaging of |
AjK | 0:7393c52297ee | 12 | * this file. Please note that GPL Section 2[b] requires that all works based |
AjK | 0:7393c52297ee | 13 | * on this software must also be made publicly available under the terms of |
AjK | 0:7393c52297ee | 14 | * the GPL ("Copyleft"). |
AjK | 0:7393c52297ee | 15 | * |
AjK | 0:7393c52297ee | 16 | * Alternatively, this software may be distributed and modified under the |
AjK | 0:7393c52297ee | 17 | * terms of Steller Technologies Limited commercial licenses, which expressly |
AjK | 0:7393c52297ee | 18 | * supersede the GPL and are specifically designed for licensees interested in |
AjK | 0:7393c52297ee | 19 | * retaining the proprietary status of their code. |
AjK | 0:7393c52297ee | 20 | * |
AjK | 0:7393c52297ee | 21 | ***************************************************************************/ |
AjK | 0:7393c52297ee | 22 | |
AjK | 0:7393c52297ee | 23 | #ifndef AJK_LIB17_IOMACROS_H |
AjK | 0:7393c52297ee | 24 | #define AJK_LIB17_IOMACROS_H |
AjK | 0:7393c52297ee | 25 | |
AjK | 0:7393c52297ee | 26 | #ifndef __LPC17xx_H__ |
AjK | 0:7393c52297ee | 27 | #include "LPC17xx.h" |
AjK | 0:7393c52297ee | 28 | #endif |
AjK | 0:7393c52297ee | 29 | |
AjK | 0:7393c52297ee | 30 | #define PIN_PULLUP 0UL |
AjK | 0:7393c52297ee | 31 | #define PIN_REPEAT 1UL |
AjK | 0:7393c52297ee | 32 | #define PIN_NONE 2UL |
AjK | 0:7393c52297ee | 33 | #define PIN_PULLDOWN 3UL |
AjK | 0:7393c52297ee | 34 | |
AjK | 0:7393c52297ee | 35 | /* p5 is P0.9 */ |
AjK | 0:7393c52297ee | 36 | #define p5_SEL_MASK ~(3UL << 18) |
AjK | 0:7393c52297ee | 37 | #define p5_SET_MASK (1UL << 9) |
AjK | 0:7393c52297ee | 38 | #define p5_CLR_MASK ~(p5_SET_MASK) |
AjK | 0:7393c52297ee | 39 | #define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK |
AjK | 0:7393c52297ee | 40 | #define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK; |
AjK | 0:7393c52297ee | 41 | #define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK |
AjK | 0:7393c52297ee | 42 | #define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK |
AjK | 0:7393c52297ee | 43 | #define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK) |
AjK | 0:7393c52297ee | 44 | #define p5_IS_CLR !(p5_IS_SET) |
AjK | 0:7393c52297ee | 45 | #define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18) |
AjK | 0:7393c52297ee | 46 | |
AjK | 0:7393c52297ee | 47 | /* p6 is P0.8 */ |
AjK | 0:7393c52297ee | 48 | #define p6_SEL_MASK ~(3UL << 16) |
AjK | 0:7393c52297ee | 49 | #define p6_SET_MASK (1UL << 8) |
AjK | 0:7393c52297ee | 50 | #define p6_CLR_MASK ~(p6_SET_MASK) |
AjK | 0:7393c52297ee | 51 | #define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6_SET_MASK |
AjK | 0:7393c52297ee | 52 | #define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK; |
AjK | 0:7393c52297ee | 53 | #define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK |
AjK | 0:7393c52297ee | 54 | #define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK |
AjK | 0:7393c52297ee | 55 | #define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK) |
AjK | 0:7393c52297ee | 56 | #define p6_IS_CLR !(p6_IS_SET) |
AjK | 0:7393c52297ee | 57 | #define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16) |
AjK | 0:7393c52297ee | 58 | |
AjK | 0:7393c52297ee | 59 | /* p7 is P0.7 */ |
AjK | 0:7393c52297ee | 60 | #define p7_SEL_MASK ~(3UL << 14) |
AjK | 0:7393c52297ee | 61 | #define p7_SET_MASK (1UL << 7) |
AjK | 0:7393c52297ee | 62 | #define p7_CLR_MASK ~(p7_SET_MASK) |
AjK | 0:7393c52297ee | 63 | #define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK |
AjK | 0:7393c52297ee | 64 | #define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK; |
AjK | 0:7393c52297ee | 65 | #define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK |
AjK | 0:7393c52297ee | 66 | #define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK |
AjK | 0:7393c52297ee | 67 | #define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK) |
AjK | 0:7393c52297ee | 68 | #define p7_IS_CLR !(p7_IS_SET) |
AjK | 0:7393c52297ee | 69 | #define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14) |
AjK | 0:7393c52297ee | 70 | |
AjK | 0:7393c52297ee | 71 | /* p8 is P0.6 */ |
AjK | 0:7393c52297ee | 72 | #define p8_SEL_MASK ~(3UL << 12) |
AjK | 0:7393c52297ee | 73 | #define p8_SET_MASK (1UL << 6) |
AjK | 0:7393c52297ee | 74 | #define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK |
AjK | 0:7393c52297ee | 75 | #define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK; |
AjK | 0:7393c52297ee | 76 | #define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK |
AjK | 0:7393c52297ee | 77 | #define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK |
AjK | 0:7393c52297ee | 78 | #define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK) |
AjK | 0:7393c52297ee | 79 | #define p8_IS_CLR !(p8_IS_SET) |
AjK | 0:7393c52297ee | 80 | #define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12) |
AjK | 0:7393c52297ee | 81 | |
AjK | 0:7393c52297ee | 82 | /* p9 is P0.0 */ |
AjK | 0:7393c52297ee | 83 | #define p9_SEL_MASK ~(3UL << 0) |
AjK | 0:7393c52297ee | 84 | #define p9_SET_MASK (1UL << 0) |
AjK | 0:7393c52297ee | 85 | #define p9_CLR_MASK ~(p9_SET_MASK) |
AjK | 0:7393c52297ee | 86 | #define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK |
AjK | 0:7393c52297ee | 87 | #define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK; |
AjK | 0:7393c52297ee | 88 | #define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK |
AjK | 0:7393c52297ee | 89 | #define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK |
AjK | 0:7393c52297ee | 90 | #define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK) |
AjK | 0:7393c52297ee | 91 | #define p9_IS_CLR !(p9_IS_SET) |
AjK | 0:7393c52297ee | 92 | #define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0) |
AjK | 0:7393c52297ee | 93 | |
AjK | 0:7393c52297ee | 94 | /* p10 is P0.1 */ |
AjK | 0:7393c52297ee | 95 | #define p10_SEL_MASK ~(3UL << 2) |
AjK | 0:7393c52297ee | 96 | #define p10_SET_MASK (1UL << 1) |
AjK | 0:7393c52297ee | 97 | #define p10_CLR_MASK ~(p10_SET_MASK) |
AjK | 0:7393c52297ee | 98 | #define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK |
AjK | 0:7393c52297ee | 99 | #define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK; |
AjK | 0:7393c52297ee | 100 | #define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK |
AjK | 0:7393c52297ee | 101 | #define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK |
AjK | 0:7393c52297ee | 102 | #define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK) |
AjK | 0:7393c52297ee | 103 | #define p10_IS_CLR !(p10_IS_SET) |
AjK | 0:7393c52297ee | 104 | #define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2) |
AjK | 0:7393c52297ee | 105 | |
AjK | 0:7393c52297ee | 106 | /* p11 is P0.18 */ |
AjK | 0:7393c52297ee | 107 | #define p11_SEL_MASK ~(3UL << 4) |
AjK | 0:7393c52297ee | 108 | #define p11_SET_MASK (1UL << 18) |
AjK | 0:7393c52297ee | 109 | #define p11_CLR_MASK ~(p11_SET_MASK) |
AjK | 0:7393c52297ee | 110 | #define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK |
AjK | 0:7393c52297ee | 111 | #define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK; |
AjK | 0:7393c52297ee | 112 | #define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK |
AjK | 0:7393c52297ee | 113 | #define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK |
AjK | 0:7393c52297ee | 114 | #define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK) |
AjK | 0:7393c52297ee | 115 | #define p11_IS_CLR !(p11_IS_SET) |
AjK | 0:7393c52297ee | 116 | #define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4) |
AjK | 0:7393c52297ee | 117 | |
AjK | 0:7393c52297ee | 118 | /* p12 is P0.17 */ |
AjK | 0:7393c52297ee | 119 | #define p12_SEL_MASK ~(3UL << 2) |
AjK | 0:7393c52297ee | 120 | #define p12_SET_MASK (1UL << 17) |
AjK | 0:7393c52297ee | 121 | #define p12_CLR_MASK ~(p12_SET_MASK) |
AjK | 0:7393c52297ee | 122 | #define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK |
AjK | 0:7393c52297ee | 123 | #define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK; |
AjK | 0:7393c52297ee | 124 | #define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK |
AjK | 0:7393c52297ee | 125 | #define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK |
AjK | 0:7393c52297ee | 126 | #define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK) |
AjK | 0:7393c52297ee | 127 | #define p12_IS_CLR !(p12_IS_SET) |
AjK | 0:7393c52297ee | 128 | #define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2) |
AjK | 0:7393c52297ee | 129 | |
AjK | 0:7393c52297ee | 130 | /* p13 is P0.15 */ |
AjK | 0:7393c52297ee | 131 | #define p13_SEL_MASK ~(3UL << 30) |
AjK | 0:7393c52297ee | 132 | #define p13_SET_MASK (1UL << 15) |
AjK | 0:7393c52297ee | 133 | #define p13_CLR_MASK ~(p13_SET_MASK) |
AjK | 0:7393c52297ee | 134 | #define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK |
AjK | 0:7393c52297ee | 135 | #define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK; |
AjK | 0:7393c52297ee | 136 | #define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK |
AjK | 0:7393c52297ee | 137 | #define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK |
AjK | 0:7393c52297ee | 138 | #define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK) |
AjK | 0:7393c52297ee | 139 | #define p13_IS_CLR !(p13_IS_SET) |
AjK | 0:7393c52297ee | 140 | #define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30) |
AjK | 0:7393c52297ee | 141 | |
AjK | 0:7393c52297ee | 142 | /* p14 is P0.16 */ |
AjK | 0:7393c52297ee | 143 | #define p14_SEL_MASK ~(3UL << 0) |
AjK | 0:7393c52297ee | 144 | #define p14_SET_MASK (1UL << 16) |
AjK | 0:7393c52297ee | 145 | #define p14_CLR_MASK ~(p14_SET_MASK) |
AjK | 0:7393c52297ee | 146 | #define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK |
AjK | 0:7393c52297ee | 147 | #define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK; |
AjK | 0:7393c52297ee | 148 | #define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK |
AjK | 0:7393c52297ee | 149 | #define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK |
AjK | 0:7393c52297ee | 150 | #define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK) |
AjK | 0:7393c52297ee | 151 | #define p14_IS_CLR !(p14_IS_SET) |
AjK | 0:7393c52297ee | 152 | #define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0) |
AjK | 0:7393c52297ee | 153 | |
AjK | 0:7393c52297ee | 154 | /* p15 is P0.23 */ |
AjK | 0:7393c52297ee | 155 | #define p15_SEL_MASK ~(3UL << 14) |
AjK | 0:7393c52297ee | 156 | #define p15_SET_MASK (1UL << 23) |
AjK | 0:7393c52297ee | 157 | #define p15_CLR_MASK ~(p15_SET_MASK) |
AjK | 0:7393c52297ee | 158 | #define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK |
AjK | 0:7393c52297ee | 159 | #define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK; |
AjK | 0:7393c52297ee | 160 | #define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK |
AjK | 0:7393c52297ee | 161 | #define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK |
AjK | 0:7393c52297ee | 162 | #define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK) |
AjK | 0:7393c52297ee | 163 | #define p15_IS_CLR !(p15_IS_SET) |
AjK | 0:7393c52297ee | 164 | #define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14) |
AjK | 0:7393c52297ee | 165 | |
AjK | 0:7393c52297ee | 166 | /* p16 is P0.24 */ |
AjK | 0:7393c52297ee | 167 | #define p16_SEL_MASK ~(3UL << 16) |
AjK | 0:7393c52297ee | 168 | #define p16_SET_MASK (1UL << 24) |
AjK | 0:7393c52297ee | 169 | #define p16_CLR_MASK ~(p16_SET_MASK) |
AjK | 0:7393c52297ee | 170 | #define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK |
AjK | 0:7393c52297ee | 171 | #define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK; |
AjK | 0:7393c52297ee | 172 | #define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK |
AjK | 0:7393c52297ee | 173 | #define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK |
AjK | 0:7393c52297ee | 174 | #define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK) |
AjK | 0:7393c52297ee | 175 | #define p16_IS_CLR !(p16_IS_SET) |
AjK | 0:7393c52297ee | 176 | #define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16) |
AjK | 0:7393c52297ee | 177 | |
AjK | 0:7393c52297ee | 178 | /* p17 is P0.25 */ |
AjK | 0:7393c52297ee | 179 | #define p17_SEL_MASK ~(3UL << 18) |
AjK | 0:7393c52297ee | 180 | #define p17_SET_MASK (1UL << 25) |
AjK | 0:7393c52297ee | 181 | #define p17_CLR_MASK ~(p17_SET_MASK) |
AjK | 0:7393c52297ee | 182 | #define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK |
AjK | 0:7393c52297ee | 183 | #define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK; |
AjK | 0:7393c52297ee | 184 | #define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK |
AjK | 0:7393c52297ee | 185 | #define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK |
AjK | 0:7393c52297ee | 186 | #define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK) |
AjK | 0:7393c52297ee | 187 | #define p17_IS_CLR !(p17_IS_SET) |
AjK | 0:7393c52297ee | 188 | #define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18) |
AjK | 0:7393c52297ee | 189 | |
AjK | 0:7393c52297ee | 190 | /* p18 is P0.26 */ |
AjK | 0:7393c52297ee | 191 | #define p18_SEL_MASK ~(3UL << 20) |
AjK | 0:7393c52297ee | 192 | #define p18_SET_MASK (1UL << 26) |
AjK | 0:7393c52297ee | 193 | #define p18_CLR_MASK ~(p18_SET_MASK) |
AjK | 0:7393c52297ee | 194 | #define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK |
AjK | 0:7393c52297ee | 195 | #define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK; |
AjK | 0:7393c52297ee | 196 | #define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK |
AjK | 0:7393c52297ee | 197 | #define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK |
AjK | 0:7393c52297ee | 198 | #define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK) |
AjK | 0:7393c52297ee | 199 | #define p18_IS_CLR !(p18_IS_SET) |
AjK | 0:7393c52297ee | 200 | #define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20) |
AjK | 0:7393c52297ee | 201 | |
AjK | 0:7393c52297ee | 202 | /* p19 is P1.30 */ |
AjK | 0:7393c52297ee | 203 | #define p19_SEL_MASK ~(3UL << 28) |
AjK | 0:7393c52297ee | 204 | #define p19_SET_MASK (1UL << 30) |
AjK | 0:7393c52297ee | 205 | #define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK |
AjK | 0:7393c52297ee | 206 | #define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK; |
AjK | 0:7393c52297ee | 207 | #define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK |
AjK | 0:7393c52297ee | 208 | #define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK |
AjK | 0:7393c52297ee | 209 | #define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK) |
AjK | 0:7393c52297ee | 210 | #define p19_IS_CLR !(p19_IS_SET) |
AjK | 0:7393c52297ee | 211 | #define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28) |
AjK | 0:7393c52297ee | 212 | |
AjK | 0:7393c52297ee | 213 | /* p20 is P1.31 */ |
AjK | 0:7393c52297ee | 214 | #define p20_SEL_MASK ~(3UL << 30) |
AjK | 0:7393c52297ee | 215 | #define p20_SET_MASK (1UL << 31) |
AjK | 0:7393c52297ee | 216 | #define p20_CLR_MASK ~(p20_SET_MASK) |
AjK | 0:7393c52297ee | 217 | #define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK |
AjK | 0:7393c52297ee | 218 | #define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK; |
AjK | 0:7393c52297ee | 219 | #define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK |
AjK | 0:7393c52297ee | 220 | #define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK |
AjK | 0:7393c52297ee | 221 | #define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK) |
AjK | 0:7393c52297ee | 222 | #define p20_IS_CLR !(p20_IS_SET) |
AjK | 0:7393c52297ee | 223 | #define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30) |
AjK | 0:7393c52297ee | 224 | #define p20_TOGGLE p20_IS_SET?p20_CLR:p20_SET |
AjK | 0:7393c52297ee | 225 | |
AjK | 0:7393c52297ee | 226 | /* p21 is P2.5 */ |
AjK | 0:7393c52297ee | 227 | #define p21_SEL_MASK ~(3UL << 10) |
AjK | 0:7393c52297ee | 228 | #define p21_SET_MASK (1UL << 5) |
AjK | 0:7393c52297ee | 229 | #define p21_CLR_MASK ~(p21_SET_MASK) |
AjK | 0:7393c52297ee | 230 | #define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK |
AjK | 0:7393c52297ee | 231 | #define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK; |
AjK | 0:7393c52297ee | 232 | #define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK |
AjK | 0:7393c52297ee | 233 | #define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK |
AjK | 0:7393c52297ee | 234 | #define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK) |
AjK | 0:7393c52297ee | 235 | #define p21_IS_CLR !(p21_IS_SET) |
AjK | 0:7393c52297ee | 236 | #define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET |
AjK | 0:7393c52297ee | 237 | #define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10) |
AjK | 0:7393c52297ee | 238 | |
AjK | 0:7393c52297ee | 239 | /* p22 is P2.4 */ |
AjK | 0:7393c52297ee | 240 | #define p22_SEL_MASK ~(3UL << 8) |
AjK | 0:7393c52297ee | 241 | #define p22_SET_MASK (1UL << 4) |
AjK | 0:7393c52297ee | 242 | #define p22_CLR_MASK ~(p22_SET_MASK) |
AjK | 0:7393c52297ee | 243 | #define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK |
AjK | 0:7393c52297ee | 244 | #define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK; |
AjK | 0:7393c52297ee | 245 | #define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK |
AjK | 0:7393c52297ee | 246 | #define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK |
AjK | 0:7393c52297ee | 247 | #define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK) |
AjK | 0:7393c52297ee | 248 | #define p22_IS_CLR !(p22_IS_SET) |
AjK | 0:7393c52297ee | 249 | #define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET |
AjK | 0:7393c52297ee | 250 | #define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8) |
AjK | 0:7393c52297ee | 251 | |
AjK | 0:7393c52297ee | 252 | /* p23 is P2.3 */ |
AjK | 0:7393c52297ee | 253 | #define p23_SEL_MASK ~(3UL << 6) |
AjK | 0:7393c52297ee | 254 | #define p23_SET_MASK (1UL << 3) |
AjK | 0:7393c52297ee | 255 | #define p23_CLR_MASK ~(p23_SET_MASK) |
AjK | 0:7393c52297ee | 256 | #define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK |
AjK | 0:7393c52297ee | 257 | #define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK; |
AjK | 0:7393c52297ee | 258 | #define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK |
AjK | 0:7393c52297ee | 259 | #define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK |
AjK | 0:7393c52297ee | 260 | #define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK) |
AjK | 0:7393c52297ee | 261 | #define p23_IS_CLR !(p23_IS_SET) |
AjK | 0:7393c52297ee | 262 | #define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET |
AjK | 0:7393c52297ee | 263 | #define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6) |
AjK | 0:7393c52297ee | 264 | |
AjK | 0:7393c52297ee | 265 | /* p24 is P2.2 */ |
AjK | 0:7393c52297ee | 266 | #define p24_SEL_MASK ~(3UL << 4) |
AjK | 0:7393c52297ee | 267 | #define p24_SET_MASK (1UL << 2) |
AjK | 0:7393c52297ee | 268 | #define p24_CLR_MASK ~(p24_SET_MASK) |
AjK | 0:7393c52297ee | 269 | #define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK |
AjK | 0:7393c52297ee | 270 | #define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK; |
AjK | 0:7393c52297ee | 271 | #define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK |
AjK | 0:7393c52297ee | 272 | #define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK |
AjK | 0:7393c52297ee | 273 | #define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK) |
AjK | 0:7393c52297ee | 274 | #define p24_IS_CLR !(p24_IS_SET) |
AjK | 0:7393c52297ee | 275 | #define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET |
AjK | 0:7393c52297ee | 276 | #define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4) |
AjK | 0:7393c52297ee | 277 | |
AjK | 0:7393c52297ee | 278 | /* p25 is P2.1 */ |
AjK | 0:7393c52297ee | 279 | #define p25_SEL_MASK ~(3UL << 2) |
AjK | 0:7393c52297ee | 280 | #define p25_SET_MASK (1UL << 1) |
AjK | 0:7393c52297ee | 281 | #define p25_CLR_MASK ~(p25_SET_MASK) |
AjK | 0:7393c52297ee | 282 | #define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK |
AjK | 0:7393c52297ee | 283 | #define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK; |
AjK | 0:7393c52297ee | 284 | #define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK |
AjK | 0:7393c52297ee | 285 | #define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK |
AjK | 0:7393c52297ee | 286 | #define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK) |
AjK | 0:7393c52297ee | 287 | #define p25_IS_CLR !(p25_IS_SET) |
AjK | 0:7393c52297ee | 288 | #define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2) |
AjK | 0:7393c52297ee | 289 | |
AjK | 0:7393c52297ee | 290 | /* p26 is P2.0 */ |
AjK | 0:7393c52297ee | 291 | #define p26_SEL_MASK ~(3UL << 0) |
AjK | 0:7393c52297ee | 292 | #define p26_SET_MASK (1UL << 0) |
AjK | 0:7393c52297ee | 293 | #define p26_CLR_MASK ~(p26_SET_MASK) |
AjK | 0:7393c52297ee | 294 | #define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK |
AjK | 0:7393c52297ee | 295 | #define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK; |
AjK | 0:7393c52297ee | 296 | #define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK |
AjK | 0:7393c52297ee | 297 | #define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK |
AjK | 0:7393c52297ee | 298 | #define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK) |
AjK | 0:7393c52297ee | 299 | #define p26_IS_CLR !(p26_IS_SET) |
AjK | 0:7393c52297ee | 300 | #define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0) |
AjK | 0:7393c52297ee | 301 | |
AjK | 0:7393c52297ee | 302 | /* p27 is P0.11 */ |
AjK | 0:7393c52297ee | 303 | #define p27_SEL_MASK ~(3UL << 22) |
AjK | 0:7393c52297ee | 304 | #define p27_SET_MASK (1UL << 11) |
AjK | 0:7393c52297ee | 305 | #define p27_CLR_MASK ~(p27_SET_MASK) |
AjK | 0:7393c52297ee | 306 | #define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK |
AjK | 0:7393c52297ee | 307 | #define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK; |
AjK | 0:7393c52297ee | 308 | #define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK |
AjK | 0:7393c52297ee | 309 | #define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK |
AjK | 0:7393c52297ee | 310 | #define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK) |
AjK | 0:7393c52297ee | 311 | #define p27_IS_CLR !(p27_IS_SET) |
AjK | 0:7393c52297ee | 312 | #define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22) |
AjK | 0:7393c52297ee | 313 | |
AjK | 0:7393c52297ee | 314 | /* p28 is P0.10 */ |
AjK | 0:7393c52297ee | 315 | #define p28_SEL_MASK ~(3UL << 20) |
AjK | 0:7393c52297ee | 316 | #define p28_SET_MASK (1UL << 10) |
AjK | 0:7393c52297ee | 317 | #define p28_CLR_MASK ~(p28_SET_MASK) |
AjK | 0:7393c52297ee | 318 | #define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK |
AjK | 0:7393c52297ee | 319 | #define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK; |
AjK | 0:7393c52297ee | 320 | #define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK |
AjK | 0:7393c52297ee | 321 | #define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK |
AjK | 0:7393c52297ee | 322 | #define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK) |
AjK | 0:7393c52297ee | 323 | #define p28_IS_CLR !(p28_IS_SET) |
AjK | 0:7393c52297ee | 324 | #define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20) |
AjK | 0:7393c52297ee | 325 | |
AjK | 0:7393c52297ee | 326 | /* p29 is P0.5 */ |
AjK | 0:7393c52297ee | 327 | #define p29_SEL_MASK ~(3UL << 10) |
AjK | 0:7393c52297ee | 328 | #define p29_SET_MASK (1UL << 5) |
AjK | 0:7393c52297ee | 329 | #define p29_CLR_MASK ~(p29_SET_MASK) |
AjK | 0:7393c52297ee | 330 | #define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK |
AjK | 0:7393c52297ee | 331 | #define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK; |
AjK | 0:7393c52297ee | 332 | #define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK |
AjK | 0:7393c52297ee | 333 | #define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK |
AjK | 0:7393c52297ee | 334 | #define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK) |
AjK | 0:7393c52297ee | 335 | #define p29_IS_CLR !(p29_IS_SET) |
AjK | 0:7393c52297ee | 336 | #define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET |
AjK | 0:7393c52297ee | 337 | #define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10) |
AjK | 0:7393c52297ee | 338 | |
AjK | 0:7393c52297ee | 339 | /* p30 is P0.4 */ |
AjK | 0:7393c52297ee | 340 | #define p30_SEL_MASK ~(3UL << 8) |
AjK | 0:7393c52297ee | 341 | #define p30_SET_MASK (1UL << 4) |
AjK | 0:7393c52297ee | 342 | #define p30_CLR_MASK ~(p30_SET_MASK) |
AjK | 0:7393c52297ee | 343 | #define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK |
AjK | 0:7393c52297ee | 344 | #define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK; |
AjK | 0:7393c52297ee | 345 | #define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK |
AjK | 0:7393c52297ee | 346 | #define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK |
AjK | 0:7393c52297ee | 347 | #define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK) |
AjK | 0:7393c52297ee | 348 | #define p30_IS_CLR !(p30_IS_SET) |
AjK | 0:7393c52297ee | 349 | #define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8) |
AjK | 0:7393c52297ee | 350 | |
AjK | 0:7393c52297ee | 351 | /* The following definitions are for the four Mbed LEDs. |
AjK | 0:7393c52297ee | 352 | LED1 = P1.18 |
AjK | 0:7393c52297ee | 353 | LED2 = P1.20 |
AjK | 0:7393c52297ee | 354 | LED3 = P1.21 |
AjK | 0:7393c52297ee | 355 | LED4 = P1.23 */ |
AjK | 0:7393c52297ee | 356 | |
AjK | 0:7393c52297ee | 357 | #define P1_18_SEL_MASK ~(3UL << 4) |
AjK | 0:7393c52297ee | 358 | #define P1_18_SET_MASK (1UL << 18) |
AjK | 0:7393c52297ee | 359 | #define P1_18_CLR_MASK ~(P1_18_SET_MASK) |
AjK | 0:7393c52297ee | 360 | #define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK |
AjK | 0:7393c52297ee | 361 | #define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK; |
AjK | 0:7393c52297ee | 362 | #define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK |
AjK | 0:7393c52297ee | 363 | #define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK |
AjK | 0:7393c52297ee | 364 | #define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK) |
AjK | 0:7393c52297ee | 365 | #define P1_18_IS_CLR !(P1_18_IS_SET) |
AjK | 0:7393c52297ee | 366 | #define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT |
AjK | 0:7393c52297ee | 367 | #define LED1_ON P1_18_SET |
AjK | 0:7393c52297ee | 368 | #define LED1_OFF P1_18_CLR |
AjK | 0:7393c52297ee | 369 | #define LED1_IS_ON P1_18_IS_SET |
AjK | 0:7393c52297ee | 370 | #define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON |
AjK | 0:7393c52297ee | 371 | |
AjK | 0:7393c52297ee | 372 | #define P1_20_SEL_MASK ~(3UL << 8) |
AjK | 0:7393c52297ee | 373 | #define P1_20_SET_MASK (1UL << 20) |
AjK | 0:7393c52297ee | 374 | #define P1_20_CLR_MASK ~(P1_20_SET_MASK) |
AjK | 0:7393c52297ee | 375 | #define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK |
AjK | 0:7393c52297ee | 376 | #define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK; |
AjK | 0:7393c52297ee | 377 | #define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK |
AjK | 0:7393c52297ee | 378 | #define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK |
AjK | 0:7393c52297ee | 379 | #define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK) |
AjK | 0:7393c52297ee | 380 | #define P1_20_IS_CLR !(P1_20_IS_SET) |
AjK | 0:7393c52297ee | 381 | #define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT |
AjK | 0:7393c52297ee | 382 | #define LED2_ON P1_20_SET |
AjK | 0:7393c52297ee | 383 | #define LED2_OFF P1_20_CLR |
AjK | 0:7393c52297ee | 384 | #define LED2_IS_ON P1_20_IS_SET |
AjK | 0:7393c52297ee | 385 | #define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON |
AjK | 0:7393c52297ee | 386 | |
AjK | 0:7393c52297ee | 387 | #define P1_21_SEL_MASK ~(3UL << 10) |
AjK | 0:7393c52297ee | 388 | #define P1_21_SET_MASK (1UL << 21) |
AjK | 0:7393c52297ee | 389 | #define P1_21_CLR_MASK ~(P1_21_SET_MASK) |
AjK | 0:7393c52297ee | 390 | #define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK |
AjK | 0:7393c52297ee | 391 | #define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK; |
AjK | 0:7393c52297ee | 392 | #define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK |
AjK | 0:7393c52297ee | 393 | #define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK |
AjK | 0:7393c52297ee | 394 | #define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK) |
AjK | 0:7393c52297ee | 395 | #define P1_21_IS_CLR !(P1_21_IS_SET) |
AjK | 0:7393c52297ee | 396 | #define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT |
AjK | 0:7393c52297ee | 397 | #define LED3_ON P1_21_SET |
AjK | 0:7393c52297ee | 398 | #define LED3_OFF P1_21_CLR |
AjK | 0:7393c52297ee | 399 | #define LED3_IS_ON P1_21_IS_SET |
AjK | 0:7393c52297ee | 400 | #define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON |
AjK | 0:7393c52297ee | 401 | |
AjK | 0:7393c52297ee | 402 | #define P1_23_SEL_MASK ~(3UL << 14) |
AjK | 0:7393c52297ee | 403 | #define P1_23_SET_MASK (1UL << 23) |
AjK | 0:7393c52297ee | 404 | #define P1_23_CLR_MASK ~(P1_23_SET_MASK) |
AjK | 0:7393c52297ee | 405 | #define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK |
AjK | 0:7393c52297ee | 406 | #define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK; |
AjK | 0:7393c52297ee | 407 | #define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK |
AjK | 0:7393c52297ee | 408 | #define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK |
AjK | 0:7393c52297ee | 409 | #define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK) |
AjK | 0:7393c52297ee | 410 | #define P1_23_IS_CLR !(P1_23_IS_SET) |
AjK | 0:7393c52297ee | 411 | #define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT |
AjK | 0:7393c52297ee | 412 | #define LED4_ON P1_23_SET |
AjK | 0:7393c52297ee | 413 | #define LED4_OFF P1_23_CLR |
AjK | 0:7393c52297ee | 414 | #define LED4_IS_ON P1_23_IS_SET |
AjK | 0:7393c52297ee | 415 | #define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON |
AjK | 0:7393c52297ee | 416 | |
AjK | 0:7393c52297ee | 417 | #ifndef UB |
AjK | 0:7393c52297ee | 418 | #define UB(x) LPC_UART0->RBR=x |
AjK | 0:7393c52297ee | 419 | #endif |
AjK | 0:7393c52297ee | 420 | |
AjK | 0:7393c52297ee | 421 | #ifndef UBB |
AjK | 0:7393c52297ee | 422 | #define UBB(x) { while((LPC_UART0->LSR&(1UL << 5)) == 0); LPC_UART0->RBR=x; } |
AjK | 0:7393c52297ee | 423 | #endif |
AjK | 0:7393c52297ee | 424 | |
AjK | 0:7393c52297ee | 425 | #endif /* AJK_LIB17_IOMACROS_H */ |
AjK | 0:7393c52297ee | 426 |