Satellite Observers Workbench. NOT yet complete, just published for forum posters to \"cherry pick\" pieces of code as requiered as an example.
gpio/gpio.h@0:0a841b89d614, 2010-10-11 (annotated)
- Committer:
- AjK
- Date:
- Mon Oct 11 10:34:55 2010 +0000
- Revision:
- 0:0a841b89d614
Totally Alpha quality as this project isn\t completed. Just publishing it as it answers many questions asked in the forums
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AjK | 0:0a841b89d614 | 1 | /**************************************************************************** |
AjK | 0:0a841b89d614 | 2 | * Copyright 2010 Andy Kirkham, Stellar Technologies Ltd |
AjK | 0:0a841b89d614 | 3 | * |
AjK | 0:0a841b89d614 | 4 | * This file is part of the Satellite Observers Workbench (SOWB). |
AjK | 0:0a841b89d614 | 5 | * |
AjK | 0:0a841b89d614 | 6 | * SOWB is free software: you can redistribute it and/or modify |
AjK | 0:0a841b89d614 | 7 | * it under the terms of the GNU General Public License as published by |
AjK | 0:0a841b89d614 | 8 | * the Free Software Foundation, either version 3 of the License, or |
AjK | 0:0a841b89d614 | 9 | * (at your option) any later version. |
AjK | 0:0a841b89d614 | 10 | * |
AjK | 0:0a841b89d614 | 11 | * SOWB is distributed in the hope that it will be useful, |
AjK | 0:0a841b89d614 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
AjK | 0:0a841b89d614 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
AjK | 0:0a841b89d614 | 14 | * GNU General Public License for more details. |
AjK | 0:0a841b89d614 | 15 | * |
AjK | 0:0a841b89d614 | 16 | * You should have received a copy of the GNU General Public License |
AjK | 0:0a841b89d614 | 17 | * along with SOWB. If not, see <http://www.gnu.org/licenses/>. |
AjK | 0:0a841b89d614 | 18 | * |
AjK | 0:0a841b89d614 | 19 | * $Id: main.cpp 5 2010-07-12 20:51:11Z ajk $ |
AjK | 0:0a841b89d614 | 20 | * |
AjK | 0:0a841b89d614 | 21 | ***************************************************************************/ |
AjK | 0:0a841b89d614 | 22 | |
AjK | 0:0a841b89d614 | 23 | #ifndef GPIO_H |
AjK | 0:0a841b89d614 | 24 | #define GPIO_H |
AjK | 0:0a841b89d614 | 25 | |
AjK | 0:0a841b89d614 | 26 | /* Switch on our macros to use the 4 LEDs on the Mbed. */ |
AjK | 0:0a841b89d614 | 27 | #define MBED_LEDS |
AjK | 0:0a841b89d614 | 28 | |
AjK | 0:0a841b89d614 | 29 | /* Used by the MAX7456 module. |
AjK | 0:0a841b89d614 | 30 | The MAX7456 !cs signal is connected to Mbed pin 8 |
AjK | 0:0a841b89d614 | 31 | which is internally connected to Port0.6 */ |
AjK | 0:0a841b89d614 | 32 | #define SET_P0_06 (LPC_GPIO0->FIOSET = (1UL << 6)) |
AjK | 0:0a841b89d614 | 33 | #define CLR_P0_06 (LPC_GPIO0->FIOCLR = (1UL << 6)) |
AjK | 0:0a841b89d614 | 34 | #define VAL_P0_06 (LPC_GPIO0->FIOPIN & (1UL << 6)) |
AjK | 0:0a841b89d614 | 35 | #define MAX7456_CS_ASSERT CLR_P0_06 |
AjK | 0:0a841b89d614 | 36 | #define MAX7456_CS_DEASSERT SET_P0_06 |
AjK | 0:0a841b89d614 | 37 | #define MAX7456_CS_VALUE VAL_P0_06 |
AjK | 0:0a841b89d614 | 38 | #define MAX7456_CS_TOGGLE MAX7456_CS_VALUE ? MAX7456_CS_DEASSERT : MAX7456_CS_ASSERT |
AjK | 0:0a841b89d614 | 39 | |
AjK | 0:0a841b89d614 | 40 | /* Used by the MAX7456 module. |
AjK | 0:0a841b89d614 | 41 | The MAX7456 !rst signal is connected to Mbed pin 20 |
AjK | 0:0a841b89d614 | 42 | which is internally connected to Port1.31 */ |
AjK | 0:0a841b89d614 | 43 | #define SET_P1_31 (LPC_GPIO1->FIOSET = (1UL << 31)) |
AjK | 0:0a841b89d614 | 44 | #define CLR_P1_31 (LPC_GPIO1->FIOCLR = (1UL << 31)) |
AjK | 0:0a841b89d614 | 45 | #define VAL_P1_31 (LPC_GPIO1->FIOPIN & (1UL << 31)) |
AjK | 0:0a841b89d614 | 46 | #define MAX7456_RST_ASSERT CLR_P1_31 |
AjK | 0:0a841b89d614 | 47 | #define MAX7456_RST_DEASSERT SET_P1_31 |
AjK | 0:0a841b89d614 | 48 | #define MAX7456_RST_VALUE VAL_P1_31 |
AjK | 0:0a841b89d614 | 49 | #define MAX7456_RST_TOGGLE MAX7456_RST_VALUE ? MAX7456_RST_DEASSERT : MAX7456_RST_ASSERT |
AjK | 0:0a841b89d614 | 50 | #define SSP0_CS_ASSERT CLR_P1_31 |
AjK | 0:0a841b89d614 | 51 | #define SSP0_CS_DEASSERT SET_P1_31 |
AjK | 0:0a841b89d614 | 52 | #define SSP0_CS_VALUE VAL_P1_31 |
AjK | 0:0a841b89d614 | 53 | #define SSP0_CS_TOGGLE MAX7456_RST_VALUE ? MAX7456_RST_DEASSERT : MAX7456_RST_ASSERT |
AjK | 0:0a841b89d614 | 54 | |
AjK | 0:0a841b89d614 | 55 | /* Used by the flash module. |
AjK | 0:0a841b89d614 | 56 | The flash !cs signal is connected to Mbed pin 14 |
AjK | 0:0a841b89d614 | 57 | which is internally connected to Port0.16 */ |
AjK | 0:0a841b89d614 | 58 | #define SET_P0_16 (LPC_GPIO0->FIOSET = (1UL << 16)) |
AjK | 0:0a841b89d614 | 59 | #define CLR_P0_16 (LPC_GPIO0->FIOCLR = (1UL << 16)) |
AjK | 0:0a841b89d614 | 60 | #define VAL_P0_16 (LPC_GPIO0->FIOPIN & (1UL << 16)) |
AjK | 0:0a841b89d614 | 61 | #define FLASH_CS_ASSERT CLR_P0_16 |
AjK | 0:0a841b89d614 | 62 | #define FLASH_CS_DEASSERT SET_P0_16 |
AjK | 0:0a841b89d614 | 63 | #define FLASH_CS_VALUE VAL_P0_16 |
AjK | 0:0a841b89d614 | 64 | #define FLASH_CS_TOGGLE FLASH_CS_VALUE ? FLASH_CS_DEASSERT : FLASH_CS_ASSERT |
AjK | 0:0a841b89d614 | 65 | |
AjK | 0:0a841b89d614 | 66 | /* Used by the 25AA02E48 module. |
AjK | 0:0a841b89d614 | 67 | The device !cs signal is connected to Mbed pin 16 |
AjK | 0:0a841b89d614 | 68 | which is internally connected to Port0.24 */ |
AjK | 0:0a841b89d614 | 69 | #define SET_P0_24 (LPC_GPIO0->FIOSET = (1UL << 24)) |
AjK | 0:0a841b89d614 | 70 | #define CLR_P0_24 (LPC_GPIO0->FIOCLR = (1UL << 24)) |
AjK | 0:0a841b89d614 | 71 | #define VAL_P0_24 (LPC_GPIO0->FIOPIN & (1UL << 24)) |
AjK | 0:0a841b89d614 | 72 | #define AA02E48_CS_ASSERT CLR_P0_24 |
AjK | 0:0a841b89d614 | 73 | #define AA02E48_CS_DEASSERT SET_P0_24 |
AjK | 0:0a841b89d614 | 74 | #define AA02E48_CS_VALUE VAL_P0_24 |
AjK | 0:0a841b89d614 | 75 | #define AA02E48_CS_TOGGLE AA02E48_CS_VALUE ? AA02E48_CS_DEASSERT : AA02E48_CS_ASSERT |
AjK | 0:0a841b89d614 | 76 | |
AjK | 0:0a841b89d614 | 77 | /* Used by the SD card. |
AjK | 0:0a841b89d614 | 78 | The device !cs signal is connected to Mbed pin 19 |
AjK | 0:0a841b89d614 | 79 | which is internally connected to Port1.30 */ |
AjK | 0:0a841b89d614 | 80 | #define SET_P1_30 (LPC_GPIO1->FIOSET = (1UL << 30)) |
AjK | 0:0a841b89d614 | 81 | #define CLR_P1_30 (LPC_GPIO1->FIOCLR = (1UL << 30)) |
AjK | 0:0a841b89d614 | 82 | #define VAL_P1_30 (LPC_GPIO1->FIOPIN & (1UL << 30)) |
AjK | 0:0a841b89d614 | 83 | #define SDCARD_CS_ASSERT CLR_P1_30 |
AjK | 0:0a841b89d614 | 84 | #define SDCARD_CS_DEASSERT SET_P1_30 |
AjK | 0:0a841b89d614 | 85 | #define SDCARD_CS_VALUE VAL_P1_30 |
AjK | 0:0a841b89d614 | 86 | #define SDCARD_CS_TOGGLE SDCARD_CS_VALUE ? SDCARD_CS_DEASSERT : SDCARD_CS_ASSERT |
AjK | 0:0a841b89d614 | 87 | |
AjK | 0:0a841b89d614 | 88 | /* Used for reading the SD Card detect pin. */ |
AjK | 0:0a841b89d614 | 89 | #define SDCARD_DETECT (LPC_GPIO0->FIOPIN & (1UL << 25)) |
AjK | 0:0a841b89d614 | 90 | |
AjK | 0:0a841b89d614 | 91 | /* For debugging. |
AjK | 0:0a841b89d614 | 92 | Mbed pin 21 which is internally connected to Port2.5 */ |
AjK | 0:0a841b89d614 | 93 | #define SET_P2_05 (LPC_GPIO2->FIOSET = (1UL << 5)) |
AjK | 0:0a841b89d614 | 94 | #define CLR_P2_05 (LPC_GPIO2->FIOCLR = (1UL << 5)) |
AjK | 0:0a841b89d614 | 95 | #define VAL_P2_05 (LPC_GPIO2->FIOPIN & (1UL << 5)) |
AjK | 0:0a841b89d614 | 96 | #define P21_ASSERT SET_P2_05 |
AjK | 0:0a841b89d614 | 97 | #define P21_DEASSERT CLR_P2_05 |
AjK | 0:0a841b89d614 | 98 | #define P21_VALUE VAL_P2_05 |
AjK | 0:0a841b89d614 | 99 | #define P21_TOGGLE P21_VALUE ? P21_DEASSERT : P21_ASSERT |
AjK | 0:0a841b89d614 | 100 | |
AjK | 0:0a841b89d614 | 101 | /* For debugging. |
AjK | 0:0a841b89d614 | 102 | Mbed pin 22 which is internally connected to Port2.4 */ |
AjK | 0:0a841b89d614 | 103 | #define SET_P2_04 (LPC_GPIO2->FIOSET = (1UL << 4)) |
AjK | 0:0a841b89d614 | 104 | #define CLR_P2_04 (LPC_GPIO2->FIOCLR = (1UL << 4)) |
AjK | 0:0a841b89d614 | 105 | #define VAL_P2_04 (LPC_GPIO2->FIOPIN & (1UL << 4)) |
AjK | 0:0a841b89d614 | 106 | #define P22_ASSERT SET_P2_04 |
AjK | 0:0a841b89d614 | 107 | #define P22_DEASSERT CLR_P2_04 |
AjK | 0:0a841b89d614 | 108 | #define P22_VALUE VAL_P2_04 |
AjK | 0:0a841b89d614 | 109 | #define P22_TOGGLE P22_VALUE ? P22_DEASSERT : P22_ASSERT |
AjK | 0:0a841b89d614 | 110 | |
AjK | 0:0a841b89d614 | 111 | #ifdef MBED_LEDS |
AjK | 0:0a841b89d614 | 112 | #define LED1_ON (LPC_GPIO1->FIOSET = (1UL << 18)) |
AjK | 0:0a841b89d614 | 113 | #define LED1_OFF (LPC_GPIO1->FIOCLR = (1UL << 18)) |
AjK | 0:0a841b89d614 | 114 | #define LED1_IS_ON (LPC_GPIO1->FIOPIN & (1UL << 18)) |
AjK | 0:0a841b89d614 | 115 | #define LED1_TOGGLE LED1_IS_ON ? LED1_OFF : LED1_ON |
AjK | 0:0a841b89d614 | 116 | #define LED2_ON (LPC_GPIO1->FIOSET = (1UL << 20)) |
AjK | 0:0a841b89d614 | 117 | #define LED2_OFF (LPC_GPIO1->FIOCLR = (1UL << 20)) |
AjK | 0:0a841b89d614 | 118 | #define LED2_IS_ON (LPC_GPIO1->FIOPIN & (1UL << 20)) |
AjK | 0:0a841b89d614 | 119 | #define LED2_TOGGLE LED2_IS_ON ? LED2_OFF : LED2_ON |
AjK | 0:0a841b89d614 | 120 | #define LED3_ON (LPC_GPIO1->FIOSET = (1UL << 21)) |
AjK | 0:0a841b89d614 | 121 | #define LED3_OFF (LPC_GPIO1->FIOCLR = (1UL << 21)) |
AjK | 0:0a841b89d614 | 122 | #define LED3_IS_ON (LPC_GPIO1->FIOPIN & (1UL << 21)) |
AjK | 0:0a841b89d614 | 123 | #define LED3_TOGGLE LED3_IS_ON ? LED3_OFF : LED3_ON |
AjK | 0:0a841b89d614 | 124 | #define LED4_ON (LPC_GPIO1->FIOSET = (1UL << 23)) |
AjK | 0:0a841b89d614 | 125 | #define LED4_OFF (LPC_GPIO1->FIOCLR = (1UL << 23)) |
AjK | 0:0a841b89d614 | 126 | #define LED4_IS_ON (LPC_GPIO1->FIOPIN & (1UL << 23)) |
AjK | 0:0a841b89d614 | 127 | #define LED4_TOGGLE LED4_IS_ON ? LED4_OFF : LED4_ON |
AjK | 0:0a841b89d614 | 128 | #endif |
AjK | 0:0a841b89d614 | 129 | |
AjK | 0:0a841b89d614 | 130 | /* Function prototypes. */ |
AjK | 0:0a841b89d614 | 131 | void gpio_init(void); |
AjK | 0:0a841b89d614 | 132 | void gpio_process(void); |
AjK | 0:0a841b89d614 | 133 | |
AjK | 0:0a841b89d614 | 134 | #endif |
AjK | 0:0a841b89d614 | 135 |