Andy K / MODDMA

MODDMA GPDMA Controller New features: transfer pins to memory buffer under periodic timer control and send double buffers to DAC

Dependents:   FirstTest WaveSim IO-dma-memmem DACDMAfuncgenlib ... more

SETUP.cpp@0:c409efd8df78, 2010-11-23 (annotated)

Committer:
AjK
Date:
Tue Nov 23 14:50:39 2010 +0000
Revision:
0:c409efd8df78
Child:
8:cb4d323ce6fd
0.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 0:c409efd8df78 1 /*
AjK 0:c409efd8df78 2 Copyright (c) 2010 Andy Kirkham
AjK 0:c409efd8df78 3
AjK 0:c409efd8df78 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 0:c409efd8df78 5 of this software and associated documentation files (the "Software"), to deal
AjK 0:c409efd8df78 6 in the Software without restriction, including without limitation the rights
AjK 0:c409efd8df78 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 0:c409efd8df78 8 copies of the Software, and to permit persons to whom the Software is
AjK 0:c409efd8df78 9 furnished to do so, subject to the following conditions:
AjK 0:c409efd8df78 10
AjK 0:c409efd8df78 11 The above copyright notice and this permission notice shall be included in
AjK 0:c409efd8df78 12 all copies or substantial portions of the Software.
AjK 0:c409efd8df78 13
AjK 0:c409efd8df78 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 0:c409efd8df78 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 0:c409efd8df78 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 0:c409efd8df78 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 0:c409efd8df78 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 0:c409efd8df78 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 0:c409efd8df78 20 THE SOFTWARE.
AjK 0:c409efd8df78 21 */
AjK 0:c409efd8df78 22
AjK 0:c409efd8df78 23 #include "MODDMA.h"
AjK 0:c409efd8df78 24
AjK 0:c409efd8df78 25 namespace AjK {
AjK 0:c409efd8df78 26
AjK 0:c409efd8df78 27 MODDMA::Status
AjK 0:c409efd8df78 28 MODDMA::Setup(MODDMA_Config *config)
AjK 0:c409efd8df78 29 {
AjK 0:c409efd8df78 30 LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() );
AjK 0:c409efd8df78 31
AjK 0:c409efd8df78 32 if (LPC_GPDMA->DMACEnbldChns & EnbldChns_Ch( config->channelNum() )) {
AjK 0:c409efd8df78 33 return ErrChInUse;
AjK 0:c409efd8df78 34 }
AjK 0:c409efd8df78 35
AjK 0:c409efd8df78 36 setups[config->channelNum() & 0x7] = config;
AjK 0:c409efd8df78 37
AjK 0:c409efd8df78 38 // Reset the Interrupt status
AjK 0:c409efd8df78 39 LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
AjK 0:c409efd8df78 40 LPC_GPDMA->DMACIntErrClr = IntErrClr_Ch ( config->channelNum() );
AjK 0:c409efd8df78 41
AjK 0:c409efd8df78 42 // Clear DMA configure
AjK 0:c409efd8df78 43 pChannel->DMACCControl = 0x00;
AjK 0:c409efd8df78 44 pChannel->DMACCConfig = 0x00;
AjK 0:c409efd8df78 45
AjK 0:c409efd8df78 46 // Assign Linker List Item value
AjK 0:c409efd8df78 47 pChannel->DMACCLLI = config->dmaLLI();
AjK 0:c409efd8df78 48
AjK 0:c409efd8df78 49 // Set value to Channel Control Registers
AjK 0:c409efd8df78 50 switch (config->transferType()) {
AjK 0:c409efd8df78 51
AjK 0:c409efd8df78 52 // Memory to memory
AjK 0:c409efd8df78 53 case m2m:
AjK 0:c409efd8df78 54 // Assign physical source and destination address
AjK 0:c409efd8df78 55 pChannel->DMACCSrcAddr = config->srcMemAddr();
AjK 0:c409efd8df78 56 pChannel->DMACCDestAddr = config->dstMemAddr();
AjK 0:c409efd8df78 57 pChannel->DMACCControl
AjK 0:c409efd8df78 58 = CxControl_TransferSize(config->transferSize())
AjK 0:c409efd8df78 59 | CxControl_SBSize(_32)
AjK 0:c409efd8df78 60 | CxControl_DBSize(_32)
AjK 0:c409efd8df78 61 | CxControl_SWidth(config->transferWidth())
AjK 0:c409efd8df78 62 | CxControl_DWidth(config->transferWidth())
AjK 0:c409efd8df78 63 | CxControl_SI()
AjK 0:c409efd8df78 64 | CxControl_DI()
AjK 0:c409efd8df78 65 | CxControl_I();
AjK 0:c409efd8df78 66 break;
AjK 0:c409efd8df78 67
AjK 0:c409efd8df78 68 // Memory to peripheral
AjK 0:c409efd8df78 69 case m2p:
AjK 0:c409efd8df78 70 // Assign physical source
AjK 0:c409efd8df78 71 pChannel->DMACCSrcAddr = config->srcMemAddr();
AjK 0:c409efd8df78 72 // Assign peripheral destination address
AjK 0:c409efd8df78 73 pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
AjK 0:c409efd8df78 74 pChannel->DMACCControl
AjK 0:c409efd8df78 75 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 0:c409efd8df78 76 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 0:c409efd8df78 77 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 0:c409efd8df78 78 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 0:c409efd8df78 79 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 0:c409efd8df78 80 | CxControl_SI()
AjK 0:c409efd8df78 81 | CxControl_I();
AjK 0:c409efd8df78 82 break;
AjK 0:c409efd8df78 83
AjK 0:c409efd8df78 84 // Peripheral to memory
AjK 0:c409efd8df78 85 case p2m:
AjK 0:c409efd8df78 86 // Assign peripheral source address
AjK 0:c409efd8df78 87 pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
AjK 0:c409efd8df78 88 // Assign memory destination address
AjK 0:c409efd8df78 89 pChannel->DMACCDestAddr = config->dstMemAddr();
AjK 0:c409efd8df78 90 pChannel->DMACCControl
AjK 0:c409efd8df78 91 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 0:c409efd8df78 92 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 0:c409efd8df78 93 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 0:c409efd8df78 94 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 0:c409efd8df78 95 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 0:c409efd8df78 96 | CxControl_DI()
AjK 0:c409efd8df78 97 | CxControl_I();
AjK 0:c409efd8df78 98 break;
AjK 0:c409efd8df78 99
AjK 0:c409efd8df78 100 // Peripheral to peripheral
AjK 0:c409efd8df78 101 case p2p:
AjK 0:c409efd8df78 102 // Assign peripheral source address
AjK 0:c409efd8df78 103 pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
AjK 0:c409efd8df78 104 // Assign peripheral destination address
AjK 0:c409efd8df78 105 pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
AjK 0:c409efd8df78 106 pChannel->DMACCControl
AjK 0:c409efd8df78 107 = CxControl_TransferSize((uint32_t)config->transferSize())
AjK 0:c409efd8df78 108 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn()))
AjK 0:c409efd8df78 109 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn()))
AjK 0:c409efd8df78 110 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn()))
AjK 0:c409efd8df78 111 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn()))
AjK 0:c409efd8df78 112 | CxControl_I();
AjK 0:c409efd8df78 113 break;
AjK 0:c409efd8df78 114
AjK 0:c409efd8df78 115 // Do not support any more transfer type, return ERROR
AjK 0:c409efd8df78 116 default:
AjK 0:c409efd8df78 117 return Error;
AjK 0:c409efd8df78 118 }
AjK 0:c409efd8df78 119
AjK 0:c409efd8df78 120 // Re-Configure DMA Request Select for source peripheral
AjK 0:c409efd8df78 121 if (config->srcConn() > 15) {
AjK 0:c409efd8df78 122 LPC_SC->RESERVED9 |= (1 << (config->srcConn() - 16));
AjK 0:c409efd8df78 123 }
AjK 0:c409efd8df78 124 else {
AjK 0:c409efd8df78 125 LPC_SC->RESERVED9 &= ~(1 << (config->srcConn() - 8));
AjK 0:c409efd8df78 126 }
AjK 0:c409efd8df78 127
AjK 0:c409efd8df78 128 // Re-Configure DMA Request Select for Destination peripheral
AjK 0:c409efd8df78 129 if (config->dstConn() > 15) {
AjK 0:c409efd8df78 130 LPC_SC->RESERVED9 |= (1 << (config->dstConn() - 16));
AjK 0:c409efd8df78 131 }
AjK 0:c409efd8df78 132 else {
AjK 0:c409efd8df78 133 LPC_SC->RESERVED9 &= ~(1 << (config->dstConn() - 8));
AjK 0:c409efd8df78 134 }
AjK 0:c409efd8df78 135
AjK 0:c409efd8df78 136 // Enable DMA channels, little endian
AjK 0:c409efd8df78 137 LPC_GPDMA->DMACConfig = _E;
AjK 0:c409efd8df78 138 while (!(LPC_GPDMA->DMACConfig & _E));
AjK 0:c409efd8df78 139
AjK 0:c409efd8df78 140 // Calculate absolute value for Connection number
AjK 0:c409efd8df78 141 uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
AjK 0:c409efd8df78 142 uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
AjK 0:c409efd8df78 143
AjK 0:c409efd8df78 144 // Configure DMA Channel, enable Error Counter and Terminate counter
AjK 0:c409efd8df78 145 pChannel->DMACCConfig
AjK 0:c409efd8df78 146 = CxConfig_IE()
AjK 0:c409efd8df78 147 | CxConfig_ITC()
AjK 0:c409efd8df78 148 | CxConfig_TransferType((uint32_t)config->transferType())
AjK 0:c409efd8df78 149 | CxConfig_SrcPeripheral(tmp1)
AjK 0:c409efd8df78 150 | CxConfig_DestPeripheral(tmp2);
AjK 0:c409efd8df78 151
AjK 0:c409efd8df78 152 return Ok;
AjK 0:c409efd8df78 153 }
AjK 0:c409efd8df78 154
AjK 0:c409efd8df78 155 }; // namespace AjK ends
AjK 0:c409efd8df78 156