Andy K / MODDMA

MODDMA GPDMA Controller New features: transfer pins to memory buffer under periodic timer control and send double buffers to DAC

Dependents:   FirstTest WaveSim IO-dma-memmem DACDMAfuncgenlib ... more

MODDMA.h@0:c409efd8df78, 2010-11-23 (annotated)

Committer:
AjK
Date:
Tue Nov 23 14:50:39 2010 +0000
Revision:
0:c409efd8df78
Child:
1:9700b9455cbf
0.1

Who changed what in which revision?

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AjK 0:c409efd8df78 1 /*
AjK 0:c409efd8df78 2 Copyright (c) 2010 Andy Kirkham
AjK 0:c409efd8df78 3
AjK 0:c409efd8df78 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 0:c409efd8df78 5 of this software and associated documentation files (the "Software"), to deal
AjK 0:c409efd8df78 6 in the Software without restriction, including without limitation the rights
AjK 0:c409efd8df78 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 0:c409efd8df78 8 copies of the Software, and to permit persons to whom the Software is
AjK 0:c409efd8df78 9 furnished to do so, subject to the following conditions:
AjK 0:c409efd8df78 10
AjK 0:c409efd8df78 11 The above copyright notice and this permission notice shall be included in
AjK 0:c409efd8df78 12 all copies or substantial portions of the Software.
AjK 0:c409efd8df78 13
AjK 0:c409efd8df78 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 0:c409efd8df78 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 0:c409efd8df78 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 0:c409efd8df78 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 0:c409efd8df78 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 0:c409efd8df78 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 0:c409efd8df78 20 THE SOFTWARE.
AjK 0:c409efd8df78 21
AjK 0:c409efd8df78 22 @file MODDMA.h
AjK 0:c409efd8df78 23 @purpose Adds DMA controller and multiple transfer configurations
AjK 0:c409efd8df78 24 @version 1.0
AjK 0:c409efd8df78 25 @date Nov 2010
AjK 0:c409efd8df78 26 @author Andy Kirkham
AjK 0:c409efd8df78 27 */
AjK 0:c409efd8df78 28
AjK 0:c409efd8df78 29 #ifndef MODDMA_H
AjK 0:c409efd8df78 30 #define MODDMA_H
AjK 0:c409efd8df78 31
AjK 0:c409efd8df78 32 /** @defgroup API The MODSERIAL API */
AjK 0:c409efd8df78 33 /** @defgroup MISC Misc MODSERIAL functions */
AjK 0:c409efd8df78 34 /** @defgroup INTERNALS MODSERIAL Internals */
AjK 0:c409efd8df78 35
AjK 0:c409efd8df78 36 #include "mbed.h"
AjK 0:c409efd8df78 37
AjK 0:c409efd8df78 38 namespace AjK {
AjK 0:c409efd8df78 39
AjK 0:c409efd8df78 40 /**
AjK 0:c409efd8df78 41 * @author Andy Kirkham
AjK 0:c409efd8df78 42 * @see http://mbed.org/cookbook/MODDMA
AjK 0:c409efd8df78 43 * @see example1.cpp
AjK 0:c409efd8df78 44 * @see API
AjK 0:c409efd8df78 45 *
AjK 0:c409efd8df78 46 * <b>MODDMA</b> defines a GPDMA controller and multiple DMA configurations that allow for DMA
AjK 0:c409efd8df78 47 * transfers from memory to memory, memory to peripheral or peripheral to memory.
AjK 0:c409efd8df78 48 *
AjK 0:c409efd8df78 49 * At the heart of the library is the MODDMA class the defines a single instance controller that
AjK 0:c409efd8df78 50 * manages all the GPDMA hardware registers and interrupts. The controller can accept multiple
AjK 0:c409efd8df78 51 * configurations that define the transfer. Each configuration specifies the src and dest information
AjK 0:c409efd8df78 52 * and other associated parts to maintain the transfer process.
AjK 0:c409efd8df78 53 *
AjK 0:c409efd8df78 54 * Standard example:
AjK 0:c409efd8df78 55 * @code
AjK 0:c409efd8df78 56 * #include "mbed.h"
AjK 0:c409efd8df78 57 * #include "MODDMA.h"
AjK 0:c409efd8df78 58 *
AjK 0:c409efd8df78 59 * DigitalOut led1(LED1);
AjK 0:c409efd8df78 60 * Serial pc(USBTX, USBRX); // tx, rx
AjK 0:c409efd8df78 61 * MODDMA dma;
AjK 0:c409efd8df78 62 *
AjK 0:c409efd8df78 63 * int main() {
AjK 0:c409efd8df78 64 *
AjK 0:c409efd8df78 65 * // Create a string buffer to send directly to a Uart/Serial
AjK 0:c409efd8df78 66 * char s[] = "***DMA*** ABCDEFGHIJKLMNOPQRSTUVWXYZ ***DMA***";
AjK 0:c409efd8df78 67 *
AjK 0:c409efd8df78 68 * // Create a transfer configuarion
AjK 0:c409efd8df78 69 * MODDMA_Config *config = new MODDMA_Config;
AjK 0:c409efd8df78 70 *
AjK 0:c409efd8df78 71 * // Provide a "minimal" setup for demo purposes.
AjK 0:c409efd8df78 72 * config
AjK 0:c409efd8df78 73 * ->channelNum ( MODDMA::Channel_0 ) // The DMA channel to use.
AjK 0:c409efd8df78 74 * ->srcMemAddr ( (uint32_t) &s ) // A pointer to the buffer to send.
AjK 0:c409efd8df78 75 * ->transferSize ( sizeof(s) ) // The size of that buffer.
AjK 0:c409efd8df78 76 * ->transferType ( MODDMA::m2p ) // Buffer is memory, dest is peripheral
AjK 0:c409efd8df78 77 * ->dstConn ( MODDMA::UART0_Tx ) // Specifically, peripheral is Uart0 TX (USBTX, USBRX)
AjK 0:c409efd8df78 78 * ; // config end.
AjK 0:c409efd8df78 79 *
AjK 0:c409efd8df78 80 * // Pass the configuration to the MODDMA controller.
AjK 0:c409efd8df78 81 * dma.Setup( config );
AjK 0:c409efd8df78 82 *
AjK 0:c409efd8df78 83 * // Enable the channel and begin transfer.
AjK 0:c409efd8df78 84 * dma.Enable( config->channelNum() );
AjK 0:c409efd8df78 85 *
AjK 0:c409efd8df78 86 * while(1) {
AjK 0:c409efd8df78 87 * led1 = !led1;
AjK 0:c409efd8df78 88 * wait(0.25);
AjK 0:c409efd8df78 89 * }
AjK 0:c409efd8df78 90 * }
AjK 0:c409efd8df78 91 * @endcode
AjK 0:c409efd8df78 92 */
AjK 0:c409efd8df78 93 class MODDMA_Config {
AjK 0:c409efd8df78 94 protected:
AjK 0:c409efd8df78 95
AjK 0:c409efd8df78 96 // *****************************************
AjK 0:c409efd8df78 97 // From GPDMA by NXP MCU SW Application Team
AjK 0:c409efd8df78 98 // *****************************************
AjK 0:c409efd8df78 99
AjK 0:c409efd8df78 100 uint32_t ChannelNum; //!< DMA channel number, should be in range from 0 to 7.
AjK 0:c409efd8df78 101 uint32_t TransferSize; //!< Length/Size of transfer
AjK 0:c409efd8df78 102 uint32_t TransferWidth; //!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_m2m only
AjK 0:c409efd8df78 103 uint32_t SrcMemAddr; //!< Physical Src Addr, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::m2p
AjK 0:c409efd8df78 104 uint32_t DstMemAddr; //!< Physical Destination Address, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::p2m
AjK 0:c409efd8df78 105 uint32_t TransferType; //!< Transfer Type
AjK 0:c409efd8df78 106 uint32_t SrcConn; //!< Peripheral Source Connection type, used in case TransferType is chosen as
AjK 0:c409efd8df78 107 uint32_t DstConn; //!< Peripheral Destination Connection type, used in case TransferType is chosen as
AjK 0:c409efd8df78 108 uint32_t DMALLI; //!< Linker List Item structure data address if there's no Linker List, set as '0'
AjK 0:c409efd8df78 109
AjK 0:c409efd8df78 110 // Mbed specifics.
AjK 0:c409efd8df78 111
AjK 0:c409efd8df78 112 public:
AjK 0:c409efd8df78 113
AjK 0:c409efd8df78 114 MODDMA_Config() {
AjK 0:c409efd8df78 115 isrIntTCStat = new FunctionPointer;
AjK 0:c409efd8df78 116 isrIntErrStat = new FunctionPointer;
AjK 0:c409efd8df78 117 ChannelNum = 0xFFFF;
AjK 0:c409efd8df78 118 TransferSize = 0;
AjK 0:c409efd8df78 119 TransferWidth = 0;
AjK 0:c409efd8df78 120 SrcMemAddr = 0;
AjK 0:c409efd8df78 121 DstMemAddr = 0;
AjK 0:c409efd8df78 122 TransferType = 0;
AjK 0:c409efd8df78 123 SrcConn = 0;
AjK 0:c409efd8df78 124 DstConn = 0;
AjK 0:c409efd8df78 125 DMALLI = 0;
AjK 0:c409efd8df78 126 }
AjK 0:c409efd8df78 127
AjK 0:c409efd8df78 128 ~MODDMA_Config() {
AjK 0:c409efd8df78 129 delete(isrIntTCStat);
AjK 0:c409efd8df78 130 delete(isrIntErrStat);
AjK 0:c409efd8df78 131 }
AjK 0:c409efd8df78 132
AjK 0:c409efd8df78 133 class MODDMA_Config * channelNum(uint32_t n) { ChannelNum = n & 0x7; return this; }
AjK 0:c409efd8df78 134 class MODDMA_Config * transferSize(uint32_t n) { TransferSize = n; return this; }
AjK 0:c409efd8df78 135 class MODDMA_Config * transferWidth(uint32_t n) { TransferWidth = n; return this; }
AjK 0:c409efd8df78 136 class MODDMA_Config * srcMemAddr(uint32_t n) { SrcMemAddr = n; return this; }
AjK 0:c409efd8df78 137 class MODDMA_Config * dstMemAddr(uint32_t n) { DstMemAddr = n; return this; }
AjK 0:c409efd8df78 138 class MODDMA_Config * transferType(uint32_t n) { TransferType = n; return this; }
AjK 0:c409efd8df78 139 class MODDMA_Config * srcConn(uint32_t n) { SrcConn = n; return this; }
AjK 0:c409efd8df78 140 class MODDMA_Config * dstConn(uint32_t n) { DstConn = n; return this; }
AjK 0:c409efd8df78 141 class MODDMA_Config * dmaLLI(uint32_t n) { DMALLI = n; return this; }
AjK 0:c409efd8df78 142
AjK 0:c409efd8df78 143 uint32_t channelNum(void) { return ChannelNum; }
AjK 0:c409efd8df78 144 uint32_t transferSize(void) { return TransferSize; }
AjK 0:c409efd8df78 145 uint32_t transferWidth(void) { return TransferWidth; }
AjK 0:c409efd8df78 146 uint32_t srcMemAddr(void) { return SrcMemAddr; }
AjK 0:c409efd8df78 147 uint32_t dstMemAddr(void) { return DstMemAddr; }
AjK 0:c409efd8df78 148 uint32_t transferType(void) { return TransferType; }
AjK 0:c409efd8df78 149 uint32_t srcConn(void) { return SrcConn; }
AjK 0:c409efd8df78 150 uint32_t dstConn(void) { return DstConn; }
AjK 0:c409efd8df78 151 uint32_t dmaLLI(void) { return DMALLI; }
AjK 0:c409efd8df78 152
AjK 0:c409efd8df78 153 FunctionPointer *isrIntTCStat;
AjK 0:c409efd8df78 154 FunctionPointer *isrIntErrStat;
AjK 0:c409efd8df78 155 };
AjK 0:c409efd8df78 156
AjK 0:c409efd8df78 157 /**
AjK 0:c409efd8df78 158 * @brief GPDMA Linker List Item structure type definition
AjK 0:c409efd8df78 159 */
AjK 0:c409efd8df78 160 /*
AjK 0:c409efd8df78 161 typedef struct {
AjK 0:c409efd8df78 162 uint32_t SrcAddr; //!< Source Address
AjK 0:c409efd8df78 163 uint32_t DstAddr; //!< Destination address
AjK 0:c409efd8df78 164 uint32_t NextLLI; //!< Next LLI address, otherwise set to '0'
AjK 0:c409efd8df78 165 uint32_t Control; //!< GPDMA Control of this LLI
AjK 0:c409efd8df78 166 } GPDMA_LLI_t;
AjK 0:c409efd8df78 167 */
AjK 0:c409efd8df78 168
AjK 0:c409efd8df78 169 /**
AjK 0:c409efd8df78 170 * @author Andy Kirkham
AjK 0:c409efd8df78 171 * @see http://mbed.org/cookbook/MODDMA_Config
AjK 0:c409efd8df78 172 * @see MODDMA
AjK 0:c409efd8df78 173 * @see API
AjK 0:c409efd8df78 174 *
AjK 0:c409efd8df78 175 * <b>MODDMA_Config</b> defines a configuration that can be passed to the MODDMA controller
AjK 0:c409efd8df78 176 * instance to perform a GPDMA data transfer.
AjK 0:c409efd8df78 177 * transfers from memory to memory, memory to peripheral or peripheral to memory.
AjK 0:c409efd8df78 178 */
AjK 0:c409efd8df78 179 class MODDMA
AjK 0:c409efd8df78 180 {
AjK 0:c409efd8df78 181 public:
AjK 0:c409efd8df78 182
AjK 0:c409efd8df78 183 //! Channel definitions.
AjK 0:c409efd8df78 184 enum CHANNELS {
AjK 0:c409efd8df78 185 Channel_0 = 0 /*!< Channel 0 */
AjK 0:c409efd8df78 186 , Channel_1 /*!< Channel 1 */
AjK 0:c409efd8df78 187 , Channel_2 /*!< Channel 2 */
AjK 0:c409efd8df78 188 , Channel_3 /*!< Channel 3 */
AjK 0:c409efd8df78 189 , Channel_4 /*!< Channel 4 */
AjK 0:c409efd8df78 190 , Channel_5 /*!< Channel 5 */
AjK 0:c409efd8df78 191 , Channel_6 /*!< Channel 6 */
AjK 0:c409efd8df78 192 , Channel_7 /*!< Channel 7 */
AjK 0:c409efd8df78 193 };
AjK 0:c409efd8df78 194
AjK 0:c409efd8df78 195 //! Interrupt callback types.
AjK 0:c409efd8df78 196 enum IrqType_t {
AjK 0:c409efd8df78 197 TcIrq = 0 /*!< Terminal Count interrupt */
AjK 0:c409efd8df78 198 , ErrIrq /*!< Error interrupt */
AjK 0:c409efd8df78 199 };
AjK 0:c409efd8df78 200
AjK 0:c409efd8df78 201 //! Return status codes.
AjK 0:c409efd8df78 202 enum Status {
AjK 0:c409efd8df78 203 Ok = 0 /*!< Ok, suceeded */
AjK 0:c409efd8df78 204 , Error = -1 /*!< General error */
AjK 0:c409efd8df78 205 , ErrChInUse = -2 /*!< Specific error, channel in use */
AjK 0:c409efd8df78 206 };
AjK 0:c409efd8df78 207
AjK 0:c409efd8df78 208 //! DMA Connection number definitions
AjK 0:c409efd8df78 209 enum GPDMA_CONNECTION {
AjK 0:c409efd8df78 210 SSP0_Tx = 0UL /*!< SSP0 Tx */
AjK 0:c409efd8df78 211 , SSP0_Rx = 1UL /*!< SSP0 Rx */
AjK 0:c409efd8df78 212 , SSP1_Tx = 2UL /*!< SSP1 Tx */
AjK 0:c409efd8df78 213 , SSP1_Rx = 3UL /*!< SSP1 Rx */
AjK 0:c409efd8df78 214 , ADC = 4UL /*!< ADC */
AjK 0:c409efd8df78 215 , I2S_Channel_0 = 5UL /*!< I2S channel 0 */
AjK 0:c409efd8df78 216 , I2S_Channel_1 = 6UL /*!< I2S channel 1 */
AjK 0:c409efd8df78 217 , DAC = 7UL /*!< DAC */
AjK 0:c409efd8df78 218 , UART0_Tx = 8UL /*!< UART0 Tx */
AjK 0:c409efd8df78 219 , UART0_Rx = 9UL /*!< UART0 Rx */
AjK 0:c409efd8df78 220 , UART1_Tx = 10UL /*!< UART1 Tx */
AjK 0:c409efd8df78 221 , UART1_Rx = 11UL /*!< UART1 Rx */
AjK 0:c409efd8df78 222 , UART2_Tx = 12UL /*!< UART2 Tx */
AjK 0:c409efd8df78 223 , UART2_Rx = 13UL /*!< UART2 Rx */
AjK 0:c409efd8df78 224 , UART3_Tx = 14UL /*!< UART3 Tx */
AjK 0:c409efd8df78 225 , UART3_Rx = 15UL /*!< UART3 Rx */
AjK 0:c409efd8df78 226 , MAT0_0 = 16UL /*!< MAT0.0 */
AjK 0:c409efd8df78 227 , MAT0_1 = 17UL /*!< MAT0.1 */
AjK 0:c409efd8df78 228 , MAT1_0 = 18UL /*!< MAT1.0 */
AjK 0:c409efd8df78 229 , MAT1_1 = 19UL /*!< MAT1.1 */
AjK 0:c409efd8df78 230 , MAT2_0 = 20UL /**< MAT2.0 */
AjK 0:c409efd8df78 231 , MAT2_1 = 21UL /*!< MAT2.1 */
AjK 0:c409efd8df78 232 , MAT3_0 = 22UL /*!< MAT3.0 */
AjK 0:c409efd8df78 233 , MAT3_1 = 23UL /*!< MAT3.1 */
AjK 0:c409efd8df78 234 };
AjK 0:c409efd8df78 235
AjK 0:c409efd8df78 236 //! GPDMA Transfer type definitions
AjK 0:c409efd8df78 237 enum GPDMA_TRANSFERTYPE {
AjK 0:c409efd8df78 238 m2m = 0UL /*!< Memory to memory - DMA control */
AjK 0:c409efd8df78 239 , m2p = 1UL /*!< Memory to peripheral - DMA control */
AjK 0:c409efd8df78 240 , p2m = 2UL /*!< Peripheral to memory - DMA control */
AjK 0:c409efd8df78 241 , p2p = 3UL /*!< Src peripheral to dest peripheral - DMA control */
AjK 0:c409efd8df78 242 };
AjK 0:c409efd8df78 243
AjK 0:c409efd8df78 244 //! Burst size in Source and Destination definitions */
AjK 0:c409efd8df78 245 enum GPDMA_BSIZE {
AjK 0:c409efd8df78 246 _1 = 0UL /*!< Burst size = 1 */
AjK 0:c409efd8df78 247 , _4 = 1UL /*!< Burst size = 4 */
AjK 0:c409efd8df78 248 , _8 = 2UL /*!< Burst size = 8 */
AjK 0:c409efd8df78 249 , _16 = 3UL /*!< Burst size = 16 */
AjK 0:c409efd8df78 250 , _32 = 4UL /*!< Burst size = 32 */
AjK 0:c409efd8df78 251 , _64 = 5UL /*!< Burst size = 64 */
AjK 0:c409efd8df78 252 , _128 = 6UL /*!< Burst size = 128 */
AjK 0:c409efd8df78 253 , _256 = 7UL /*!< Burst size = 256 */
AjK 0:c409efd8df78 254 };
AjK 0:c409efd8df78 255
AjK 0:c409efd8df78 256 //! Width in Src transfer width and Dest transfer width definitions */
AjK 0:c409efd8df78 257 enum GPDMA_WIDTH {
AjK 0:c409efd8df78 258 byte = 0UL /*!< Width = 1 byte */
AjK 0:c409efd8df78 259 , halfword = 1UL /*!< Width = 2 bytes */
AjK 0:c409efd8df78 260 , word = 2UL /*!< Width = 4 bytes */
AjK 0:c409efd8df78 261 };
AjK 0:c409efd8df78 262
AjK 0:c409efd8df78 263 //! DMA Request Select Mode definitions. */
AjK 0:c409efd8df78 264 enum GPDMA_REQSEL {
AjK 0:c409efd8df78 265 uart = 0UL /*!< UART TX/RX is selected */
AjK 0:c409efd8df78 266 , timer = 1UL /*!< Timer match is selected */
AjK 0:c409efd8df78 267 };
AjK 0:c409efd8df78 268
AjK 0:c409efd8df78 269 //! GPDMA Control register bits.
AjK 0:c409efd8df78 270 enum Config {
AjK 0:c409efd8df78 271 _E = 1 /*!< DMA Controller enable */
AjK 0:c409efd8df78 272 , _M = 2 /*!< AHB Master endianness configuration */
AjK 0:c409efd8df78 273 };
AjK 0:c409efd8df78 274
AjK 0:c409efd8df78 275 //! GPDMA Channel config register bits.
AjK 0:c409efd8df78 276 enum CConfig {
AjK 0:c409efd8df78 277 _CE = (1UL << 0) /*!< Channel enable */
AjK 0:c409efd8df78 278 , _IE = (1UL << 14) /*!< Interrupt error mask */
AjK 0:c409efd8df78 279 , _ITC = (1UL << 15) /*!< Terminal count interrupt mask */
AjK 0:c409efd8df78 280 , _L = (1UL << 16) /*!< Lock */
AjK 0:c409efd8df78 281 , _A = (1UL << 17) /*!< Active */
AjK 0:c409efd8df78 282 , _H = (1UL << 18) /*!< Halt */
AjK 0:c409efd8df78 283 };
AjK 0:c409efd8df78 284
AjK 0:c409efd8df78 285 /**
AjK 0:c409efd8df78 286 * The MODDMA constructor is used to initialise the DMA controller object.
AjK 0:c409efd8df78 287 */
AjK 0:c409efd8df78 288 MODDMA() { init(true); }
AjK 0:c409efd8df78 289
AjK 0:c409efd8df78 290 /**
AjK 0:c409efd8df78 291 * The MODDMA destructor.
AjK 0:c409efd8df78 292 */
AjK 0:c409efd8df78 293 ~MODDMA() {}
AjK 0:c409efd8df78 294
AjK 0:c409efd8df78 295 /**
AjK 0:c409efd8df78 296 * Used to setup the DMA controller to prepare for a data transfer.
AjK 0:c409efd8df78 297 *
AjK 0:c409efd8df78 298 * @param c A pointer to an instance of MODDMA_Config to setup.
AjK 0:c409efd8df78 299 */
AjK 0:c409efd8df78 300 Status Setup(MODDMA_Config *c);
AjK 0:c409efd8df78 301
AjK 0:c409efd8df78 302 /**
AjK 0:c409efd8df78 303 * Enable and begin data transfer.
AjK 0:c409efd8df78 304 *
AjK 0:c409efd8df78 305 * @param ChannelNumber Type CHANNELS, the channel number to enable
AjK 0:c409efd8df78 306 */
AjK 0:c409efd8df78 307 void Enable(CHANNELS ChannelNumber);
AjK 0:c409efd8df78 308
AjK 0:c409efd8df78 309 /**
AjK 0:c409efd8df78 310 * Enable and begin data transfer (overloaded function)
AjK 0:c409efd8df78 311 *
AjK 0:c409efd8df78 312 * @param ChannelNumber Type uin32_t, the channel number to enable
AjK 0:c409efd8df78 313 */
AjK 0:c409efd8df78 314 void Enable(uint32_t ChannelNumber) { Enable((CHANNELS)(ChannelNumber & 0x7)); }
AjK 0:c409efd8df78 315
AjK 0:c409efd8df78 316 /**
AjK 0:c409efd8df78 317 * Disable a channel and end data transfer.
AjK 0:c409efd8df78 318 *
AjK 0:c409efd8df78 319 * @param ChannelNumber Type CHANNELS, the channel number to enable
AjK 0:c409efd8df78 320 */
AjK 0:c409efd8df78 321 void Disable(CHANNELS ChannelNumber);
AjK 0:c409efd8df78 322
AjK 0:c409efd8df78 323 /**
AjK 0:c409efd8df78 324 * Disable a channel and end data transfer (overloaded function)
AjK 0:c409efd8df78 325 *
AjK 0:c409efd8df78 326 * @param ChannelNumber Type uin32_t, the channel number to disable
AjK 0:c409efd8df78 327 */
AjK 0:c409efd8df78 328 void Disable(uint32_t ChannelNumber) { Disable((CHANNELS)(ChannelNumber & 0x7)); }
AjK 0:c409efd8df78 329
AjK 0:c409efd8df78 330 /**
AjK 0:c409efd8df78 331 * Is the specified channel enabled?
AjK 0:c409efd8df78 332 *
AjK 0:c409efd8df78 333 * @param ChannelNumber Type CHANNELS, the channel number to test
AjK 0:c409efd8df78 334 * @return bool true if enabled, false otherwise.
AjK 0:c409efd8df78 335 */
AjK 0:c409efd8df78 336 bool Enabled(CHANNELS ChannelNumber);
AjK 0:c409efd8df78 337
AjK 0:c409efd8df78 338 /**
AjK 0:c409efd8df78 339 * Is the specified channel enabled? (overloaded function)
AjK 0:c409efd8df78 340 *
AjK 0:c409efd8df78 341 * @param ChannelNumber Type uin32_t, the channel number to test
AjK 0:c409efd8df78 342 * @return bool true if enabled, false otherwise.
AjK 0:c409efd8df78 343 */
AjK 0:c409efd8df78 344 bool Enabled(uint32_t ChannelNumber) { Enabled((CHANNELS)(ChannelNumber & 0x7)); }
AjK 0:c409efd8df78 345
AjK 0:c409efd8df78 346 __INLINE uint32_t IntStat(uint32_t n) { return (1UL << n) & 0xFF; }
AjK 0:c409efd8df78 347 __INLINE uint32_t IntTCStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
AjK 0:c409efd8df78 348 __INLINE uint32_t IntTCClear_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
AjK 0:c409efd8df78 349 __INLINE uint32_t IntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
AjK 0:c409efd8df78 350 __INLINE uint32_t IntErrClr_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
AjK 0:c409efd8df78 351 __INLINE uint32_t RawIntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
AjK 0:c409efd8df78 352 __INLINE uint32_t EnbldChns_Ch(uint32_t n) { return (1UL << n) & 0xFF; }
AjK 0:c409efd8df78 353 __INLINE uint32_t SoftBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
AjK 0:c409efd8df78 354 __INLINE uint32_t SoftSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
AjK 0:c409efd8df78 355 __INLINE uint32_t SoftLBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
AjK 0:c409efd8df78 356 __INLINE uint32_t SoftLSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
AjK 0:c409efd8df78 357 __INLINE uint32_t Sync_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }
AjK 0:c409efd8df78 358 __INLINE uint32_t ReqSel_Input(uint32_t n) { return (1UL << (n - 8)) & 0xFF; }
AjK 0:c409efd8df78 359
AjK 0:c409efd8df78 360
AjK 0:c409efd8df78 361 __INLINE uint32_t CxControl_TransferSize(uint32_t n) { return (n & 0xFFF) << 0; }
AjK 0:c409efd8df78 362 __INLINE uint32_t CxControl_SBSize(uint32_t n) { return (n & 0x7) << 12; }
AjK 0:c409efd8df78 363 __INLINE uint32_t CxControl_DBSize(uint32_t n) { return (n & 0x7) << 15; }
AjK 0:c409efd8df78 364 __INLINE uint32_t CxControl_SWidth(uint32_t n) { return (n & 0x7) << 18; }
AjK 0:c409efd8df78 365 __INLINE uint32_t CxControl_DWidth(uint32_t n) { return (n & 0x7) << 21; }
AjK 0:c409efd8df78 366 __INLINE uint32_t CxControl_SI() { return (1UL << 26); }
AjK 0:c409efd8df78 367 __INLINE uint32_t CxControl_DI() { return (1UL << 27); }
AjK 0:c409efd8df78 368 __INLINE uint32_t CxControl_Prot1() { return (1UL << 28); }
AjK 0:c409efd8df78 369 __INLINE uint32_t CxControl_Prot2() { return (1UL << 29); }
AjK 0:c409efd8df78 370 __INLINE uint32_t CxControl_Prot3() { return (1UL << 30); }
AjK 0:c409efd8df78 371 __INLINE uint32_t CxControl_I() { return (1UL << 31); }
AjK 0:c409efd8df78 372 __INLINE uint32_t CxControl_E() { return (1UL << 0); }
AjK 0:c409efd8df78 373 __INLINE uint32_t CxConfig_SrcPeripheral(uint32_t n) { return (n & 0x1F) << 1; }
AjK 0:c409efd8df78 374 __INLINE uint32_t CxConfig_DestPeripheral(uint32_t n) { return (n & 0x1F) << 6; }
AjK 0:c409efd8df78 375 __INLINE uint32_t CxConfig_TransferType(uint32_t n) { return (n & 0x7) << 11; }
AjK 0:c409efd8df78 376 __INLINE uint32_t CxConfig_IE() { return (1UL << 14); }
AjK 0:c409efd8df78 377 __INLINE uint32_t CxConfig_ITC() { return (1UL << 15); }
AjK 0:c409efd8df78 378 __INLINE uint32_t CxConfig_L() { return (1UL << 16); }
AjK 0:c409efd8df78 379 __INLINE uint32_t CxConfig_A() { return (1UL << 17); }
AjK 0:c409efd8df78 380 __INLINE uint32_t CxConfig_H() { return (1UL << 18); }
AjK 0:c409efd8df78 381
AjK 0:c409efd8df78 382 /**
AjK 0:c409efd8df78 383 * A store for up to 8 (8 channels) of configurations.
AjK 0:c409efd8df78 384 * @see MODDMA_Config
AjK 0:c409efd8df78 385 */
AjK 0:c409efd8df78 386 MODDMA_Config *setups[8];
AjK 0:c409efd8df78 387
AjK 0:c409efd8df78 388 /**
AjK 0:c409efd8df78 389 * Get a pointer to the current configuration the ISR is servicing.
AjK 0:c409efd8df78 390 *
AjK 0:c409efd8df78 391 * @return MODDMA_Config * A pointer to the setup the ISR is currently servicing.
AjK 0:c409efd8df78 392 */
AjK 0:c409efd8df78 393 MODDMA_Config *getConfig(void) { return setups[IrqProcessingChannel]; }
AjK 0:c409efd8df78 394
AjK 0:c409efd8df78 395 /**
AjK 0:c409efd8df78 396 * Set which channel the ISR is currently servicing.
AjK 0:c409efd8df78 397 *
AjK 0:c409efd8df78 398 * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***
AjK 0:c409efd8df78 399 *
AjK 0:c409efd8df78 400 * Must be public so the extern "C" ISR can use it.
AjK 0:c409efd8df78 401 */
AjK 0:c409efd8df78 402 void setIrqProcessingChannel(CHANNELS n) { IrqProcessingChannel = n; }
AjK 0:c409efd8df78 403
AjK 0:c409efd8df78 404 /**
AjK 0:c409efd8df78 405 * Gets which channel the ISR is currently servicing.
AjK 0:c409efd8df78 406 *
AjK 0:c409efd8df78 407 * @return CHANNELS The current channel the ISR is servicing.
AjK 0:c409efd8df78 408 */
AjK 0:c409efd8df78 409 CHANNELS irqProcessingChannel(void) { return IrqProcessingChannel; }
AjK 0:c409efd8df78 410
AjK 0:c409efd8df78 411 /**
AjK 0:c409efd8df78 412 * Gets which channel the ISR is currently servicing.
AjK 0:c409efd8df78 413 *
AjK 0:c409efd8df78 414 * @return uint32_t The current channel the ISR is servicing.
AjK 0:c409efd8df78 415 */
AjK 0:c409efd8df78 416 uint32_t irqProcessingChannel(void) { return (uint32_t)(IrqProcessingChannel & 0x7); }
AjK 0:c409efd8df78 417
AjK 0:c409efd8df78 418 /**
AjK 0:c409efd8df78 419 * Sets which type of IRQ the ISR is making a callback for.
AjK 0:c409efd8df78 420 *
AjK 0:c409efd8df78 421 * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***
AjK 0:c409efd8df78 422 *
AjK 0:c409efd8df78 423 * Must be public so the extern "C" ISR can use it.
AjK 0:c409efd8df78 424 */
AjK 0:c409efd8df78 425 void setIrqType(IrqType_t n) { IrqType = n; }
AjK 0:c409efd8df78 426
AjK 0:c409efd8df78 427 /**
AjK 0:c409efd8df78 428 * Get which type of IRQ the ISR is calling you about,
AjK 0:c409efd8df78 429 * terminal count or error.
AjK 0:c409efd8df78 430 */
AjK 0:c409efd8df78 431 IrqType_t irqType(void) { return IrqType; }
AjK 0:c409efd8df78 432
AjK 0:c409efd8df78 433 /**
AjK 0:c409efd8df78 434 * Clear the interrupt after handling.
AjK 0:c409efd8df78 435 *
AjK 0:c409efd8df78 436 * @param CHANNELS The channel the IQR occured on.
AjK 0:c409efd8df78 437 */
AjK 0:c409efd8df78 438 void clearTcIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); }
AjK 0:c409efd8df78 439
AjK 0:c409efd8df78 440 /**
AjK 0:c409efd8df78 441 * Clear the interrupt the ISR is currently handing..
AjK 0:c409efd8df78 442 */
AjK 0:c409efd8df78 443 void clearTcIrq(void) { clearTcIrq( IrqProcessingChannel ); }
AjK 0:c409efd8df78 444
AjK 0:c409efd8df78 445 /**
AjK 0:c409efd8df78 446 * Clear the error interrupt after handling.
AjK 0:c409efd8df78 447 *
AjK 0:c409efd8df78 448 * @param CHANNELS The channel the IQR occured on.
AjK 0:c409efd8df78 449 */
AjK 0:c409efd8df78 450 void clearErrIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); }
AjK 0:c409efd8df78 451
AjK 0:c409efd8df78 452 /**
AjK 0:c409efd8df78 453 * Clear the error interrupt the ISR is currently handing.
AjK 0:c409efd8df78 454 */
AjK 0:c409efd8df78 455 void clearErrIrq(void) { clearErrIrq( IrqProcessingChannel ); }
AjK 0:c409efd8df78 456
AjK 0:c409efd8df78 457 /**
AjK 0:c409efd8df78 458 * Is the supplied channel currently active?
AjK 0:c409efd8df78 459 *
AjK 0:c409efd8df78 460 * @param CHANNELS The channel to inquire about.
AjK 0:c409efd8df78 461 * @return bool true if active, false otherwise.
AjK 0:c409efd8df78 462 */
AjK 0:c409efd8df78 463 bool isActive(CHANNELS ChannelNumber);
AjK 0:c409efd8df78 464
AjK 0:c409efd8df78 465 /**
AjK 0:c409efd8df78 466 * Halt the supplied channel.
AjK 0:c409efd8df78 467 *
AjK 0:c409efd8df78 468 * @param CHANNELS The channel to halt.
AjK 0:c409efd8df78 469 */
AjK 0:c409efd8df78 470 void haltChannel(CHANNELS ChannelNumber);
AjK 0:c409efd8df78 471
AjK 0:c409efd8df78 472 /**
AjK 0:c409efd8df78 473 * Wait for channel transfer to complete and then halt.
AjK 0:c409efd8df78 474 *
AjK 0:c409efd8df78 475 * @param CHANNELS The channel to wait for then halt.
AjK 0:c409efd8df78 476 */
AjK 0:c409efd8df78 477 void haltAndWaitChannelComplete(CHANNELS n) { haltChannel(n); while (isActive(n)); }
AjK 0:c409efd8df78 478
AjK 0:c409efd8df78 479 /**
AjK 0:c409efd8df78 480 * The MODDMA controllers terminal count interrupt callback.
AjK 0:c409efd8df78 481 */
AjK 0:c409efd8df78 482 FunctionPointer isrIntTCStat;
AjK 0:c409efd8df78 483
AjK 0:c409efd8df78 484 /**
AjK 0:c409efd8df78 485 * The MODDMA controllers error interrupt callback.
AjK 0:c409efd8df78 486 */
AjK 0:c409efd8df78 487 FunctionPointer isrIntErrStat;
AjK 0:c409efd8df78 488
AjK 0:c409efd8df78 489 protected:
AjK 0:c409efd8df78 490
AjK 0:c409efd8df78 491 void init(bool isConstructorCalling, int Channels = 0xFF, int Tc = 0xFF, int Err = 0xFF);
AjK 0:c409efd8df78 492
AjK 0:c409efd8df78 493 // Data LUTs.
AjK 0:c409efd8df78 494 uint32_t LUTPerAddr(int n);
AjK 0:c409efd8df78 495 uint8_t LUTPerBurst(int n);
AjK 0:c409efd8df78 496 uint8_t LUTPerWid(int n);
AjK 0:c409efd8df78 497 uint32_t Channel_p(int channel);
AjK 0:c409efd8df78 498
AjK 0:c409efd8df78 499 CHANNELS IrqProcessingChannel;
AjK 0:c409efd8df78 500
AjK 0:c409efd8df78 501 IrqType_t IrqType;
AjK 0:c409efd8df78 502 };
AjK 0:c409efd8df78 503
AjK 0:c409efd8df78 504 }; // namespace AjK ends.
AjK 0:c409efd8df78 505
AjK 0:c409efd8df78 506 using namespace AjK;
AjK 0:c409efd8df78 507
AjK 0:c409efd8df78 508 #endif