Andy K / MODDMA

MODDMA GPDMA Controller New features: transfer pins to memory buffer under periodic timer control and send double buffers to DAC

Dependents:   FirstTest WaveSim IO-dma-memmem DACDMAfuncgenlib ... more

DATALUTS.cpp@0:c409efd8df78, 2010-11-23 (annotated)

Committer:
AjK
Date:
Tue Nov 23 14:50:39 2010 +0000
Revision:
0:c409efd8df78
Child:
8:cb4d323ce6fd
0.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 0:c409efd8df78 1 /*
AjK 0:c409efd8df78 2 Copyright (c) 2010 Andy Kirkham
AjK 0:c409efd8df78 3
AjK 0:c409efd8df78 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 0:c409efd8df78 5 of this software and associated documentation files (the "Software"), to deal
AjK 0:c409efd8df78 6 in the Software without restriction, including without limitation the rights
AjK 0:c409efd8df78 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 0:c409efd8df78 8 copies of the Software, and to permit persons to whom the Software is
AjK 0:c409efd8df78 9 furnished to do so, subject to the following conditions:
AjK 0:c409efd8df78 10
AjK 0:c409efd8df78 11 The above copyright notice and this permission notice shall be included in
AjK 0:c409efd8df78 12 all copies or substantial portions of the Software.
AjK 0:c409efd8df78 13
AjK 0:c409efd8df78 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 0:c409efd8df78 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 0:c409efd8df78 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 0:c409efd8df78 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 0:c409efd8df78 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 0:c409efd8df78 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 0:c409efd8df78 20 THE SOFTWARE.
AjK 0:c409efd8df78 21 */
AjK 0:c409efd8df78 22
AjK 0:c409efd8df78 23 #include "MODDMA.h"
AjK 0:c409efd8df78 24
AjK 0:c409efd8df78 25 #ifndef MBED_H
AjK 0:c409efd8df78 26 #include "mbed.h"
AjK 0:c409efd8df78 27 #endif
AjK 0:c409efd8df78 28
AjK 0:c409efd8df78 29 #ifndef MODDMA_CONFIG_H
AjK 0:c409efd8df78 30 #include "CONFIG.h"
AjK 0:c409efd8df78 31 #endif
AjK 0:c409efd8df78 32
AjK 0:c409efd8df78 33 namespace AjK {
AjK 0:c409efd8df78 34
AjK 0:c409efd8df78 35 uint32_t
AjK 0:c409efd8df78 36 MODDMA::LUTPerAddr(int n)
AjK 0:c409efd8df78 37 {
AjK 0:c409efd8df78 38 const uint32_t lut[] = {
AjK 0:c409efd8df78 39 (uint32_t)&LPC_SSP0->DR // SSP0 Tx
AjK 0:c409efd8df78 40 , (uint32_t)&LPC_SSP0->DR // SSP0 Rx
AjK 0:c409efd8df78 41 , (uint32_t)&LPC_SSP1->DR // SSP1 Tx
AjK 0:c409efd8df78 42 , (uint32_t)&LPC_SSP1->DR // SSP1 Rx
AjK 0:c409efd8df78 43 , (uint32_t)&LPC_ADC->ADGDR // ADC
AjK 0:c409efd8df78 44 , (uint32_t)&LPC_I2S->I2STXFIFO // I2S Tx
AjK 0:c409efd8df78 45 , (uint32_t)&LPC_I2S->I2SRXFIFO // I2S Rx
AjK 0:c409efd8df78 46 , (uint32_t)&LPC_DAC->DACR // DAC
AjK 0:c409efd8df78 47 , (uint32_t)&LPC_UART0->THR // UART0 Tx
AjK 0:c409efd8df78 48 , (uint32_t)&LPC_UART0->RBR // UART0 Rx
AjK 0:c409efd8df78 49 , (uint32_t)&LPC_UART1->THR // UART1 Tx
AjK 0:c409efd8df78 50 , (uint32_t)&LPC_UART1->RBR // UART1 Rx
AjK 0:c409efd8df78 51 , (uint32_t)&LPC_UART2->THR // UART2 Tx
AjK 0:c409efd8df78 52 , (uint32_t)&LPC_UART2->RBR // UART2 Rx
AjK 0:c409efd8df78 53 , (uint32_t)&LPC_UART3->THR // UART3 Tx
AjK 0:c409efd8df78 54 , (uint32_t)&LPC_UART3->RBR // UART3 Rx
AjK 0:c409efd8df78 55 , (uint32_t)&LPC_TIM0->MR0 // MAT0.0
AjK 0:c409efd8df78 56 , (uint32_t)&LPC_TIM0->MR1 // MAT0.1
AjK 0:c409efd8df78 57 , (uint32_t)&LPC_TIM1->MR0 // MAT1.0
AjK 0:c409efd8df78 58 , (uint32_t)&LPC_TIM1->MR1 // MAT1.1
AjK 0:c409efd8df78 59 , (uint32_t)&LPC_TIM2->MR0 // MAT2.0
AjK 0:c409efd8df78 60 , (uint32_t)&LPC_TIM2->MR1 // MAT2.1
AjK 0:c409efd8df78 61 , (uint32_t)&LPC_TIM3->MR0 // MAT3.0
AjK 0:c409efd8df78 62 , (uint32_t)&LPC_TIM3->MR1 // MAT3.1
AjK 0:c409efd8df78 63 };
AjK 0:c409efd8df78 64 return lut[n & 0xFF];
AjK 0:c409efd8df78 65 }
AjK 0:c409efd8df78 66
AjK 0:c409efd8df78 67 uint32_t
AjK 0:c409efd8df78 68 MODDMA::Channel_p(int channel)
AjK 0:c409efd8df78 69 {
AjK 0:c409efd8df78 70 const uint32_t lut[] = {
AjK 0:c409efd8df78 71 (uint32_t)LPC_GPDMACH0
AjK 0:c409efd8df78 72 , (uint32_t)LPC_GPDMACH1
AjK 0:c409efd8df78 73 , (uint32_t)LPC_GPDMACH2
AjK 0:c409efd8df78 74 , (uint32_t)LPC_GPDMACH3
AjK 0:c409efd8df78 75 , (uint32_t)LPC_GPDMACH4
AjK 0:c409efd8df78 76 , (uint32_t)LPC_GPDMACH5
AjK 0:c409efd8df78 77 , (uint32_t)LPC_GPDMACH6
AjK 0:c409efd8df78 78 , (uint32_t)LPC_GPDMACH7
AjK 0:c409efd8df78 79 };
AjK 0:c409efd8df78 80 return lut[channel & 0xFF];
AjK 0:c409efd8df78 81 }
AjK 0:c409efd8df78 82
AjK 0:c409efd8df78 83 uint8_t
AjK 0:c409efd8df78 84 MODDMA::LUTPerBurst(int n)
AjK 0:c409efd8df78 85 {
AjK 0:c409efd8df78 86 const uint8_t lut[] = {
AjK 0:c409efd8df78 87 (uint8_t)_4 // SSP0 Tx
AjK 0:c409efd8df78 88 , (uint8_t)_4 // SSP0 Rx
AjK 0:c409efd8df78 89 , (uint8_t)_4 // SSP1 Tx
AjK 0:c409efd8df78 90 , (uint8_t)_4 // SSP1 Rx
AjK 0:c409efd8df78 91 , (uint8_t)_4 // ADC
AjK 0:c409efd8df78 92 , (uint8_t)_32 // I2S channel 0
AjK 0:c409efd8df78 93 , (uint8_t)_32 // I2S channel 1
AjK 0:c409efd8df78 94 , (uint8_t)_1 // DAC
AjK 0:c409efd8df78 95 , (uint8_t)_1 // UART0 Tx
AjK 0:c409efd8df78 96 , (uint8_t)_1 // UART0 Rx
AjK 0:c409efd8df78 97 , (uint8_t)_1 // UART1 Tx
AjK 0:c409efd8df78 98 , (uint8_t)_1 // UART1 Rx
AjK 0:c409efd8df78 99 , (uint8_t)_1 // UART2 Tx
AjK 0:c409efd8df78 100 , (uint8_t)_1 // UART2 Rx
AjK 0:c409efd8df78 101 , (uint8_t)_1 // UART3 Tx
AjK 0:c409efd8df78 102 , (uint8_t)_1 // UART3 Rx
AjK 0:c409efd8df78 103 , (uint8_t)_1 // MAT0.0
AjK 0:c409efd8df78 104 , (uint8_t)_1 // MAT0.1
AjK 0:c409efd8df78 105 , (uint8_t)_1 // MAT1.0
AjK 0:c409efd8df78 106 , (uint8_t)_1 // MAT1.1
AjK 0:c409efd8df78 107 , (uint8_t)_1 // MAT2.0
AjK 0:c409efd8df78 108 , (uint8_t)_1 // MAT2.1
AjK 0:c409efd8df78 109 , (uint8_t)_1 // MAT3.0
AjK 0:c409efd8df78 110 , (uint8_t)_1 // MAT3.1
AjK 0:c409efd8df78 111 };
AjK 0:c409efd8df78 112 return lut[n & 0xFFF];
AjK 0:c409efd8df78 113 }
AjK 0:c409efd8df78 114
AjK 0:c409efd8df78 115 uint8_t
AjK 0:c409efd8df78 116 MODDMA::LUTPerWid(int n)
AjK 0:c409efd8df78 117 {
AjK 0:c409efd8df78 118 const uint8_t lut[] = {
AjK 0:c409efd8df78 119 (uint8_t)byte // SSP0 Tx
AjK 0:c409efd8df78 120 , (uint8_t)byte // SSP0 Rx
AjK 0:c409efd8df78 121 , (uint8_t)byte // SSP1 Tx
AjK 0:c409efd8df78 122 , (uint8_t)byte // SSP1 Rx
AjK 0:c409efd8df78 123 , (uint8_t)word // ADC
AjK 0:c409efd8df78 124 , (uint8_t)word // I2S channel 0
AjK 0:c409efd8df78 125 , (uint8_t)word // I2S channel 1
AjK 0:c409efd8df78 126 , (uint8_t)byte // DAC
AjK 0:c409efd8df78 127 , (uint8_t)byte // UART0 Tx
AjK 0:c409efd8df78 128 , (uint8_t)byte // UART0 Rx
AjK 0:c409efd8df78 129 , (uint8_t)byte // UART1 Tx
AjK 0:c409efd8df78 130 , (uint8_t)byte // UART1 Rx
AjK 0:c409efd8df78 131 , (uint8_t)byte // UART2 Tx
AjK 0:c409efd8df78 132 , (uint8_t)byte // UART2 Rx
AjK 0:c409efd8df78 133 , (uint8_t)byte // UART3 Tx
AjK 0:c409efd8df78 134 , (uint8_t)byte // UART3 Rx
AjK 0:c409efd8df78 135 , (uint8_t)word // MAT0.0
AjK 0:c409efd8df78 136 , (uint8_t)word // MAT0.1
AjK 0:c409efd8df78 137 , (uint8_t)word // MAT1.0
AjK 0:c409efd8df78 138 , (uint8_t)word // MAT1.1
AjK 0:c409efd8df78 139 , (uint8_t)word // MAT2.0
AjK 0:c409efd8df78 140 , (uint8_t)word // MAT2.1
AjK 0:c409efd8df78 141 , (uint8_t)word // MAT3.0
AjK 0:c409efd8df78 142 , (uint8_t)word // MAT3.1
AjK 0:c409efd8df78 143 };
AjK 0:c409efd8df78 144 return lut[n & 0xFFF];
AjK 0:c409efd8df78 145 }
AjK 0:c409efd8df78 146
AjK 0:c409efd8df78 147 }; // namespace AjK ends